Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'pinctrl-v4.20-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control fixes from Linus Walleij:
"Three pin control fixes for the v4.20 series. Just odd drivers, so
nothing particularly interesting:
- Set the tile property on Qualcomm SDM60.
- Fix up enable register calculation for the Meson
- Fix an IRQ offset on the Sunxi (Allwinner)"
* tag 'pinctrl-v4.20-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
pinctrl: sunxi: a83t: Fix IRQ offset typo for PH11
pinctrl: meson: fix pull enable register calculation
pinctrl: sdm660: Set tile property for pingroups
+18
-15
+2
-1
drivers/pinctrl/meson/pinctrl-meson.c
+2
-1
drivers/pinctrl/meson/pinctrl-meson.c
···
191
191
case PIN_CONFIG_BIAS_DISABLE:
192
192
dev_dbg(pc->dev, "pin %u: disable bias\n", pin);
193
193
194
-
meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit);
194
+
meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®,
195
+
&bit);
195
196
ret = regmap_update_bits(pc->reg_pullen, reg,
196
197
BIT(bit), 0);
197
198
if (ret)
+15
-13
drivers/pinctrl/qcom/pinctrl-sdm660.c
+15
-13
drivers/pinctrl/qcom/pinctrl-sdm660.c
···
33
33
}
34
34
35
35
36
-
#define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
36
+
#define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
37
37
{ \
38
38
.name = "gpio" #id, \
39
39
.pins = gpio##id##_pins, \
···
51
51
msm_mux_##f9 \
52
52
}, \
53
53
.nfuncs = 10, \
54
-
.ctl_reg = base + REG_SIZE * id, \
55
-
.io_reg = base + 0x4 + REG_SIZE * id, \
56
-
.intr_cfg_reg = base + 0x8 + REG_SIZE * id, \
57
-
.intr_status_reg = base + 0xc + REG_SIZE * id, \
58
-
.intr_target_reg = base + 0x8 + REG_SIZE * id, \
54
+
.ctl_reg = REG_SIZE * id, \
55
+
.io_reg = 0x4 + REG_SIZE * id, \
56
+
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
57
+
.intr_status_reg = 0xc + REG_SIZE * id, \
58
+
.intr_target_reg = 0x8 + REG_SIZE * id, \
59
+
.tile = _tile, \
59
60
.mux_bit = 2, \
60
61
.pull_bit = 0, \
61
62
.drv_bit = 6, \
···
83
82
.intr_cfg_reg = 0, \
84
83
.intr_status_reg = 0, \
85
84
.intr_target_reg = 0, \
85
+
.tile = NORTH, \
86
86
.mux_bit = -1, \
87
87
.pull_bit = pull, \
88
88
.drv_bit = drv, \
···
1399
1397
PINGROUP(111, SOUTH, _, _, _, _, _, _, _, _, _),
1400
1398
PINGROUP(112, SOUTH, _, _, _, _, _, _, _, _, _),
1401
1399
PINGROUP(113, SOUTH, _, _, _, _, _, _, _, _, _),
1402
-
SDC_QDSD_PINGROUP(sdc1_clk, 0x99a000, 13, 6),
1403
-
SDC_QDSD_PINGROUP(sdc1_cmd, 0x99a000, 11, 3),
1404
-
SDC_QDSD_PINGROUP(sdc1_data, 0x99a000, 9, 0),
1405
-
SDC_QDSD_PINGROUP(sdc2_clk, 0x99b000, 14, 6),
1406
-
SDC_QDSD_PINGROUP(sdc2_cmd, 0x99b000, 11, 3),
1407
-
SDC_QDSD_PINGROUP(sdc2_data, 0x99b000, 9, 0),
1408
-
SDC_QDSD_PINGROUP(sdc1_rclk, 0x99a000, 15, 0),
1400
+
SDC_QDSD_PINGROUP(sdc1_clk, 0x9a000, 13, 6),
1401
+
SDC_QDSD_PINGROUP(sdc1_cmd, 0x9a000, 11, 3),
1402
+
SDC_QDSD_PINGROUP(sdc1_data, 0x9a000, 9, 0),
1403
+
SDC_QDSD_PINGROUP(sdc2_clk, 0x9b000, 14, 6),
1404
+
SDC_QDSD_PINGROUP(sdc2_cmd, 0x9b000, 11, 3),
1405
+
SDC_QDSD_PINGROUP(sdc2_data, 0x9b000, 9, 0),
1406
+
SDC_QDSD_PINGROUP(sdc1_rclk, 0x9a000, 15, 0),
1409
1407
};
1410
1408
1411
1409
static const struct msm_pinctrl_soc_data sdm660_pinctrl = {
+1
-1
drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c
+1
-1
drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c
···
568
568
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
569
569
SUNXI_FUNCTION(0x0, "gpio_in"),
570
570
SUNXI_FUNCTION(0x1, "gpio_out"),
571
-
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PH_EINT11 */
571
+
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PH_EINT11 */
572
572
};
573
573
574
574
static const struct sunxi_pinctrl_desc sun8i_a83t_pinctrl_data = {