Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm/dpu: use full scale alpha in _dpu_crtc_setup_blend_cfg()
Both _dpu_crtc_setup_blend_cfg() and setup_blend_config_alpha()
callbacks embed knowledge about platform's alpha range (8-bit or
10-bit). Make _dpu_crtc_setup_blend_cfg() use full 16-bit values for
alpha and reduce alpha only in DPU-specific callbacks.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/697898/
Link: https://lore.kernel.org/r/20260112-dpu-rework-alpha-v2-2-d168785911d5@oss.qualcomm.com
+19
-20
+5
-11
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+5
-11
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
···
326
326
{
327
327
struct dpu_hw_mixer *lm = mixer->hw_lm;
328
328
u32 blend_op;
329
-
u32 fg_alpha, bg_alpha, max_alpha;
329
+
u32 fg_alpha, bg_alpha;
330
330
331
-
if (mdss_ver->core_major_ver < 12) {
332
-
max_alpha = 0xff;
333
-
fg_alpha = pstate->base.alpha >> 8;
334
-
} else {
335
-
max_alpha = 0x3ff;
336
-
fg_alpha = pstate->base.alpha >> 6;
337
-
}
331
+
fg_alpha = pstate->base.alpha;
338
332
339
333
/* default to opaque blending */
340
334
if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE ||
341
335
!format->alpha_enable) {
342
336
blend_op = DPU_BLEND_FG_ALPHA_FG_CONST |
343
337
DPU_BLEND_BG_ALPHA_BG_CONST;
344
-
bg_alpha = max_alpha - fg_alpha;
338
+
bg_alpha = DRM_BLEND_ALPHA_OPAQUE - fg_alpha;
345
339
} else if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
346
340
blend_op = DPU_BLEND_FG_ALPHA_FG_CONST |
347
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DPU_BLEND_BG_ALPHA_FG_PIXEL;
348
-
if (fg_alpha != max_alpha) {
342
+
if (fg_alpha != DRM_BLEND_ALPHA_OPAQUE) {
349
343
bg_alpha = fg_alpha;
350
344
blend_op |= DPU_BLEND_BG_MOD_ALPHA |
351
345
DPU_BLEND_BG_INV_MOD_ALPHA;
···
351
357
/* coverage blending */
352
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blend_op = DPU_BLEND_FG_ALPHA_FG_PIXEL |
353
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DPU_BLEND_BG_ALPHA_FG_PIXEL;
354
-
if (fg_alpha != max_alpha) {
360
+
if (fg_alpha != DRM_BLEND_ALPHA_OPAQUE) {
355
361
bg_alpha = fg_alpha;
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blend_op |= DPU_BLEND_FG_MOD_ALPHA |
357
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DPU_BLEND_FG_INV_MOD_ALPHA |
+13
-8
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
+13
-8
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
···
126
126
}
127
127
128
128
static void dpu_hw_lm_setup_blend_config_combined_alpha(struct dpu_hw_mixer *ctx,
129
-
u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op)
129
+
u32 stage,
130
+
u16 fg_alpha, u16 bg_alpha,
131
+
u32 blend_op)
130
132
{
131
133
struct dpu_hw_blk_reg_map *c = &ctx->hw;
132
134
int stage_off;
···
141
139
if (WARN_ON(stage_off < 0))
142
140
return;
143
141
144
-
const_alpha = (bg_alpha & 0xFF) | ((fg_alpha & 0xFF) << 16);
142
+
const_alpha = (bg_alpha >> 8) | ((fg_alpha >> 8) << 16);
145
143
DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA + stage_off, const_alpha);
146
144
DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op);
147
145
}
148
146
149
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static void
150
148
dpu_hw_lm_setup_blend_config_combined_alpha_v12(struct dpu_hw_mixer *ctx,
151
-
u32 stage, u32 fg_alpha,
152
-
u32 bg_alpha, u32 blend_op)
149
+
u32 stage,
150
+
u16 fg_alpha, u16 bg_alpha,
151
+
u32 blend_op)
153
152
{
154
153
struct dpu_hw_blk_reg_map *c = &ctx->hw;
155
154
int stage_off;
···
163
160
if (WARN_ON(stage_off < 0))
164
161
return;
165
162
166
-
const_alpha = (bg_alpha & 0x3ff) | ((fg_alpha & 0x3ff) << 16);
163
+
const_alpha = (bg_alpha >> 6) | ((fg_alpha >> 6) << 16);
167
164
DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA_V12 + stage_off, const_alpha);
168
165
DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op);
169
166
}
170
167
171
168
static void dpu_hw_lm_setup_blend_config(struct dpu_hw_mixer *ctx,
172
-
u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op)
169
+
u32 stage,
170
+
u16 fg_alpha, u16 bg_alpha,
171
+
u32 blend_op)
173
172
{
174
173
struct dpu_hw_blk_reg_map *c = &ctx->hw;
175
174
int stage_off;
···
183
178
if (WARN_ON(stage_off < 0))
184
179
return;
185
180
186
-
DPU_REG_WRITE(c, LM_BLEND0_FG_ALPHA + stage_off, fg_alpha);
187
-
DPU_REG_WRITE(c, LM_BLEND0_BG_ALPHA + stage_off, bg_alpha);
181
+
DPU_REG_WRITE(c, LM_BLEND0_FG_ALPHA + stage_off, fg_alpha >> 8);
182
+
DPU_REG_WRITE(c, LM_BLEND0_BG_ALPHA + stage_off, bg_alpha >> 8);
188
183
DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op);
189
184
}
190
185
+1
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
+1
-1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
···
41
41
* for the specified stage
42
42
*/
43
43
void (*setup_blend_config)(struct dpu_hw_mixer *ctx, uint32_t stage,
44
-
uint32_t fg_alpha, uint32_t bg_alpha, uint32_t blend_op);
44
+
u16 fg_alpha, u16 bg_alpha, uint32_t blend_op);
45
45
46
46
/**
47
47
* @setup_alpha_out: Alpha color component selection from either fg or bg