tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'nand/for-6.19' into mtd/next

Raw NAND changes:

* The major change in this MR will be the support for the Allwinner H616
NAND controller, which lead to numerous changes and cleanups in the
driver.

* Another notable change on this driver is the use of
field_get()/field_prep(), but since the global support for this
helpers is going to be merged in the same release as we start using
these helpers, it implies undefining them in the first place to avoid
warnings. Depending on the merging order (Yuri's bitmap branch or
mtd/next), a temporary warning may arise.

* Marvell drivers layout handling changes have also landed, they fix
previous definitions and abuses that have been made previously, which
implied to relax the ECC parameters validation in the core a bit.

* The Cadence NAND controller driver gets NV-DDR interface support.

SPI NAND changes:

* Support for FudanMicro FM25S01BI3 and ESMT F50L1G41LC is added.

Aside from these main changes, there is the usual load of fixes and API
updates.

Miquel Raynal 801b0840 de95c587

+761 -100
+38 -3
Documentation/devicetree/bindings/mtd/allwinner,sun4i-a10-nand.yaml
··· 6 6 7 7 title: Allwinner A10 NAND Controller 8 8 9 - allOf: 10 - - $ref: nand-controller.yaml 11 - 12 9 maintainers: 13 10 - Chen-Yu Tsai <wens@csie.org> 14 11 - Maxime Ripard <mripard@kernel.org> ··· 15 18 enum: 16 19 - allwinner,sun4i-a10-nand 17 20 - allwinner,sun8i-a23-nand-controller 21 + - allwinner,sun50i-h616-nand-controller 22 + 18 23 reg: 19 24 maxItems: 1 20 25 ··· 24 25 maxItems: 1 25 26 26 27 clocks: 28 + minItems: 2 27 29 items: 28 30 - description: Bus Clock 29 31 - description: Module Clock 32 + - description: ECC Clock 33 + - description: MBus Clock 30 34 31 35 clock-names: 36 + minItems: 2 32 37 items: 33 38 - const: ahb 34 39 - const: mod 40 + - const: ecc 41 + - const: mbus 35 42 36 43 resets: 37 44 maxItems: 1 ··· 89 84 - clock-names 90 85 91 86 unevaluatedProperties: false 87 + 88 + allOf: 89 + - $ref: nand-controller.yaml 90 + 91 + - if: 92 + properties: 93 + compatible: 94 + contains: 95 + enum: 96 + - allwinner,sun4i-a10-nand 97 + - allwinner,sun8i-a23-nand-controller 98 + then: 99 + properties: 100 + clocks: 101 + maxItems: 2 102 + clock-names: 103 + maxItems: 2 104 + 105 + - if: 106 + properties: 107 + compatible: 108 + contains: 109 + enum: 110 + - allwinner,sun50i-h616-nand-controller 111 + then: 112 + properties: 113 + clocks: 114 + minItems: 4 115 + clock-names: 116 + minItems: 4 92 117 93 118 examples: 94 119 - |
+1 -1
drivers/mtd/nand/Kconfig
··· 63 63 64 64 config MTD_NAND_ECC_REALTEK 65 65 tristate "Realtek RTL93xx hardware ECC engine" 66 - depends on HAS_IOMEM 66 + depends on HAS_IOMEM && HAS_DMA 67 67 depends on MACH_REALTEK_RTL || COMPILE_TEST 68 68 select MTD_NAND_ECC 69 69 help
+265 -10
drivers/mtd/nand/raw/cadence-nand-controller.c
··· 199 199 200 200 /* Common settings. */ 201 201 #define COMMON_SET 0x1008 202 + #define OPR_MODE_NVDDR BIT(0) 202 203 /* 16 bit device connected to the NAND Flash interface. */ 203 204 #define COMMON_SET_DEVICE_16BIT BIT(8) 204 205 ··· 212 211 #define SKIP_BYTES_OFFSET_VALUE GENMASK(23, 0) 213 212 214 213 /* Timings configuration. */ 214 + #define TOGGLE_TIMINGS_0 0x1014 215 + #define TOGGLE_TIMINGS_1 0x1018 216 + 215 217 #define ASYNC_TOGGLE_TIMINGS 0x101c 216 218 #define ASYNC_TOGGLE_TIMINGS_TRH GENMASK(28, 24) 217 219 #define ASYNC_TOGGLE_TIMINGS_TRP GENMASK(20, 16) 218 220 #define ASYNC_TOGGLE_TIMINGS_TWH GENMASK(12, 8) 219 221 #define ASYNC_TOGGLE_TIMINGS_TWP GENMASK(4, 0) 222 + 223 + #define SYNC_TIMINGS 0x1020 224 + #define SYNC_TCKWR GENMASK(21, 16) 225 + #define SYNC_TWRCK GENMASK(13, 8) 226 + #define SYNC_TCAD GENMASK(5, 0) 220 227 221 228 #define TIMINGS0 0x1024 222 229 #define TIMINGS0_TADL GENMASK(31, 24) ··· 235 226 #define TIMINGS1 0x1028 236 227 #define TIMINGS1_TRHZ GENMASK(31, 24) 237 228 #define TIMINGS1_TWB GENMASK(23, 16) 229 + #define TIMINGS1_TCWAW GENMASK(15, 8) 238 230 #define TIMINGS1_TVDLY GENMASK(7, 0) 239 231 240 232 #define TIMINGS2 0x102c ··· 253 243 254 244 /* Register controlling DQ related timing. */ 255 245 #define PHY_DQ_TIMING 0x2000 246 + #define PHY_DQ_TIMING_OE_END GENMASK(2, 0) 247 + #define PHY_DQ_TIMING_OE_START GENMASK(6, 4) 248 + #define PHY_DQ_TIMING_TSEL_END GENMASK(11, 8) 249 + #define PHY_DQ_TIMING_TSEL_START GENMASK(15, 12) 250 + 256 251 /* Register controlling DSQ related timing. */ 257 252 #define PHY_DQS_TIMING 0x2004 258 253 #define PHY_DQS_TIMING_DQS_SEL_OE_END GENMASK(3, 0) 254 + #define PHY_DQS_TIMING_DQS_SEL_OE_START GENMASK(7, 4) 255 + #define PHY_DQS_TIMING_DQS_SEL_TSEL_END GENMASK(11, 8) 259 256 #define PHY_DQS_TIMING_PHONY_DQS_SEL BIT(16) 260 257 #define PHY_DQS_TIMING_USE_PHONY_DQS BIT(20) 261 258 262 259 /* Register controlling the gate and loopback control related timing. */ 263 260 #define PHY_GATE_LPBK_CTRL 0x2008 261 + #define PHY_GATE_LPBK_CTRL_GATE_CFG GENMASK(3, 0) 262 + #define PHY_GATE_LPBK_CTRL_GATE_CFG_CLOSE GENMASK(5, 4) 264 263 #define PHY_GATE_LPBK_CTRL_RDS GENMASK(24, 19) 265 264 266 265 /* Register holds the control for the master DLL logic. */ ··· 278 259 279 260 /* Register holds the control for the slave DLL logic. */ 280 261 #define PHY_DLL_SLAVE_CTRL 0x2010 262 + 263 + /* Register controls the DQS related timing. */ 264 + #define PHY_IE_TIMING 0x2014 265 + #define PHY_IE_TIMING_DQS_IE_START GENMASK(10, 8) 266 + #define PHY_IE_TIMING_DQ_IE_START GENMASK(18, 16) 267 + #define PHY_IE_TIMING_IE_ALWAYS_ON BIT(20) 281 268 282 269 /* This register handles the global control settings for the PHY. */ 283 270 #define PHY_CTRL 0x2080 ··· 400 375 #define BCH_MAX_NUM_CORR_CAPS 8 401 376 #define BCH_MAX_NUM_SECTOR_SIZES 2 402 377 378 + /* NVDDR mode specific parameters and register values based on cadence specs */ 379 + #define NVDDR_PHY_RD_DELAY 29 380 + #define NVDDR_PHY_RD_DELAY_MAX 31 381 + #define NVDDR_GATE_CFG_OPT 14 382 + #define NVDDR_GATE_CFG_STD 7 383 + #define NVDDR_GATE_CFG_MAX 15 384 + #define NVDDR_DATA_SEL_OE_START 1 385 + #define NVDDR_DATA_SEL_OE_START_MAX 7 386 + #define NVDDR_DATA_SEL_OE_END 6 387 + #define NVDDR_DATA_SEL_OE_END_MIN 4 388 + #define NVDDR_DATA_SEL_OE_END_MAX 15 389 + #define NVDDR_RS_HIGH_WAIT_CNT 7 390 + #define NVDDR_RS_IDLE_CNT 7 391 + #define NVDDR_TCWAW_DELAY 250000 392 + #define NVDDR_TVDLY_DELAY 500000 393 + #define NVDDR_TOGGLE_TIMINGS_0 0x00000301 394 + #define NVDDR_TOGGLE_TIMINGS_1 0x0a060102 395 + #define NVDDR_ASYNC_TOGGLE_TIMINGS 0 396 + #define NVDDR_PHY_CTRL 0x00004000 397 + #define NVDDR_PHY_TSEL 0 398 + #define NVDDR_PHY_DLL_MASTER_CTRL 0x00140004 399 + #define NVDDR_PHY_DLL_SLAVE_CTRL 0x00003c3c 400 + 403 401 struct cadence_nand_timings { 404 402 u32 async_toggle_timings; 403 + u32 sync_timings; 405 404 u32 timings0; 406 405 u32 timings1; 407 406 u32 timings2; 408 407 u32 dll_phy_ctrl; 409 408 u32 phy_ctrl; 409 + u32 phy_dq_timing; 410 410 u32 phy_dqs_timing; 411 411 u32 phy_gate_lpbk_ctrl; 412 + u32 phy_ie_timing; 412 413 }; 413 414 414 415 /* Command DMA descriptor. */ ··· 2396 2345 return (trp_cnt + 1) * clk_period + trhoh_min - trea_max; 2397 2346 } 2398 2347 2399 - static int 2400 - cadence_nand_setup_interface(struct nand_chip *chip, int chipnr, 2401 - const struct nand_interface_config *conf) 2348 + static int cadence_nand_setup_sdr_interface(struct nand_chip *chip, 2349 + const struct nand_sdr_timings *sdr) 2402 2350 { 2403 - const struct nand_sdr_timings *sdr; 2404 2351 struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller); 2405 2352 struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip); 2406 2353 struct cadence_nand_timings *t = &cdns_chip->timings; ··· 2419 2370 u32 dll_phy_dqs_timing = 0, phony_dqs_timing = 0, rd_del_sel = 0; 2420 2371 u32 sampling_point; 2421 2372 2422 - sdr = nand_get_sdr_timings(conf); 2423 - if (IS_ERR(sdr)) 2424 - return PTR_ERR(sdr); 2425 - 2426 2373 memset(t, 0, sizeof(*t)); 2427 2374 /* Sampling point calculation. */ 2428 - 2429 2375 if (cdns_ctrl->caps2.is_phy_type_dll) 2430 2376 phony_dqs_mod = 2; 2431 2377 else ··· 2677 2633 PHY_DLL_MASTER_CTRL_BYPASS_MODE); 2678 2634 dev_dbg(cdns_ctrl->dev, "PHY_DLL_SLAVE_CTRL_REG_SDR\t%x\n", 0); 2679 2635 } 2680 - 2681 2636 return 0; 2637 + } 2638 + 2639 + static int 2640 + cadence_nand_setup_nvddr_interface(struct nand_chip *chip, 2641 + const struct nand_nvddr_timings *nvddr) 2642 + { 2643 + struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller); 2644 + struct cdns_nand_chip *cdns_chip = to_cdns_nand_chip(chip); 2645 + struct cadence_nand_timings *t = &cdns_chip->timings; 2646 + u32 board_delay = cdns_ctrl->board_delay; 2647 + u32 clk_period = DIV_ROUND_DOWN_ULL(1000000000000ULL, 2648 + cdns_ctrl->nf_clk_rate); 2649 + u32 ddr_clk_ctrl_period = clk_period * 2; 2650 + u32 if_skew = cdns_ctrl->caps1->if_skew; 2651 + u32 tceh_cnt, tcs_cnt, tadl_cnt, tccs_cnt; 2652 + u32 twrck_cnt, tcad_cnt, tckwr_cnt = 0; 2653 + u32 tfeat_cnt, trhz_cnt, tvdly_cnt, tcwaw_cnt; 2654 + u32 trhw_cnt, twb_cnt, twhr_cnt; 2655 + u32 oe_start, oe_end, oe_end_dqsd; 2656 + u32 rd_del_sel = 0; 2657 + u32 dqs_driven_by_device, dqs_toogle_by_device, gate_open_delay; 2658 + u32 dll_phy_gate_open_delay, gate_close_delay, ie_start; 2659 + u32 dll_phy_rd_delay; 2660 + u32 reg; 2661 + 2662 + memset(t, 0, sizeof(*t)); 2663 + twrck_cnt = calc_cycl(nvddr->tWRCK_min, ddr_clk_ctrl_period); 2664 + tcad_cnt = calc_cycl(nvddr->tCAD_min, ddr_clk_ctrl_period); 2665 + 2666 + reg = FIELD_PREP(SYNC_TWRCK, twrck_cnt); 2667 + reg |= FIELD_PREP(SYNC_TCAD, tcad_cnt); 2668 + t->sync_timings = reg; 2669 + dev_dbg(cdns_ctrl->dev, "SYNC_TIMINGS_NVDDR\t%08x\n", reg); 2670 + 2671 + tadl_cnt = calc_cycl((nvddr->tADL_min + if_skew), ddr_clk_ctrl_period); 2672 + tccs_cnt = calc_cycl((nvddr->tCCS_min + if_skew), ddr_clk_ctrl_period); 2673 + twhr_cnt = calc_cycl((nvddr->tWHR_min + if_skew), ddr_clk_ctrl_period); 2674 + trhw_cnt = calc_cycl((nvddr->tRHW_min + if_skew), ddr_clk_ctrl_period); 2675 + reg = FIELD_PREP(TIMINGS0_TADL, tadl_cnt); 2676 + reg |= FIELD_PREP(TIMINGS0_TCCS, tccs_cnt); 2677 + reg |= FIELD_PREP(TIMINGS0_TWHR, twhr_cnt); 2678 + reg |= FIELD_PREP(TIMINGS0_TRHW, trhw_cnt); 2679 + t->timings0 = reg; 2680 + dev_dbg(cdns_ctrl->dev, "TIMINGS0_NVDDR\t%08x\n", reg); 2681 + 2682 + twb_cnt = calc_cycl((nvddr->tWB_max + board_delay), 2683 + ddr_clk_ctrl_period); 2684 + /* 2685 + * Because of the two stage syncflop the value must be increased by 3 2686 + * first value is related with sync, second value is related 2687 + * with output if delay. 2688 + */ 2689 + twb_cnt = twb_cnt + 3 + 5; 2690 + tvdly_cnt = calc_cycl(NVDDR_TVDLY_DELAY + if_skew, ddr_clk_ctrl_period); 2691 + tcwaw_cnt = calc_cycl(NVDDR_TCWAW_DELAY, ddr_clk_ctrl_period); 2692 + trhz_cnt = 1; 2693 + reg = FIELD_PREP(TIMINGS1_TWB, twb_cnt); 2694 + reg |= FIELD_PREP(TIMINGS1_TVDLY, tvdly_cnt); 2695 + reg |= FIELD_PREP(TIMINGS1_TRHZ, trhz_cnt); 2696 + reg |= FIELD_PREP(TIMINGS1_TCWAW, tcwaw_cnt); 2697 + t->timings1 = reg; 2698 + dev_dbg(cdns_ctrl->dev, "TIMINGS1_NVDDR\t%08x\n", reg); 2699 + 2700 + tfeat_cnt = calc_cycl(nvddr->tFEAT_max, ddr_clk_ctrl_period); 2701 + if (tfeat_cnt < twb_cnt) 2702 + tfeat_cnt = twb_cnt; 2703 + 2704 + tceh_cnt = calc_cycl(nvddr->tCEH_min, ddr_clk_ctrl_period); 2705 + tcs_cnt = calc_cycl((nvddr->tCS_min + if_skew), ddr_clk_ctrl_period); 2706 + reg = FIELD_PREP(TIMINGS2_TFEAT, tfeat_cnt); 2707 + reg |= FIELD_PREP(TIMINGS2_CS_HOLD_TIME, tceh_cnt); 2708 + reg |= FIELD_PREP(TIMINGS2_CS_SETUP_TIME, tcs_cnt); 2709 + t->timings2 = reg; 2710 + dev_dbg(cdns_ctrl->dev, "TIMINGS2_NVDDR\t%08x\n", reg); 2711 + 2712 + reg = FIELD_PREP(DLL_PHY_CTRL_RS_HIGH_WAIT_CNT, NVDDR_RS_HIGH_WAIT_CNT); 2713 + reg |= FIELD_PREP(DLL_PHY_CTRL_RS_IDLE_CNT, NVDDR_RS_IDLE_CNT); 2714 + t->dll_phy_ctrl = reg; 2715 + dev_dbg(cdns_ctrl->dev, "DLL_PHY_CTRL_NVDDR\t%08x\n", reg); 2716 + 2717 + reg = PHY_CTRL_SDR_DQS; 2718 + t->phy_ctrl = reg; 2719 + dev_dbg(cdns_ctrl->dev, "PHY_CTRL_REG_NVDDR\t%08x\n", reg); 2720 + 2721 + dqs_driven_by_device = (nvddr->tDQSD_max + board_delay) / 1000 + 2722 + if_skew; 2723 + dqs_toogle_by_device = (nvddr->tDQSCK_max + board_delay) / 1000 - 2724 + if_skew; 2725 + gate_open_delay = dqs_toogle_by_device / (clk_period / 1000); 2726 + if (dqs_toogle_by_device > clk_period / 1000) { 2727 + if (gate_open_delay > NVDDR_GATE_CFG_OPT) 2728 + dll_phy_gate_open_delay = NVDDR_GATE_CFG_MAX; 2729 + else 2730 + dll_phy_gate_open_delay = gate_open_delay + 1; 2731 + gate_close_delay = 0; 2732 + } else { 2733 + twrck_cnt = calc_cycl(dqs_driven_by_device * 1000, clk_period); 2734 + dll_phy_gate_open_delay = 1; 2735 + gate_close_delay = 0; 2736 + 2737 + reg = FIELD_PREP(SYNC_TCKWR, tckwr_cnt); 2738 + reg |= FIELD_PREP(SYNC_TWRCK, twrck_cnt); 2739 + reg |= FIELD_PREP(SYNC_TCAD, tcad_cnt); 2740 + t->sync_timings = reg; 2741 + dev_dbg(cdns_ctrl->dev, "SYNC_TIMINGS_NVDDR\t%08x\n", reg); 2742 + } 2743 + 2744 + if (dll_phy_gate_open_delay > NVDDR_GATE_CFG_STD) 2745 + ie_start = NVDDR_GATE_CFG_STD; 2746 + else 2747 + ie_start = dll_phy_gate_open_delay; 2748 + 2749 + dll_phy_rd_delay = ((nvddr->tDQSCK_max + board_delay) + 2750 + (clk_period / 2)) / clk_period; 2751 + if (dll_phy_rd_delay <= NVDDR_PHY_RD_DELAY) 2752 + rd_del_sel = dll_phy_rd_delay + 2; 2753 + else 2754 + rd_del_sel = NVDDR_PHY_RD_DELAY_MAX; 2755 + 2756 + reg = FIELD_PREP(PHY_GATE_LPBK_CTRL_GATE_CFG, dll_phy_gate_open_delay); 2757 + reg |= FIELD_PREP(PHY_GATE_LPBK_CTRL_GATE_CFG_CLOSE, gate_close_delay); 2758 + reg |= FIELD_PREP(PHY_GATE_LPBK_CTRL_RDS, rd_del_sel); 2759 + t->phy_gate_lpbk_ctrl = reg; 2760 + dev_dbg(cdns_ctrl->dev, "PHY_GATE_LPBK_CTRL_REG_NVDDR\t%08x\n", reg); 2761 + 2762 + oe_end_dqsd = ((nvddr->tDQSD_max / 1000) / ((clk_period / 2) / 1000)) 2763 + + NVDDR_DATA_SEL_OE_END_MIN; 2764 + oe_end = (NVDDR_DATA_SEL_OE_END_MIN + oe_end_dqsd) / 2; 2765 + if (oe_end > NVDDR_DATA_SEL_OE_END_MAX) 2766 + oe_end = NVDDR_DATA_SEL_OE_END_MAX; 2767 + 2768 + oe_start = ((nvddr->tDQSHZ_max / 1000) / ((clk_period / 2) / 1000)) + 1; 2769 + if (oe_start > NVDDR_DATA_SEL_OE_START_MAX) 2770 + oe_start = NVDDR_DATA_SEL_OE_START_MAX; 2771 + 2772 + reg = FIELD_PREP(PHY_DQ_TIMING_OE_END, NVDDR_DATA_SEL_OE_END); 2773 + reg |= FIELD_PREP(PHY_DQ_TIMING_OE_START, NVDDR_DATA_SEL_OE_START); 2774 + reg |= FIELD_PREP(PHY_DQ_TIMING_TSEL_END, NVDDR_DATA_SEL_OE_END); 2775 + reg |= FIELD_PREP(PHY_DQ_TIMING_TSEL_START, NVDDR_DATA_SEL_OE_START); 2776 + t->phy_dq_timing = reg; 2777 + dev_dbg(cdns_ctrl->dev, "PHY_DQ_TIMING_REG_NVDDR\t%08x\n", reg); 2778 + 2779 + reg = FIELD_PREP(PHY_DQS_TIMING_DQS_SEL_OE_END, oe_end); 2780 + reg |= FIELD_PREP(PHY_DQS_TIMING_DQS_SEL_OE_START, oe_start); 2781 + reg |= FIELD_PREP(PHY_DQS_TIMING_DQS_SEL_TSEL_END, oe_end); 2782 + t->phy_dqs_timing = reg; 2783 + dev_dbg(cdns_ctrl->dev, "PHY_DQS_TIMING_REG_NVDDR\t%08x\n", reg); 2784 + 2785 + reg = FIELD_PREP(PHY_IE_TIMING_DQS_IE_START, ie_start); 2786 + reg |= FIELD_PREP(PHY_IE_TIMING_DQ_IE_START, ie_start); 2787 + reg |= FIELD_PREP(PHY_IE_TIMING_IE_ALWAYS_ON, 0); 2788 + t->phy_ie_timing = reg; 2789 + dev_dbg(cdns_ctrl->dev, "PHY_IE_TIMING_REG_NVDDR\t%08x\n", reg); 2790 + 2791 + reg = readl_relaxed(cdns_ctrl->reg + DLL_PHY_CTRL); 2792 + reg &= ~(DLL_PHY_CTRL_DLL_RST_N | 2793 + DLL_PHY_CTRL_EXTENDED_RD_MODE | 2794 + DLL_PHY_CTRL_EXTENDED_WR_MODE); 2795 + writel_relaxed(reg, cdns_ctrl->reg + DLL_PHY_CTRL); 2796 + writel_relaxed(OPR_MODE_NVDDR, cdns_ctrl->reg + COMMON_SET); 2797 + writel_relaxed(NVDDR_TOGGLE_TIMINGS_0, 2798 + cdns_ctrl->reg + TOGGLE_TIMINGS_0); 2799 + writel_relaxed(NVDDR_TOGGLE_TIMINGS_1, 2800 + cdns_ctrl->reg + TOGGLE_TIMINGS_1); 2801 + writel_relaxed(NVDDR_ASYNC_TOGGLE_TIMINGS, 2802 + cdns_ctrl->reg + ASYNC_TOGGLE_TIMINGS); 2803 + writel_relaxed(t->sync_timings, cdns_ctrl->reg + SYNC_TIMINGS); 2804 + writel_relaxed(t->timings0, cdns_ctrl->reg + TIMINGS0); 2805 + writel_relaxed(t->timings1, cdns_ctrl->reg + TIMINGS1); 2806 + writel_relaxed(t->timings2, cdns_ctrl->reg + TIMINGS2); 2807 + writel_relaxed(t->dll_phy_ctrl, cdns_ctrl->reg + DLL_PHY_CTRL); 2808 + writel_relaxed(t->phy_ctrl, cdns_ctrl->reg + PHY_CTRL); 2809 + writel_relaxed(NVDDR_PHY_TSEL, cdns_ctrl->reg + PHY_TSEL); 2810 + writel_relaxed(t->phy_dq_timing, cdns_ctrl->reg + PHY_DQ_TIMING); 2811 + writel_relaxed(t->phy_dqs_timing, cdns_ctrl->reg + PHY_DQS_TIMING); 2812 + writel_relaxed(t->phy_gate_lpbk_ctrl, 2813 + cdns_ctrl->reg + PHY_GATE_LPBK_CTRL); 2814 + writel_relaxed(NVDDR_PHY_DLL_MASTER_CTRL, 2815 + cdns_ctrl->reg + PHY_DLL_MASTER_CTRL); 2816 + writel_relaxed(NVDDR_PHY_DLL_SLAVE_CTRL, 2817 + cdns_ctrl->reg + PHY_DLL_SLAVE_CTRL); 2818 + writel_relaxed(t->phy_ie_timing, cdns_ctrl->reg + PHY_IE_TIMING); 2819 + writel_relaxed((reg | DLL_PHY_CTRL_DLL_RST_N), 2820 + cdns_ctrl->reg + DLL_PHY_CTRL); 2821 + return 0; 2822 + } 2823 + 2824 + static int 2825 + cadence_nand_setup_interface(struct nand_chip *chip, int chipnr, 2826 + const struct nand_interface_config *conf) 2827 + { 2828 + int ret = 0; 2829 + 2830 + if (chipnr < 0) 2831 + return ret; 2832 + 2833 + if (nand_interface_is_sdr(conf)) { 2834 + const struct nand_sdr_timings *sdr = nand_get_sdr_timings(conf); 2835 + 2836 + if (IS_ERR(sdr)) 2837 + return PTR_ERR(sdr); 2838 + 2839 + ret = cadence_nand_setup_sdr_interface(chip, sdr); 2840 + } else { 2841 + const struct nand_nvddr_timings *nvddr = nand_get_nvddr_timings(conf); 2842 + 2843 + if (IS_ERR(nvddr)) 2844 + return PTR_ERR(nvddr); 2845 + 2846 + ret = cadence_nand_setup_nvddr_interface(chip, nvddr); 2847 + } 2848 + return ret; 2682 2849 } 2683 2850 2684 2851 static int cadence_nand_attach_chip(struct nand_chip *chip)
-3
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
··· 191 191 r->gpmi_regs + HW_GPMI_CTRL1_SET); 192 192 193 193 err_out: 194 - pm_runtime_mark_last_busy(this->dev); 195 194 pm_runtime_put_autosuspend(this->dev); 196 195 return ret; 197 196 } ··· 760 761 761 762 ret = 0; 762 763 err_out: 763 - pm_runtime_mark_last_busy(this->dev); 764 764 pm_runtime_put_autosuspend(this->dev); 765 765 766 766 return ret; ··· 2665 2667 this->bch = false; 2666 2668 2667 2669 out_pm: 2668 - pm_runtime_mark_last_busy(this->dev); 2669 2670 pm_runtime_put_autosuspend(this->dev); 2670 2671 2671 2672 return ret;
+1 -1
drivers/mtd/nand/raw/lpc32xx_slc.c
··· 854 854 } 855 855 856 856 /* Start with WP disabled, if available */ 857 - host->wp_gpio = gpiod_get_optional(&pdev->dev, NULL, GPIOD_OUT_LOW); 857 + host->wp_gpio = devm_gpiod_get_optional(&pdev->dev, NULL, GPIOD_OUT_LOW); 858 858 res = PTR_ERR_OR_ZERO(host->wp_gpio); 859 859 if (res) { 860 860 if (res != -EPROBE_DEFER)
+8 -5
drivers/mtd/nand/raw/marvell_nand.c
··· 290 290 MARVELL_LAYOUT( 2048, 512, 4, 1, 1, 2048, 32, 30, 0, 0, 0), 291 291 MARVELL_LAYOUT( 2048, 512, 8, 2, 1, 1024, 0, 30,1024,32, 30), 292 292 MARVELL_LAYOUT( 2048, 512, 8, 2, 1, 1024, 0, 30,1024,64, 30), 293 - MARVELL_LAYOUT( 2048, 512, 16, 4, 4, 512, 0, 30, 0, 32, 30), 293 + MARVELL_LAYOUT( 2048, 512, 12, 3, 2, 704, 0, 30,640, 0, 30), 294 + MARVELL_LAYOUT( 2048, 512, 16, 5, 4, 512, 0, 30, 0, 32, 30), 294 295 MARVELL_LAYOUT( 4096, 512, 4, 2, 2, 2048, 32, 30, 0, 0, 0), 295 - MARVELL_LAYOUT( 4096, 512, 8, 4, 4, 1024, 0, 30, 0, 64, 30), 296 - MARVELL_LAYOUT( 4096, 512, 16, 8, 8, 512, 0, 30, 0, 32, 30), 296 + MARVELL_LAYOUT( 4096, 512, 8, 5, 4, 1024, 0, 30, 0, 64, 30), 297 + MARVELL_LAYOUT( 4096, 512, 12, 6, 5, 704, 0, 30,576, 32, 30), 298 + MARVELL_LAYOUT( 4096, 512, 16, 9, 8, 512, 0, 30, 0, 32, 30), 297 299 MARVELL_LAYOUT( 8192, 512, 4, 4, 4, 2048, 0, 30, 0, 0, 0), 298 - MARVELL_LAYOUT( 8192, 512, 8, 8, 8, 1024, 0, 30, 0, 160, 30), 299 - MARVELL_LAYOUT( 8192, 512, 16, 16, 16, 512, 0, 30, 0, 32, 30), 300 + MARVELL_LAYOUT( 8192, 512, 8, 9, 8, 1024, 0, 30, 0, 160, 30), 301 + MARVELL_LAYOUT( 8192, 512, 12, 12, 11, 704, 0, 30,448, 64, 30), 302 + MARVELL_LAYOUT( 8192, 512, 16, 17, 16, 512, 0, 30, 0, 32, 30), 300 303 }; 301 304 302 305 /**
+8 -5
drivers/mtd/nand/raw/nand_base.c
··· 6338 6338 ecc->steps = mtd->writesize / ecc->size; 6339 6339 if (!base->ecc.ctx.nsteps) 6340 6340 base->ecc.ctx.nsteps = ecc->steps; 6341 - if (ecc->steps * ecc->size != mtd->writesize) { 6342 - WARN(1, "Invalid ECC parameters\n"); 6343 - ret = -EINVAL; 6344 - goto err_nand_manuf_cleanup; 6345 - } 6341 + 6342 + /* 6343 + * Validity check: Warn if ECC parameters are not compatible with page size. 6344 + * Due to the custom handling of ECC blocks in certain controllers the check 6345 + * may result in an expected failure. 6346 + */ 6347 + if (ecc->steps * ecc->size != mtd->writesize) 6348 + pr_warn("ECC parameters may be invalid in reference to underlying NAND chip\n"); 6346 6349 6347 6350 if (!ecc->total) { 6348 6351 ecc->total = ecc->steps * ecc->bytes;
+4 -1
drivers/mtd/nand/raw/renesas-nand-controller.c
··· 1336 1336 if (IS_ERR(rnandc->regs)) 1337 1337 return PTR_ERR(rnandc->regs); 1338 1338 1339 - devm_pm_runtime_enable(&pdev->dev); 1339 + ret = devm_pm_runtime_enable(&pdev->dev); 1340 + if (ret) 1341 + return ret; 1342 + 1340 1343 ret = pm_runtime_resume_and_get(&pdev->dev); 1341 1344 if (ret < 0) 1342 1345 return ret;
+338 -71
drivers/mtd/nand/raw/sunxi_nand.c
··· 29 29 #include <linux/iopoll.h> 30 30 #include <linux/reset.h> 31 31 32 + /* non compile-time field get/prep */ 33 + #undef field_get 34 + #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) 35 + #undef field_prep 36 + #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) 37 + 32 38 #define NFC_REG_CTL 0x0000 33 39 #define NFC_REG_ST 0x0004 34 40 #define NFC_REG_INT 0x0008 ··· 51 45 #define NFC_REG_A23_IO_DATA 0x0300 52 46 #define NFC_REG_ECC_CTL 0x0034 53 47 #define NFC_REG_ECC_ST 0x0038 54 - #define NFC_REG_DEBUG 0x003C 55 - #define NFC_REG_ECC_ERR_CNT(x) ((0x0040 + (x)) & ~0x3) 56 - #define NFC_REG_USER_DATA(x) (0x0050 + ((x) * 4)) 57 - #define NFC_REG_SPARE_AREA 0x00A0 58 - #define NFC_REG_PAT_ID 0x00A4 48 + #define NFC_REG_H6_PAT_FOUND 0x003C 49 + #define NFC_REG_A10_ECC_ERR_CNT 0x0040 50 + #define NFC_REG_H6_ECC_ERR_CNT 0x0050 51 + #define NFC_REG_ECC_ERR_CNT(nfc, x) ((nfc->caps->reg_ecc_err_cnt + (x)) & ~0x3) 52 + #define NFC_REG_H6_RDATA_CTL 0x0044 53 + #define NFC_REG_H6_RDATA_0 0x0048 54 + #define NFC_REG_H6_RDATA_1 0x004C 55 + #define NFC_REG_A10_USER_DATA 0x0050 56 + #define NFC_REG_H6_USER_DATA 0x0080 57 + #define NFC_REG_USER_DATA(nfc, x) (nfc->caps->reg_user_data + ((x) * 4)) 58 + #define NFC_REG_H6_USER_DATA_LEN 0x0070 59 + /* A USER_DATA_LEN register can hold the length of 8 USER_DATA registers */ 60 + #define NFC_REG_USER_DATA_LEN_CAPACITY 8 61 + #define NFC_REG_USER_DATA_LEN(nfc, step) \ 62 + (nfc->caps->reg_user_data_len + \ 63 + ((step) / NFC_REG_USER_DATA_LEN_CAPACITY) * 4) 64 + #define NFC_REG_SPARE_AREA(nfc) (nfc->caps->reg_spare_area) 65 + #define NFC_REG_A10_SPARE_AREA 0x00A0 66 + #define NFC_REG_PAT_ID(nfc) (nfc->caps->reg_pat_id) 67 + #define NFC_REG_A10_PAT_ID 0x00A4 59 68 #define NFC_REG_MDMA_ADDR 0x00C0 60 69 #define NFC_REG_MDMA_CNT 0x00C4 70 + #define NFC_REG_H6_EFNAND_STATUS 0x0110 71 + #define NFC_REG_H6_SPARE_AREA 0x0114 72 + #define NFC_REG_H6_PAT_ID 0x0118 73 + #define NFC_REG_H6_DDR2_SPEC_CTL 0x011C 74 + #define NFC_REG_H6_NDMA_MODE_CTL 0x0120 75 + #define NFC_REG_H6_MDMA_DLBA_REG 0x0200 76 + #define NFC_REG_H6_MDMA_STA 0x0204 77 + #define NFC_REG_H6_MDMA_INT_MAS 0x0208 78 + #define NFC_REG_H6_MDMA_DESC_ADDR 0x020C 79 + #define NFC_REG_H6_MDMA_BUF_ADDR 0x0210 80 + #define NFC_REG_H6_MDMA_CNT 0x0214 81 + 61 82 #define NFC_RAM0_BASE 0x0400 62 83 #define NFC_RAM1_BASE 0x0800 63 84 ··· 96 63 #define NFC_BUS_WIDTH_16 (1 << 2) 97 64 #define NFC_RB_SEL_MSK BIT(3) 98 65 #define NFC_RB_SEL(x) ((x) << 3) 66 + /* CE_SEL BIT 27 is meant to be used for GPIO chipselect */ 99 67 #define NFC_CE_SEL_MSK GENMASK(26, 24) 100 68 #define NFC_CE_SEL(x) ((x) << 24) 101 69 #define NFC_CE_CTL BIT(6) ··· 115 81 #define NFC_STA BIT(4) 116 82 #define NFC_NATCH_INT_FLAG BIT(5) 117 83 #define NFC_RB_STATE(x) BIT(x + 8) 84 + #define NFC_RB_STATE_MSK GENMASK(11, 8) 85 + #define NDFC_RDATA_STA_1 BIT(12) 86 + #define NDFC_RDATA_STA_0 BIT(13) 118 87 119 88 /* define bit use in NFC_INT */ 120 89 #define NFC_B2R_INT_ENABLE BIT(0) ··· 129 92 130 93 /* define bit use in NFC_TIMING_CTL */ 131 94 #define NFC_TIMING_CTL_EDO BIT(8) 95 + #define NFC_TIMING_CTL_E_EDO BIT(9) 132 96 133 97 /* define NFC_TIMING_CFG register layout */ 134 98 #define NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD) \ ··· 137 99 (((tWHR) & 0x3) << 4) | (((tRHW) & 0x3) << 6) | \ 138 100 (((tCAD) & 0x7) << 8)) 139 101 102 + #define NFC_TIMING_CFG2(tCDQSS, tSC, tCLHZ, tCSS, tWC) \ 103 + ((((tCDQSS) & 0x1) << 11) | (((tSC) & 0x3) << 12) | \ 104 + (((tCLHZ) & 0x3) << 14) | (((tCSS) & 0x3) << 16) | \ 105 + (((tWC) & 0x3) << 18)) 106 + 140 107 /* define bit use in NFC_CMD */ 141 108 #define NFC_CMD_LOW_BYTE_MSK GENMASK(7, 0) 142 - #define NFC_CMD_HIGH_BYTE_MSK GENMASK(15, 8) 109 + #define NFC_CMD_HIGH_BYTE_MSK GENMASK(15, 8) /* 15-10 reserved on H6 */ 110 + #define NFC_CMD_ADR_NUM_MSK GENMASK(9, 8) 143 111 #define NFC_CMD(x) (x) 144 112 #define NFC_ADR_NUM_MSK GENMASK(18, 16) 145 113 #define NFC_ADR_NUM(x) (((x) - 1) << 16) ··· 158 114 #define NFC_SEQ BIT(25) 159 115 #define NFC_DATA_SWAP_METHOD BIT(26) 160 116 #define NFC_ROW_AUTO_INC BIT(27) 117 + #define NFC_H6_SEND_RND_CMD2 BIT(27) 161 118 #define NFC_SEND_CMD3 BIT(28) 162 119 #define NFC_SEND_CMD4 BIT(29) 163 120 #define NFC_CMD_TYPE_MSK GENMASK(31, 30) ··· 170 125 #define NFC_READ_CMD_MSK GENMASK(7, 0) 171 126 #define NFC_RND_READ_CMD0_MSK GENMASK(15, 8) 172 127 #define NFC_RND_READ_CMD1_MSK GENMASK(23, 16) 128 + #define NFC_RND_READ_CMD2_MSK GENMASK(31, 24) 173 129 174 130 /* define bit use in NFC_WCMD_SET */ 175 131 #define NFC_PROGRAM_CMD_MSK GENMASK(7, 0) ··· 184 138 #define NFC_ECC_EXCEPTION BIT(4) 185 139 #define NFC_ECC_BLOCK_SIZE_MSK BIT(5) 186 140 #define NFC_ECC_BLOCK_512 BIT(5) 187 - #define NFC_RANDOM_EN BIT(9) 188 - #define NFC_RANDOM_DIRECTION BIT(10) 189 - #define NFC_ECC_MODE_MSK GENMASK(15, 12) 190 - #define NFC_ECC_MODE(x) ((x) << 12) 141 + #define NFC_RANDOM_EN(nfc) (nfc->caps->random_en_mask) 142 + #define NFC_RANDOM_DIRECTION(nfc) (nfc->caps->random_dir_mask) 143 + #define NFC_ECC_MODE_MSK(nfc) (nfc->caps->ecc_mode_mask) 144 + #define NFC_ECC_MODE(nfc, x) field_prep(NFC_ECC_MODE_MSK(nfc), (x)) 145 + /* RANDOM_PAGE_SIZE: 0: ECC block size 1: page size */ 146 + #define NFC_A23_RANDOM_PAGE_SIZE BIT(11) 147 + #define NFC_H6_RANDOM_PAGE_SIZE BIT(7) 191 148 #define NFC_RANDOM_SEED_MSK GENMASK(30, 16) 192 149 #define NFC_RANDOM_SEED(x) ((x) << 16) 193 150 194 151 /* define bit use in NFC_ECC_ST */ 195 152 #define NFC_ECC_ERR(x) BIT(x) 196 - #define NFC_ECC_ERR_MSK GENMASK(15, 0) 197 - #define NFC_ECC_PAT_FOUND(x) BIT(x + 16) 153 + #define NFC_ECC_ERR_MSK(nfc) (nfc->caps->ecc_err_mask) 154 + 155 + /* 156 + * define bit use in NFC_REG_PAT_FOUND 157 + * For A10/A23, NFC_REG_PAT_FOUND == NFC_ECC_ST register 158 + */ 159 + #define NFC_ECC_PAT_FOUND_MSK(nfc) (nfc->caps->pat_found_mask) 160 + 198 161 #define NFC_ECC_ERR_CNT(b, x) (((x) >> (((b) % 4) * 8)) & 0xff) 162 + 163 + #define NFC_USER_DATA_LEN_MSK(step) \ 164 + (0xf << (((step) % NFC_REG_USER_DATA_LEN_CAPACITY) * 4)) 199 165 200 166 #define NFC_DEFAULT_TIMEOUT_MS 1000 201 167 202 - #define NFC_SRAM_SIZE 1024 203 - 204 168 #define NFC_MAX_CS 7 169 + 170 + /* 171 + * On A10/A23, this is the size of the NDFC User Data Register, containing the 172 + * mandatory user data bytes following the ECC for each ECC step. 173 + * Thus, for each ECC step, we need the ECC bytes + USER_DATA_SZ. 174 + * Those bits are currently unsused, and kept as default value 0xffffffff. 175 + * 176 + * On H6/H616, this size became configurable, from 0 bytes to 32, via the 177 + * USER_DATA_LEN registers. 178 + */ 179 + #define USER_DATA_SZ 4 205 180 206 181 /** 207 182 * struct sunxi_nand_chip_sel - stores information related to NAND Chip Select ··· 278 211 * 279 212 * @has_mdma: Use mbus dma mode, otherwise general dma 280 213 * through MBUS on A23/A33 needs extra configuration. 214 + * @has_ecc_block_512: If the ECC can handle 512B or only 1024B chuncks 215 + * @has_ecc_clk: If the controller needs an ECC clock. 216 + * @has_mbus_clk: If the controller needs a mbus clock. 281 217 * @reg_io_data: I/O data register 218 + * @reg_ecc_err_cnt: ECC error counter register 219 + * @reg_user_data: User data register 220 + * @reg_user_data_len: User data length register 221 + * @reg_spare_area: Spare Area Register 222 + * @reg_pat_id: Pattern ID Register 223 + * @reg_pat_found: Data Pattern Status Register 224 + * @random_en_mask: RANDOM_EN mask in NFC_ECC_CTL register 225 + * @random_dir_mask: RANDOM_DIRECTION mask in NFC_ECC_CTL register 226 + * @ecc_mode_mask: ECC_MODE mask in NFC_ECC_CTL register 227 + * @ecc_err_mask: NFC_ECC_ERR mask in NFC_ECC_ST register 228 + * @pat_found_mask: ECC_PAT_FOUND mask in NFC_REG_PAT_FOUND register 282 229 * @dma_maxburst: DMA maxburst 230 + * @ecc_strengths: Available ECC strengths array 231 + * @nstrengths: Size of @ecc_strengths 232 + * @max_ecc_steps: Maximum supported steps for ECC, this is also the 233 + * number of user data registers 234 + * @user_data_len_tab: Table of lenghts supported by USER_DATA_LEN register 235 + * The table index is the value to set in NFC_USER_DATA_LEN 236 + * registers, and the corresponding value is the number of 237 + * bytes to write 238 + * @nuser_data_tab: Size of @user_data_len_tab 239 + * @sram_size: Size of the NAND controller SRAM 283 240 */ 284 241 struct sunxi_nfc_caps { 285 242 bool has_mdma; 243 + bool has_ecc_block_512; 244 + bool has_ecc_clk; 245 + bool has_mbus_clk; 286 246 unsigned int reg_io_data; 247 + unsigned int reg_ecc_err_cnt; 248 + unsigned int reg_user_data; 249 + unsigned int reg_user_data_len; 250 + unsigned int reg_spare_area; 251 + unsigned int reg_pat_id; 252 + unsigned int reg_pat_found; 253 + unsigned int random_en_mask; 254 + unsigned int random_dir_mask; 255 + unsigned int ecc_mode_mask; 256 + unsigned int ecc_err_mask; 257 + unsigned int pat_found_mask; 287 258 unsigned int dma_maxburst; 259 + const u8 *ecc_strengths; 260 + unsigned int nstrengths; 261 + const u8 *user_data_len_tab; 262 + unsigned int nuser_data_tab; 263 + unsigned int max_ecc_steps; 264 + int sram_size; 288 265 }; 289 266 290 267 /** ··· 339 228 * @regs: NAND controller registers 340 229 * @ahb_clk: NAND controller AHB clock 341 230 * @mod_clk: NAND controller mod clock 231 + * @ecc_clk: NAND controller ECC clock 232 + * @mbus_clk: NAND controller MBUS clock 342 233 * @reset: NAND controller reset line 343 234 * @assigned_cs: bitmask describing already assigned CS lines 344 235 * @clk_rate: NAND controller current clock rate ··· 356 243 void __iomem *regs; 357 244 struct clk *ahb_clk; 358 245 struct clk *mod_clk; 246 + struct clk *ecc_clk; 247 + struct clk *mbus_clk; 359 248 struct reset_control *reset; 360 249 unsigned long assigned_cs; 361 250 unsigned long clk_rate; ··· 546 431 if (sel->rb >= 0) 547 432 ctl |= NFC_RB_SEL(sel->rb); 548 433 549 - writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA); 434 + writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA(nfc)); 550 435 551 436 if (nfc->clk_rate != sunxi_nand->clk_rate) { 552 437 clk_set_rate(nfc->mod_clk, sunxi_nand->clk_rate); ··· 570 455 while (len > offs) { 571 456 bool poll = false; 572 457 573 - cnt = min(len - offs, NFC_SRAM_SIZE); 458 + cnt = min(len - offs, nfc->caps->sram_size); 574 459 575 460 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc); 576 461 if (ret) ··· 608 493 while (len > offs) { 609 494 bool poll = false; 610 495 611 - cnt = min(len - offs, NFC_SRAM_SIZE); 496 + cnt = min(len - offs, nfc->caps->sram_size); 612 497 613 498 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc); 614 499 if (ret) ··· 738 623 bool ecc) 739 624 { 740 625 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller); 741 - u32 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL); 626 + u32 ecc_ctl; 742 627 u16 state; 743 628 744 629 if (!(nand->options & NAND_NEED_SCRAMBLING)) 745 630 return; 746 631 747 - ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL); 748 632 state = sunxi_nfc_randomizer_state(nand, page, ecc); 749 633 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_SEED_MSK; 750 634 writel(ecc_ctl | NFC_RANDOM_SEED(state), nfc->regs + NFC_REG_ECC_CTL); ··· 756 642 if (!(nand->options & NAND_NEED_SCRAMBLING)) 757 643 return; 758 644 759 - writel(readl(nfc->regs + NFC_REG_ECC_CTL) | NFC_RANDOM_EN, 645 + writel(readl(nfc->regs + NFC_REG_ECC_CTL) | NFC_RANDOM_EN(nfc), 760 646 nfc->regs + NFC_REG_ECC_CTL); 761 647 } 762 648 ··· 767 653 if (!(nand->options & NAND_NEED_SCRAMBLING)) 768 654 return; 769 655 770 - writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_EN, 656 + writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_EN(nfc), 771 657 nfc->regs + NFC_REG_ECC_CTL); 772 658 } 773 659 ··· 831 717 { 832 718 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller); 833 719 834 - sunxi_nfc_user_data_to_buf(readl(nfc->regs + NFC_REG_USER_DATA(step)), 835 - oob); 720 + sunxi_nfc_user_data_to_buf(readl(nfc->regs + NFC_REG_USER_DATA(nfc, step)), oob); 836 721 837 722 /* De-randomize the Bad Block Marker. */ 838 723 if (bbm && (nand->options & NAND_NEED_SCRAMBLING)) 839 724 sunxi_nfc_randomize_bbm(nand, page, oob); 725 + } 726 + 727 + /* 728 + * On H6/H6 the user_data length has to be set in specific registers 729 + * before writing. 730 + */ 731 + static void sunxi_nfc_reset_user_data_len(struct sunxi_nfc *nfc) 732 + { 733 + int loop_step = NFC_REG_USER_DATA_LEN_CAPACITY; 734 + 735 + /* not all SoCs have this register */ 736 + if (!nfc->caps->reg_user_data_len) 737 + return; 738 + 739 + for (int i = 0; i < nfc->caps->max_ecc_steps; i += loop_step) 740 + writel(0, nfc->regs + NFC_REG_USER_DATA_LEN(nfc, i)); 741 + } 742 + 743 + static void sunxi_nfc_set_user_data_len(struct sunxi_nfc *nfc, 744 + int len, int step) 745 + { 746 + bool found = false; 747 + u32 val; 748 + int i; 749 + 750 + /* not all SoCs have this register */ 751 + if (!nfc->caps->reg_user_data_len) 752 + return; 753 + 754 + for (i = 0; i < nfc->caps->nuser_data_tab; i++) { 755 + if (len == nfc->caps->user_data_len_tab[i]) { 756 + found = true; 757 + break; 758 + } 759 + } 760 + 761 + if (!found) { 762 + dev_warn(nfc->dev, 763 + "Unsupported length for user data reg: %d\n", len); 764 + return; 765 + } 766 + 767 + val = readl(nfc->regs + NFC_REG_USER_DATA_LEN(nfc, step)); 768 + 769 + val &= ~NFC_USER_DATA_LEN_MSK(step); 770 + val |= field_prep(NFC_USER_DATA_LEN_MSK(step), i); 771 + writel(val, nfc->regs + NFC_REG_USER_DATA_LEN(nfc, step)); 840 772 } 841 773 842 774 static void sunxi_nfc_hw_ecc_set_prot_oob_bytes(struct nand_chip *nand, ··· 890 730 bool bbm, int page) 891 731 { 892 732 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller); 893 - u8 user_data[4]; 733 + u8 user_data[USER_DATA_SZ]; 894 734 895 735 /* Randomize the Bad Block Marker. */ 896 736 if (bbm && (nand->options & NAND_NEED_SCRAMBLING)) { ··· 900 740 } 901 741 902 742 writel(sunxi_nfc_buf_to_user_data(oob), 903 - nfc->regs + NFC_REG_USER_DATA(step)); 743 + nfc->regs + NFC_REG_USER_DATA(nfc, step)); 904 744 } 905 745 906 746 static void sunxi_nfc_hw_ecc_update_stats(struct nand_chip *nand, ··· 917 757 } 918 758 919 759 static int sunxi_nfc_hw_ecc_correct(struct nand_chip *nand, u8 *data, u8 *oob, 920 - int step, u32 status, bool *erased) 760 + int step, u32 status, u32 pattern_found, 761 + bool *erased) 921 762 { 922 763 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller); 923 764 struct nand_ecc_ctrl *ecc = &nand->ecc; ··· 929 768 if (status & NFC_ECC_ERR(step)) 930 769 return -EBADMSG; 931 770 932 - if (status & NFC_ECC_PAT_FOUND(step)) { 771 + if (pattern_found & BIT(step)) { 933 772 u8 pattern; 934 773 935 - if (unlikely(!(readl(nfc->regs + NFC_REG_PAT_ID) & 0x1))) { 774 + if (unlikely(!(readl(nfc->regs + NFC_REG_PAT_ID(nfc)) & 0x1))) { 936 775 pattern = 0x0; 937 776 } else { 938 777 pattern = 0xff; ··· 943 782 memset(data, pattern, ecc->size); 944 783 945 784 if (oob) 946 - memset(oob, pattern, ecc->bytes + 4); 785 + memset(oob, pattern, ecc->bytes + USER_DATA_SZ); 947 786 948 787 return 0; 949 788 } 950 789 951 - tmp = readl(nfc->regs + NFC_REG_ECC_ERR_CNT(step)); 790 + tmp = readl(nfc->regs + NFC_REG_ECC_ERR_CNT(nfc, step)); 952 791 953 792 return NFC_ECC_ERR_CNT(step, tmp); 954 793 } ··· 963 802 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller); 964 803 struct nand_ecc_ctrl *ecc = &nand->ecc; 965 804 int raw_mode = 0; 805 + u32 pattern_found; 966 806 bool erased; 967 807 int ret; 968 808 ··· 979 817 if (ret) 980 818 return ret; 981 819 820 + sunxi_nfc_reset_user_data_len(nfc); 821 + sunxi_nfc_set_user_data_len(nfc, USER_DATA_SZ, 0); 982 822 sunxi_nfc_randomizer_config(nand, page, false); 983 823 sunxi_nfc_randomizer_enable(nand); 984 824 writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ECC_OP, ··· 991 827 if (ret) 992 828 return ret; 993 829 994 - *cur_off = oob_off + ecc->bytes + 4; 830 + *cur_off = oob_off + ecc->bytes + USER_DATA_SZ; 831 + 832 + pattern_found = readl(nfc->regs + nfc->caps->reg_pat_found); 833 + pattern_found = field_get(NFC_ECC_PAT_FOUND_MSK(nfc), pattern_found); 995 834 996 835 ret = sunxi_nfc_hw_ecc_correct(nand, data, oob_required ? oob : NULL, 0, 997 836 readl(nfc->regs + NFC_REG_ECC_ST), 837 + pattern_found, 998 838 &erased); 999 839 if (erased) 1000 840 return 1; ··· 1015 847 memcpy_fromio(data, nfc->regs + NFC_RAM0_BASE, 1016 848 ecc->size); 1017 849 1018 - nand_change_read_column_op(nand, oob_off, oob, ecc->bytes + 4, 1019 - false); 850 + nand_change_read_column_op(nand, oob_off, oob, 851 + ecc->bytes + USER_DATA_SZ, false); 1020 852 1021 - ret = nand_check_erased_ecc_chunk(data, ecc->size, 1022 - oob, ecc->bytes + 4, 853 + ret = nand_check_erased_ecc_chunk(data, ecc->size, oob, 854 + ecc->bytes + USER_DATA_SZ, 1023 855 NULL, 0, ecc->strength); 1024 856 if (ret >= 0) 1025 857 raw_mode = 1; ··· 1029 861 if (oob_required) { 1030 862 nand_change_read_column_op(nand, oob_off, NULL, 0, 1031 863 false); 1032 - sunxi_nfc_randomizer_read_buf(nand, oob, ecc->bytes + 4, 864 + sunxi_nfc_randomizer_read_buf(nand, oob, ecc->bytes + USER_DATA_SZ, 1033 865 true, page); 1034 866 1035 867 sunxi_nfc_hw_ecc_get_prot_oob_bytes(nand, oob, 0, ··· 1079 911 unsigned int max_bitflips = 0; 1080 912 int ret, i, raw_mode = 0; 1081 913 struct scatterlist sg; 1082 - u32 status, wait; 914 + u32 status, pattern_found, wait; 1083 915 1084 916 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc); 1085 917 if (ret) ··· 1091 923 return ret; 1092 924 1093 925 sunxi_nfc_hw_ecc_enable(nand); 926 + sunxi_nfc_reset_user_data_len(nfc); 927 + sunxi_nfc_set_user_data_len(nfc, USER_DATA_SZ, 0); 1094 928 sunxi_nfc_randomizer_config(nand, page, false); 1095 929 sunxi_nfc_randomizer_enable(nand); 1096 930 ··· 1122 952 return ret; 1123 953 1124 954 status = readl(nfc->regs + NFC_REG_ECC_ST); 955 + pattern_found = readl(nfc->regs + nfc->caps->reg_pat_found); 956 + pattern_found = field_get(NFC_ECC_PAT_FOUND_MSK(nfc), pattern_found); 1125 957 1126 958 for (i = 0; i < nchunks; i++) { 1127 959 int data_off = i * ecc->size; 1128 - int oob_off = i * (ecc->bytes + 4); 960 + int oob_off = i * (ecc->bytes + USER_DATA_SZ); 1129 961 u8 *data = buf + data_off; 1130 962 u8 *oob = nand->oob_poi + oob_off; 1131 963 bool erased; 1132 964 1133 965 ret = sunxi_nfc_hw_ecc_correct(nand, randomized ? data : NULL, 1134 966 oob_required ? oob : NULL, 1135 - i, status, &erased); 967 + i, status, pattern_found, 968 + &erased); 1136 969 1137 970 /* ECC errors are handled in the second loop. */ 1138 971 if (ret < 0) ··· 1145 972 /* TODO: use DMA to retrieve OOB */ 1146 973 nand_change_read_column_op(nand, 1147 974 mtd->writesize + oob_off, 1148 - oob, ecc->bytes + 4, false); 975 + oob, ecc->bytes + USER_DATA_SZ, false); 1149 976 1150 977 sunxi_nfc_hw_ecc_get_prot_oob_bytes(nand, oob, i, 1151 978 !i, page); ··· 1157 984 sunxi_nfc_hw_ecc_update_stats(nand, &max_bitflips, ret); 1158 985 } 1159 986 1160 - if (status & NFC_ECC_ERR_MSK) { 987 + if (status & NFC_ECC_ERR_MSK(nfc)) { 1161 988 for (i = 0; i < nchunks; i++) { 1162 989 int data_off = i * ecc->size; 1163 - int oob_off = i * (ecc->bytes + 4); 990 + int oob_off = i * (ecc->bytes + USER_DATA_SZ); 1164 991 u8 *data = buf + data_off; 1165 992 u8 *oob = nand->oob_poi + oob_off; 1166 993 ··· 1180 1007 /* TODO: use DMA to retrieve OOB */ 1181 1008 nand_change_read_column_op(nand, 1182 1009 mtd->writesize + oob_off, 1183 - oob, ecc->bytes + 4, false); 1010 + oob, ecc->bytes + USER_DATA_SZ, false); 1184 1011 1185 - ret = nand_check_erased_ecc_chunk(data, ecc->size, 1186 - oob, ecc->bytes + 4, 1012 + ret = nand_check_erased_ecc_chunk(data, ecc->size, oob, 1013 + ecc->bytes + USER_DATA_SZ, 1187 1014 NULL, 0, 1188 1015 ecc->strength); 1189 1016 if (ret >= 0) ··· 1225 1052 1226 1053 sunxi_nfc_randomizer_config(nand, page, false); 1227 1054 sunxi_nfc_randomizer_enable(nand); 1055 + sunxi_nfc_reset_user_data_len(nfc); 1056 + sunxi_nfc_set_user_data_len(nfc, USER_DATA_SZ, 0); 1228 1057 sunxi_nfc_hw_ecc_set_prot_oob_bytes(nand, oob, 0, bbm, page); 1229 1058 1230 1059 writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | ··· 1238 1063 if (ret) 1239 1064 return ret; 1240 1065 1241 - *cur_off = oob_off + ecc->bytes + 4; 1066 + *cur_off = oob_off + ecc->bytes + USER_DATA_SZ; 1242 1067 1243 1068 return 0; 1244 1069 } ··· 1249 1074 { 1250 1075 struct mtd_info *mtd = nand_to_mtd(nand); 1251 1076 struct nand_ecc_ctrl *ecc = &nand->ecc; 1252 - int offset = ((ecc->bytes + 4) * ecc->steps); 1077 + int offset = ((ecc->bytes + USER_DATA_SZ) * ecc->steps); 1253 1078 int len = mtd->oobsize - offset; 1254 1079 1255 1080 if (len <= 0) ··· 1282 1107 1283 1108 for (i = 0; i < ecc->steps; i++) { 1284 1109 int data_off = i * ecc->size; 1285 - int oob_off = i * (ecc->bytes + 4); 1110 + int oob_off = i * (ecc->bytes + USER_DATA_SZ); 1286 1111 u8 *data = buf + data_off; 1287 1112 u8 *oob = nand->oob_poi + oob_off; 1288 1113 ··· 1341 1166 for (i = data_offs / ecc->size; 1342 1167 i < DIV_ROUND_UP(data_offs + readlen, ecc->size); i++) { 1343 1168 int data_off = i * ecc->size; 1344 - int oob_off = i * (ecc->bytes + 4); 1169 + int oob_off = i * (ecc->bytes + USER_DATA_SZ); 1345 1170 u8 *data = bufpoi + data_off; 1346 1171 u8 *oob = nand->oob_poi + oob_off; 1347 1172 ··· 1395 1220 1396 1221 for (i = 0; i < ecc->steps; i++) { 1397 1222 int data_off = i * ecc->size; 1398 - int oob_off = i * (ecc->bytes + 4); 1223 + int oob_off = i * (ecc->bytes + USER_DATA_SZ); 1399 1224 const u8 *data = buf + data_off; 1400 1225 const u8 *oob = nand->oob_poi + oob_off; 1401 1226 ··· 1433 1258 for (i = data_offs / ecc->size; 1434 1259 i < DIV_ROUND_UP(data_offs + data_len, ecc->size); i++) { 1435 1260 int data_off = i * ecc->size; 1436 - int oob_off = i * (ecc->bytes + 4); 1261 + int oob_off = i * (ecc->bytes + USER_DATA_SZ); 1437 1262 const u8 *data = buf + data_off; 1438 1263 const u8 *oob = nand->oob_poi + oob_off; 1439 1264 ··· 1471 1296 if (ret) 1472 1297 goto pio_fallback; 1473 1298 1299 + sunxi_nfc_reset_user_data_len(nfc); 1474 1300 for (i = 0; i < ecc->steps; i++) { 1475 - const u8 *oob = nand->oob_poi + (i * (ecc->bytes + 4)); 1301 + const u8 *oob = nand->oob_poi + (i * (ecc->bytes + USER_DATA_SZ)); 1476 1302 1477 1303 sunxi_nfc_hw_ecc_set_prot_oob_bytes(nand, oob, i, !i, page); 1304 + sunxi_nfc_set_user_data_len(nfc, USER_DATA_SZ, i); 1478 1305 } 1479 1306 1480 1307 nand_prog_page_begin_op(nand, page, 0, NULL, 0); ··· 1744 1567 if (section >= ecc->steps) 1745 1568 return -ERANGE; 1746 1569 1747 - oobregion->offset = section * (ecc->bytes + 4) + 4; 1570 + oobregion->offset = section * (ecc->bytes + USER_DATA_SZ) + 4; 1748 1571 oobregion->length = ecc->bytes; 1749 1572 1750 1573 return 0; ··· 1778 1601 if (section == ecc->steps && ecc->engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) 1779 1602 return -ERANGE; 1780 1603 1781 - oobregion->offset = section * (ecc->bytes + 4); 1604 + oobregion->offset = section * (ecc->bytes + USER_DATA_SZ); 1782 1605 1783 1606 if (section < ecc->steps) 1784 - oobregion->length = 4; 1607 + oobregion->length = USER_DATA_SZ; 1785 1608 else 1786 1609 oobregion->length = mtd->oobsize - oobregion->offset; 1787 1610 ··· 1797 1620 struct nand_ecc_ctrl *ecc, 1798 1621 struct device_node *np) 1799 1622 { 1800 - static const u8 strengths[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 }; 1801 1623 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand); 1802 1624 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller); 1625 + const u8 *strengths = nfc->caps->ecc_strengths; 1803 1626 struct mtd_info *mtd = nand_to_mtd(nand); 1804 1627 struct nand_device *nanddev = mtd_to_nanddev(mtd); 1805 1628 int nsectors; ··· 1815 1638 bytes = (mtd->oobsize - 2) / nsectors; 1816 1639 1817 1640 /* 4 non-ECC bytes are added before each ECC bytes section */ 1818 - bytes -= 4; 1641 + bytes -= USER_DATA_SZ; 1819 1642 1820 1643 /* and bytes has to be even. */ 1821 1644 if (bytes % 2) ··· 1823 1646 1824 1647 ecc->strength = bytes * 8 / fls(8 * ecc->size); 1825 1648 1826 - for (i = 0; i < ARRAY_SIZE(strengths); i++) { 1649 + for (i = 0; i < nfc->caps->nstrengths; i++) { 1827 1650 if (strengths[i] > ecc->strength) 1828 1651 break; 1829 1652 } ··· 1844 1667 } 1845 1668 1846 1669 /* Add ECC info retrieval from DT */ 1847 - for (i = 0; i < ARRAY_SIZE(strengths); i++) { 1670 + for (i = 0; i < nfc->caps->nstrengths; i++) { 1848 1671 if (ecc->strength <= strengths[i]) { 1849 1672 /* 1850 1673 * Update ecc->strength value with the actual strength ··· 1855 1678 } 1856 1679 } 1857 1680 1858 - if (i >= ARRAY_SIZE(strengths)) { 1681 + if (i >= nfc->caps->nstrengths) { 1859 1682 dev_err(nfc->dev, "unsupported strength\n"); 1860 1683 return -ENOTSUPP; 1861 1684 } ··· 1868 1691 1869 1692 nsectors = mtd->writesize / ecc->size; 1870 1693 1871 - if (mtd->oobsize < ((ecc->bytes + 4) * nsectors)) 1694 + if (mtd->oobsize < ((ecc->bytes + USER_DATA_SZ) * nsectors)) 1872 1695 return -EINVAL; 1873 1696 1874 1697 ecc->read_oob = sunxi_nfc_hw_ecc_read_oob; ··· 1891 1714 ecc->read_oob_raw = nand_read_oob_std; 1892 1715 ecc->write_oob_raw = nand_write_oob_std; 1893 1716 1894 - sunxi_nand->ecc.ecc_ctl = NFC_ECC_MODE(i) | NFC_ECC_EXCEPTION | 1717 + sunxi_nand->ecc.ecc_ctl = NFC_ECC_MODE(nfc, i) | NFC_ECC_EXCEPTION | 1895 1718 NFC_ECC_PIPELINE | NFC_ECC_EN; 1896 1719 1897 - if (ecc->size == 512) 1898 - sunxi_nand->ecc.ecc_ctl |= NFC_ECC_BLOCK_512; 1720 + if (ecc->size == 512) { 1721 + if (nfc->caps->has_ecc_block_512) { 1722 + sunxi_nand->ecc.ecc_ctl |= NFC_ECC_BLOCK_512; 1723 + } else { 1724 + dev_err(nfc->dev, "512B ECC block not supported\n"); 1725 + return -EOPNOTSUPP; 1726 + } 1727 + } 1899 1728 1900 1729 return 0; 1901 1730 } ··· 1990 1807 case NAND_OP_DATA_OUT_INSTR: 1991 1808 start = nand_subop_get_data_start_off(subop, i); 1992 1809 remaining = nand_subop_get_data_len(subop, i); 1993 - cnt = min_t(u32, remaining, NFC_SRAM_SIZE); 1810 + cnt = min_t(u32, remaining, nfc->caps->sram_size); 1994 1811 cmd |= NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD; 1995 1812 1996 1813 if (instr->type == NAND_OP_DATA_OUT_INSTR) { ··· 2277 2094 if (irq < 0) 2278 2095 return irq; 2279 2096 2097 + nfc->caps = of_device_get_match_data(dev); 2098 + if (!nfc->caps) 2099 + return -EINVAL; 2100 + 2280 2101 nfc->ahb_clk = devm_clk_get_enabled(dev, "ahb"); 2281 2102 if (IS_ERR(nfc->ahb_clk)) { 2282 2103 dev_err(dev, "failed to retrieve ahb clk\n"); ··· 2293 2106 return PTR_ERR(nfc->mod_clk); 2294 2107 } 2295 2108 2109 + if (nfc->caps->has_ecc_clk) { 2110 + nfc->ecc_clk = devm_clk_get_enabled(dev, "ecc"); 2111 + if (IS_ERR(nfc->ecc_clk)) { 2112 + dev_err(dev, "failed to retrieve ecc clk\n"); 2113 + return PTR_ERR(nfc->ecc_clk); 2114 + } 2115 + } 2116 + 2117 + if (nfc->caps->has_mbus_clk) { 2118 + nfc->mbus_clk = devm_clk_get_enabled(dev, "mbus"); 2119 + if (IS_ERR(nfc->mbus_clk)) { 2120 + dev_err(dev, "failed to retrieve mbus clk\n"); 2121 + return PTR_ERR(nfc->mbus_clk); 2122 + } 2123 + } 2124 + 2296 2125 nfc->reset = devm_reset_control_get_optional_exclusive(dev, "ahb"); 2297 2126 if (IS_ERR(nfc->reset)) 2298 2127 return PTR_ERR(nfc->reset); ··· 2317 2114 if (ret) { 2318 2115 dev_err(dev, "reset err %d\n", ret); 2319 2116 return ret; 2320 - } 2321 - 2322 - nfc->caps = of_device_get_match_data(&pdev->dev); 2323 - if (!nfc->caps) { 2324 - ret = -EINVAL; 2325 - goto out_ahb_reset_reassert; 2326 2117 } 2327 2118 2328 2119 ret = sunxi_nfc_rst(nfc); ··· 2365 2168 dma_release_channel(nfc->dmac); 2366 2169 } 2367 2170 2171 + static const u8 sunxi_ecc_strengths_a10[] = { 2172 + 16, 24, 28, 32, 40, 48, 56, 60, 64 2173 + }; 2174 + 2175 + static const u8 sunxi_ecc_strengths_h6[] = { 2176 + 16, 24, 28, 32, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80 2177 + }; 2178 + 2179 + static const u8 sunxi_user_data_len_h6[] = { 2180 + 0, 4, 8, 12, 16, 20, 24, 28, 32 2181 + }; 2182 + 2368 2183 static const struct sunxi_nfc_caps sunxi_nfc_a10_caps = { 2184 + .has_ecc_block_512 = true, 2369 2185 .reg_io_data = NFC_REG_A10_IO_DATA, 2186 + .reg_ecc_err_cnt = NFC_REG_A10_ECC_ERR_CNT, 2187 + .reg_user_data = NFC_REG_A10_USER_DATA, 2188 + .reg_spare_area = NFC_REG_A10_SPARE_AREA, 2189 + .reg_pat_id = NFC_REG_A10_PAT_ID, 2190 + .reg_pat_found = NFC_REG_ECC_ST, 2191 + .random_en_mask = BIT(9), 2192 + .random_dir_mask = BIT(10), 2193 + .ecc_mode_mask = GENMASK(15, 12), 2194 + .ecc_err_mask = GENMASK(15, 0), 2195 + .pat_found_mask = GENMASK(31, 16), 2370 2196 .dma_maxburst = 4, 2197 + .ecc_strengths = sunxi_ecc_strengths_a10, 2198 + .nstrengths = ARRAY_SIZE(sunxi_ecc_strengths_a10), 2199 + .max_ecc_steps = 16, 2200 + .sram_size = 1024, 2371 2201 }; 2372 2202 2373 2203 static const struct sunxi_nfc_caps sunxi_nfc_a23_caps = { 2374 2204 .has_mdma = true, 2205 + .has_ecc_block_512 = true, 2375 2206 .reg_io_data = NFC_REG_A23_IO_DATA, 2207 + .reg_ecc_err_cnt = NFC_REG_A10_ECC_ERR_CNT, 2208 + .reg_user_data = NFC_REG_A10_USER_DATA, 2209 + .reg_spare_area = NFC_REG_A10_SPARE_AREA, 2210 + .reg_pat_id = NFC_REG_A10_PAT_ID, 2211 + .reg_pat_found = NFC_REG_ECC_ST, 2212 + .random_en_mask = BIT(9), 2213 + .random_dir_mask = BIT(10), 2214 + .ecc_mode_mask = GENMASK(15, 12), 2215 + .ecc_err_mask = GENMASK(15, 0), 2216 + .pat_found_mask = GENMASK(31, 16), 2376 2217 .dma_maxburst = 8, 2218 + .ecc_strengths = sunxi_ecc_strengths_a10, 2219 + .nstrengths = ARRAY_SIZE(sunxi_ecc_strengths_a10), 2220 + .max_ecc_steps = 16, 2221 + .sram_size = 1024, 2222 + }; 2223 + 2224 + static const struct sunxi_nfc_caps sunxi_nfc_h616_caps = { 2225 + .has_ecc_clk = true, 2226 + .has_mbus_clk = true, 2227 + .reg_io_data = NFC_REG_A23_IO_DATA, 2228 + .reg_ecc_err_cnt = NFC_REG_H6_ECC_ERR_CNT, 2229 + .reg_user_data = NFC_REG_H6_USER_DATA, 2230 + .reg_user_data_len = NFC_REG_H6_USER_DATA_LEN, 2231 + .reg_spare_area = NFC_REG_H6_SPARE_AREA, 2232 + .reg_pat_id = NFC_REG_H6_PAT_ID, 2233 + .reg_pat_found = NFC_REG_H6_PAT_FOUND, 2234 + .random_en_mask = BIT(5), 2235 + .random_dir_mask = BIT(6), 2236 + .ecc_mode_mask = GENMASK(15, 8), 2237 + .ecc_err_mask = GENMASK(31, 0), 2238 + .pat_found_mask = GENMASK(31, 0), 2239 + .dma_maxburst = 8, 2240 + .ecc_strengths = sunxi_ecc_strengths_h6, 2241 + .nstrengths = ARRAY_SIZE(sunxi_ecc_strengths_h6), 2242 + .user_data_len_tab = sunxi_user_data_len_h6, 2243 + .nuser_data_tab = ARRAY_SIZE(sunxi_user_data_len_h6), 2244 + .max_ecc_steps = 32, 2245 + .sram_size = 8192, 2377 2246 }; 2378 2247 2379 2248 static const struct of_device_id sunxi_nfc_ids[] = { ··· 2450 2187 { 2451 2188 .compatible = "allwinner,sun8i-a23-nand-controller", 2452 2189 .data = &sunxi_nfc_a23_caps, 2190 + }, 2191 + { 2192 + .compatible = "allwinner,sun50i-h616-nand-controller", 2193 + .data = &sunxi_nfc_h616_caps, 2453 2194 }, 2454 2195 { /* sentinel */ } 2455 2196 };
+1
drivers/mtd/nand/spi/core.c
··· 1227 1227 static const struct spinand_manufacturer *spinand_manufacturers[] = { 1228 1228 &alliancememory_spinand_manufacturer, 1229 1229 &ato_spinand_manufacturer, 1230 + &esmt_8c_spinand_manufacturer, 1230 1231 &esmt_c8_spinand_manufacturer, 1231 1232 &fmsh_spinand_manufacturer, 1232 1233 &foresee_spinand_manufacturer,
+24
drivers/mtd/nand/spi/esmt.c
··· 12 12 13 13 /* ESMT uses GigaDevice 0xc8 JECDEC ID on some SPI NANDs */ 14 14 #define SPINAND_MFR_ESMT_C8 0xc8 15 + #define SPINAND_MFR_ESMT_8C 0x8c 15 16 16 17 #define ESMT_F50L1G41LB_CFG_OTP_PROTECT BIT(7) 17 18 #define ESMT_F50L1G41LB_CFG_OTP_LOCK \ ··· 185 184 .read = spinand_fact_otp_read, 186 185 }; 187 186 187 + 188 + static const struct spinand_info esmt_8c_spinand_table[] = { 189 + SPINAND_INFO("F50L1G41LC", 190 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x2C), 191 + NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), 192 + NAND_ECCREQ(1, 512), 193 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 194 + &write_cache_variants, 195 + &update_cache_variants), 196 + 0, 197 + SPINAND_ECCINFO(&f50l1g41lb_ooblayout, NULL), 198 + SPINAND_USER_OTP_INFO(28, 2, &f50l1g41lb_user_otp_ops), 199 + SPINAND_FACT_OTP_INFO(2, 0, &f50l1g41lb_fact_otp_ops)), 200 + }; 201 + 188 202 static const struct spinand_info esmt_c8_spinand_table[] = { 189 203 SPINAND_INFO("F50L1G41LB", 190 204 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x01, 0x7f, ··· 238 222 }; 239 223 240 224 static const struct spinand_manufacturer_ops esmt_spinand_manuf_ops = { 225 + }; 226 + 227 + const struct spinand_manufacturer esmt_8c_spinand_manufacturer = { 228 + .id = SPINAND_MFR_ESMT_8C, 229 + .name = "ESMT", 230 + .chips = esmt_8c_spinand_table, 231 + .nchips = ARRAY_SIZE(esmt_8c_spinand_table), 232 + .ops = &esmt_spinand_manuf_ops, 241 233 }; 242 234 243 235 const struct spinand_manufacturer esmt_c8_spinand_manufacturer = {
+72
drivers/mtd/nand/spi/fmsh.c
··· 9 9 #include <linux/kernel.h> 10 10 #include <linux/mtd/spinand.h> 11 11 12 + #define FM25S01BI3_STATUS_ECC_MASK (7 << 4) 13 + #define FM25S01BI3_STATUS_ECC_NO_BITFLIPS (0 << 4) 14 + #define FM25S01BI3_STATUS_ECC_1_3_BITFLIPS (1 << 4) 15 + #define FM25S01BI3_STATUS_ECC_UNCOR_ERROR (2 << 4) 16 + #define FM25S01BI3_STATUS_ECC_4_6_BITFLIPS (3 << 4) 17 + #define FM25S01BI3_STATUS_ECC_7_8_BITFLIPS (5 << 4) 18 + 12 19 #define SPINAND_MFR_FMSH 0xA1 13 20 14 21 static SPINAND_OP_VARIANTS(read_cache_variants, ··· 52 45 return 0; 53 46 } 54 47 48 + static int fm25s01bi3_ecc_get_status(struct spinand_device *spinand, 49 + u8 status) 50 + { 51 + switch (status & FM25S01BI3_STATUS_ECC_MASK) { 52 + case FM25S01BI3_STATUS_ECC_NO_BITFLIPS: 53 + return 0; 54 + 55 + case FM25S01BI3_STATUS_ECC_UNCOR_ERROR: 56 + return -EBADMSG; 57 + 58 + case FM25S01BI3_STATUS_ECC_1_3_BITFLIPS: 59 + return 3; 60 + 61 + case FM25S01BI3_STATUS_ECC_4_6_BITFLIPS: 62 + return 6; 63 + 64 + case FM25S01BI3_STATUS_ECC_7_8_BITFLIPS: 65 + return 8; 66 + 67 + default: 68 + break; 69 + } 70 + 71 + return -EINVAL; 72 + } 73 + 74 + static int fm25s01bi3_ooblayout_ecc(struct mtd_info *mtd, int section, 75 + struct mtd_oob_region *region) 76 + { 77 + if (section) 78 + return -ERANGE; 79 + 80 + region->offset = 64; 81 + region->length = 64; 82 + 83 + return 0; 84 + } 85 + 86 + static int fm25s01bi3_ooblayout_free(struct mtd_info *mtd, int section, 87 + struct mtd_oob_region *region) 88 + { 89 + if (section > 3) 90 + return -ERANGE; 91 + 92 + region->offset = (16 * section) + 4; 93 + region->length = 12; 94 + 95 + return 0; 96 + } 97 + 55 98 static const struct mtd_ooblayout_ops fm25s01a_ooblayout = { 56 99 .ecc = fm25s01a_ooblayout_ecc, 57 100 .free = fm25s01a_ooblayout_free, 101 + }; 102 + 103 + static const struct mtd_ooblayout_ops fm25s01bi3_ooblayout = { 104 + .ecc = fm25s01bi3_ooblayout_ecc, 105 + .free = fm25s01bi3_ooblayout_free, 58 106 }; 59 107 60 108 static const struct spinand_info fmsh_spinand_table[] = { ··· 122 60 &update_cache_variants), 123 61 SPINAND_HAS_QE_BIT, 124 62 SPINAND_ECCINFO(&fm25s01a_ooblayout, NULL)), 63 + SPINAND_INFO("FM25S01BI3", 64 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xd4), 65 + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), 66 + NAND_ECCREQ(8, 512), 67 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 68 + &write_cache_variants, 69 + &update_cache_variants), 70 + SPINAND_HAS_QE_BIT, 71 + SPINAND_ECCINFO(&fm25s01bi3_ooblayout, 72 + fm25s01bi3_ecc_get_status)), 125 73 }; 126 74 127 75 static const struct spinand_manufacturer_ops fmsh_spinand_manuf_ops = {
+1
include/linux/mtd/spinand.h
··· 354 354 /* SPI NAND manufacturers */ 355 355 extern const struct spinand_manufacturer alliancememory_spinand_manufacturer; 356 356 extern const struct spinand_manufacturer ato_spinand_manufacturer; 357 + extern const struct spinand_manufacturer esmt_8c_spinand_manufacturer; 357 358 extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer; 358 359 extern const struct spinand_manufacturer fmsh_spinand_manufacturer; 359 360 extern const struct spinand_manufacturer foresee_spinand_manufacturer;