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clk: qcom: gcc-sc8180x: Add GPLL9 support

Add the missing GPLL9 pll and fix the gcc_parents_7 data to use
the correct pll hw.

Fixes: 4433594bbe5d ("clk: qcom: gcc: Add global clock controller driver for SC8180x")
Cc: stable@vger.kernel.org
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Link: https://lore.kernel.org/r/20240812-gcc-sc8180x-fixes-v2-3-8b3eaa5fb856@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Satya Priya Kakitapalli and committed by
Bjorn Andersson 818a2f8d 648b4bde

+19 -1
+19 -1
drivers/clk/qcom/gcc-sc8180x.c
··· 142 142 }, 143 143 }; 144 144 145 + static struct clk_alpha_pll gpll9 = { 146 + .offset = 0x1c000, 147 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION], 148 + .clkr = { 149 + .enable_reg = 0x52000, 150 + .enable_mask = BIT(9), 151 + .hw.init = &(const struct clk_init_data) { 152 + .name = "gpll9", 153 + .parent_data = &(const struct clk_parent_data) { 154 + .fw_name = "bi_tcxo", 155 + }, 156 + .num_parents = 1, 157 + .ops = &clk_alpha_pll_fixed_trion_ops, 158 + }, 159 + }, 160 + }; 161 + 145 162 static const struct parent_map gcc_parent_map_0[] = { 146 163 { P_BI_TCXO, 0 }, 147 164 { P_GPLL0_OUT_MAIN, 1 }, ··· 258 241 static const struct clk_parent_data gcc_parents_7[] = { 259 242 { .fw_name = "bi_tcxo", }, 260 243 { .hw = &gpll0.clkr.hw }, 261 - { .name = "gppl9" }, 244 + { .hw = &gpll9.clkr.hw }, 262 245 { .hw = &gpll4.clkr.hw }, 263 246 { .hw = &gpll0_out_even.clkr.hw }, 264 247 }; ··· 4569 4552 [GPLL1] = &gpll1.clkr, 4570 4553 [GPLL4] = &gpll4.clkr, 4571 4554 [GPLL7] = &gpll7.clkr, 4555 + [GPLL9] = &gpll9.clkr, 4572 4556 }; 4573 4557 4574 4558 static const struct qcom_reset_map gcc_sc8180x_resets[] = {