dt-bindings: phy: google: Add Google Tensor G5 USB PHY

Document the device tree bindings for the USB PHY interfaces integrated
with the DWC3 controller on Google Tensor SoCs, starting with G5
generation (Laguna). The USB PHY on Tensor G5 includes two integrated
Synopsys PHY IPs: the eUSB 2.0 PHY IP and the USB 3.2/DisplayPort combo
PHY IP.

Due to a complete architectural overhaul in the Google Tensor G5, the
existing Samsung/Exynos USB PHY binding for older generations of Google
silicons such as gs101 are no longer compatible, necessitating this new
device tree binding.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Roy Luo <royluo@google.com>
Link: https://patch.msgid.link/20251227-phyb4-v10-1-e8caf6b93fe7@google.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Roy Luo and committed by

Vinod Koul 4 months ago 876dc58c f1674131

+134

2 changed files

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Documentation

devicetree

bindings

phy

google,lga-usb-phy.yaml

MAINTAINERS

+133

Documentation/devicetree/bindings/phy/google,lga-usb-phy.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + # Copyright (C) 2025, Google LLC 3 + %YAML 1.2 4 + --- 5 + $id: http://devicetree.org/schemas/phy/google,lga-usb-phy.yaml# 6 + $schema: http://devicetree.org/meta-schemas/core.yaml# 7 + 8 + title: Google Tensor Series G5 (Laguna) USB PHY 9 + 10 + maintainers: 11 + - Roy Luo <royluo@google.com> 12 + 13 + description: 14 + Describes the USB PHY interfaces integrated with the DWC3 USB controller on 15 + Google Tensor SoCs, starting with the G5 generation (laguna). 16 + Two specific PHY IPs from Synopsys are integrated, including eUSB 2.0 PHY IP 17 + and USB3.2/DisplayPort combo PHY IP. 18 + 19 + properties: 20 + compatible: 21 + const: google,lga-usb-phy 22 + 23 + reg: 24 + items: 25 + - description: USB3.2/DisplayPort combo PHY core registers. 26 + - description: USB3.2/DisplayPort combo PHY Type-C Assist registers. 27 + - description: eUSB 2.0 PHY core registers. 28 + - description: Top-level wrapper registers for the integrated PHYs. 29 + 30 + reg-names: 31 + items: 32 + - const: usb3_core 33 + - const: usb3_tca 34 + - const: usb2_core 35 + - const: usbdp_top 36 + 37 + "#phy-cells": 38 + description: | 39 + The phandle's argument in the PHY specifier selects one of the three 40 + following PHY interfaces. 41 + - 0 for USB high-speed. 42 + - 1 for USB super-speed. 43 + - 2 for DisplayPort. 44 + const: 1 45 + 46 + clocks: 47 + items: 48 + - description: USB2 PHY clock. 49 + - description: USB2 PHY APB clock. 50 + - description: USB3.2/DisplayPort combo PHY clock. 51 + - description: USB3.2/DisplayPort combo PHY firmware clock. 52 + 53 + clock-names: 54 + items: 55 + - const: usb2 56 + - const: usb2_apb 57 + - const: usb3 58 + - const: usb3_fw 59 + 60 + resets: 61 + items: 62 + - description: USB2 PHY reset. 63 + - description: USB2 PHY APB reset. 64 + - description: USB3.2/DisplayPort combo PHY reset. 65 + 66 + reset-names: 67 + items: 68 + - const: usb2 69 + - const: usb2_apb 70 + - const: usb3 71 + 72 + power-domains: 73 + maxItems: 1 74 + 75 + orientation-switch: 76 + type: boolean 77 + description: 78 + Indicates the PHY as a handler of USB Type-C orientation changes 79 + 80 + google,usb-cfg-csr: 81 + description: 82 + A phandle to a syscon node used to access the USB configuration 83 + registers. These registers are the top-level wrapper of the USB 84 + subsystem and provide control and status for the integrated USB 85 + controller and USB PHY. 86 + $ref: /schemas/types.yaml#/definitions/phandle-array 87 + items: 88 + - items: 89 + - description: phandle to the syscon node. 90 + - description: USB2 PHY configuration register offset. 91 + 92 + required: 93 + - compatible 94 + - reg 95 + - reg-names 96 + - "#phy-cells" 97 + - clocks 98 + - clock-names 99 + - resets 100 + - reset-names 101 + - power-domains 102 + - orientation-switch 103 + - google,usb-cfg-csr 104 + 105 + additionalProperties: false 106 + 107 + examples: 108 + - | 109 + soc { 110 + #address-cells = <2>; 111 + #size-cells = <2>; 112 + 113 + usb-phy@c410000 { 114 + compatible = "google,lga-usb-phy"; 115 + reg = <0 0x0c410000 0 0x20000>, 116 + <0 0x0c430000 0 0x1000>, 117 + <0 0x0c440000 0 0x10000>, 118 + <0 0x0c637000 0 0xa0>; 119 + reg-names = "usb3_core", "usb3_tca", "usb2_core", "usbdp_top"; 120 + #phy-cells = <1>; 121 + clocks = <&hsion_usb2_phy_clk>, <&hsion_u2phy_apb_clk>, 122 + <&hsion_usb3_phy_clk>, <&hsion_usb3_phy_fw_clk>; 123 + clock-names = "usb2", "usb2_apb", "usb3", "usb3_fw"; 124 + resets = <&hsion_resets_usb2_phy>, 125 + <&hsion_resets_u2phy_apb>, 126 + <&hsion_resets_usb3_phy>; 127 + reset-names = "usb2", "usb2_apb", "usb3"; 128 + power-domains = <&hsio_n_usb_pd>; 129 + orientation-switch; 130 + google,usb-cfg-csr = <&usb_cfg_csr 0x14>; 131 + }; 132 + }; 133 + ...

MAINTAINERS

··· 10723 10723 P: Documentation/process/maintainer-soc-clean-dts.rst 10724 10724 C: irc://irc.oftc.net/pixel6-kernel-dev 10725 10725 F: Documentation/devicetree/bindings/clock/google,gs101-clock.yaml 10726 + F: Documentation/devicetree/bindings/phy/google,lga-usb-phy.yaml 10726 10727 F: Documentation/devicetree/bindings/soc/google/google,gs101-pmu-intr-gen.yaml 10727 10728 F: arch/arm64/boot/dts/exynos/google/ 10728 10729 F: drivers/clk/samsung/clk-gs101.c

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