Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
dt-bindings: pwm: Convert PWM bindings to json-schema
Convert generic PWM controller bindings to DT schema format using
json-schema. The consumer bindings are provided by dt-schema.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Paul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: Rob Herring <robh@kernel.org>
authored by
Krzysztof Kozlowski
and committed by
Rob Herring
89650a1e
d6a62a4b
+68
-48
+1
-1
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt
+1
-1
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt
···
21
21
- #gpio-cells : Should be two. The first cell is the pin number and
22
22
the second cell is used to specify flags.
23
23
See ../../gpio/gpio.txt for more information.
24
-
- #pwm-cells : Should be one. See ../../pwm/pwm.txt for description of
24
+
- #pwm-cells : Should be one. See ../../pwm/pwm.yaml for description of
25
25
the cell formats.
26
26
27
27
- clock-names: should be "refclk"
+1
-1
Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt
+1
-1
Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt
···
10
10
- pinctrl-0: should contain the pinctrl states described by pinctrl
11
11
default.
12
12
- #pwm-cells: should be set to 3. This PWM chip use the default 3 cells
13
-
bindings defined in pwm.txt in this directory.
13
+
bindings defined in pwm.yaml in this directory.
14
14
15
15
Example:
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16
+1
-1
Documentation/devicetree/bindings/pwm/atmel-pwm.txt
+1
-1
Documentation/devicetree/bindings/pwm/atmel-pwm.txt
···
7
7
- "atmel,sama5d2-pwm"
8
8
- "microchip,sam9x60-pwm"
9
9
- reg: physical base address and length of the controller's registers
10
-
- #pwm-cells: Should be 3. See pwm.txt in this directory for a
10
+
- #pwm-cells: Should be 3. See pwm.yaml in this directory for a
11
11
description of the cells format.
12
12
13
13
Example:
+1
-1
Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt
+1
-1
Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt
···
2
2
3
3
Required properties:
4
4
- compatible: should be "atmel,tcb-pwm"
5
-
- #pwm-cells: should be 3. See pwm.txt in this directory for a description of
5
+
- #pwm-cells: should be 3. See pwm.yaml in this directory for a description of
6
6
the cells format. The only third cell flag supported by this binding is
7
7
PWM_POLARITY_INVERTED.
8
8
- tc-block: The Timer Counter block to use as a PWM chip.
+1
-1
Documentation/devicetree/bindings/pwm/brcm,bcm7038-pwm.txt
+1
-1
Documentation/devicetree/bindings/pwm/brcm,bcm7038-pwm.txt
···
4
4
5
5
- compatible: must be "brcm,bcm7038-pwm"
6
6
- reg: physical base address and length for this controller
7
-
- #pwm-cells: should be 2. See pwm.txt in this directory for a description
7
+
- #pwm-cells: should be 2. See pwm.yaml in this directory for a description
8
8
of the cells format
9
9
- clocks: a phandle to the reference clock for this block which is fed through
10
10
its internal variable clock frequency generator
+1
-1
Documentation/devicetree/bindings/pwm/brcm,iproc-pwm.txt
+1
-1
Documentation/devicetree/bindings/pwm/brcm,iproc-pwm.txt
···
6
6
- compatible: must be "brcm,iproc-pwm"
7
7
- reg: physical base address and length of the controller's registers
8
8
- clocks: phandle + clock specifier pair for the external clock
9
-
- #pwm-cells: Should be 3. See pwm.txt in this directory for a
9
+
- #pwm-cells: Should be 3. See pwm.yaml in this directory for a
10
10
description of the cells format.
11
11
12
12
Refer to clocks/clock-bindings.txt for generic clock consumer properties.
+1
-1
Documentation/devicetree/bindings/pwm/brcm,kona-pwm.txt
+1
-1
Documentation/devicetree/bindings/pwm/brcm,kona-pwm.txt
···
6
6
- compatible: should contain "brcm,kona-pwm"
7
7
- reg: physical base address and length of the controller's registers
8
8
- clocks: phandle + clock specifier pair for the external clock
9
-
- #pwm-cells: Should be 3. See pwm.txt in this directory for a
9
+
- #pwm-cells: Should be 3. See pwm.yaml in this directory for a
10
10
description of the cells format.
11
11
12
12
Refer to clocks/clock-bindings.txt for generic clock consumer properties.
+1
-1
Documentation/devicetree/bindings/pwm/img-pwm.txt
+1
-1
Documentation/devicetree/bindings/pwm/img-pwm.txt
···
8
8
- clock-names: Must include the following entries.
9
9
- pwm: PWM operating clock.
10
10
- sys: PWM system interface clock.
11
-
- #pwm-cells: Should be 2. See pwm.txt in this directory for the
11
+
- #pwm-cells: Should be 2. See pwm.yaml in this directory for the
12
12
description of the cells format.
13
13
- img,cr-periph: Must contain a phandle to the peripheral control
14
14
syscon node which contains PWM control registers.
+1
-1
Documentation/devicetree/bindings/pwm/imx-pwm.txt
+1
-1
Documentation/devicetree/bindings/pwm/imx-pwm.txt
···
6
6
- "fsl,imx1-pwm" for PWM compatible with the one integrated on i.MX1
7
7
- "fsl,imx27-pwm" for PWM compatible with the one integrated on i.MX27
8
8
- reg: physical base address and length of the controller's registers
9
-
- #pwm-cells: 2 for i.MX1 and 3 for i.MX27 and newer SoCs. See pwm.txt
9
+
- #pwm-cells: 2 for i.MX1 and 3 for i.MX27 and newer SoCs. See pwm.yaml
10
10
in this directory for a description of the cells format.
11
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- clocks : Clock specifiers for both ipg and per clocks.
12
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- clock-names : Clock names should include both "ipg" and "per"
+1
-1
Documentation/devicetree/bindings/pwm/imx-tpm-pwm.txt
+1
-1
Documentation/devicetree/bindings/pwm/imx-tpm-pwm.txt
···
3
3
Required properties:
4
4
- compatible : Should be "fsl,imx7ulp-pwm".
5
5
- reg: Physical base address and length of the controller's registers.
6
-
- #pwm-cells: Should be 3. See pwm.txt in this directory for a description of the cells format.
6
+
- #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of the cells format.
7
7
- clocks : The clock provided by the SoC to drive the PWM.
8
8
- interrupts: The interrupt for the PWM controller.
9
9
+1
-1
Documentation/devicetree/bindings/pwm/lpc1850-sct-pwm.txt
+1
-1
Documentation/devicetree/bindings/pwm/lpc1850-sct-pwm.txt
···
7
7
See ../clock/clock-bindings.txt for details.
8
8
- clock-names: Must include the following entries.
9
9
- pwm: PWM operating clock.
10
-
- #pwm-cells: Should be 3. See pwm.txt in this directory for the description
10
+
- #pwm-cells: Should be 3. See pwm.yaml in this directory for the description
11
11
of the cells format.
12
12
13
13
Example:
+1
-1
Documentation/devicetree/bindings/pwm/mxs-pwm.txt
+1
-1
Documentation/devicetree/bindings/pwm/mxs-pwm.txt
···
3
3
Required properties:
4
4
- compatible: should be "fsl,imx23-pwm"
5
5
- reg: physical base address and length of the controller's registers
6
-
- #pwm-cells: should be 2. See pwm.txt in this directory for a description of
6
+
- #pwm-cells: should be 2. See pwm.yaml in this directory for a description of
7
7
the cells format.
8
8
- fsl,pwm-number: the number of PWM devices
9
9
+1
-1
Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
+1
-1
Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
···
10
10
- "nvidia,tegra210-pwm", "nvidia,tegra20-pwm": for Tegra210
11
11
- "nvidia,tegra186-pwm": for Tegra186
12
12
- reg: physical base address and length of the controller's registers
13
-
- #pwm-cells: should be 2. See pwm.txt in this directory for a description of
13
+
- #pwm-cells: should be 2. See pwm.yaml in this directory for a description of
14
14
the cells format.
15
15
- clocks: Must contain one entry, for the module clock.
16
16
See ../clocks/clock-bindings.txt for details.
+1
-1
Documentation/devicetree/bindings/pwm/nxp,pca9685-pwm.txt
+1
-1
Documentation/devicetree/bindings/pwm/nxp,pca9685-pwm.txt
···
3
3
4
4
Required properties:
5
5
- compatible: "nxp,pca9685-pwm"
6
-
- #pwm-cells: Should be 2. See pwm.txt in this directory for a description of
6
+
- #pwm-cells: Should be 2. See pwm.yaml in this directory for a description of
7
7
the cells format.
8
8
The index 16 is the ALLCALL channel, that sets all PWM channels at the same
9
9
time.
+1
-1
Documentation/devicetree/bindings/pwm/pwm-bcm2835.txt
+1
-1
Documentation/devicetree/bindings/pwm/pwm-bcm2835.txt
···
6
6
- clocks: This clock defines the base clock frequency of the PWM hardware
7
7
system, the period and the duty_cycle of the PWM signal is a multiple of
8
8
the base period.
9
-
- #pwm-cells: Should be 3. See pwm.txt in this directory for a description of
9
+
- #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
10
10
the cells format.
11
11
12
12
Examples:
+1
-1
Documentation/devicetree/bindings/pwm/pwm-berlin.txt
+1
-1
Documentation/devicetree/bindings/pwm/pwm-berlin.txt
···
4
4
- compatible: should be "marvell,berlin-pwm"
5
5
- reg: physical base address and length of the controller's registers
6
6
- clocks: phandle to the input clock
7
-
- #pwm-cells: should be 3. See pwm.txt in this directory for a description of
7
+
- #pwm-cells: should be 3. See pwm.yaml in this directory for a description of
8
8
the cells format.
9
9
10
10
Example:
+1
-1
Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt
+1
-1
Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt
···
21
21
- "fsl,vf610-ftm-pwm" for PWM compatible with the one integrated on VF610
22
22
- "fsl,imx8qm-ftm-pwm" for PWM compatible with the one integrated on i.MX8QM
23
23
- reg: Physical base address and length of the controller's registers
24
-
- #pwm-cells: Should be 3. See pwm.txt in this directory for a description of
24
+
- #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
25
25
the cells format.
26
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- clock-names: Should include the following module clock source entries:
27
27
"ftm_sys" (module clock, also can be used as counter clock),
+1
-1
Documentation/devicetree/bindings/pwm/pwm-hibvt.txt
+1
-1
Documentation/devicetree/bindings/pwm/pwm-hibvt.txt
···
10
10
- reg: physical base address and length of the controller's registers.
11
11
- clocks: phandle and clock specifier of the PWM reference clock.
12
12
- resets: phandle and reset specifier for the PWM controller reset.
13
-
- #pwm-cells: Should be 3. See pwm.txt in this directory for a description of
13
+
- #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
14
14
the cells format.
15
15
16
16
Example:
+1
-1
Documentation/devicetree/bindings/pwm/pwm-lp3943.txt
+1
-1
Documentation/devicetree/bindings/pwm/pwm-lp3943.txt
···
2
2
3
3
Required properties:
4
4
- compatible: "ti,lp3943-pwm"
5
-
- #pwm-cells: Should be 2. See pwm.txt in this directory for a
5
+
- #pwm-cells: Should be 2. See pwm.yaml in this directory for a
6
6
description of the cells format.
7
7
Note that this hardware limits the period length to the
8
8
range 6250~1600000.
+1
-1
Documentation/devicetree/bindings/pwm/pwm-mediatek.txt
+1
-1
Documentation/devicetree/bindings/pwm/pwm-mediatek.txt
···
9
9
- "mediatek,mt7629-pwm", "mediatek,mt7622-pwm": found on mt7629 SoC.
10
10
- "mediatek,mt8516-pwm": found on mt8516 SoC.
11
11
- reg: physical base address and length of the controller's registers.
12
-
- #pwm-cells: must be 2. See pwm.txt in this directory for a description of
12
+
- #pwm-cells: must be 2. See pwm.yaml in this directory for a description of
13
13
the cell format.
14
14
- clocks: phandle and clock specifier of the PWM reference clock.
15
15
- clock-names: must contain the following, except for MT7628 which
+1
-1
Documentation/devicetree/bindings/pwm/pwm-meson.txt
+1
-1
Documentation/devicetree/bindings/pwm/pwm-meson.txt
···
10
10
or "amlogic,meson-g12a-ee-pwm"
11
11
or "amlogic,meson-g12a-ao-pwm-ab"
12
12
or "amlogic,meson-g12a-ao-pwm-cd"
13
-
- #pwm-cells: Should be 3. See pwm.txt in this directory for a description of
13
+
- #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
14
14
the cells format.
15
15
16
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Optional properties:
+1
-1
Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt
+1
-1
Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt
···
6
6
- "mediatek,mt6595-disp-pwm": found on mt6595 SoC.
7
7
- "mediatek,mt8173-disp-pwm": found on mt8173 SoC.
8
8
- reg: physical base address and length of the controller's registers.
9
-
- #pwm-cells: must be 2. See pwm.txt in this directory for a description of
9
+
- #pwm-cells: must be 2. See pwm.yaml in this directory for a description of
10
10
the cell format.
11
11
- clocks: phandle and clock specifier of the PWM reference clock.
12
12
- clock-names: must contain the following:
+1
-1
Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt
+1
-1
Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt
···
4
4
- compatible: Shall contain "ti,omap-dmtimer-pwm".
5
5
- ti,timers: phandle to PWM capable OMAP timer. See timer/ti,timer.txt for info
6
6
about these timers.
7
-
- #pwm-cells: Should be 3. See pwm.txt in this directory for a description of
7
+
- #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
8
8
the cells format.
9
9
10
10
Optional properties:
+1
-1
Documentation/devicetree/bindings/pwm/pwm-rockchip.txt
+1
-1
Documentation/devicetree/bindings/pwm/pwm-rockchip.txt
···
14
14
- For newer hardware (rk3328 and future socs): specified by name
15
15
- "pwm": This is used to derive the functional clock.
16
16
- "pclk": This is the APB bus clock.
17
-
- #pwm-cells: must be 2 (rk2928) or 3 (rk3288). See pwm.txt in this directory
17
+
- #pwm-cells: must be 2 (rk2928) or 3 (rk3288). See pwm.yaml in this directory
18
18
for a description of the cell format.
19
19
20
20
Example:
+1
-1
Documentation/devicetree/bindings/pwm/pwm-sifive.txt
+1
-1
Documentation/devicetree/bindings/pwm/pwm-sifive.txt
···
17
17
Please refer to sifive-blocks-ip-versioning.txt for details.
18
18
- reg: physical base address and length of the controller's registers
19
19
- clocks: Should contain a clock identifier for the PWM's parent clock.
20
-
- #pwm-cells: Should be 3. See pwm.txt in this directory
20
+
- #pwm-cells: Should be 3. See pwm.yaml in this directory
21
21
for a description of the cell format.
22
22
- interrupts: one interrupt per PWM channel
23
23
+1
-1
Documentation/devicetree/bindings/pwm/pwm-sprd.txt
+1
-1
Documentation/devicetree/bindings/pwm/pwm-sprd.txt
···
9
9
- clock-names: Should contain following entries:
10
10
"pwmn": used to derive the functional clock for PWM channel n (n range: 0 ~ 3).
11
11
"enablen": for PWM channel n enable clock (n range: 0 ~ 3).
12
-
- #pwm-cells: Should be 2. See pwm.txt in this directory for a description of
12
+
- #pwm-cells: Should be 2. See pwm.yaml in this directory for a description of
13
13
the cells format.
14
14
15
15
Optional properties:
+1
-1
Documentation/devicetree/bindings/pwm/pwm-stm32-lp.txt
+1
-1
Documentation/devicetree/bindings/pwm/pwm-stm32-lp.txt
···
8
8
Required parameters:
9
9
- compatible: Must be "st,stm32-pwm-lp".
10
10
- #pwm-cells: Should be set to 3. This PWM chip uses the default 3 cells
11
-
bindings defined in pwm.txt.
11
+
bindings defined in pwm.yaml.
12
12
13
13
Optional properties:
14
14
- pinctrl-names: Set to "default". An additional "sleep" state can be
+1
-1
Documentation/devicetree/bindings/pwm/pwm-tiecap.txt
+1
-1
Documentation/devicetree/bindings/pwm/pwm-tiecap.txt
···
8
8
for dra746 - compatible = "ti,dra746-ecap", "ti,am3352-ecap";
9
9
for 66ak2g - compatible = "ti,k2g-ecap", "ti,am3352-ecap";
10
10
for am654 - compatible = "ti,am654-ecap", "ti,am3352-ecap";
11
-
- #pwm-cells: should be 3. See pwm.txt in this directory for a description of
11
+
- #pwm-cells: should be 3. See pwm.yaml in this directory for a description of
12
12
the cells format. The PWM channel index ranges from 0 to 4. The only third
13
13
cell flag supported by this binding is PWM_POLARITY_INVERTED.
14
14
- reg: physical base address and size of the registers map.
+1
-1
Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt
+1
-1
Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt
···
7
7
for am654 - compatible = "ti,am654-ehrpwm", "ti-am3352-ehrpwm";
8
8
for da850 - compatible = "ti,da850-ehrpwm", "ti-am3352-ehrpwm", "ti,am33xx-ehrpwm";
9
9
for dra746 - compatible = "ti,dra746-ehrpwm", "ti-am3352-ehrpwm";
10
-
- #pwm-cells: should be 3. See pwm.txt in this directory for a description of
10
+
- #pwm-cells: should be 3. See pwm.yaml in this directory for a description of
11
11
the cells format. The only third cell flag supported by this binding is
12
12
PWM_POLARITY_INVERTED.
13
13
- reg: physical base address and size of the registers map.
+1
-1
Documentation/devicetree/bindings/pwm/pwm-zx.txt
+1
-1
Documentation/devicetree/bindings/pwm/pwm-zx.txt
···
7
7
- clock-names: "pclk" for PCLK, "wclk" for WCLK to the PWM controller. The
8
8
PCLK is for register access, while WCLK is the reference clock for
9
9
calculating period and duty cycles.
10
-
- #pwm-cells: Should be 3. See pwm.txt in this directory for a description of
10
+
- #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
11
11
the cells format.
12
12
13
13
Example:
+1
-10
Documentation/devicetree/bindings/pwm/pwm.txt
+1
-10
Documentation/devicetree/bindings/pwm/pwm.txt
···
57
57
2) PWM controller nodes
58
58
-----------------------
59
59
60
-
PWM controller nodes must specify the number of cells used for the
61
-
specifier using the '#pwm-cells' property.
62
-
63
-
An example PWM controller might look like this:
64
-
65
-
pwm: pwm@7000a000 {
66
-
compatible = "nvidia,tegra20-pwm";
67
-
reg = <0x7000a000 0x100>;
68
-
#pwm-cells = <2>;
69
-
};
60
+
See pwm.yaml.
+29
Documentation/devicetree/bindings/pwm/pwm.yaml
+29
Documentation/devicetree/bindings/pwm/pwm.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pwm/pwm.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: PWM controllers (providers)
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
12
+
properties:
13
+
$nodename:
14
+
pattern: "^pwm(@.*|-[0-9a-f])*$"
15
+
16
+
"#pwm-cells":
17
+
description:
18
+
Number of cells in a PWM specifier.
19
+
20
+
required:
21
+
- "#pwm-cells"
22
+
23
+
examples:
24
+
- |
25
+
pwm: pwm@7000a000 {
26
+
compatible = "nvidia,tegra20-pwm";
27
+
reg = <0x7000a000 0x100>;
28
+
#pwm-cells = <2>;
29
+
};
+1
-1
Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.yaml
+1
-1
Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.yaml
+1
-1
Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml
+1
-1
Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml
···
35
35
maxItems: 1
36
36
37
37
'#pwm-cells':
38
-
# should be 3. See pwm.txt in this directory for a description of
38
+
# should be 3. See pwm.yaml in this directory for a description of
39
39
# the cells format. The only third cell flag supported by this binding is
40
40
# PWM_POLARITY_INVERTED.
41
41
const: 3
+1
-1
Documentation/devicetree/bindings/pwm/spear-pwm.txt
+1
-1
Documentation/devicetree/bindings/pwm/spear-pwm.txt
···
5
5
- "st,spear320-pwm"
6
6
- "st,spear1340-pwm"
7
7
- reg: physical base address and length of the controller's registers
8
-
- #pwm-cells: should be 2. See pwm.txt in this directory for a description of
8
+
- #pwm-cells: should be 2. See pwm.yaml in this directory for a description of
9
9
the cells format.
10
10
11
11
Example:
+1
-1
Documentation/devicetree/bindings/pwm/st,stmpe-pwm.txt
+1
-1
Documentation/devicetree/bindings/pwm/st,stmpe-pwm.txt
+1
-1
Documentation/devicetree/bindings/pwm/ti,twl-pwm.txt
+1
-1
Documentation/devicetree/bindings/pwm/ti,twl-pwm.txt
+1
-1
Documentation/devicetree/bindings/pwm/ti,twl-pwmled.txt
+1
-1
Documentation/devicetree/bindings/pwm/ti,twl-pwmled.txt
···
6
6
7
7
Required properties:
8
8
- compatible: "ti,twl4030-pwmled" or "ti,twl6030-pwmled"
9
-
- #pwm-cells: should be 2. See pwm.txt in this directory for a description of
9
+
- #pwm-cells: should be 2. See pwm.yaml in this directory for a description of
10
10
the cells format.
11
11
12
12
Example:
+1
-1
Documentation/devicetree/bindings/pwm/vt8500-pwm.txt
+1
-1
Documentation/devicetree/bindings/pwm/vt8500-pwm.txt
···
3
3
Required properties:
4
4
- compatible: should be "via,vt8500-pwm"
5
5
- reg: physical base address and length of the controller's registers
6
-
- #pwm-cells: should be 3. See pwm.txt in this directory for a description of
6
+
- #pwm-cells: should be 3. See pwm.yaml in this directory for a description of
7
7
the cells format. The only third cell flag supported by this binding is
8
8
PWM_POLARITY_INVERTED.
9
9
- clocks: phandle to the PWM source clock
+1
-1
Documentation/devicetree/bindings/timer/ingenic,tcu.txt
+1
-1
Documentation/devicetree/bindings/timer/ingenic,tcu.txt
···
42
42
- compatible: Must be one of:
43
43
* ingenic,jz4740-pwm
44
44
* ingenic,jz4725b-pwm
45
-
- #pwm-cells: Should be 3. See ../pwm/pwm.txt for a description of the cell
45
+
- #pwm-cells: Should be 3. See ../pwm/pwm.yaml for a description of the cell
46
46
format.
47
47
- clocks: List of phandle & clock specifiers for the TCU clocks.
48
48
- clock-names: List of name strings for the TCU clocks.