+5

Documentation/devicetree/bindings/.yamllint

reviewed

··· 1 1 extends: relaxed 2 2 3 3 rules: 4 4 + quoted-strings: 5 5 + required: only-when-needed 6 6 + extra-allowed: 7 7 + - '[$^,[]' 8 8 + - '^/$' 4 9 line-length: 5 10 # 80 chars should be enough, but don't fail if a line is longer 6 11 max: 110

+1 -1

Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 # Copyright 2019 Linaro Ltd. 3 3 %YAML 1.2 4 4 ---

+1 -1

Documentation/devicetree/bindings/arm/arm,coresight-dummy-sink.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/arm/arm,coresight-dummy-sink.yaml#

+1 -1

Documentation/devicetree/bindings/arm/arm,coresight-dummy-source.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/arm/arm,coresight-dummy-source.yaml#

+3 -3

Documentation/devicetree/bindings/arm/arm,embedded-trace-extension.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 # Copyright 2021, Arm Ltd 3 3 %YAML 1.2 4 4 --- 5 5 - $id: "http://devicetree.org/schemas/arm/arm,embedded-trace-extension.yaml#" 6 6 - $schema: "http://devicetree.org/meta-schemas/core.yaml#" 5 5 + $id: http://devicetree.org/schemas/arm/arm,embedded-trace-extension.yaml# 6 6 + $schema: http://devicetree.org/meta-schemas/core.yaml# 7 7 8 8 title: ARM Embedded Trace Extensions 9 9

+5 -4

Documentation/devicetree/bindings/arm/arm,trace-buffer-extension.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 # Copyright 2021, Arm Ltd 3 3 %YAML 1.2 4 4 --- 5 5 - $id: "http://devicetree.org/schemas/arm/arm,trace-buffer-extension.yaml#" 6 6 - $schema: "http://devicetree.org/meta-schemas/core.yaml#" 5 5 + $id: http://devicetree.org/schemas/arm/arm,trace-buffer-extension.yaml# 6 6 + $schema: http://devicetree.org/meta-schemas/core.yaml# 7 7 8 8 title: ARM Trace Buffer Extensions 9 9 ··· 19 19 20 20 properties: 21 21 $nodename: 22 22 - const: "trbe" 22 22 + const: trbe 23 23 + 23 24 compatible: 24 25 items: 25 26 - const: arm,trace-buffer-extension

+1 -1

Documentation/devicetree/bindings/arm/arm,versatile-sysreg.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/arm/arm,versatile-sysreg.yaml#

+1 -1

Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml

reviewed

··· 143 143 "simple-bus". If the compatible is placed in the "motherboard-bus" node, 144 144 it is stricter and always has two compatibles. 145 145 type: object 146 146 - $ref: '/schemas/simple-bus.yaml' 146 146 + $ref: /schemas/simple-bus.yaml 147 147 unevaluatedProperties: false 148 148 149 149 properties:

+2 -2

Documentation/devicetree/bindings/arm/aspeed/aspeed,sbc.yaml

reviewed

··· 2 2 # Copyright 2021 Joel Stanley, IBM Corp. 3 3 %YAML 1.2 4 4 --- 5 5 - $id: "http://devicetree.org/schemas/arm/aspeed/aspeed,sbc.yaml#" 6 6 - $schema: "http://devicetree.org/meta-schemas/core.yaml#" 5 5 + $id: http://devicetree.org/schemas/arm/aspeed/aspeed,sbc.yaml# 6 6 + $schema: http://devicetree.org/meta-schemas/core.yaml# 7 7 8 8 title: ASPEED Secure Boot Controller 9 9

+1 -1

Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/arm/aspeed/aspeed.yaml#

+3

Documentation/devicetree/bindings/arm/cpus.yaml

reviewed

··· 143 143 - arm,cortex-a78ae 144 144 - arm,cortex-a78c 145 145 - arm,cortex-a510 146 146 + - arm,cortex-a520 146 147 - arm,cortex-a710 147 148 - arm,cortex-a715 149 149 + - arm,cortex-a720 148 150 - arm,cortex-m0 149 151 - arm,cortex-m0+ 150 152 - arm,cortex-m1 ··· 160 158 - arm,cortex-x1c 161 159 - arm,cortex-x2 162 160 - arm,cortex-x3 161 161 + - arm,cortex-x4 163 162 - arm,neoverse-e1 164 163 - arm,neoverse-n1 165 164 - arm,neoverse-n2

+2 -2

Documentation/devicetree/bindings/arm/firmware/tlm,trusted-foundations.yaml

reviewed

··· 1 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 - $id: "http://devicetree.org/schemas/arm/firmware/tlm,trusted-foundations.yaml#" 5 5 - $schema: "http://devicetree.org/meta-schemas/core.yaml#" 4 4 + $id: http://devicetree.org/schemas/arm/firmware/tlm,trusted-foundations.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 7 title: Trusted Foundations 8 8

+2 -2

Documentation/devicetree/bindings/arm/fsl.yaml

reviewed

··· 1257 1257 - description: 1258 1258 Freescale Vybrid Platform Device Tree Bindings 1259 1259 1260 1260 - For the Vybrid SoC familiy all variants with DDR controller are supported, 1260 1260 + For the Vybrid SoC family all variants with DDR controller are supported, 1261 1261 which is the VF5xx and VF6xx series. Out of historical reasons, in most 1262 1262 - places the kernel uses vf610 to refer to the whole familiy. 1262 1262 + places the kernel uses vf610 to refer to the whole family. 1263 1263 The compatible string "fsl,vf610m4" is used for the secondary Cortex-M4 1264 1264 core support. 1265 1265 items:

+1 -1

Documentation/devicetree/bindings/arm/keystone/ti,k3-sci-common.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/arm/keystone/ti,k3-sci-common.yaml#

+1 -1

Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/arm/keystone/ti,sci.yaml#

+4 -4

Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt

reviewed

··· 21 21 number of clocks: 22 22 23 23 - a set of core clocks 24 24 - - a set of gatable clocks 24 24 + - a set of gateable clocks 25 25 26 26 Those clocks can be referenced by other Device Tree nodes using two 27 27 cells: 28 28 - The first cell must be 0 or 1. 0 for the core clocks and 1 for the 29 29 - gatable clocks. 30 30 - - The second cell identifies the particular core clock or gatable 29 29 + gateable clocks. 30 30 + - The second cell identifies the particular core clock or gateable 31 31 clocks. 32 32 33 33 The following clocks are available: ··· 38 38 - 0 3 Core 39 39 - 0 4 NAND core 40 40 - 0 5 SDIO core 41 41 - - Gatable clocks 41 41 + - Gateable clocks 42 42 - 1 0 Audio 43 43 - 1 1 Comm Unit 44 44 - 1 2 NAND

+1 -1

Documentation/devicetree/bindings/arm/mediatek/mediatek,mipi0a.txt

reviewed

··· 16 16 17 17 The mipi0a controller also uses the common power domain from 18 18 Documentation/devicetree/bindings/soc/mediatek/scpsys.txt 19 19 - The available power doamins are defined in dt-bindings/power/mt*-power.h. 19 19 + The available power domains are defined in dt-bindings/power/mt*-power.h. 20 20 21 21 Example: 22 22

+1 -1

Documentation/devicetree/bindings/arm/mediatek/mediatek,vcodecsys.txt

reviewed

··· 15 15 16 16 The vcodecsys controller also uses the common power domain from 17 17 Documentation/devicetree/bindings/soc/mediatek/scpsys.txt 18 18 - The available power doamins are defined in dt-bindings/power/mt*-power.h. 18 18 + The available power domains are defined in dt-bindings/power/mt*-power.h. 19 19 20 20 Example: 21 21

-18

Documentation/devicetree/bindings/arm/msm/ssbi.txt

reviewed

··· 1 1 - * Qualcomm SSBI 2 2 - 3 3 - Some Qualcomm MSM devices contain a point-to-point serial bus used to 4 4 - communicate with a limited range of devices (mostly power management 5 5 - chips). 6 6 - 7 7 - These require the following properties: 8 8 - 9 9 - - compatible: "qcom,ssbi" 10 10 - 11 11 - - qcom,controller-type 12 12 - indicates the SSBI bus variant the controller should use to talk 13 13 - with the slave device. This should be one of "ssbi", "ssbi2", or 14 14 - "pmic-arbiter". The type chosen is determined by the attached 15 15 - slave. 16 16 - 17 17 - The slave device should be the single child node of the ssbi device 18 18 - with a compatible field.

+2 -2

Documentation/devicetree/bindings/arm/mstar/mstar,l3bridge.yaml

reviewed

··· 2 2 # Copyright 2020 thingy.jp. 3 3 %YAML 1.2 4 4 --- 5 5 - $id: "http://devicetree.org/schemas/arm/mstar/mstar,l3bridge.yaml#" 6 6 - $schema: "http://devicetree.org/meta-schemas/core.yaml#" 5 5 + $id: http://devicetree.org/schemas/arm/mstar/mstar,l3bridge.yaml# 6 6 + $schema: http://devicetree.org/meta-schemas/core.yaml# 7 7 8 8 title: MStar/SigmaStar Armv7 SoC l3bridge 9 9

+2 -2

Documentation/devicetree/bindings/arm/mstar/mstar,smpctrl.yaml

reviewed

··· 2 2 # Copyright 2020 thingy.jp. 3 3 %YAML 1.2 4 4 --- 5 5 - $id: "http://devicetree.org/schemas/arm/mstar/mstar,smpctrl.yaml#" 6 6 - $schema: "http://devicetree.org/meta-schemas/core.yaml#" 5 5 + $id: http://devicetree.org/schemas/arm/mstar/mstar,smpctrl.yaml# 6 6 + $schema: http://devicetree.org/meta-schemas/core.yaml# 7 7 8 8 title: MStar/SigmaStar Armv7 SoC SMP control registers 9 9

+1 -1

Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 # Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 3 %YAML 1.2 4 4 ---

+1 -1

Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 # Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 3 %YAML 1.2 4 4 ---

+2 -2

Documentation/devicetree/bindings/arm/stm32/st,mlahb.yaml

reviewed

··· 1 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 - $id: "http://devicetree.org/schemas/arm/stm32/st,mlahb.yaml#" 5 5 - $schema: "http://devicetree.org/meta-schemas/core.yaml#" 4 4 + $id: http://devicetree.org/schemas/arm/stm32/st,mlahb.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 7 title: STMicroelectronics STM32 ML-AHB interconnect 8 8

+2 -2

Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml

reviewed

··· 1 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 - $id: "http://devicetree.org/schemas/arm/stm32/st,stm32-syscon.yaml#" 5 5 - $schema: "http://devicetree.org/meta-schemas/core.yaml#" 4 4 + $id: http://devicetree.org/schemas/arm/stm32/st,stm32-syscon.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 7 title: STMicroelectronics STM32 Platforms System Controller 8 8

+2 -2

Documentation/devicetree/bindings/arm/sunxi.yaml

reviewed

··· 541 541 - const: msi,primo81 542 542 - const: allwinner,sun6i-a31s 543 543 544 544 - - description: Emlid Neutis N5 Developper Board 544 544 + - description: Emlid Neutis N5 Developer Board 545 545 items: 546 546 - const: emlid,neutis-n5-devboard 547 547 - const: emlid,neutis-n5 548 548 - const: allwinner,sun50i-h5 549 549 550 550 - - description: Emlid Neutis N5H3 Developper Board 550 550 + - description: Emlid Neutis N5H3 Developer Board 551 551 items: 552 552 - const: emlid,neutis-n5h3-devboard 553 553 - const: emlid,neutis-n5h3

+1 -1

Documentation/devicetree/bindings/ata/pata-common.yaml

reviewed

··· 12 12 description: | 13 13 This document defines device tree properties common to most Parallel 14 14 ATA (PATA, also known as IDE) AT attachment storage devices. 15 15 - It doesn't constitue a device tree binding specification by itself but is 15 15 + It doesn't constitute a device tree binding specification by itself but is 16 16 meant to be referenced by device tree bindings. 17 17 18 18 The PATA (IDE) controller-specific device tree bindings are responsible for

+1 -1

Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml

reviewed

··· 43 43 brcm,gisb-arb-master-names: 44 44 $ref: /schemas/types.yaml#/definitions/string-array 45 45 description: > 46 46 - String list of the litteral name of the GISB masters. Should match the 46 46 + String list of the literal name of the GISB masters. Should match the 47 47 number of bits set in brcm,gisb-master-mask and the order in which they 48 48 appear from MSB to LSB. 49 49

+2 -2

Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.yaml

reviewed

··· 7 7 title: NVIDIA Tegra ACONNECT Bus 8 8 9 9 description: | 10 10 - The Tegra ACONNECT bus is an AXI switch which is used to connnect various 10 10 + The Tegra ACONNECT bus is an AXI switch which is used to connect various 11 11 components inside the Audio Processing Engine (APE). All CPU accesses to 12 12 the APE subsystem go through the ACONNECT via an APB to AXI wrapper. All 13 13 - devices accessed via the ACONNNECT are described by child-nodes. 13 13 + devices accessed via the ACONNECT are described by child-nodes. 14 14 15 15 maintainers: 16 16 - Jon Hunter <jonathanh@nvidia.com>

+63

Documentation/devicetree/bindings/bus/qcom,ssbi.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/bus/qcom,ssbi.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Qualcomm Single-wire Serial Bus Interface (SSBI) 8 8 + 9 9 + description: 10 10 + Some Qualcomm MSM devices contain a point-to-point serial bus used to 11 11 + communicate with a limited range of devices (mostly power management 12 12 + chips). 13 13 + 14 14 + maintainers: 15 15 + - Andy Gross <agross@kernel.org> 16 16 + - Bjorn Andersson <andersson@kernel.org> 17 17 + 18 18 + properties: 19 19 + compatible: 20 20 + const: qcom,ssbi 21 21 + 22 22 + reg: 23 23 + maxItems: 1 24 24 + 25 25 + qcom,controller-type: 26 26 + description: 27 27 + Indicates the SSBI bus variant the controller should use to talk 28 28 + with the slave device. The type chosen is determined by the attached 29 29 + slave. 30 30 + enum: 31 31 + - ssbi 32 32 + - ssbi2 33 33 + - pmic-arbiter 34 34 + 35 35 + pmic: 36 36 + $ref: /schemas/mfd/qcom-pm8xxx.yaml# 37 37 + 38 38 + required: 39 39 + - compatible 40 40 + - reg 41 41 + - qcom,controller-type 42 42 + 43 43 + additionalProperties: false 44 44 + 45 45 + examples: 46 46 + - | 47 47 + #include <dt-bindings/interrupt-controller/irq.h> 48 48 + ssbi@c00000 { 49 49 + compatible = "qcom,ssbi"; 50 50 + reg = <0x00c00000 0x1000>; 51 51 + qcom,controller-type = "pmic-arbiter"; 52 52 + 53 53 + pmic { 54 54 + compatible = "qcom,pm8821"; 55 55 + interrupt-parent = <&msmgpio>; 56 56 + interrupts = <76 IRQ_TYPE_LEVEL_LOW>; 57 57 + #interrupt-cells = <2>; 58 58 + interrupt-controller; 59 59 + #address-cells = <1>; 60 60 + #size-cells = <0>; 61 61 + }; 62 62 + }; 63 63 + ...

+2 -4

Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml

reviewed

··· 29 29 patternProperties: 30 30 '^connector@[0-9a-f]+$': 31 31 $ref: /schemas/connector/usb-connector.yaml# 32 32 - unevaluatedProperties: false 33 33 - properties: 34 34 - reg: 35 35 - maxItems: 1 32 32 + required: 33 33 + - reg 36 34 37 35 required: 38 36 - compatible

+1 -1

Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-osc-clk.yaml

reviewed

··· 4 4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-osc-clk.yaml# 5 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 7 - title: Allwinner A10 Gatable Oscillator Clock 7 7 + title: Allwinner A10 Gateable Oscillator Clock 8 8 9 9 maintainers: 10 10 - Chen-Yu Tsai <wens@csie.org>

+2 -2

Documentation/devicetree/bindings/clock/alphascale,acc.txt

reviewed

··· 1 1 Alphascale Clock Controller 2 2 3 3 - The ACC (Alphascale Clock Controller) is responsible of choising proper 4 4 - clock source, setting deviders and clock gates. 3 3 + The ACC (Alphascale Clock Controller) is responsible for choosing proper 4 4 + clock source, setting dividers and clock gates. 5 5 6 6 Required properties for the ACC node: 7 7 - compatible: must be "alphascale,asm9260-clock-controller"

+1 -1

Documentation/devicetree/bindings/clock/keystone-pll.txt

reviewed

··· 14 14 - #clock-cells : from common clock binding; shall be set to 0. 15 15 - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock" 16 16 - clocks : parent clock phandle 17 17 - - reg - pll control0 and pll multipler registers 17 17 + - reg - pll control0 and pll multiplier registers 18 18 - reg-names : control, multiplier and post-divider. The multiplier and 19 19 post-divider registers are applicable only for main pll clock 20 20 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits

+1 -1

Documentation/devicetree/bindings/clock/lpc1850-ccu.txt

reviewed

··· 68 68 "base_ssp0_clk", "base_sdio_clk"; 69 69 }; 70 70 71 71 - /* A user of CCU brach clocks */ 71 71 + /* A user of CCU branch clocks */ 72 72 uart1: serial@40082000 { 73 73 ... 74 74 clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>;

+2 -2

Documentation/devicetree/bindings/clock/lpc1850-creg-clk.txt

reviewed

··· 5 5 32 kHz oscillator driver with power up/down and clock gating. Next 6 6 is a fixed divider that creates a 1 kHz clock from the 32 kHz osc. 7 7 8 8 - These clocks are used by the RTC and the Event Router peripherials. 9 9 - The 32 kHz can also be routed to other peripherials to enable low 8 8 + These clocks are used by the RTC and the Event Router peripherals. 9 9 + The 32 kHz can also be routed to other peripherals to enable low 10 10 power modes. 11 11 12 12 This binding uses the common clock binding:

+1 -1

Documentation/devicetree/bindings/clock/maxim,max9485.txt

reviewed

··· 12 12 13 13 Required properties: 14 14 - compatible: "maxim,max9485" 15 15 - - clocks: Input clock, must provice 27.000 MHz 15 15 + - clocks: Input clock, must provide 27.000 MHz 16 16 - clock-names: Must be set to "xclk" 17 17 - #clock-cells: From common clock binding; shall be set to 1 18 18

+1 -1

Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml

reviewed

··· 25 25 - description: Sleep clock source 26 26 - description: PCIE 0 Pipe clock source (Optional clock) 27 27 - description: PCIE 1 Pipe clock source (Optional clock) 28 28 - - description: PCIE 1 Phy Auxillary clock source (Optional clock) 28 28 + - description: PCIE 1 Phy Auxiliary clock source (Optional clock) 29 29 - description: UFS Phy Rx symbol 0 clock source (Optional clock) 30 30 - description: UFS Phy Rx symbol 1 clock source (Optional clock) 31 31 - description: UFS Phy Tx symbol 0 clock source (Optional clock)

+1 -1

Documentation/devicetree/bindings/clock/qcom,kpss-acc-v1.yaml

reviewed

··· 14 14 There is one ACC register region per CPU within the KPSS remapped region as 15 15 well as an alias register region that remaps accesses to the ACC associated 16 16 with the CPU accessing the region. ACC v1 is currently used as a 17 17 - clock-controller for enabling the cpu and hanling the aux clocks. 17 17 + clock-controller for enabling the cpu and handling the aux clocks. 18 18 19 19 properties: 20 20 compatible:

+1 -1

Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml

reviewed

··· 66 66 else: 67 67 description: | 68 68 Other SC9863a clock nodes should be the child of a syscon node in 69 69 - which compatible string shoule be: 69 69 + which compatible string should be: 70 70 "sprd,sc9863a-glbregs", "syscon", "simple-mfd" 71 71 72 72 The 'reg' property for the clock node is also required if there is a sub

+1 -1

Documentation/devicetree/bindings/clock/ti,cdce925.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/clock/ti,cdce925.yaml#

+1 -1

Documentation/devicetree/bindings/clock/ti,sci-clk.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/clock/ti,sci-clk.yaml#

+1 -1

Documentation/devicetree/bindings/clock/ti/mux.txt

reviewed

··· 8 8 gate or adjust the parent rate via a divider or multiplier. 9 9 10 10 By default the "clocks" property lists the parents in the same order 11 11 - as they are programmed into the regster. E.g: 11 11 + as they are programmed into the register. E.g: 12 12 13 13 clocks = <&foo_clock>, <&bar_clock>, <&baz_clock>; 14 14

+1 -1

Documentation/devicetree/bindings/clock/vf610-clock.txt

reviewed

··· 9 9 - clocks: list of clock identifiers which are external input clocks to the 10 10 given clock controller. Please refer the next section to find 11 11 the input clocks for a given controller. 12 12 - - clock-names: list of names of clocks which are exteral input clocks to the 12 12 + - clock-names: list of names of clocks which are external input clocks to the 13 13 given clock controller. 14 14 15 15 Input clocks for top clock controller:

+7 -4

Documentation/devicetree/bindings/connector/usb-connector.yaml

reviewed

··· 30 30 - const: samsung,usb-connector-11pin 31 31 - const: usb-b-connector 32 32 33 33 + reg: 34 34 + maxItems: 1 35 35 + 33 36 label: 34 37 description: Symbolic name for the connector. 35 38 ··· 227 224 state as defined in 7.4.2 Sink Electrical Parameters of USB Power Delivery Specification 228 225 Revision 3.0, Version 1.2. When the property is set, the port requests pSnkStby(2.5W - 229 226 5V@500mA) upon entering SNK_DISCOVERY(instead of 3A or the 1.5A, Rp current advertised, during 230 230 - SNK_DISCOVERY) and the actual currrent limit after reception of PS_Ready for PD link or during 227 227 + SNK_DISCOVERY) and the actual current limit after reception of PS_Ready for PD link or during 231 228 SNK_READY for non-pd link. 232 229 type: boolean 233 230 234 231 dependencies: 235 235 - sink-vdos-v1: [ 'sink-vdos' ] 236 236 - sink-vdos: [ 'sink-vdos-v1' ] 232 232 + sink-vdos-v1: [ sink-vdos ] 233 233 + sink-vdos: [ sink-vdos-v1 ] 237 234 238 235 required: 239 236 - compatible ··· 267 264 - typec-power-opmode 268 265 - new-source-frs-typec-current 269 266 270 270 - additionalProperties: true 267 267 + additionalProperties: false 271 268 272 269 examples: 273 270 # Micro-USB connector with HS lines routed via controller (MUIC).

+1

Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml

reviewed

··· 13 13 compatible: 14 14 items: 15 15 - enum: 16 16 + - qcom,sm8450-inline-crypto-engine 16 17 - qcom,sm8550-inline-crypto-engine 17 18 - const: qcom,inline-crypto-engine 18 19

+1

Documentation/devicetree/bindings/crypto/qcom-qce.yaml

reviewed

··· 34 34 - enum: 35 35 - qcom,ipq6018-qce 36 36 - qcom,ipq8074-qce 37 37 + - qcom,ipq9574-qce 37 38 - qcom,msm8996-qce 38 39 - qcom,qcm2290-qce 39 40 - qcom,sdm845-qce

+1 -1

Documentation/devicetree/bindings/crypto/ti,sa2ul.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/crypto/ti,sa2ul.yaml#

+1 -1

Documentation/devicetree/bindings/devfreq/event/samsung,exynos-ppmu.yaml

reviewed

··· 18 18 each IP (DMC, CPU, RIGHTBUS, LEFTBUS, CAM interface, LCD, G3D, MFC). The 19 19 Exynos PPMU driver uses the devfreq-event class to provide event data to 20 20 various devfreq devices. The devfreq devices would use the event data when 21 21 - derterming the current state of each IP. 21 21 + determining the current state of each IP. 22 22 23 23 properties: 24 24 compatible:

+1 -1

Documentation/devicetree/bindings/display/atmel/hlcdc-dc.txt

reviewed

··· 12 12 13 13 Required children nodes: 14 14 Children nodes are encoding available output ports and their connections 15 15 - to external devices using the OF graph reprensentation (see ../graph.txt). 15 15 + to external devices using the OF graph representation (see ../graph.txt). 16 16 At least one port node is required. 17 17 18 18 Optional properties in grandchild nodes:

+1 -1

Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml

reviewed

··· 11 11 12 12 description: | 13 13 This document defines device tree properties for the Synopsys DesignWare MIPI 14 14 - DSI host controller. It doesn't constitue a device tree binding specification 14 14 + DSI host controller. It doesn't constitute a device tree binding specification 15 15 by itself but is meant to be referenced by platform-specific device tree 16 16 bindings. 17 17

+1 -1

Documentation/devicetree/bindings/display/cirrus,clps711x-fb.txt

reviewed

··· 1 1 - * Currus Logic CLPS711X Framebuffer 1 1 + * Cirrus Logic CLPS711X Framebuffer 2 2 3 3 Required properties: 4 4 - compatible: Shall contain "cirrus,ep7209-fb".

+2 -1

Documentation/devicetree/bindings/display/msm/dp-controller.yaml

reviewed

··· 80 80 81 81 operating-points-v2: true 82 82 83 83 - opp-table: true 83 83 + opp-table: 84 84 + type: object 84 85 85 86 power-domains: 86 87 maxItems: 1

+1 -1

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#

+1 -1

Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-10nm.yaml#

+1 -1

Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-14nm.yaml#

+1 -1

Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-20nm.yaml#

+1 -1

Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-28nm.yaml#

+1 -1

Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-7nm.yaml#

+1 -1

Documentation/devicetree/bindings/display/msm/dsi-phy-common.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-common.yaml#

+1 -1

Documentation/devicetree/bindings/display/msm/mdss-common.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/msm/mdss-common.yaml#

+1 -1

Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/msm/qcom,mdp5.yaml#

+2 -2

Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/msm/qcom,mdss.yaml# ··· 11 11 - Rob Clark <robdclark@gmail.com> 12 12 13 13 description: 14 14 - This is the bindings documentation for the Mobile Display Subsytem(MDSS) that 14 14 + This is the bindings documentation for the Mobile Display Subsystem(MDSS) that 15 15 encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc. 16 16 17 17 properties:

+1 -1

Documentation/devicetree/bindings/display/msm/qcom,msm8998-dpu.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/msm/qcom,msm8998-dpu.yaml#

+1 -1

Documentation/devicetree/bindings/display/msm/qcom,msm8998-mdss.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/msm/qcom,msm8998-mdss.yaml#

+1 -1

Documentation/devicetree/bindings/display/msm/qcom,qcm2290-dpu.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/msm/qcom,qcm2290-dpu.yaml#

+1 -1

Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/msm/qcom,qcm2290-mdss.yaml#

+1 -1

Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/msm/qcom,sc7180-dpu.yaml#

+1 -1

Documentation/devicetree/bindings/display/msm/qcom,sc7180-mdss.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/msm/qcom,sc7180-mdss.yaml#

+1 -1

Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/msm/qcom,sc7280-dpu.yaml#

+1 -1

Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/msm/qcom,sc7280-mdss.yaml#

+1 -1

Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-dpu.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/msm/qcom,sc8280xp-dpu.yaml#

+1 -1

Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-mdss.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/msm/qcom,sc8280xp-mdss.yaml#

+1 -1

Documentation/devicetree/bindings/display/msm/qcom,sdm845-dpu.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/msm/qcom,sdm845-dpu.yaml#

+1 -1

Documentation/devicetree/bindings/display/msm/qcom,sdm845-mdss.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/msm/qcom,sdm845-mdss.yaml#

+1 -1

Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm6115-dpu.yaml#

+1 -1

Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm6115-mdss.yaml#

+1 -1

Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm6350-mdss.yaml#

+1 -1

Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm6375-mdss.yaml#

+1 -1

Documentation/devicetree/bindings/display/msm/qcom,sm8150-dpu.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8150-dpu.yaml#

+1 -1

Documentation/devicetree/bindings/display/msm/qcom,sm8150-mdss.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8150-mdss.yaml#

+1 -1

Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8250-dpu.yaml#

+1 -1

Documentation/devicetree/bindings/display/msm/qcom,sm8250-mdss.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8250-mdss.yaml#

+1 -1

Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8350-dpu.yaml#

+1 -1

Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8350-mdss.yaml#

+1 -1

Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8450-dpu.yaml#

+1 -1

Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8450-mdss.yaml#

+1 -1

Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8550-dpu.yaml#

+1 -1

Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8550-mdss.yaml#

+3

Documentation/devicetree/bindings/display/panel/advantech,idk-2121wr.yaml

reviewed

··· 19 19 second port, therefore the ports must be marked accordingly (with either 20 20 dual-lvds-odd-pixels or dual-lvds-even-pixels). 21 21 22 22 + allOf: 23 23 + - $ref: panel-common.yaml# 24 24 + 22 25 properties: 23 26 compatible: 24 27 items:

+1 -1

Documentation/devicetree/bindings/display/panel/himax,hx8394.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/panel/himax,hx8394.yaml#

+1 -1

Documentation/devicetree/bindings/display/panel/mantix,mlaf057we51-x.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/panel/mantix,mlaf057we51-x.yaml#

+1 -1

Documentation/devicetree/bindings/display/panel/olimex,lcd-olinuxino.yaml

reviewed

··· 20 20 The panel itself contains: 21 21 - AT24C16C EEPROM holding panel identification and timing requirements 22 22 - AR1021 resistive touch screen controller (optional) 23 23 - - FT5x6 capacitive touch screnn controller (optional) 23 23 + - FT5x6 capacitive touch screen controller (optional) 24 24 - GT911/GT928 capacitive touch screen controller (optional) 25 25 26 26 The above chips share same I2C bus. The EEPROM is factory preprogrammed with

+1 -1

Documentation/devicetree/bindings/display/panel/orisetech,otm8009a.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/panel/orisetech,otm8009a.yaml#

+1 -1

Documentation/devicetree/bindings/display/panel/panel-common.yaml

reviewed

··· 12 12 13 13 description: | 14 14 This document defines device tree properties common to several classes of 15 15 - display panels. It doesn't constitue a device tree binding specification by 15 15 + display panels. It doesn't constitute a device tree binding specification by 16 16 itself but is meant to be referenced by device tree bindings. 17 17 18 18 When referenced from panel device tree bindings the properties defined in this

+1 -1

Documentation/devicetree/bindings/display/panel/panel-dsi-cm.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/panel/panel-dsi-cm.yaml#

+2 -1

Documentation/devicetree/bindings/display/panel/panel-mipi-dbi-spi.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/panel/panel-mipi-dbi-spi.yaml# ··· 66 66 compatible: 67 67 items: 68 68 - enum: 69 69 + - saef,sftc154b 69 70 - sainsmart18 70 71 - shineworld,lh133k 71 72 - const: panel-mipi-dbi-spi

+1 -1

Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/panel/panel-simple-dsi.yaml#

+1 -1

Documentation/devicetree/bindings/display/panel/raydium,rm68200.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/panel/raydium,rm68200.yaml#

+1 -1

Documentation/devicetree/bindings/display/panel/rocktech,jh057n00900.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/panel/rocktech,jh057n00900.yaml#

+1 -1

Documentation/devicetree/bindings/display/panel/visionox,rm69299.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/panel/visionox,rm69299.yaml#

+1 -1

Documentation/devicetree/bindings/display/panel/visionox,vtdr6130.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/panel/visionox,vtdr6130.yaml#

+1 -1

Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/display/rockchip/rockchip-vop2.yaml#

+1 -1

Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-sor.yaml

reviewed

··· 97 97 98 98 # optional when driving an eDP output 99 99 nvidia,dpaux: 100 100 - description: phandle to a DispayPort AUX interface 100 100 + description: phandle to a DisplayPort AUX interface 101 101 $ref: /schemas/types.yaml#/definitions/phandle 102 102 103 103 allOf:

+1 -1

Documentation/devicetree/bindings/dma/ingenic,dma.yaml

reviewed

··· 68 68 $ref: /schemas/types.yaml#/definitions/uint32 69 69 description: > 70 70 Bitmask of channels to reserve for devices that need a specific 71 71 - channel. These channels will only be assigned when explicitely 71 71 + channel. These channels will only be assigned when explicitly 72 72 requested by a client. The primary use for this is channels 0 and 73 73 1, which can be configured to have special behaviour for NAND/BCH 74 74 when using programmable firmware.

+1 -1

Documentation/devicetree/bindings/dma/nvidia,tegra20-apbdma.txt

reviewed

··· 2 2 3 3 Required properties: 4 4 - compatible: Should be "nvidia,<chip>-apbdma" 5 5 - - reg: Should contain DMA registers location and length. This shuld include 5 5 + - reg: Should contain DMA registers location and length. This should include 6 6 all of the per-channel registers. 7 7 - interrupts: Should contain all of the per-channel DMA interrupts. 8 8 - clocks: Must contain one entry, for the module clock.

+1 -1

Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml

reviewed

··· 48 48 qcom,controlled-remotely: 49 49 type: boolean 50 50 description: 51 51 - Indicates that the bam is controlled by remote proccessor i.e. execution 51 51 + Indicates that the bam is controlled by remote processor i.e. execution 52 52 environment. 53 53 54 54 qcom,ee:

+1 -1

Documentation/devicetree/bindings/dma/stericsson,dma40.yaml

reviewed

··· 148 148 memcpy-channels: 149 149 $ref: /schemas/types.yaml#/definitions/uint32-array 150 150 description: Array of u32 elements indicating which channels on the DMA 151 151 - engine are elegible for memcpy transfers 151 151 + engine are eligible for memcpy transfers 152 152 153 153 required: 154 154 - "#dma-cells"

+2 -2

Documentation/devicetree/bindings/eeprom/at24.yaml

reviewed

··· 2 2 # Copyright 2019 BayLibre SAS 3 3 %YAML 1.2 4 4 --- 5 5 - $id: "http://devicetree.org/schemas/eeprom/at24.yaml#" 6 6 - $schema: "http://devicetree.org/meta-schemas/core.yaml#" 5 5 + $id: http://devicetree.org/schemas/eeprom/at24.yaml# 6 6 + $schema: http://devicetree.org/meta-schemas/core.yaml# 7 7 8 8 title: I2C EEPROMs compatible with Atmel's AT24 9 9

+2 -2

Documentation/devicetree/bindings/eeprom/at25.yaml

reviewed

··· 1 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 - $id: "http://devicetree.org/schemas/eeprom/at25.yaml#" 5 5 - $schema: "http://devicetree.org/meta-schemas/core.yaml#" 4 4 + $id: http://devicetree.org/schemas/eeprom/at25.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 7 title: SPI EEPROMs or FRAMs compatible with Atmel's AT25 8 8

+1 -1

Documentation/devicetree/bindings/extcon/qcom,pm8941-misc.yaml

reviewed

··· 7 7 title: Qualcomm Technologies, Inc. PM8941 USB ID Extcon device 8 8 9 9 maintainers: 10 10 - - Guru Das Srinagesh <gurus@codeaurora.org> 10 10 + - Guru Das Srinagesh <quic_gurus@quicinc.com> 11 11 12 12 description: | 13 13 Some Qualcomm PMICs have a "misc" module that can be used to detect when

+2 -2

Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml

reviewed

··· 2 2 # Copyright 2019 Linaro Ltd. 3 3 %YAML 1.2 4 4 --- 5 5 - $id: "http://devicetree.org/schemas/firmware/intel,ixp4xx-network-processing-engine.yaml#" 6 6 - $schema: "http://devicetree.org/meta-schemas/core.yaml#" 5 5 + $id: http://devicetree.org/schemas/firmware/intel,ixp4xx-network-processing-engine.yaml# 6 6 + $schema: http://devicetree.org/meta-schemas/core.yaml# 7 7 8 8 title: Intel IXP4xx Network Processing Engine 9 9

+14

Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml

reviewed

··· 38 38 - smc 39 39 - hvc 40 40 41 41 + "#power-domain-cells": 42 42 + const: 1 43 43 + 41 44 versal_fpga: 42 45 $ref: /schemas/fpga/xlnx,versal-fpga.yaml# 43 46 description: Compatible of the FPGA device. ··· 69 66 70 67 examples: 71 68 - | 69 69 + #include <dt-bindings/power/xlnx-zynqmp-power.h> 70 70 + firmware { 71 71 + zynqmp_firmware: zynqmp-firmware { 72 72 + #power-domain-cells = <1>; 73 73 + }; 74 74 + }; 75 75 + 76 76 + sata { 77 77 + power-domains = <&zynqmp_firmware PD_SATA>; 78 78 + }; 79 79 + 72 80 versal-firmware { 73 81 compatible = "xlnx,versal-firmware"; 74 82 method = "smc";

+2 -2

Documentation/devicetree/bindings/fpga/fpga-region.txt

reviewed

··· 63 63 will be disabled. 64 64 * During Partial Reconfiguration of a specific region, that region's bridge 65 65 will be used to gate the busses. Traffic to other regions is not affected. 66 66 - * In some implementations, the FPGA Manager transparantly handles gating the 66 66 + * In some implementations, the FPGA Manager transparently handles gating the 67 67 buses, eliminating the need to show the hardware FPGA bridges in the 68 68 device tree. 69 69 * An FPGA image may create a set of reprogrammable regions, each having its ··· 466 466 constraints required to make partial reconfiguration work[1] [2] [3], but a few 467 467 deserve quick mention. 468 468 469 469 - A persona must have boundary connections that line up with those of the partion 469 469 + A persona must have boundary connections that line up with those of the partition 470 470 or region it is designed to go into. 471 471 472 472 During programming, transactions through those connections must be stopped and

+1 -1

Documentation/devicetree/bindings/gpio/gpio-xgene-sb.txt

reviewed

··· 27 27 - gpio-controller: Marks the device node as a GPIO controller. 28 28 - interrupts: The EXT_INT_0 parent interrupt resource must be listed first. 29 29 - interrupt-cells: Should be two. 30 30 - - first cell is 0-N coresponding for EXT_INT_0 to EXT_INT_N. 30 30 + - first cell is 0-N corresponding for EXT_INT_0 to EXT_INT_N. 31 31 - second cell is used to specify flags. 32 32 - interrupt-controller: Marks the device node as an interrupt controller. 33 33 - apm,nr-gpios: Optional, specify number of gpios pin.

+1 -1

Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml

reviewed

··· 9 9 description: | 10 10 Synopsys DesignWare GPIO controllers have a configurable number of ports, 11 11 each of which are intended to be represented as child nodes with the generic 12 12 - GPIO-controller properties as desribed in this bindings file. 12 12 + GPIO-controller properties as described in this bindings file. 13 13 14 14 maintainers: 15 15 - Hoan Tran <hoan@os.amperecomputing.com>

+2 -2

Documentation/devicetree/bindings/gpio/ti,omap-gpio.yaml

reviewed

··· 58 58 deprecated: true 59 59 description: 60 60 Name of the hwmod associated with the GPIO. Needed on some legacy OMAP 61 61 - SoCs which have not been converted to the ti,sysc interconnect hierarachy. 61 61 + SoCs which have not been converted to the ti,sysc interconnect hierarchy. 62 62 63 63 ti,no-reset-on-init: 64 64 $ref: /schemas/types.yaml#/definitions/flag 65 65 deprecated: true 66 66 description: 67 67 Do not reset on init. Used with ti,hwmods on some legacy OMAP SoCs which 68 68 - have not been converted to the ti,sysc interconnect hierarachy. 68 68 + have not been converted to the ti,sysc interconnect hierarchy. 69 69 70 70 patternProperties: 71 71 "^(.+-hog(-[0-9]+)?)$":

+2 -2

Documentation/devicetree/bindings/gpio/x-powers,axp209-gpio.yaml

reviewed

··· 1 1 # SPDX-License-Identifier: GPL-2.0 2 2 %YAML 1.2 3 3 --- 4 4 - $id: "http://devicetree.org/schemas/gpio/x-powers,axp209-gpio.yaml#" 5 5 - $schema: "http://devicetree.org/meta-schemas/core.yaml#" 4 4 + $id: http://devicetree.org/schemas/gpio/x-powers,axp209-gpio.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 7 title: X-Powers AXP209 GPIO 8 8

+2 -2

Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml

reviewed

··· 1 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 - $id: "http://devicetree.org/schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml#" 5 5 - $schema: "http://devicetree.org/meta-schemas/core.yaml#" 4 4 + $id: http://devicetree.org/schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 7 title: ZynqMP Mode Pin GPIO controller 8 8

+2 -2

Documentation/devicetree/bindings/gpio/xylon,logicvc-gpio.yaml

reviewed

··· 2 2 # Copyright 2019 Bootlin 3 3 %YAML 1.2 4 4 --- 5 5 - $id: "http://devicetree.org/schemas/gpio/xylon,logicvc-gpio.yaml#" 6 6 - $schema: "http://devicetree.org/meta-schemas/core.yaml#" 5 5 + $id: http://devicetree.org/schemas/gpio/xylon,logicvc-gpio.yaml# 6 6 + $schema: http://devicetree.org/meta-schemas/core.yaml# 7 7 8 8 title: Xylon LogiCVC GPIO controller 9 9

+1 -1

Documentation/devicetree/bindings/hwlock/allwinner,sun6i-a31-hwspinlock.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/hwlock/allwinner,sun6i-a31-hwspinlock.yaml#

+1 -1

Documentation/devicetree/bindings/hwlock/ti,omap-hwspinlock.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/hwlock/ti,omap-hwspinlock.yaml#

+1 -1

Documentation/devicetree/bindings/hwmon/adi,adm1177.yaml

reviewed

··· 27 27 28 28 shunt-resistor-micro-ohms: 29 29 description: 30 30 - The value of curent sense resistor in microohms. If not provided, 30 30 + The value of current sense resistor in microohms. If not provided, 31 31 the current reading and overcurrent alert is disabled. 32 32 33 33 adi,shutdown-threshold-microamp:

+1 -1

Documentation/devicetree/bindings/hwmon/adi,axi-fan-control.yaml

reviewed

··· 11 11 - Nuno Sá <nuno.sa@analog.com> 12 12 13 13 description: |+ 14 14 - Bindings for the Analog Devices AXI FAN Control driver. Spefications of the 14 14 + Bindings for the Analog Devices AXI FAN Control driver. Specifications of the 15 15 core can be found in: 16 16 17 17 https://wiki.analog.com/resources/fpga/docs/axi_fan_control

+1 -1

Documentation/devicetree/bindings/hwmon/adi,ltc2992.yaml

reviewed

··· 46 46 47 47 shunt-resistor-micro-ohms: 48 48 description: 49 49 - The value of curent sense resistor in microohms. 49 49 + The value of current sense resistor in microohms. 50 50 51 51 required: 52 52 - compatible

+1 -1

Documentation/devicetree/bindings/hwmon/aspeed-pwm-tacho.txt

reviewed

··· 45 45 - aspeed,fan-tach-ch : should specify the Fan tach input channel. 46 46 integer value in the range 0 through 15, with 0 indicating 47 47 Fan tach channel 0 and 15 indicating Fan tach channel 15. 48 48 - Atleast one Fan tach input channel is required. 48 48 + At least one Fan tach input channel is required. 49 49 50 50 Examples: 51 51

+2 -2

Documentation/devicetree/bindings/hwmon/iio-hwmon.yaml

reviewed

··· 1 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 - $id: "http://devicetree.org/schemas/hwmon/iio-hwmon.yaml#" 5 5 - $schema: "http://devicetree.org/meta-schemas/core.yaml#" 4 4 + $id: http://devicetree.org/schemas/hwmon/iio-hwmon.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 7 title: ADC-attached Hardware Sensor 8 8

+1 -1

Documentation/devicetree/bindings/hwmon/jedec,jc42.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/hwmon/jedec,jc42.yaml#

+1 -1

Documentation/devicetree/bindings/hwmon/lltc,ltc4151.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/hwmon/lltc,ltc4151.yaml#

+1 -1

Documentation/devicetree/bindings/hwmon/lm75.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/hwmon/lm75.yaml#

+1 -1

Documentation/devicetree/bindings/hwmon/lm87.txt

reviewed

··· 18 18 in7. Otherwise the pin is set as FAN2 input. 19 19 20 20 - vcc-supply: a Phandle for the regulator supplying power, can be 21 21 - cofigured to measure 5.0V power supply. Default is 3.3V. 21 21 + configured to measure 5.0V power supply. Default is 3.3V. 22 22 23 23 Example: 24 24

+1 -1

Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt

reviewed

··· 1 1 - Lantiq cpu temperatur sensor 1 1 + Lantiq cpu temperature sensor 2 2 3 3 Requires node properties: 4 4 - compatible value :

+1 -1

Documentation/devicetree/bindings/hwmon/microchip,mcp3021.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/hwmon/microchip,mcp3021.yaml#

+1 -1

Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml

reviewed

··· 42 42 reg: 43 43 items: 44 44 - description: PVT common registers 45 45 - - description: PVT temprature sensor registers 45 45 + - description: PVT temperature sensor registers 46 46 - description: PVT process detector registers 47 47 - description: PVT voltage monitor registers 48 48

+1 -1

Documentation/devicetree/bindings/hwmon/national,lm90.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/hwmon/national,lm90.yaml#

+1 -1

Documentation/devicetree/bindings/hwmon/npcm750-pwm-fan.txt

reviewed

··· 23 23 fan subnode format: 24 24 =================== 25 25 Under fan subnode can be upto 8 child nodes, each child node representing a fan. 26 26 - Each fan subnode must have one PWM channel and atleast one Fan tach channel. 26 26 + Each fan subnode must have one PWM channel and at least one Fan tach channel. 27 27 28 28 For PWM channel can be configured cooling-levels to create cooling device. 29 29 Cooling device could be bound to a thermal zone for the thermal control.

+1 -1

Documentation/devicetree/bindings/hwmon/nxp,mc34vr500.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/hwmon/nxp,mc34vr500.yaml#

+1 -1

Documentation/devicetree/bindings/hwmon/sensirion,sht15.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/hwmon/sensirion,sht15.yaml#

+1 -1

Documentation/devicetree/bindings/hwmon/sensirion,shtc1.yaml

reviewed

··· 13 13 The SHTC1, SHTW1 and SHTC3 are digital humidity and temperature sensors 14 14 designed especially for battery-driven high-volume consumer electronics 15 15 applications. 16 16 - For further information refere to Documentation/hwmon/shtc1.rst 16 16 + For further information refer to Documentation/hwmon/shtc1.rst 17 17 18 18 This binding document describes the binding for the hardware monitor 19 19 portion of the driver.

+4 -4

Documentation/devicetree/bindings/hwmon/starfive,jh71x0-temp.yaml

reviewed

··· 27 27 28 28 clock-names: 29 29 items: 30 30 - - const: "sense" 31 31 - - const: "bus" 30 30 + - const: sense 31 31 + - const: bus 32 32 33 33 '#thermal-sensor-cells': 34 34 const: 0 ··· 39 39 40 40 reset-names: 41 41 items: 42 42 - - const: "sense" 43 43 - - const: "bus" 42 42 + - const: sense 43 43 + - const: bus 44 44 45 45 required: 46 46 - compatible

+1 -1

Documentation/devicetree/bindings/hwmon/ti,tmp102.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/hwmon/ti,tmp102.yaml#

+1 -1

Documentation/devicetree/bindings/hwmon/ti,tmp108.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/hwmon/ti,tmp108.yaml#

+1 -1

Documentation/devicetree/bindings/hwmon/ti,tmp513.yaml

reviewed

··· 33 33 34 34 shunt-resistor-micro-ohms: 35 35 description: | 36 36 - If 0, the calibration process will be skiped and the current and power 36 36 + If 0, the calibration process will be skipped and the current and power 37 37 measurement engine will not work. Temperature and voltage measurement 38 38 will continue to work. The shunt value also need to respect: 39 39 rshunt <= pga-gain * 40 * 1000 * 1000.

+1 -1

Documentation/devicetree/bindings/hwmon/ti,tps23861.yaml

reviewed

··· 26 26 maxItems: 1 27 27 28 28 shunt-resistor-micro-ohms: 29 29 - description: The value of curent sense resistor in microohms. 29 29 + description: The value of current sense resistor in microohms. 30 30 default: 255000 31 31 minimum: 250000 32 32 maximum: 255000

+1 -1

Documentation/devicetree/bindings/i2c/i2c-sprd.txt

reviewed

··· 10 10 "source" for I2C source (parent) clock, 11 11 "enable" for I2C module enable clock. 12 12 - clocks: Should contain a clock specifier for each entry in clock-names. 13 13 - - clock-frequency: Constains desired I2C bus clock frequency in Hz. 13 13 + - clock-frequency: Contains desired I2C bus clock frequency in Hz. 14 14 - #address-cells: Should be 1 to describe address cells for I2C device address. 15 15 - #size-cells: Should be 0 means no size cell for I2C device address. 16 16

+2 -2

Documentation/devicetree/bindings/i3c/mipi-i3c-hci.yaml

reviewed

··· 1 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 - $id: "http://devicetree.org/schemas/i3c/mipi-i3c-hci.yaml#" 5 5 - $schema: "http://devicetree.org/meta-schemas/core.yaml#" 4 4 + $id: http://devicetree.org/schemas/i3c/mipi-i3c-hci.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 7 title: MIPI I3C HCI 8 8

+2 -2

Documentation/devicetree/bindings/iio/accel/fsl,mma7455.yaml

reviewed

··· 36 36 maxItems: 2 37 37 items: 38 38 enum: 39 39 - - "INT1" 40 40 - - "INT2" 39 39 + - INT1 40 40 + - INT2 41 41 42 42 required: 43 43 - compatible

+2 -2

Documentation/devicetree/bindings/iio/adc/atmel,sama9260-adc.yaml

reviewed

··· 56 56 String corresponding to an identifier from atmel,adc-res-names property. 57 57 If not specified, the highest resolution will be used. 58 58 enum: 59 59 - - "lowres" 60 60 - - "highres" 59 59 + - lowres 60 60 + - highres 61 61 62 62 atmel,adc-sleep-mode: 63 63 $ref: /schemas/types.yaml#/definitions/flag

+1 -1

Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml

reviewed

··· 57 57 |27 |FPD Internal voltage measurement, VCC_PSINTFP (supply5). |Voltage 58 58 |28 |PS Auxiliary voltage measurement (supply6). |Voltage 59 59 |29 |PL VCCADC voltage measurement (vccams). |Voltage 60 60 - |30 |Differential analog input signal voltage measurment. |Voltage 60 60 + |30 |Differential analog input signal voltage measurement. |Voltage 61 61 |31 |VUser0 voltage measurement (supply7). |Voltage 62 62 |32 |VUser1 voltage measurement (supply8). |Voltage 63 63 |33 |VUser2 voltage measurement (supply9). |Voltage

+1 -1

Documentation/devicetree/bindings/iio/cdc/adi,ad7150.yaml

reviewed

··· 4 4 $id: http://devicetree.org/schemas/iio/cdc/adi,ad7150.yaml# 5 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 7 - title: Analog device AD7150 and similar capacitance to digital convertors. 7 7 + title: Analog device AD7150 and similar capacitance to digital converters. 8 8 9 9 maintainers: 10 10 - Jonathan Cameron <jic23@kernel.org>

+1 -1

Documentation/devicetree/bindings/iio/common.yaml

reviewed

··· 12 12 13 13 description: | 14 14 This document defines device tree properties common to several iio 15 15 - sensors. It doesn't constitue a device tree binding specification by itself but 15 15 + sensors. It doesn't constitute a device tree binding specification by itself but 16 16 is meant to be referenced by device tree bindings. 17 17 18 18 When referenced from sensor tree bindings the properties defined in this

+1 -1

Documentation/devicetree/bindings/iio/frequency/adi,admv1014.yaml

reviewed

··· 33 33 items: 34 34 - const: lo_in 35 35 description: 36 36 - External clock that provides the Local Oscilator input. 36 36 + External clock that provides the Local Oscillator input. 37 37 38 38 vcm-supply: 39 39 description:

+1 -1

Documentation/devicetree/bindings/iio/humidity/ti,hdc2010.yaml

reviewed

··· 10 10 - Eugene Zaikonnikov <ez@norophonic.com> 11 11 12 12 description: | 13 13 - Relative humidity and tempereature sensors on I2C bus 13 13 + Relative humidity and temperature sensors on I2C bus 14 14 15 15 Datasheets are available at: 16 16 http://www.ti.com/product/HDC2010/datasheet

+1 -1

Documentation/devicetree/bindings/iio/pressure/honeywell,mprls0025pa.yaml

reviewed

··· 47 47 reset-gpios: 48 48 description: 49 49 Optional GPIO for resetting the device. 50 50 - If not present the device is not resetted during the probe. 50 50 + If not present the device is not reset during the probe. 51 51 maxItems: 1 52 52 53 53 honeywell,pmin-pascal:

+1 -1

Documentation/devicetree/bindings/iio/proximity/ams,as3935.yaml

reviewed

··· 10 10 - Matt Ranostay <matt.ranostay@konsulko.com> 11 11 12 12 description: 13 13 - This lightening distance sensor uses an I2C or SPI interface. The 13 13 + This lightning distance sensor uses an I2C or SPI interface. The 14 14 binding currently only covers the SPI option. 15 15 16 16 properties:

+1 -1

Documentation/devicetree/bindings/iio/st,st-sensors.yaml

reviewed

··· 97 97 98 98 interrupts: 99 99 description: interrupt line(s) connected to the DRDY line(s) and/or the 100 100 - Intertial interrupt lines INT1 and INT2 if these exist. This means up to 100 100 + Inertial interrupt lines INT1 and INT2 if these exist. This means up to 101 101 three interrupts, and the DRDY must be the first one if it exists on 102 102 the package. The trigger edge of the interrupts is sometimes software 103 103 configurable in the hardware so the operating system should parse this

+1 -1

Documentation/devicetree/bindings/input/elan,ekth3000.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/input/elan,ekth3000.yaml#

-56

Documentation/devicetree/bindings/input/rmi4/rmi_2d_sensor.txt

reviewed

··· 1 1 - Synaptics RMI4 2D Sensor Device Binding 2 2 - 3 3 - The Synaptics RMI4 core is able to support RMI4 devices using different 4 4 - transports and different functions. This file describes the device tree 5 5 - bindings for devices which contain 2D sensors using Function 11 or 6 6 - Function 12. Complete documentation for transports and other functions 7 7 - can be found in: 8 8 - Documentation/devicetree/bindings/input/rmi4. 9 9 - 10 10 - RMI4 Function 11 and Function 12 are for 2D touch position sensing. 11 11 - Additional documentation for F11 can be found at: 12 12 - http://www.synaptics.com/sites/default/files/511-000136-01-Rev-E-RMI4-Interfacing-Guide.pdf 13 13 - 14 14 - Optional Touch Properties: 15 15 - Description in Documentation/devicetree/bindings/input/touchscreen 16 16 - - touchscreen-inverted-x 17 17 - - touchscreen-inverted-y 18 18 - - touchscreen-swapped-x-y 19 19 - - touchscreen-x-mm 20 20 - - touchscreen-y-mm 21 21 - 22 22 - Optional Properties: 23 23 - - syna,clip-x-low: Sets a minimum value for X. 24 24 - - syna,clip-y-low: Sets a minimum value for Y. 25 25 - - syna,clip-x-high: Sets a maximum value for X. 26 26 - - syna,clip-y-high: Sets a maximum value for Y. 27 27 - - syna,offset-x: Add an offset to X. 28 28 - - syna,offset-y: Add an offset to Y. 29 29 - - syna,delta-x-threshold: Set the minimum distance on the X axis required 30 30 - to generate an interrupt in reduced reporting 31 31 - mode. 32 32 - - syna,delta-y-threshold: Set the minimum distance on the Y axis required 33 33 - to generate an interrupt in reduced reporting 34 34 - mode. 35 35 - - syna,sensor-type: Set the sensor type. 1 for touchscreen 2 for touchpad. 36 36 - - syna,disable-report-mask: Mask for disabling posiiton reporting. Used to 37 37 - disable reporing absolute position data. 38 38 - - syna,rezero-wait-ms: Time in miliseconds to wait after issuing a rezero 39 39 - command. 40 40 - 41 41 - 42 42 - Example of a RMI4 I2C device with F11: 43 43 - Example: 44 44 - &i2c1 { 45 45 - rmi4-i2c-dev@2c { 46 46 - compatible = "syna,rmi4-i2c"; 47 47 - 48 48 - ... 49 49 - 50 50 - rmi4-f11@11 { 51 51 - reg = <0x11>; 52 52 - touchscreen-inverted-y; 53 53 - syna,sensor-type = <2>; 54 54 - }; 55 55 - }; 56 56 - };

-39

Documentation/devicetree/bindings/input/rmi4/rmi_f01.txt

reviewed

··· 1 1 - Synaptics RMI4 F01 Device Binding 2 2 - 3 3 - The Synaptics RMI4 core is able to support RMI4 devices using different 4 4 - transports and different functions. This file describes the device tree 5 5 - bindings for devices which contain Function 1. Complete documentation 6 6 - for transports and other functions can be found in: 7 7 - Documentation/devicetree/bindings/input/rmi4. 8 8 - 9 9 - Additional documentation for F01 can be found at: 10 10 - http://www.synaptics.com/sites/default/files/511-000136-01-Rev-E-RMI4-Interfacing-Guide.pdf 11 11 - 12 12 - Optional Properties: 13 13 - - syna,nosleep-mode: If set the device will run at full power without sleeping. 14 14 - nosleep has 3 modes, 0 will not change the default 15 15 - setting, 1 will disable nosleep (allow sleeping), 16 16 - and 2 will enable nosleep (disabling sleep). 17 17 - - syna,wakeup-threshold: Defines the amplitude of the disturbance to the 18 18 - background capacitance that will cause the 19 19 - device to wake from dozing. 20 20 - - syna,doze-holdoff-ms: The delay to wait after the last finger lift and the 21 21 - first doze cycle. 22 22 - - syna,doze-interval-ms: The time period that the device sleeps between finger 23 23 - activity. 24 24 - 25 25 - 26 26 - Example of a RMI4 I2C device with F01: 27 27 - Example: 28 28 - &i2c1 { 29 29 - rmi4-i2c-dev@2c { 30 30 - compatible = "syna,rmi4-i2c"; 31 31 - 32 32 - ... 33 33 - 34 34 - rmi4-f01@1 { 35 35 - reg = <0x1>; 36 36 - syna,nosleep-mode = <1>; 37 37 - }; 38 38 - }; 39 39 - };

-61

Documentation/devicetree/bindings/input/rmi4/rmi_i2c.txt

reviewed

··· 1 1 - Synaptics RMI4 I2C Device Binding 2 2 - 3 3 - The Synaptics RMI4 core is able to support RMI4 devices using different 4 4 - transports and different functions. This file describes the device tree 5 5 - bindings for devices using the I2C transport driver. Complete documentation 6 6 - for other transports and functions can be found in 7 7 - Documentation/devicetree/bindings/input/rmi4. 8 8 - 9 9 - Required Properties: 10 10 - - compatible: syna,rmi4-i2c 11 11 - - reg: I2C address 12 12 - - #address-cells: Set to 1 to indicate that the function child nodes 13 13 - consist of only on uint32 value. 14 14 - - #size-cells: Set to 0 to indicate that the function child nodes do not 15 15 - have a size property. 16 16 - 17 17 - Optional Properties: 18 18 - - interrupts: interrupt which the rmi device is connected to. 19 19 - See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt 20 20 - 21 21 - - syna,reset-delay-ms: The number of milliseconds to wait after resetting the 22 22 - device. 23 23 - 24 24 - - syna,startup-delay-ms: The number of milliseconds to wait after powering on 25 25 - the device. 26 26 - 27 27 - - vdd-supply: VDD power supply. 28 28 - See ../regulator/regulator.txt 29 29 - 30 30 - - vio-supply: VIO power supply 31 31 - See ../regulator/regulator.txt 32 32 - 33 33 - Function Parameters: 34 34 - Parameters specific to RMI functions are contained in child nodes of the rmi device 35 35 - node. Documentation for the parameters of each function can be found in: 36 36 - Documentation/devicetree/bindings/input/rmi4/rmi_f*.txt. 37 37 - 38 38 - 39 39 - 40 40 - Example: 41 41 - &i2c1 { 42 42 - rmi4-i2c-dev@2c { 43 43 - compatible = "syna,rmi4-i2c"; 44 44 - reg = <0x2c>; 45 45 - #address-cells = <1>; 46 46 - #size-cells = <0>; 47 47 - interrupt-parent = <&gpio>; 48 48 - interrupts = <4 2>; 49 49 - 50 50 - rmi4-f01@1 { 51 51 - reg = <0x1>; 52 52 - syna,nosleep-mode = <1>; 53 53 - }; 54 54 - 55 55 - rmi4-f11@11 { 56 56 - reg = <0x11>; 57 57 - touchscreen-inverted-y; 58 58 - syna,sensor-type = <2>; 59 59 - }; 60 60 - }; 61 61 - };

-56

Documentation/devicetree/bindings/input/rmi4/rmi_spi.txt

reviewed

··· 1 1 - Synaptics RMI4 SPI Device Binding 2 2 - 3 3 - The Synaptics RMI4 core is able to support RMI4 devices using different 4 4 - transports and different functions. This file describes the device tree 5 5 - bindings for devices using the SPI transport driver. Complete documentation 6 6 - for other transports and functions can be found in 7 7 - Documentation/devicetree/bindings/input/rmi4. 8 8 - 9 9 - Required Properties: 10 10 - - compatible: syna,rmi4-spi 11 11 - - reg: Chip select address for the device 12 12 - - #address-cells: Set to 1 to indicate that the function child nodes 13 13 - consist of only on uint32 value. 14 14 - - #size-cells: Set to 0 to indicate that the function child nodes do not 15 15 - have a size property. 16 16 - 17 17 - Optional Properties: 18 18 - - interrupts: interrupt which the rmi device is connected to. 19 19 - See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt 20 20 - 21 21 - - spi-rx-delay-us: microsecond delay after a read transfer. 22 22 - - spi-tx-delay-us: microsecond delay after a write transfer. 23 23 - 24 24 - Function Parameters: 25 25 - Parameters specific to RMI functions are contained in child nodes of the rmi device 26 26 - node. Documentation for the parameters of each function can be found in: 27 27 - Documentation/devicetree/bindings/input/rmi4/rmi_f*.txt. 28 28 - 29 29 - 30 30 - 31 31 - Example: 32 32 - spi@7000d800 { 33 33 - rmi4-spi-dev@0 { 34 34 - compatible = "syna,rmi4-spi"; 35 35 - reg = <0x0>; 36 36 - #address-cells = <1>; 37 37 - #size-cells = <0>; 38 38 - spi-max-frequency = <4000000>; 39 39 - spi-cpha; 40 40 - spi-cpol; 41 41 - interrupt-parent = <&gpio>; 42 42 - interrupts = <TEGRA_GPIO(K, 2) 0x2>; 43 43 - spi-rx-delay-us = <30>; 44 44 - 45 45 - rmi4-f01@1 { 46 46 - reg = <0x1>; 47 47 - syna,nosleep-mode = <1>; 48 48 - }; 49 49 - 50 50 - rmi4-f11@11 { 51 51 - reg = <0x11>; 52 52 - touchscreen-inverted-y; 53 53 - syna,sensor-type = <2>; 54 54 - }; 55 55 - }; 56 56 - };

+271

Documentation/devicetree/bindings/input/syna,rmi4.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/input/syna,rmi4.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Synaptics RMI4 compliant devices 8 8 + 9 9 + maintainers: 10 10 + - Jason A. Donenfeld <Jason@zx2c4.com> 11 11 + - Matthias Schiffer <matthias.schiffer@ew.tq-group.com 12 12 + - Vincent Huang <vincent.huang@tw.synaptics.com> 13 13 + 14 14 + description: | 15 15 + The Synaptics RMI4 (Register Mapped Interface 4) core is able to support RMI4 16 16 + devices using different transports (I2C, SPI) and different functions (e.g. 17 17 + Function 1, 2D sensors using Function 11 or 12). 18 18 + 19 19 + properties: 20 20 + compatible: 21 21 + enum: 22 22 + - syna,rmi4-i2c 23 23 + - syna,rmi4-spi 24 24 + 25 25 + reg: 26 26 + maxItems: 1 27 27 + 28 28 + '#address-cells': 29 29 + const: 1 30 30 + 31 31 + '#size-cells': 32 32 + const: 0 33 33 + 34 34 + interrupts: 35 35 + maxItems: 1 36 36 + 37 37 + reset-gpios: 38 38 + maxItems: 1 39 39 + description: Active low signal 40 40 + 41 41 + spi-cpha: true 42 42 + spi-cpol: true 43 43 + 44 44 + syna,reset-delay-ms: 45 45 + description: 46 46 + Delay to wait after resetting the device. 47 47 + 48 48 + syna,startup-delay-ms: 49 49 + description: 50 50 + Delay to wait after powering on the device. 51 51 + 52 52 + vdd-supply: true 53 53 + vio-supply: true 54 54 + 55 55 + rmi4-f01@1: 56 56 + type: object 57 57 + additionalProperties: false 58 58 + description: 59 59 + Function 1 60 60 + 61 61 + properties: 62 62 + reg: 63 63 + maxItems: 1 64 64 + 65 65 + syna,nosleep-mode: 66 66 + $ref: /schemas/types.yaml#/definitions/uint32 67 67 + enum: [0, 1, 2] 68 68 + description: 69 69 + If set the device will run at full power without sleeping. nosleep 70 70 + has 3 modes, 0 will not change the default setting, 1 will disable 71 71 + nosleep (allow sleeping), and 2 will enable nosleep (disabling 72 72 + sleep). 73 73 + 74 74 + syna,wakeup-threshold: 75 75 + $ref: /schemas/types.yaml#/definitions/uint32 76 76 + description: 77 77 + Defines the amplitude of the disturbance to the background 78 78 + capacitance that will cause the device to wake from dozing. 79 79 + 80 80 + syna,doze-holdoff-ms: 81 81 + description: 82 82 + The delay to wait after the last finger lift and the first doze 83 83 + cycle. 84 84 + 85 85 + syna,doze-interval-ms: 86 86 + description: 87 87 + The time period that the device sleeps between finger activity. 88 88 + 89 89 + required: 90 90 + - reg 91 91 + 92 92 + patternProperties: 93 93 + "^rmi4-f1[12]@1[12]$": 94 94 + type: object 95 95 + unevaluatedProperties: false 96 96 + $ref: /schemas/input/touchscreen/touchscreen.yaml# 97 97 + description: 98 98 + RMI4 Function 11 and Function 12 are for 2D touch position sensing. 99 99 + 100 100 + properties: 101 101 + reg: 102 102 + maxItems: 1 103 103 + 104 104 + syna,clip-x-low: 105 105 + $ref: /schemas/types.yaml#/definitions/uint32 106 106 + description: 107 107 + Minimum value for X. 108 108 + 109 109 + syna,clip-y-low: 110 110 + $ref: /schemas/types.yaml#/definitions/uint32 111 111 + description: 112 112 + Minimum value for Y. 113 113 + 114 114 + syna,clip-x-high: 115 115 + $ref: /schemas/types.yaml#/definitions/uint32 116 116 + description: 117 117 + Maximum value for X. 118 118 + 119 119 + syna,clip-y-high: 120 120 + $ref: /schemas/types.yaml#/definitions/uint32 121 121 + description: 122 122 + Maximum value for Y. 123 123 + 124 124 + syna,offset-x: 125 125 + $ref: /schemas/types.yaml#/definitions/uint32 126 126 + description: 127 127 + Add an offset to X. 128 128 + 129 129 + syna,offset-y: 130 130 + $ref: /schemas/types.yaml#/definitions/uint32 131 131 + description: 132 132 + Add an offset to Y. 133 133 + 134 134 + syna,delta-x-threshold: 135 135 + $ref: /schemas/types.yaml#/definitions/uint32 136 136 + description: 137 137 + Minimum distance on the X axis required to generate an interrupt in 138 138 + reduced reporting mode. 139 139 + 140 140 + syna,delta-y-threshold: 141 141 + $ref: /schemas/types.yaml#/definitions/uint32 142 142 + description: 143 143 + Minimum distance on the Y axis required to generate an interrupt in 144 144 + reduced reporting mode. 145 145 + 146 146 + syna,sensor-type: 147 147 + $ref: /schemas/types.yaml#/definitions/uint32 148 148 + enum: [1, 2] 149 149 + description: | 150 150 + Sensor type: 1 for touchscreen 2 for touchpad. 151 151 + 152 152 + syna,disable-report-mask: 153 153 + $ref: /schemas/types.yaml#/definitions/uint32 154 154 + description: 155 155 + Mask for disabling posiiton reporting. Used to disable reporing 156 156 + absolute position data. 157 157 + 158 158 + syna,rezero-wait-ms: 159 159 + description: 160 160 + Time to wait after issuing a rezero command. 161 161 + 162 162 + required: 163 163 + - reg 164 164 + 165 165 + "^rmi4-f[0-9a-f]+@[0-9a-f]+$": 166 166 + type: object 167 167 + description: 168 168 + Other functions, not documented yet. 169 169 + 170 170 + properties: 171 171 + reg: 172 172 + maxItems: 1 173 173 + 174 174 + required: 175 175 + - reg 176 176 + 177 177 + required: 178 178 + - compatible 179 179 + - reg 180 180 + 181 181 + unevaluatedProperties: false 182 182 + 183 183 + allOf: 184 184 + - $ref: /schemas/spi/spi-peripheral-props.yaml# 185 185 + 186 186 + - if: 187 187 + properties: 188 188 + compatible: 189 189 + contains: 190 190 + const: syna,rmi4-i2c 191 191 + then: 192 192 + properties: 193 193 + spi-rx-delay-us: false 194 194 + spi-tx-delay-us: false 195 195 + else: 196 196 + properties: 197 197 + syna,reset-delay-ms: false 198 198 + syna,startup-delay-ms: false 199 199 + 200 200 + examples: 201 201 + - | 202 202 + #include <dt-bindings/interrupt-controller/irq.h> 203 203 + 204 204 + i2c { 205 205 + #address-cells = <1>; 206 206 + #size-cells = <0>; 207 207 + 208 208 + touchscreen@20 { 209 209 + compatible = "syna,rmi4-i2c"; 210 210 + reg = <0x20>; 211 211 + interrupt-parent = <&gpx1>; 212 212 + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; 213 213 + 214 214 + syna,startup-delay-ms = <100>; 215 215 + vdd-supply = <&tsp_vdd>; 216 216 + vio-supply = <&ldo32_reg>; 217 217 + 218 218 + pinctrl-0 = <&touch_irq>; 219 219 + pinctrl-names = "default"; 220 220 + #address-cells = <1>; 221 221 + #size-cells = <0>; 222 222 + 223 223 + rmi4-f01@1 { 224 224 + reg = <0x1>; 225 225 + syna,nosleep-mode = <1>; 226 226 + }; 227 227 + 228 228 + rmi4-f12@12 { 229 229 + reg = <0x12>; 230 230 + syna,sensor-type = <1>; 231 231 + }; 232 232 + 233 233 + rmi4-f1a@1a { 234 234 + reg = <0x1a>; 235 235 + }; 236 236 + }; 237 237 + }; 238 238 + 239 239 + - | 240 240 + #include <dt-bindings/interrupt-controller/irq.h> 241 241 + 242 242 + spi { 243 243 + #address-cells = <1>; 244 244 + #size-cells = <0>; 245 245 + 246 246 + touchscreen@0 { 247 247 + compatible = "syna,rmi4-spi"; 248 248 + reg = <0x0>; 249 249 + interrupt-parent = <&gpx1>; 250 250 + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; 251 251 + 252 252 + spi-max-frequency = <4000000>; 253 253 + spi-rx-delay-us = <30>; 254 254 + spi-cpha; 255 255 + spi-cpol; 256 256 + 257 257 + #address-cells = <1>; 258 258 + #size-cells = <0>; 259 259 + 260 260 + rmi4-f01@1 { 261 261 + reg = <0x1>; 262 262 + syna,nosleep-mode = <1>; 263 263 + }; 264 264 + 265 265 + rmi4-f11@11 { 266 266 + reg = <0x11>; 267 267 + touchscreen-inverted-y; 268 268 + syna,sensor-type = <2>; 269 269 + }; 270 270 + }; 271 271 + };

+1 -1

Documentation/devicetree/bindings/input/touchscreen/tsc2007.txt

reviewed

··· 6 6 - ti,x-plate-ohms: X-plate resistance in ohms. 7 7 8 8 Optional properties: 9 9 - - gpios: the interrupt gpio the chip is connected to (trough the penirq pin). 9 9 + - gpios: the interrupt gpio the chip is connected to (through the penirq pin). 10 10 The penirq pin goes to low when the panel is touched. 11 11 (see GPIO binding[1] for more details). 12 12 - interrupts: (gpio) interrupt to which the chip is connected

+1 -1

Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml

reviewed

··· 49 49 50 50 The 2nd cell contains the interrupt number for the interrupt type. 51 51 SPI interrupts are in the range [0-987]. PPI interrupts are in the 52 52 - range [0-15]. Extented SPI interrupts are in the range [0-1023]. 52 52 + range [0-15]. Extended SPI interrupts are in the range [0-1023]. 53 53 Extended PPI interrupts are in the range [0-127]. 54 54 55 55 The 3rd cell is the flags, encoded as follows:

+1 -1

Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt

reviewed

··· 70 70 25: DMA9 71 71 26: DMA10 72 72 27: DMA11-14 - shared interrupt for DMA 11 to 14 73 73 - 28: DMAALL - triggers on all dma interrupts (including chanel 15) 73 73 + 28: DMAALL - triggers on all dma interrupts (including channel 15) 74 74 29: AUX 75 75 30: ARM 76 76 31: VPUDMA

+1 -1

Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml

reviewed

··· 59 59 .. 60 60 31 ........................ X 61 61 62 62 - The BCM3380 Level 1 / Level 2 interrrupt controller shows up in various forms 62 62 + The BCM3380 Level 1 / Level 2 interrupt controller shows up in various forms 63 63 on many BCM338x/BCM63xx chipsets. It has the following properties: 64 64 65 65 - outputs a single interrupt signal to its interrupt controller parent

+1

Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml

reviewed

··· 31 31 - qcom,sc7180-pdc 32 32 - qcom,sc7280-pdc 33 33 - qcom,sc8280xp-pdc 34 34 + - qcom,sdm670-pdc 34 35 - qcom,sdm845-pdc 35 36 - qcom,sdx55-pdc 36 37 - qcom,sdx65-pdc

+1 -1

Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/interrupt-controller/ti,pruss-intc.yaml#

+1 -1

Documentation/devicetree/bindings/iommu/xen,grant-dma.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/iommu/xen,grant-dma.yaml#

+4 -4

Documentation/devicetree/bindings/ipmi/aspeed,ast2400-kcs-bmc.yaml

reviewed

··· 41 41 - description: STR register 42 42 43 43 aspeed,lpc-io-reg: 44 44 - $ref: '/schemas/types.yaml#/definitions/uint32-array' 44 44 + $ref: /schemas/types.yaml#/definitions/uint32-array 45 45 minItems: 1 46 46 maxItems: 2 47 47 description: | ··· 50 50 status address may be optionally provided. 51 51 52 52 aspeed,lpc-interrupts: 53 53 - $ref: "/schemas/types.yaml#/definitions/uint32-array" 53 53 + $ref: /schemas/types.yaml#/definitions/uint32-array 54 54 minItems: 2 55 55 maxItems: 2 56 56 description: | ··· 63 63 64 64 kcs_chan: 65 65 deprecated: true 66 66 - $ref: '/schemas/types.yaml#/definitions/uint32' 66 66 + $ref: /schemas/types.yaml#/definitions/uint32 67 67 description: The LPC channel number in the controller 68 68 69 69 kcs_addr: 70 70 deprecated: true 71 71 - $ref: '/schemas/types.yaml#/definitions/uint32' 71 71 + $ref: /schemas/types.yaml#/definitions/uint32 72 72 description: The host CPU IO map address 73 73 74 74 required:

+1 -1

Documentation/devicetree/bindings/ipmi/ipmi-ipmb.yaml

reviewed

··· 18 18 19 19 device_type: 20 20 items: 21 21 - - const: "ipmi" 21 21 + - const: ipmi 22 22 23 23 reg: 24 24 maxItems: 1

+1 -1

Documentation/devicetree/bindings/ipmi/ipmi-smic.yaml

reviewed

··· 20 20 21 21 device_type: 22 22 items: 23 23 - - const: "ipmi" 23 23 + - const: ipmi 24 24 25 25 reg: 26 26 maxItems: 1

+1 -1

Documentation/devicetree/bindings/leds/backlight/mediatek,mt6370-backlight.yaml

reviewed

··· 66 66 67 67 mediatek,bled-ocp-shutdown: 68 68 description: | 69 69 - Enable the backlight shutdown when OCP level triggerred. 69 69 + Enable the backlight shutdown when OCP level triggered. 70 70 type: boolean 71 71 72 72 mediatek,bled-ocp-microamp:

+2 -2

Documentation/devicetree/bindings/leds/leds-lp55xx.yaml

reviewed

··· 106 106 107 107 max-cur: 108 108 $ref: /schemas/types.yaml#/definitions/uint8 109 109 - description: Maximun current at each LED channel. 109 109 + description: Maximum current at each LED channel. 110 110 111 111 reg: 112 112 maximum: 8 ··· 129 129 130 130 max-cur: 131 131 $ref: /schemas/types.yaml#/definitions/uint8 132 132 - description: Maximun current at each LED channel. 132 132 + description: Maximum current at each LED channel. 133 133 134 134 reg: 135 135 description: |

+1 -1

Documentation/devicetree/bindings/leds/leds-qcom-lpg.yaml

reviewed

··· 56 56 description: > 57 57 A list of integer pairs, where each pair represent the dtest line the 58 58 particular channel should be connected to and the flags denoting how the 59 59 - value should be outputed, as defined in the datasheet. The number of 59 59 + value should be outputted, as defined in the datasheet. The number of 60 60 pairs should be the same as the number of channels. 61 61 items: 62 62 items:

+1 -1

Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.txt

reviewed

··· 29 29 where N is the value specified by 2nd cell above. If FlexRM 30 30 does not get required number of completion messages in time 31 31 specified by this cell then it will inject one MSI interrupt 32 32 - to CPU provided atleast one completion message is available. 32 32 + to CPU provided at least one completion message is available. 33 33 34 34 Optional properties: 35 35 --------------------

+2 -2

Documentation/devicetree/bindings/mailbox/ti,omap-mailbox.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/mailbox/ti,omap-mailbox.yaml# ··· 159 159 a corresponding sysc interconnect node. 160 160 161 161 This property is only needed on some legacy OMAP SoCs which have not 162 162 - yet been converted to the ti,sysc interconnect hierarachy, but is 162 162 + yet been converted to the ti,sysc interconnect hierarchy, but is 163 163 otherwise considered obsolete. 164 164 165 165 patternProperties:

+1 -1

Documentation/devicetree/bindings/media/i2c/toshiba,tc358746.yaml

reviewed

··· 12 12 description: |- 13 13 The Toshiba TC358746 converts a parallel video stream into a MIPI CSI-2 14 14 stream. The direction can be either parallel-in -> csi-out or csi-in -> 15 15 - parallel-out The chip is programmable trough I2C and SPI but the SPI 15 15 + parallel-out The chip is programmable through I2C and SPI but the SPI 16 16 interface is only supported in parallel-in -> csi-out mode. 17 17 18 18 Note that the current device tree bindings only support the

+1 -1

Documentation/devicetree/bindings/media/i2c/tvp5150.txt

reviewed

··· 53 53 ============================== 54 54 55 55 - sdtv-standards: Set the possible signals to which the hardware tries to lock 56 56 - instead of using the autodetection mechnism. Please look at 56 56 + instead of using the autodetection mechanism. Please look at 57 57 [1] for more information. 58 58 59 59 [1] Documentation/devicetree/bindings/display/connector/analog-tv-connector.yaml.

+1 -1

Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml

reviewed

··· 36 36 controls the information of each hardware independent which include clk/power/irq. 37 37 38 38 There are two workqueues in parent device: lat workqueue and core workqueue. They are used 39 39 - to lat and core hardware deocder. Lat workqueue need to get input bitstream and lat buffer, 39 39 + to lat and core hardware decoder. Lat workqueue need to get input bitstream and lat buffer, 40 40 then enable lat to decode, writing the result to lat buffer, dislabe hardware when lat decode 41 41 done. Core workqueue need to get lat buffer and output buffer, then enable core to decode, 42 42 writing the result to output buffer, disable hardware when core decode done. These two

+2 -2

Documentation/devicetree/bindings/media/qcom,msm8916-venus.yaml

reviewed

··· 40 40 41 41 properties: 42 42 compatible: 43 43 - const: "venus-decoder" 43 43 + const: venus-decoder 44 44 45 45 required: 46 46 - compatible ··· 52 52 53 53 properties: 54 54 compatible: 55 55 - const: "venus-encoder" 55 55 + const: venus-encoder 56 56 57 57 required: 58 58 - compatible

+1 -1

Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml

reviewed

··· 67 67 minimum: 0 68 68 maximum: 31 69 69 description: the hardware id of this larb. It's only required when this 70 70 - hardward id is not consecutive from its M4U point of view. 70 70 + hardware id is not consecutive from its M4U point of view. 71 71 72 72 required: 73 73 - compatible

+2 -2

Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-dmc.yaml

reviewed

··· 152 152 $ref: /schemas/types.yaml#/definitions/uint32 153 153 description: 154 154 When the DRAM type is DDR3, this parameter defines the phy side CA line 155 155 - (incluing command line, address line and clock line) drive strength. 155 155 + (including command line, address line and clock line) drive strength. 156 156 default: 40 157 157 158 158 rockchip,phy_ddr3_dq_drv: ··· 305 305 description: 306 306 Defines the self-refresh power down idle period in which memories are 307 307 placed into self-refresh power down mode if bus is idle for 308 308 - srpd_lite_idle nanoseonds. This parameter is for LPDDR4 only. 308 308 + srpd_lite_idle nanoseconds. This parameter is for LPDDR4 only. 309 309 310 310 rockchip,standby-idle-ns: 311 311 description:

+1 -1

Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml

reviewed

··· 12 12 13 13 description: 14 14 The Zynq DDR ECC controller has an optional ECC support in half-bus width 15 15 - (16-bit) configuration. It is cappable of correcting single bit ECC errors 15 15 + (16-bit) configuration. It is capable of correcting single bit ECC errors 16 16 and detecting double bit ECC errors. 17 17 18 18 properties:

+1 -1

Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml

reviewed

··· 27 27 as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART 28 28 management and bus snoop configuration. 29 29 30 30 - * A set of SuperIO[3] scratch registers enableing implementation of e.g. custom 30 30 + * A set of SuperIO[3] scratch registers enabling implementation of e.g. custom 31 31 hardware management protocols for handover between the host and baseboard 32 32 management controller. 33 33

+1 -1

Documentation/devicetree/bindings/mfd/qcom,pm8008.yaml

reviewed

··· 7 7 title: Qualcomm Technologies, Inc. PM8008 PMIC 8 8 9 9 maintainers: 10 10 - - Guru Das Srinagesh <gurus@codeaurora.org> 10 10 + - Guru Das Srinagesh <quic_gurus@quicinc.com> 11 11 12 12 description: | 13 13 Qualcomm Technologies, Inc. PM8008 is a dedicated camera PMIC that integrates

+2 -2

Documentation/devicetree/bindings/mfd/rohm,bd9576-pmic.yaml

reviewed

··· 34 34 BD9576 and BD9573 VOUT1 regulator enable state can be individually 35 35 controlled by a GPIO. This is dictated by state of vout1-en pin during 36 36 the PMIC startup. If vout1-en is LOW during PMIC startup then the VOUT1 37 37 - enable sate is controlled via this pin. Set this property if vout1-en 37 37 + enable state is controlled via this pin. Set this property if vout1-en 38 38 is wired to be down at PMIC start-up. 39 39 type: boolean 40 40 ··· 61 61 rohm,hw-timeout-ms: 62 62 maxItems: 2 63 63 description: 64 64 - Watchog timeout in milliseconds. If single value is given it is 64 64 + Watchdog timeout in milliseconds. If single value is given it is 65 65 the maximum timeout. Eg. if pinging watchdog is not done within this time 66 66 limit the watchdog will be triggered. If two values are given watchdog 67 67 is configured in "window mode". Then first value is limit for short-ping

+8 -8

Documentation/devicetree/bindings/mfd/stericsson,ab8500.yaml

reviewed

··· 313 313 - const: audioclk 314 314 315 315 stericsson,earpeice-cmv: 316 316 - description: Earpeice voltage 316 316 + description: Earpiece voltage 317 317 $ref: /schemas/types.yaml#/definitions/uint32 318 318 enum: [ 950, 1100, 1270, 1580 ] 319 319 ··· 337 337 with power. 338 338 339 339 ab8500_ldo_aux1: 340 340 - description: The voltage for the auxilary LDO regulator 1 340 340 + description: The voltage for the auxiliary LDO regulator 1 341 341 type: object 342 342 $ref: ../regulator/regulator.yaml# 343 343 unevaluatedProperties: false 344 344 345 345 ab8500_ldo_aux2: 346 346 - description: The voltage for the auxilary LDO regulator 2 346 346 + description: The voltage for the auxiliary LDO regulator 2 347 347 type: object 348 348 $ref: ../regulator/regulator.yaml# 349 349 unevaluatedProperties: false 350 350 351 351 ab8500_ldo_aux3: 352 352 - description: The voltage for the auxilary LDO regulator 3 352 352 + description: The voltage for the auxiliary LDO regulator 3 353 353 type: object 354 354 $ref: ../regulator/regulator.yaml# 355 355 unevaluatedProperties: false 356 356 357 357 ab8500_ldo_aux4: 358 358 - description: The voltage for the auxilary LDO regulator 4 358 358 + description: The voltage for the auxiliary LDO regulator 4 359 359 only present on AB8505 360 360 type: object 361 361 $ref: ../regulator/regulator.yaml# 362 362 unevaluatedProperties: false 363 363 364 364 ab8500_ldo_aux5: 365 365 - description: The voltage for the auxilary LDO regulator 5 365 365 + description: The voltage for the auxiliary LDO regulator 5 366 366 only present on AB8505 367 367 type: object 368 368 $ref: ../regulator/regulator.yaml# 369 369 unevaluatedProperties: false 370 370 371 371 ab8500_ldo_aux6: 372 372 - description: The voltage for the auxilary LDO regulator 6 372 372 + description: The voltage for the auxiliary LDO regulator 6 373 373 only present on AB8505 374 374 type: object 375 375 $ref: ../regulator/regulator.yaml# ··· 378 378 # There is never any AUX7 regulator which is confusing 379 379 380 380 ab8500_ldo_aux8: 381 381 - description: The voltage for the auxilary LDO regulator 8 381 381 + description: The voltage for the auxiliary LDO regulator 8 382 382 only present on AB8505 383 383 type: object 384 384 $ref: ../regulator/regulator.yaml#

+1 -1

Documentation/devicetree/bindings/mfd/stericsson,db8500-prcmu.yaml

reviewed

··· 107 107 $ref: ../regulator/regulator.yaml# 108 108 109 109 db8500_vrf1: 110 110 - description: RF transciever voltage regulator. 110 110 + description: RF transceiver voltage regulator. 111 111 type: object 112 112 $ref: ../regulator/regulator.yaml# 113 113

+2 -2

Documentation/devicetree/bindings/mips/loongson/ls2k-reset.yaml

reviewed

··· 1 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 - $id: "http://devicetree.org/schemas/mips/loongson/ls2k-reset.yaml#" 5 5 - $schema: "http://devicetree.org/meta-schemas/core.yaml#" 4 4 + $id: http://devicetree.org/schemas/mips/loongson/ls2k-reset.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 7 title: Loongson 2K1000 PM Controller 8 8

+2 -2

Documentation/devicetree/bindings/mips/loongson/rs780e-acpi.yaml

reviewed

··· 1 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 - $id: "http://devicetree.org/schemas/mips/loongson/rs780e-acpi.yaml#" 5 5 - $schema: "http://devicetree.org/meta-schemas/core.yaml#" 4 4 + $id: http://devicetree.org/schemas/mips/loongson/rs780e-acpi.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 7 title: Loongson RS780E PCH ACPI Controller 8 8

+2 -2

Documentation/devicetree/bindings/misc/intel,ixp4xx-ahb-queue-manager.yaml

reviewed

··· 2 2 # Copyright 2019 Linaro Ltd. 3 3 %YAML 1.2 4 4 --- 5 5 - $id: "http://devicetree.org/schemas/misc/intel,ixp4xx-ahb-queue-manager.yaml#" 6 6 - $schema: "http://devicetree.org/meta-schemas/core.yaml#" 5 5 + $id: http://devicetree.org/schemas/misc/intel,ixp4xx-ahb-queue-manager.yaml# 6 6 + $schema: http://devicetree.org/meta-schemas/core.yaml# 7 7 8 8 title: Intel IXP4xx AHB Queue Manager 9 9

+2 -2

Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml

reviewed

··· 71 71 marvell,xenon-phy-type: 72 72 $ref: /schemas/types.yaml#/definitions/string 73 73 enum: 74 74 - - "emmc 5.1 phy" 75 75 - - "emmc 5.0 phy" 74 74 + - emmc 5.1 phy 75 75 + - emmc 5.0 phy 76 76 description: | 77 77 Xenon support multiple types of PHYs. To select eMMC 5.1 PHY, set: 78 78 marvell,xenon-phy-type = "emmc 5.1 phy" eMMC 5.1 PHY is the default

+1 -1

Documentation/devicetree/bindings/mmc/pxa-mmc.txt

reviewed

··· 9 9 Optional properties: 10 10 - marvell,detect-delay-ms: sets the detection delay timeout in ms. 11 11 12 12 - In addition to the properties described in this docuent, the details 12 12 + In addition to the properties described in this document, the details 13 13 described in mmc.txt are supported. 14 14 15 15 Examples:

+1 -1

Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt

reviewed

··· 95 95 | card | -- CIRQ --> | hsmmc | -- IRQ --> | CPU | 96 96 ------ ------- ----- 97 97 98 98 - In suspend the fclk is off and the module is disfunctional. Even register reads 98 98 + In suspend the fclk is off and the module is dysfunctional. Even register reads 99 99 will fail. A small logic in the host will request fclk restore, when an 100 100 external event is detected. Once the clock is restored, the host detects the 101 101 event normally. Since am33xx doesn't have this line it never wakes from

+2 -2

Documentation/devicetree/bindings/mtd/microchip,mchp48l640.yaml

reviewed

··· 1 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 - $id: "http://devicetree.org/schemas/mtd/microchip,mchp48l640.yaml#" 5 5 - $schema: "http://devicetree.org/meta-schemas/core.yaml#" 4 4 + $id: http://devicetree.org/schemas/mtd/microchip,mchp48l640.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 7 title: Microchip 48l640 (and similar) serial EERAM 8 8

+1 -1

Documentation/devicetree/bindings/net/brcm,bcm7445-switch-v4.0.txt

reviewed

··· 1 1 - * Broadcom Starfighter 2 integrated swich 1 1 + * Broadcom Starfighter 2 integrated switch 2 2 3 3 See dsa/brcm,bcm7445-switch-v4.0.yaml for the documentation. 4 4

+1 -1

Documentation/devicetree/bindings/net/can/cc770.txt

reviewed

··· 26 26 will be disabled. 27 27 28 28 - bosch,slew-rate : slew rate of the CLKOUT signal. If not specified, 29 29 - a resonable value will be calculated. 29 29 + a reasonable value will be calculated. 30 30 31 31 - bosch,disconnect-rx0-input : see data sheet. 32 32

+1 -1

Documentation/devicetree/bindings/net/dsa/brcm,sf2.yaml

reviewed

··· 4 4 $id: http://devicetree.org/schemas/net/dsa/brcm,sf2.yaml# 5 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 7 - title: Broadcom Starfighter 2 integrated swich 7 7 + title: Broadcom Starfighter 2 integrated switch 8 8 9 9 maintainers: 10 10 - Florian Fainelli <f.fainelli@gmail.com>

+1 -1

Documentation/devicetree/bindings/net/ethernet-phy.yaml

reviewed

··· 110 110 $ref: /schemas/types.yaml#/definitions/flag 111 111 description: 112 112 If set, indicates that PHY will disable swap of the 113 113 - TX/RX lanes. This property allows the PHY to work correcly after 113 113 + TX/RX lanes. This property allows the PHY to work correctly after 114 114 e.g. wrong bootstrap configuration caused by issues in PCB 115 115 layout design. 116 116

+102

Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: GPL-2.0 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/net/faraday,ftgmac100.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Faraday Technology FTGMAC100 gigabit ethernet controller 8 8 + 9 9 + allOf: 10 10 + - $ref: ethernet-controller.yaml# 11 11 + 12 12 + maintainers: 13 13 + - Po-Yu Chuang <ratbert@faraday-tech.com> 14 14 + 15 15 + properties: 16 16 + compatible: 17 17 + oneOf: 18 18 + - const: faraday,ftgmac100 19 19 + - items: 20 20 + - enum: 21 21 + - aspeed,ast2400-mac 22 22 + - aspeed,ast2500-mac 23 23 + - aspeed,ast2600-mac 24 24 + - const: faraday,ftgmac100 25 25 + 26 26 + reg: 27 27 + maxItems: 1 28 28 + 29 29 + interrupts: 30 30 + maxItems: 1 31 31 + 32 32 + clocks: 33 33 + minItems: 1 34 34 + items: 35 35 + - description: MAC IP clock 36 36 + - description: RMII RCLK gate for AST2500/2600 37 37 + 38 38 + clock-names: 39 39 + minItems: 1 40 40 + items: 41 41 + - const: MACCLK 42 42 + - const: RCLK 43 43 + 44 44 + phy-mode: 45 45 + enum: 46 46 + - rgmii 47 47 + - rmii 48 48 + 49 49 + phy-handle: true 50 50 + 51 51 + use-ncsi: 52 52 + description: 53 53 + Use the NC-SI stack instead of an MDIO PHY. Currently assumes 54 54 + rmii (100bT) but kept as a separate property in case NC-SI grows support 55 55 + for a gigabit link. 56 56 + type: boolean 57 57 + 58 58 + no-hw-checksum: 59 59 + description: 60 60 + Used to disable HW checksum support. Here for backward 61 61 + compatibility as the driver now should have correct defaults based on 62 62 + the SoC. 63 63 + type: boolean 64 64 + deprecated: true 65 65 + 66 66 + mdio: 67 67 + $ref: /schemas/net/mdio.yaml# 68 68 + 69 69 + required: 70 70 + - compatible 71 71 + - reg 72 72 + - interrupts 73 73 + 74 74 + unevaluatedProperties: false 75 75 + 76 76 + examples: 77 77 + - | 78 78 + ethernet@1e660000 { 79 79 + compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; 80 80 + reg = <0x1e660000 0x180>; 81 81 + interrupts = <2>; 82 82 + use-ncsi; 83 83 + }; 84 84 + 85 85 + ethernet@1e680000 { 86 86 + compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; 87 87 + reg = <0x1e680000 0x180>; 88 88 + interrupts = <2>; 89 89 + 90 90 + phy-handle = <&phy>; 91 91 + phy-mode = "rgmii"; 92 92 + 93 93 + mdio { 94 94 + #address-cells = <1>; 95 95 + #size-cells = <0>; 96 96 + 97 97 + phy: ethernet-phy@1 { 98 98 + compatible = "ethernet-phy-ieee802.3-c22"; 99 99 + reg = <1>; 100 100 + }; 101 101 + }; 102 102 + };

-67

Documentation/devicetree/bindings/net/ftgmac100.txt

reviewed

··· 1 1 - * Faraday Technology FTGMAC100 gigabit ethernet controller 2 2 - 3 3 - Required properties: 4 4 - - compatible: "faraday,ftgmac100" 5 5 - 6 6 - Must also contain one of these if used as part of an Aspeed AST2400 7 7 - or 2500 family SoC as they have some subtle tweaks to the 8 8 - implementation: 9 9 - 10 10 - - "aspeed,ast2400-mac" 11 11 - - "aspeed,ast2500-mac" 12 12 - - "aspeed,ast2600-mac" 13 13 - 14 14 - - reg: Address and length of the register set for the device 15 15 - - interrupts: Should contain ethernet controller interrupt 16 16 - 17 17 - Optional properties: 18 18 - - phy-handle: See ethernet.txt file in the same directory. 19 19 - - phy-mode: See ethernet.txt file in the same directory. If the property is 20 20 - absent, "rgmii" is assumed. Supported values are "rgmii*" and "rmii" for 21 21 - aspeed parts. Other (unknown) parts will accept any value. 22 22 - - use-ncsi: Use the NC-SI stack instead of an MDIO PHY. Currently assumes 23 23 - rmii (100bT) but kept as a separate property in case NC-SI grows support 24 24 - for a gigabit link. 25 25 - - no-hw-checksum: Used to disable HW checksum support. Here for backward 26 26 - compatibility as the driver now should have correct defaults based on 27 27 - the SoC. 28 28 - - clocks: In accordance with the generic clock bindings. Must describe the MAC 29 29 - IP clock, and optionally an RMII RCLK gate for the AST2500/AST2600. The 30 30 - required MAC clock must be the first cell. 31 31 - - clock-names: 32 32 - 33 33 - - "MACCLK": The MAC IP clock 34 34 - - "RCLK": Clock gate for the RMII RCLK 35 35 - 36 36 - Optional subnodes: 37 37 - - mdio: See mdio.txt file in the same directory. 38 38 - 39 39 - Example: 40 40 - 41 41 - mac0: ethernet@1e660000 { 42 42 - compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; 43 43 - reg = <0x1e660000 0x180>; 44 44 - interrupts = <2>; 45 45 - use-ncsi; 46 46 - }; 47 47 - 48 48 - Example with phy-handle: 49 49 - 50 50 - mac1: ethernet@1e680000 { 51 51 - compatible = "aspeed,ast2500-mac", "faraday,ftgmac100"; 52 52 - reg = <0x1e680000 0x180>; 53 53 - interrupts = <2>; 54 54 - 55 55 - phy-handle = <&phy>; 56 56 - phy-mode = "rgmii"; 57 57 - 58 58 - mdio { 59 59 - #address-cells = <1>; 60 60 - #size-cells = <0>; 61 61 - 62 62 - phy: ethernet-phy@1 { 63 63 - compatible = "ethernet-phy-ieee802.3-c22"; 64 64 - reg = <1>; 65 65 - }; 66 66 - }; 67 67 - };

+1 -1

Documentation/devicetree/bindings/net/mediatek-dwmac.yaml

reviewed

··· 129 129 type: boolean 130 130 description: 131 131 If present, indicates that MAC supports WOL(Wake-On-LAN), and MAC WOL will be enabled. 132 132 - Otherwise, PHY WOL is perferred. 132 132 + Otherwise, PHY WOL is preferred. 133 133 134 134 required: 135 135 - compatible

+1 -1

Documentation/devicetree/bindings/net/microchip,lan95xx.yaml

reviewed

··· 33 33 - usb424,9906 # SMSC9505A USB Ethernet Device (HAL) 34 34 - usb424,9907 # SMSC9500 USB Ethernet Device (Alternate ID) 35 35 - usb424,9908 # SMSC9500A USB Ethernet Device (Alternate ID) 36 36 - - usb424,9909 # SMSC9512/9514 USB Hub & Ethernet Devic. ID) 36 36 + - usb424,9909 # SMSC9512/9514 USB Hub & Ethernet Device ID) 37 37 - usb424,9e00 # SMSC9500A USB Ethernet Device 38 38 - usb424,9e01 # SMSC9505A USB Ethernet Device 39 39 - usb424,9e08 # SMSC LAN89530 USB Ethernet Device

+2 -2

Documentation/devicetree/bindings/net/nfc/marvell,nci.yaml

reviewed

··· 37 37 type: boolean 38 38 description: | 39 39 For I2C type of connection. Specifies that the chip read event shall be 40 40 - trigged on falling edge. 40 40 + triggered on falling edge. 41 41 42 42 i2c-int-rising: 43 43 type: boolean 44 44 description: | 45 45 For I2C type of connection. Specifies that the chip read event shall be 46 46 - trigged on rising edge. 46 46 + triggered on rising edge. 47 47 48 48 break-control: 49 49 type: boolean

+2 -2

Documentation/devicetree/bindings/net/samsung-sxgbe.txt

reviewed

··· 5 5 - reg: Address and length of the register set for the device 6 6 - interrupts: Should contain the SXGBE interrupts 7 7 These interrupts are ordered by fixed and follows variable 8 8 - trasmit DMA interrupts, receive DMA interrupts and lpi interrupt. 8 8 + transmit DMA interrupts, receive DMA interrupts and lpi interrupt. 9 9 index 0 - this is fixed common interrupt of SXGBE and it is always 10 10 available. 11 11 - index 1 to 25 - 8 variable trasmit interrupts, variable 16 receive interrupts 11 11 + index 1 to 25 - 8 variable transmit interrupts, variable 16 receive interrupts 12 12 and 1 optional lpi interrupt. 13 13 - phy-mode: String, operation mode of the PHY interface. 14 14 Supported values are: "sgmii", "xgmii".

+1 -1

Documentation/devicetree/bindings/net/snps,dwc-qos-ethernet.txt

reviewed

··· 110 110 It depends on the SoC configuration. 111 111 - snps,read-requests: Number of read requests that the AXI port can issue. 112 112 It depends on the SoC configuration. 113 113 - - snps,burst-map: Bitmap of allowed AXI burst lengts, with the LSB 113 113 + - snps,burst-map: Bitmap of allowed AXI burst lengths, with the LSB 114 114 representing 4, then 8 etc. 115 115 - snps,txpbl: DMA Programmable burst length for the TX DMA 116 116 - snps,rxpbl: DMA Programmable burst length for the RX DMA

+1 -1

Documentation/devicetree/bindings/net/sti-dwmac.txt

reviewed

··· 21 21 MAC can generate it. 22 22 - st,tx-retime-src: This specifies which clk is wired up to the mac for 23 23 retimeing tx lines. This is totally board dependent and can take one of the 24 24 - posssible values from "txclk", "clk_125" or "clkgen". 24 24 + possible values from "txclk", "clk_125" or "clkgen". 25 25 If not passed, the internal clock will be used by default. 26 26 - sti-ethclk: this is the phy clock. 27 27 - sti-clkconf: this is an extra sysconfig register, available in new SoCs,

+1 -1

Documentation/devicetree/bindings/nios2/nios2.txt

reviewed

··· 23 23 - altr,tlb-num-ways: Specifies the number of set-associativity ways in the TLB. 24 24 - altr,tlb-num-entries: Specifies the number of entries in the TLB. 25 25 - altr,tlb-ptr-sz: Specifies size of TLB pointer. 26 26 - - altr,has-mul: Specifies CPU hardware multipy support, should be 1. 26 26 + - altr,has-mul: Specifies CPU hardware multiply support, should be 1. 27 27 - altr,has-mmu: Specifies CPU support MMU support, should be 1. 28 28 - altr,has-initda: Specifies CPU support initda instruction, should be 1. 29 29 - altr,reset-addr: Specifies CPU reset address

+1 -1

Documentation/devicetree/bindings/nvmem/layouts/onie,tlv-layout.yaml

reviewed

··· 14 14 infrastructure shall provide a non-volatile memory with a table whose the 15 15 content is well specified and gives many information about the manufacturer 16 16 (name, country of manufacture, etc) as well as device caracteristics (serial 17 17 - number, hardware version, mac addresses, etc). The underlaying device type 17 17 + number, hardware version, mac addresses, etc). The underlying device type 18 18 (flash, EEPROM,...) is not specified. The exact location of each value is also 19 19 dynamic and should be discovered at run time because it depends on the 20 20 parameters the manufacturer decided to embed.

+70

Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml

reviewed

··· 60 60 - const: aux 61 61 - const: pipe 62 62 63 63 + interrupts: 64 64 + items: 65 65 + - description: 66 66 + Combined system interrupt, which is used to signal the following 67 67 + interrupts - phy_link_up, dll_link_up, link_req_rst_not, hp_pme, 68 68 + hp, hp_msi, link_auto_bw, link_auto_bw_msi, bw_mgt, bw_mgt_msi, 69 69 + edma_wr, edma_rd, dpa_sub_upd, rbar_update, link_eq_req, ep_elbi_app 70 70 + - description: 71 71 + Combined PM interrupt, which is used to signal the following 72 72 + interrupts - linkst_in_l1sub, linkst_in_l1, linkst_in_l2, 73 73 + linkst_in_l0s, linkst_out_l1sub, linkst_out_l1, linkst_out_l2, 74 74 + linkst_out_l0s, pm_dstate_update 75 75 + - description: 76 76 + Combined message interrupt, which is used to signal the following 77 77 + interrupts - ven_msg, unlock_msg, ltr_msg, cfg_pme, cfg_pme_msi, 78 78 + pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active 79 79 + - description: 80 80 + Combined legacy interrupt, which is used to signal the following 81 81 + interrupts - inta, intb, intc, intd 82 82 + - description: 83 83 + Combined error interrupt, which is used to signal the following 84 84 + interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout, 85 85 + tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx, 86 86 + nf_err_rx, f_err_rx, radm_qoverflow 87 87 + 88 88 + interrupt-names: 89 89 + items: 90 90 + - const: sys 91 91 + - const: pmc 92 92 + - const: msg 93 93 + - const: legacy 94 94 + - const: err 95 95 + 96 96 + legacy-interrupt-controller: 97 97 + description: Interrupt controller node for handling legacy PCI interrupts. 98 98 + type: object 99 99 + additionalProperties: false 100 100 + properties: 101 101 + "#address-cells": 102 102 + const: 0 103 103 + 104 104 + "#interrupt-cells": 105 105 + const: 1 106 106 + 107 107 + interrupt-controller: true 108 108 + 109 109 + interrupts: 110 110 + items: 111 111 + - description: combined legacy interrupt 112 112 + required: 113 113 + - "#address-cells" 114 114 + - "#interrupt-cells" 115 115 + - interrupt-controller 116 116 + - interrupts 117 117 + 63 118 msi-map: true 64 119 65 120 num-lanes: true ··· 163 108 164 109 examples: 165 110 - | 111 111 + #include <dt-bindings/interrupt-controller/arm-gic.h> 166 112 167 113 bus { 168 114 #address-cells = <2>; ··· 183 127 "aclk_dbi", "pclk", 184 128 "aux"; 185 129 device_type = "pci"; 130 130 + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 131 131 + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 132 132 + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 133 133 + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 134 134 + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 135 135 + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 186 136 linux,pci-domain = <2>; 187 137 max-link-speed = <2>; 188 138 msi-map = <0x2000 &its 0x2000 0x1000>; ··· 202 140 reset-names = "pipe"; 203 141 #address-cells = <3>; 204 142 #size-cells = <2>; 143 143 + 144 144 + legacy-interrupt-controller { 145 145 + interrupt-controller; 146 146 + #address-cells = <0>; 147 147 + #interrupt-cells = <1>; 148 148 + interrupt-parent = <&gic>; 149 149 + interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>; 150 150 + }; 205 151 }; 206 152 }; 207 153 ...

+14 -4

Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml

reviewed

··· 25 25 allOf: 26 26 - $ref: /schemas/pci/pci-bus.yaml# 27 27 - $ref: /schemas/pci/snps,dw-pcie-common.yaml# 28 28 + - if: 29 29 + not: 30 30 + required: 31 31 + - msi-map 32 32 + then: 33 33 + properties: 34 34 + interrupt-names: 35 35 + contains: 36 36 + const: msi 28 37 29 38 properties: 30 39 reg: ··· 197 188 Link Control register). 198 189 const: bw_mg 199 190 - description: 191 191 + Combined Legacy A/B/C/D interrupt signal. See "^int(a|b|c|d)$" for 192 192 + details. 193 193 + const: legacy 194 194 + - description: 200 195 Vendor-specific IRQ names. Consider using the generic names above 201 196 for new bindings. 202 197 oneOf: 203 198 - description: See native "app" IRQ for details 204 204 - enum: [ intr ] 205 205 - allOf: 206 206 - - contains: 207 207 - const: msi 199 199 + enum: [ intr, sys, pmc, msg, err ] 208 200 209 201 additionalProperties: true 210 202

+1 -1

Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/phy/mediatek,mt7621-pci-phy.yaml#

+1 -1

Documentation/devicetree/bindings/phy/nvidia,tegra210-xusb-padctl.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#

+1 -1

Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt

reviewed

··· 14 14 - #size-cells: Must be 0. 15 15 16 16 The INNO USB2 PHY device should be a child node of peripheral controller that 17 17 - contains the PHY configuration register, and each device suppports up to 2 PHY 17 17 + contains the PHY configuration register, and each device supports up to 2 PHY 18 18 ports which are represented as child nodes of INNO USB2 PHY device. 19 19 20 20 Required properties for PHY port node:

+1 -1

Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt

reviewed

··· 8 8 - clocks: Must contain an entry for each entry in clock-names. 9 9 See ../clock/clock-bindings.txt for details. 10 10 - clock-names: Must include "usb_phy". 11 11 - - img,cr-top: Must constain a phandle to the CR_TOP syscon node. 11 11 + - img,cr-top: Must contain a phandle to the CR_TOP syscon node. 12 12 - img,refclk: Indicates the reference clock source for the USB PHY. 13 13 See <dt-bindings/phy/phy-pistachio-usb.h> for a list of valid values. 14 14

+1 -1

Documentation/devicetree/bindings/phy/pxa1928-usb-phy.txt

reviewed

··· 4 4 - compatible: "marvell,pxa1928-usb-phy" or "marvell,pxa1928-hsic-phy" 5 5 - reg: base address and length of the registers 6 6 - clocks - A single clock. From common clock binding. 7 7 - - #phys-cells: should be 0. From commmon phy binding. 7 7 + - #phys-cells: should be 0. From common phy binding. 8 8 - resets: reference to the reset controller 9 9 10 10 Example:

+1 -1

Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml

reviewed

··· 10 10 - Heiko Stuebner <heiko@sntech.de> 11 11 12 12 description: | 13 13 - The Rockchip SoC has a MIPI CSI D-PHY based on an Innosilicon IP wich 13 13 + The Rockchip SoC has a MIPI CSI D-PHY based on an Innosilicon IP which 14 14 connects to the ISP1 (Image Signal Processing unit v1.0) for CSI cameras. 15 15 16 16 properties:

+1 -1

Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml

reviewed

··· 59 59 description: 60 60 GPIO to signal Type-C cable orientation for lane swap. 61 61 If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to 62 62 - achieve the funtionality of an external type-C plug flip mux. 62 62 + achieve the functionality of an external type-C plug flip mux. 63 63 64 64 typec-dir-debounce-ms: 65 65 minimum: 100

+1 -1

Documentation/devicetree/bindings/phy/ti-phy.txt

reviewed

··· 62 62 - ctrl-module : phandle of the control module used by PHY driver to power on 63 63 the PHY. 64 64 65 65 - Recommended properies: 65 65 + Recommended properties: 66 66 - syscon-phy-power : phandle/offset pair. Phandle to the system control 67 67 module and the register offset to power on/off the PHY. 68 68

+1 -1

Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml

reviewed

··· 97 97 # It's pretty scary, but the basic idea is that: 98 98 # - One node name can start with either s- or r- for PRCM nodes, 99 99 # - Then, the name itself can be any repetition of <string>- (to 100 100 - # accomodate with nodes like uart4-rts-cts-pins), where each 100 100 + # accommodate with nodes like uart4-rts-cts-pins), where each 101 101 # string can be either starting with 'p' but in a string longer 102 102 # than 3, or something that doesn't start with 'p', 103 103 # - Then, the bank name is optional and will be between pa and pg,

+1 -1

Documentation/devicetree/bindings/pinctrl/canaan,k210-fpioa.yaml

reviewed

··· 11 11 12 12 description: 13 13 The Canaan Kendryte K210 SoC Fully Programmable IO Array (FPIOA) 14 14 - controller allows assiging any of 256 possible functions to any of 14 14 + controller allows assigning any of 256 possible functions to any of 15 15 48 IO pins of the SoC. Pin function configuration is performed on 16 16 a per-pin basis. 17 17

+1 -1

Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml

reviewed

··· 159 159 160 160 mediatek,pull-up-adv: 161 161 description: | 162 162 - Pull up setings for 2 pull resistors, R0 and R1. User can 162 162 + Pull up settings for 2 pull resistors, R0 and R1. User can 163 163 configure those special pins. Valid arguments are described as 164 164 below: 165 165 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.

+1 -1

Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml

reviewed

··· 130 130 131 131 mediatek,pull-up-adv: 132 132 description: | 133 133 - Pull up setings for 2 pull resistors, R0 and R1. User can 133 133 + Pull up settings for 2 pull resistors, R0 and R1. User can 134 134 configure those special pins. Valid arguments are described as 135 135 below: 136 136 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.

+2 -2

Documentation/devicetree/bindings/pinctrl/mediatek,mt7981-pinctrl.yaml

reviewed

··· 386 386 mediatek,pull-up-adv: 387 387 description: | 388 388 Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3' 389 389 - Pull up setings for 2 pull resistors, R0 and R1. Valid arguments 389 389 + Pull up settings for 2 pull resistors, R0 and R1. Valid arguments 390 390 are described as below: 391 391 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 392 392 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. ··· 398 398 mediatek,pull-down-adv: 399 399 description: | 400 400 Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3' 401 401 - Pull down setings for 2 pull resistors, R0 and R1. Valid arguments 401 401 + Pull down settings for 2 pull resistors, R0 and R1. Valid arguments 402 402 are described as below: 403 403 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 404 404 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.

+2 -2

Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml

reviewed

··· 332 332 mediatek,pull-up-adv: 333 333 description: | 334 334 Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3' 335 335 - Pull up setings for 2 pull resistors, R0 and R1. Valid arguments 335 335 + Pull up settings for 2 pull resistors, R0 and R1. Valid arguments 336 336 are described as below: 337 337 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 338 338 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. ··· 344 344 mediatek,pull-down-adv: 345 345 description: | 346 346 Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3' 347 347 - Pull down setings for 2 pull resistors, R0 and R1. Valid arguments 347 347 + Pull down settings for 2 pull resistors, R0 and R1. Valid arguments 348 348 are described as below: 349 349 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 350 350 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.

+1 -1

Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml

reviewed

··· 143 143 144 144 mediatek,pull-up-adv: 145 145 description: | 146 146 - Pull up setings for 2 pull resistors, R0 and R1. User can 146 146 + Pull up settings for 2 pull resistors, R0 and R1. User can 147 147 configure those special pins. Valid arguments are described as 148 148 below: 149 149 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.

+1 -1

Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml

reviewed

··· 149 149 deprecated: true 150 150 description: | 151 151 DEPRECATED: Please use bias-pull-up instead. 152 152 - Pull up setings for 2 pull resistors, R0 and R1. User can 152 152 + Pull up settings for 2 pull resistors, R0 and R1. User can 153 153 configure those special pins. Valid arguments are described as 154 154 below: 155 155 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.

+1 -1

Documentation/devicetree/bindings/pinctrl/pinctrl-max77620.txt

reviewed

··· 38 38 gpio, lpm-control-in, fps-out, 32k-out, sd0-dvs-in, sd1-dvs-in, 39 39 reference-out 40 40 41 41 - Theres is also customised properties for the GPIO1, GPIO2 and GPIO3. These 41 41 + There are also customised properties for the GPIO1, GPIO2 and GPIO3. These 42 42 customised properties are required to configure FPS configuration parameters 43 43 of these GPIOs. Please refer <devicetree/bindings/mfd/max77620.txt> for more 44 44 detail of Flexible Power Sequence (FPS).

+1 -1

Documentation/devicetree/bindings/pinctrl/pinctrl-rk805.txt

reviewed

··· 40 40 41 41 Valid values for function properties are: gpio. 42 42 43 43 - Theres is also not customised properties for any GPIO. 43 43 + There are also not customised properties for any GPIO. 44 44 45 45 Example: 46 46 --------

+1 -1

Documentation/devicetree/bindings/pinctrl/sprd,pinctrl.txt

reviewed

··· 8 8 pad driving level, system control select and so on ("domain pad 9 9 driving level": One pin can output 3.0v or 1.8v, depending on the 10 10 related domain pad driving selection, if the related domain pad 11 11 - slect 3.0v, then the pin can output 3.0v. "system control" is used 11 11 + select 3.0v, then the pin can output 3.0v. "system control" is used 12 12 to choose one function (like: UART0) for which system, since we 13 13 have several systems (AP/CP/CM4) on one SoC.). 14 14

+2 -2

Documentation/devicetree/bindings/pmem/pmem-region.txt

reviewed

··· 19 19 - compatible = "pmem-region" 20 20 21 21 - reg = <base, size>; 22 22 - The reg property should specificy an address range that is 22 22 + The reg property should specify an address range that is 23 23 translatable to a system physical address range. This address 24 24 range should be mappable as normal system memory would be 25 25 (i.e cacheable). ··· 30 30 node implies no special relationship between the two ranges. 31 31 32 32 Optional properties: 33 33 - - Any relevant NUMA assocativity properties for the target platform. 33 33 + - Any relevant NUMA associativity properties for the target platform. 34 34 35 35 - volatile; This property indicates that this region is actually 36 36 backed by non-persistent memory. This lets the OS know that it

+1 -1

Documentation/devicetree/bindings/power/renesas,sysc-rmobile.yaml

reviewed

··· 58 58 pd-node: 59 59 type: object 60 60 description: 61 61 - PM domain node representing a PM domain. This node hould be named by 61 61 + PM domain node representing a PM domain. This node should be named by 62 62 the real power area name, and thus its name should be unique. 63 63 64 64 properties:

+1 -1

Documentation/devicetree/bindings/power/reset/gpio-poweroff.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/power/reset/gpio-poweroff.yaml#

+1 -1

Documentation/devicetree/bindings/power/reset/gpio-restart.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/power/reset/gpio-restart.yaml#

+1 -1

Documentation/devicetree/bindings/power/reset/restart-handler.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/power/reset/restart-handler.yaml#

+1 -1

Documentation/devicetree/bindings/power/supply/bq256xx.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 # Copyright (C) 2020 Texas Instruments Incorporated 3 3 %YAML 1.2 4 4 ---

+1 -1

Documentation/devicetree/bindings/power/supply/sbs,sbs-manager.yaml

reviewed

··· 4 4 $id: http://devicetree.org/schemas/power/supply/sbs,sbs-manager.yaml# 5 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 7 - title: SBS compliant manger 7 7 + title: SBS compliant manager 8 8 9 9 maintainers: 10 10 - Sebastian Reichel <sre@kernel.org>

-34

Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt

reviewed

··· 1 1 - ----------------------------------------------------------- 2 2 - Device Tree Bindings for the Xilinx Zynq MPSoC PM domains 3 3 - ----------------------------------------------------------- 4 4 - The binding for zynqmp-power-controller follow the common 5 5 - generic PM domain binding[1]. 6 6 - 7 7 - [1] Documentation/devicetree/bindings/power/power-domain.yaml 8 8 - 9 9 - == Zynq MPSoC Generic PM Domain Node == 10 10 - 11 11 - Required property: 12 12 - - Below property should be in zynqmp-firmware node. 13 13 - - #power-domain-cells: Number of cells in a PM domain specifier. Must be 1. 14 14 - 15 15 - Power domain ID indexes are mentioned in 16 16 - include/dt-bindings/power/xlnx-zynqmp-power.h. 17 17 - 18 18 - ------- 19 19 - Example 20 20 - ------- 21 21 - 22 22 - firmware { 23 23 - zynqmp_firmware: zynqmp-firmware { 24 24 - ... 25 25 - #power-domain-cells = <1>; 26 26 - ... 27 27 - }; 28 28 - }; 29 29 - 30 30 - sata { 31 31 - ... 32 32 - power-domains = <&zynqmp_firmware 28>; 33 33 - ... 34 34 - };

+1 -1

Documentation/devicetree/bindings/powerpc/fsl/cpus.txt

reviewed

··· 28 28 Snoop ID Port Mapping registers, which are part of the CoreNet 29 29 Coherency fabric (CCF), provide a CoreNet Coherency Subdomain 30 30 ID/CoreNet Snoop ID to cpu mapping functions. Certain bits from 31 31 - these registers should be set if the coresponding CPU should be 31 31 + these registers should be set if the corresponding CPU should be 32 32 snooped. This property defines a bitmask which selects the bit 33 33 that should be set if this cpu should be snooped.

+2 -2

Documentation/devicetree/bindings/powerpc/fsl/dcsr.txt

reviewed

··· 185 185 with distinct functionality. 186 186 187 187 The first register range describes the CoreNet Debug Controller 188 188 - functionalty to perform transaction and transaction attribute matches. 188 188 + functionality to perform transaction and transaction attribute matches. 189 189 190 190 The second register range describes the CoreNet Debug Controller 191 191 - functionalty to trigger event notifications and debug traces. 191 191 + functionality to trigger event notifications and debug traces. 192 192 193 193 EXAMPLE 194 194 dcsr-corenet {

+1 -1

Documentation/devicetree/bindings/powerpc/fsl/raideng.txt

reviewed

··· 60 60 - fsl,liodn: Specifies the LIODN to be used for Job Ring. This 61 61 property is normally set by firmware. Value 62 62 is of 12-bits which is the LIODN number for this JR. 63 63 - This property is used by the IOMMU (PAMU) to distinquish 63 63 + This property is used by the IOMMU (PAMU) to distinguish 64 64 transactions from this JR and than be able to do address 65 65 translation & protection accordingly. 66 66

+1 -1

Documentation/devicetree/bindings/powerpc/nintendo/gamecube.txt

reviewed

··· 42 42 43 43 - compatible : should be "nintendo,flipper-pic" 44 44 45 45 - 1.c) The Digital Signal Procesor (DSP) node 45 45 + 1.c) The Digital Signal Processor (DSP) node 46 46 47 47 Represents the digital signal processor interface, designed to offload 48 48 audio related tasks.

+1 -1

Documentation/devicetree/bindings/powerpc/nintendo/wii.txt

reviewed

··· 53 53 - compatible : should be "nintendo,flipper-pic" 54 54 - interrupt-controller 55 55 56 56 - 1.c) The Digital Signal Procesor (DSP) node 56 56 + 1.c) The Digital Signal Processor (DSP) node 57 57 58 58 Represents the digital signal processor interface, designed to offload 59 59 audio related tasks.

-30

Documentation/devicetree/bindings/pps/pps-gpio.txt

reviewed

··· 1 1 - Device-Tree Bindings for a PPS Signal on GPIO 2 2 - 3 3 - These properties describe a PPS (pulse-per-second) signal connected to 4 4 - a GPIO pin. 5 5 - 6 6 - Required properties: 7 7 - - compatible: should be "pps-gpio" 8 8 - - gpios: one PPS GPIO in the format described by ../gpio/gpio.txt 9 9 - 10 10 - Additional required properties for the PPS ECHO functionality: 11 11 - - echo-gpios: one PPS ECHO GPIO in the format described by ../gpio/gpio.txt 12 12 - - echo-active-ms: duration in ms of the active portion of the echo pulse 13 13 - 14 14 - Optional properties: 15 15 - - assert-falling-edge: when present, assert is indicated by a falling edge 16 16 - (instead of by a rising edge) 17 17 - 18 18 - Example: 19 19 - pps { 20 20 - pinctrl-names = "default"; 21 21 - pinctrl-0 = <&pinctrl_pps>; 22 22 - 23 23 - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 24 24 - assert-falling-edge; 25 25 - 26 26 - echo-gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; 27 27 - echo-active-ms = <100>; 28 28 - 29 29 - compatible = "pps-gpio"; 30 30 - };

+49

Documentation/devicetree/bindings/pps/pps-gpio.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/pps/pps-gpio.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: PPS Signal via GPIO 8 8 + 9 9 + maintainers: 10 10 + - Fabio Estevam <festevam@gmail.com> 11 11 + 12 12 + properties: 13 13 + compatible: 14 14 + const: pps-gpio 15 15 + 16 16 + gpios: 17 17 + description: The GPIO that provides the PPS signal. 18 18 + maxItems: 1 19 19 + 20 20 + echo-gpios: 21 21 + description: The GPIO that provides the PPS ECHO signal. 22 22 + maxItems: 1 23 23 + 24 24 + echo-active-ms: 25 25 + description: Duration in ms of the active portion of the echo pulse. 26 26 + 27 27 + assert-falling-edge: 28 28 + description: Indicates a falling edge assert, when present. Rising edge if absent. 29 29 + type: boolean 30 30 + 31 31 + required: 32 32 + - compatible 33 33 + - gpios 34 34 + 35 35 + additionalProperties: false 36 36 + 37 37 + examples: 38 38 + - | 39 39 + #include <dt-bindings/gpio/gpio.h> 40 40 + 41 41 + pps { 42 42 + compatible = "pps-gpio"; 43 43 + pinctrl-names = "default"; 44 44 + pinctrl-0 = <&pinctrl_pps>; 45 45 + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 46 46 + assert-falling-edge; 47 47 + echo-gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; 48 48 + echo-active-ms = <100>; 49 49 + };

+1 -1

Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml

reviewed

··· 18 18 19 19 The IP block has a version register so this can be used for detection 20 20 instead of having to encode the IP version number in the device tree 21 21 - comaptible. 21 21 + compatible. 22 22 23 23 allOf: 24 24 - $ref: pwm.yaml#

+1 -1

Documentation/devicetree/bindings/regulator/regulator-max77620.txt

reviewed

··· 35 35 nodes is defined using the standard binding for regulators found at 36 36 <Documentation/devicetree/bindings/regulator/regulator.txt>. 37 37 38 38 - Theres are also additional properties for SD/LDOs. These additional properties 38 38 + There are also additional properties for SD/LDOs. These additional properties 39 39 are required to configure FPS configuration parameters for SDs and LDOs. 40 40 Please refer <devicetree/bindings/mfd/max77620.txt> for more detail of Flexible 41 41 Power Sequence (FPS).

+4 -4

Documentation/devicetree/bindings/regulator/regulator.yaml

reviewed

··· 126 126 127 127 regulator-oc-error-microamp: 128 128 description: Set over current error limit. This is a limit where part of 129 129 - the hardware propably is malfunctional and damage prevention is requested. 129 129 + the hardware probably is malfunctional and damage prevention is requested. 130 130 Zero can be passed to disable error detection and value '1' indicates 131 131 that detection should be enabled but limit setting can be omitted. 132 132 ··· 146 146 147 147 regulator-ov-error-microvolt: 148 148 description: Set over voltage error limit. This is a limit where part of 149 149 - the hardware propably is malfunctional and damage prevention is requested 149 149 + the hardware probably is malfunctional and damage prevention is requested 150 150 Zero can be passed to disable error detection and value '1' indicates 151 151 that detection should be enabled but limit setting can be omitted. Limit 152 152 is given as microvolt offset from voltage set to regulator. ··· 168 168 169 169 regulator-uv-error-microvolt: 170 170 description: Set under voltage error limit. This is a limit where part of 171 171 - the hardware propably is malfunctional and damage prevention is requested 171 171 + the hardware probably is malfunctional and damage prevention is requested 172 172 Zero can be passed to disable error detection and value '1' indicates 173 173 that detection should be enabled but limit setting can be omitted. Limit 174 174 is given as microvolt offset from voltage set to regulator. ··· 189 189 190 190 regulator-temp-error-kelvin: 191 191 description: Set over temperature error limit. This is a limit where part of 192 192 - the hardware propably is malfunctional and damage prevention is requested 192 192 + the hardware probably is malfunctional and damage prevention is requested 193 193 Zero can be passed to disable error detection and value '1' indicates 194 194 that detection should be enabled but limit setting can be omitted. 195 195

+1 -1

Documentation/devicetree/bindings/regulator/richtek,rt5190a-regulator.yaml

reviewed

··· 11 11 12 12 description: | 13 13 The RT5190A integrates 1 channel buck controller, 3 channels high efficiency 14 14 - synchronous buck converters, 1 LDO, I2C control interface and peripherial 14 14 + synchronous buck converters, 1 LDO, I2C control interface and peripheral 15 15 logical control. 16 16 17 17 It also supports mute AC OFF depop sound and quick setting storage while

+1 -1

Documentation/devicetree/bindings/regulator/vctrl.txt

reviewed

··· 21 21 margin from the expected value for a given control 22 22 voltage. On larger voltage decreases this can occur 23 23 undesiredly since the output voltage does not adjust 24 24 - inmediately to changes in the control voltage. To 24 24 + immediately to changes in the control voltage. To 25 25 avoid this situation the vctrl driver breaks down 26 26 larger voltage decreases into multiple steps, where 27 27 each step is within the OVP threshold.

+1 -1

Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-dsp-rproc.yaml#

+2 -2

Documentation/devicetree/bindings/remoteproc/ti,k3-r5f-rproc.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml# ··· 102 102 caches. Each of the TCMs can be enabled or disabled independently and 103 103 either of them can be configured to appear at that R5F's address 0x0. 104 104 105 105 - The cores do not use an MMU, but has a Region Address Translater 105 105 + The cores do not use an MMU, but has a Region Address Translator 106 106 (RAT) module that is accessible only from the R5Fs for providing 107 107 translations between 32-bit CPU addresses into larger system bus 108 108 addresses. Cache and memory access settings are provided through a

+1 -1

Documentation/devicetree/bindings/remoteproc/ti,omap-remoteproc.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/remoteproc/ti,omap-remoteproc.yaml#

+1 -1

Documentation/devicetree/bindings/remoteproc/ti,pru-consumer.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/remoteproc/ti,pru-consumer.yaml#

+1 -1

Documentation/devicetree/bindings/remoteproc/ti,pru-rproc.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/remoteproc/ti,pru-rproc.yaml#

+1 -1

Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml#

+10 -2

Documentation/devicetree/bindings/reset/altr,rst-mgr.yaml

reviewed

··· 7 7 title: Altera SOCFPGA Reset Manager 8 8 9 9 maintainers: 10 10 - - Dinh Nguyen <dinguyen@altera.com> 10 10 + - Dinh Nguyen <dinguyen@kernel.org> 11 11 12 12 properties: 13 13 compatible: ··· 32 32 required: 33 33 - compatible 34 34 - reg 35 35 - - altr,modrst-offset 36 35 - '#reset-cells' 36 36 + 37 37 + if: 38 38 + properties: 39 39 + compatible: 40 40 + contains: 41 41 + const: altr,stratix10-rst-mgr 42 42 + then: 43 43 + properties: 44 44 + altr,modrst-offset: false 37 45 38 46 additionalProperties: false 39 47

+1 -1

Documentation/devicetree/bindings/reset/ti,sci-reset.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/reset/ti,sci-reset.yaml#

+1 -1

Documentation/devicetree/bindings/reset/ti,tps380x-reset.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/reset/ti,tps380x-reset.yaml#

+1 -1

Documentation/devicetree/bindings/reset/ti-syscon-reset.txt

reviewed

··· 43 43 Cell #6 : bit position of the reset in the 44 44 reset status register 45 45 Cell #7 : Flags used to control reset behavior, 46 46 - availible flags defined in the DT include 46 46 + available flags defined in the DT include 47 47 file <dt-bindings/reset/ti-syscon.h> 48 48 49 49 SysCon Reset Consumer Nodes

+2 -2

Documentation/devicetree/bindings/rng/omap_rng.yaml

reviewed

··· 30 30 clocks: 31 31 minItems: 1 32 32 items: 33 33 - - description: EIP150 gatable clock 34 34 - - description: Main gatable clock 33 33 + - description: EIP150 gateable clock 34 34 + - description: Main gateable clock 35 35 36 36 clock-names: 37 37 minItems: 1

+1 -1

Documentation/devicetree/bindings/rtc/rtc-cmos.txt

reviewed

··· 10 10 - ctrl-reg : Contains the initial value of the control register also 11 11 called "Register B". 12 12 - freq-reg : Contains the initial value of the frequency register also 13 13 - called "Regsiter A". 13 13 + called "Register A". 14 14 15 15 "Register A" and "B" are usually initialized by the firmware (BIOS for 16 16 instance). If this is not done, it can be performed by the driver.

+1 -1

Documentation/devicetree/bindings/serial/st-asc.txt

reviewed

··· 8 8 9 9 Optional properties: 10 10 - st,hw-flow-ctrl bool flag to enable hardware flow control. 11 11 - - st,force-m1 bool flat to force asc to be in Mode-1 recommeded 11 11 + - st,force-m1 bool flat to force asc to be in Mode-1 recommended 12 12 for high bit rates (above 19.2K) 13 13 Example: 14 14 serial@fe440000{

+2 -2

Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml

reviewed

··· 3 3 # # Copyright (c) 2021 Aspeed Technology Inc. 4 4 %YAML 1.2 5 5 --- 6 6 - $id: "http://devicetree.org/schemas/soc/aspeed/uart-routing.yaml#" 7 7 - $schema: "http://devicetree.org/meta-schemas/core.yaml#" 6 6 + $id: http://devicetree.org/schemas/soc/aspeed/uart-routing.yaml# 7 7 + $schema: http://devicetree.org/meta-schemas/core.yaml# 8 8 9 9 title: Aspeed UART Routing Controller 10 10

+2 -2

Documentation/devicetree/bindings/soc/intel/intel,hps-copy-engine.yaml

reviewed

··· 2 2 # Copyright (C) 2022, Intel Corporation 3 3 %YAML 1.2 4 4 --- 5 5 - $id: "http://devicetree.org/schemas/soc/intel/intel,hps-copy-engine.yaml#" 6 6 - $schema: "http://devicetree.org/meta-schemas/core.yaml#" 5 5 + $id: http://devicetree.org/schemas/soc/intel/intel,hps-copy-engine.yaml# 6 6 + $schema: http://devicetree.org/meta-schemas/core.yaml# 7 7 8 8 title: Intel HPS Copy Engine 9 9

+2 -2

Documentation/devicetree/bindings/soc/litex/litex,soc-controller.yaml

reviewed

··· 2 2 # Copyright 2020 Antmicro <www.antmicro.com> 3 3 %YAML 1.2 4 4 --- 5 5 - $id: "http://devicetree.org/schemas/soc/litex/litex,soc-controller.yaml#" 6 6 - $schema: "http://devicetree.org/meta-schemas/core.yaml#" 5 5 + $id: http://devicetree.org/schemas/soc/litex/litex,soc-controller.yaml# 6 6 + $schema: http://devicetree.org/meta-schemas/core.yaml# 7 7 8 8 title: LiteX SoC Controller driver 9 9

+1 -1

Documentation/devicetree/bindings/soc/mediatek/mediatek,mt7986-wo-ccif.yaml

reviewed

··· 12 12 13 13 description: 14 14 The MediaTek wo-ccif provides a configuration interface for WED WO 15 15 - controller used to perfrom offload rx packet processing (e.g. 802.11 15 15 + controller used to perform offload rx packet processing (e.g. 802.11 16 16 aggregation packet reordering or rx header translation) on MT7986 soc. 17 17 18 18 properties:

+1 -1

Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml

reviewed

··· 12 12 description: | 13 13 PolarFire SoC devices include a microcontroller acting as the system controller, 14 14 which provides "services" to the main processor and to the FPGA fabric. These 15 15 - services include hardware rng, reprogramming of the FPGA and verfification of the 15 15 + services include hardware rng, reprogramming of the FPGA and verification of the 16 16 eNVM contents etc. More information on these services can be found online, at 17 17 https://onlinedocs.microchip.com/pr/GUID-1409CF11-8EF9-4C24-A94E-70979A688632-en-US-1/index.html 18 18

+1 -1

Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml

reviewed

··· 77 77 description: 78 78 The AOSS side channel also provides the controls for three cooling devices, 79 79 these are expressed as subnodes of the QMP node. The name of the node is 80 80 - used to identify the resource and must therefor be "cx", "mx" or "ebi". 80 80 + used to identify the resource and must therefore be "cx", "mx" or "ebi". 81 81 82 82 properties: 83 83 "#cooling-cells":

-6

Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml

reviewed

··· 38 38 patternProperties: 39 39 '^connector@\d$': 40 40 $ref: /schemas/connector/usb-connector.yaml# 41 41 - 42 42 - properties: 43 43 - reg: true 44 44 - 45 41 required: 46 42 - reg 47 47 - 48 48 - unevaluatedProperties: false 49 43 50 44 required: 51 45 - compatible

+2 -2

Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml

reviewed

··· 1 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 - $id: "http://devicetree.org/schemas/soc/renesas/renesas,rzg2l-sysc.yaml#" 5 5 - $schema: "http://devicetree.org/meta-schemas/core.yaml#" 4 4 + $id: http://devicetree.org/schemas/soc/renesas/renesas,rzg2l-sysc.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 7 title: Renesas RZ/{G2L,V2L} System Controller (SYSC) 8 8

+2 -2

Documentation/devicetree/bindings/soc/ti/k3-ringacc.yaml

reviewed

··· 2 2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ 3 3 %YAML 1.2 4 4 --- 5 5 - $id: "http://devicetree.org/schemas/soc/ti/k3-ringacc.yaml#" 6 6 - $schema: "http://devicetree.org/meta-schemas/core.yaml#" 5 5 + $id: http://devicetree.org/schemas/soc/ti/k3-ringacc.yaml# 6 6 + $schema: http://devicetree.org/meta-schemas/core.yaml# 7 7 8 8 title: Texas Instruments K3 NavigatorSS Ring Accelerator 9 9

+1 -1

Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/soc/ti/sci-pm-domain.yaml#

+1 -1

Documentation/devicetree/bindings/sound/axentia,tse850-pcm5142.txt

reviewed

··· 29 29 IN2 +---o--+------------+--o---+ OUT2 30 30 loop2 relays 31 31 32 32 - The 'loop1' gpio pin controlls two relays, which are either in loop position, 32 32 + The 'loop1' gpio pin controls two relays, which are either in loop position, 33 33 meaning that input and output are directly connected, or they are in mixer 34 34 position, meaning that the signal is passed through the 'Sum' mixer. Similarly 35 35 for 'loop2'.

+1 -1

Documentation/devicetree/bindings/sound/cs35l35.txt

reviewed

··· 110 110 111 111 See Sections 4.8.2 through 4.8.4 Serial-Port Control in the Datasheet 112 112 113 113 - -cirrus,monitor-signal-format : Sub-node for the Monitor Signaling Formating 113 113 + -cirrus,monitor-signal-format : Sub-node for the Monitor Signaling Formatting 114 114 on the I2S Port. Each of the 3 8 bit values in the array contain the settings 115 115 for depth, location, and frame. 116 116

+1 -1

Documentation/devicetree/bindings/sound/cs35l36.txt

reviewed

··· 33 33 one amplifier in the system. If more than one it is best to Hi-Z the ASP 34 34 port to prevent bus contention on the output signal 35 35 36 36 - - cirrus,boost-ctl-select : Boost conerter control source selection. 36 36 + - cirrus,boost-ctl-select : Boost converter control source selection. 37 37 Selects the source of the BST_CTL target VBST voltage for the boost 38 38 converter to generate. 39 39 0x00 - Control Port Value

+1 -1

Documentation/devicetree/bindings/sound/cs53l30.txt

reviewed

··· 30 30 * frame using two different ways: 31 31 * 1) Normal I2S mode on two data pins -- each SDOUT 32 32 * carries 2-channel data in the same time. 33 33 - * 2) TDM mode on one signle data pin -- SDOUT1 carries 33 33 + * 2) TDM mode on one single data pin -- SDOUT1 carries 34 34 * 4-channel data per frame. 35 35 36 36 Example:

+2 -2

Documentation/devicetree/bindings/sound/dialog,da7219.yaml

reviewed

··· 74 74 $ref: /schemas/types.yaml#/definitions/uint32 75 75 76 76 dlg,mic-amp-in-sel: 77 77 - enum: ["diff", "se_p", "se_n"] 77 77 + enum: [diff, se_p, se_n] 78 78 description: 79 79 Mic input source type. 80 80 ··· 123 123 $ref: /schemas/types.yaml#/definitions/uint32 124 124 125 125 dlg,jack-ins-det-pty: 126 126 - enum: ["low", "high"] 126 126 + enum: [low, high] 127 127 description: 128 128 Polarity for jack insertion detection. 129 129 $ref: /schemas/types.yaml#/definitions/string

+1 -1

Documentation/devicetree/bindings/sound/fsl,esai.txt

reviewed

··· 44 44 - fsl,esai-synchronous: This is a boolean property. If present, indicating 45 45 that ESAI would work in the synchronous mode, which 46 46 means all the settings for Receiving would be 47 47 - duplicated from Transmition related registers. 47 47 + duplicated from Transmission related registers. 48 48 49 49 Optional properties: 50 50

+1 -1

Documentation/devicetree/bindings/sound/mediatek,mt8188-afe.yaml

reviewed

··· 141 141 maxItems: 16 142 142 description: 143 143 This is a list of channel IDs which should be disabled. 144 144 - By default, all data received from ETDM pins will be outputed to 144 144 + By default, all data received from ETDM pins will be outputted to 145 145 memory. etdm in supports disable_out in direct mode(w/o interconn), 146 146 so user can disable the specified channels by the property. 147 147 uniqueItems: true

+1 -1

Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt

reviewed

··· 1 1 Mediatek AFE PCM controller for mt2701 2 2 3 3 Required properties: 4 4 - - compatible: should be one of the followings. 4 4 + - compatible: should be one of the following. 5 5 - "mediatek,mt2701-audio" 6 6 - "mediatek,mt7622-audio" 7 7 - interrupts: should contain AFE and ASYS interrupts

+2 -2

Documentation/devicetree/bindings/sound/mt8195-afe-pcm.yaml

reviewed

··· 111 111 $ref: /schemas/types.yaml#/definitions/uint32 112 112 description: | 113 113 etdm modules can share the same external clock pin. Specify 114 114 - which etdm clock source is required by this etdm in moudule. 114 114 + which etdm clock source is required by this etdm in module. 115 115 enum: 116 116 - 0 # etdm1_in 117 117 - 1 # etdm2_in ··· 122 122 $ref: /schemas/types.yaml#/definitions/uint32 123 123 description: | 124 124 etdm modules can share the same external clock pin. Specify 125 125 - which etdm clock source is required by this etdm out moudule. 125 125 + which etdm clock source is required by this etdm out module. 126 126 enum: 127 127 - 0 # etdm1_in 128 128 - 1 # etdm2_in

+6 -6

Documentation/devicetree/bindings/sound/nvidia,tegra-audio-max9808x.yaml

reviewed

··· 35 35 items: 36 36 enum: 37 37 # Board Connectors 38 38 - - "Int Spk" 39 39 - - "Headphone Jack" 40 40 - - "Earpiece" 41 41 - - "Headset Mic" 42 42 - - "Internal Mic 1" 43 43 - - "Internal Mic 2" 38 38 + - Int Spk 39 39 + - Headphone Jack 40 40 + - Earpiece 41 41 + - Headset Mic 42 42 + - Internal Mic 1 43 43 + - Internal Mic 2 44 44 45 45 # CODEC Pins 46 46 - HPL

+4 -4

Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5631.yaml

reviewed

··· 31 31 items: 32 32 enum: 33 33 # Board Connectors 34 34 - - "Int Spk" 35 35 - - "Headphone Jack" 36 36 - - "Mic Jack" 37 37 - - "Int Mic" 34 34 + - Int Spk 35 35 + - Headphone Jack 36 36 + - Mic Jack 37 37 + - Int Mic 38 38 39 39 # CODEC Pins 40 40 - MIC1

+1 -1

Documentation/devicetree/bindings/sound/renesas,rsnd.txt

reviewed

··· 94 94 [xx]ch [yy]ch 95 95 ------> [CTU] --------> 96 96 97 97 - CTU can convert [xx]ch to [yy]ch, or exchange outputed channel. 97 97 + CTU can convert [xx]ch to [yy]ch, or exchange outputted channel. 98 98 CTU conversion needs matrix settings. 99 99 For more detail information, see below 100 100

+1 -1

Documentation/devicetree/bindings/sound/rockchip,rk3288-hdmi-analog.txt

reviewed

··· 12 12 source. For this driver the first string should always be 13 13 "Analog". 14 14 15 15 - Optionnal properties: 15 15 + Optional properties: 16 16 - rockchip,hp-en-gpios = The phandle of the GPIO that power up/down the 17 17 headphone (when the analog output is an headphone). 18 18 - rockchip,hp-det-gpios = The phandle of the GPIO that detects the headphone

+1 -1

Documentation/devicetree/bindings/sound/rt5663.txt

reviewed

··· 28 28 If the value is 0, it means the impedance sensing is not supported. 29 29 - "realtek,impedance_sensing_table" 30 30 The matrix rows of the impedance sensing table are consisted by impedance 31 31 - minimum, impedance maximun, volume, DC offset w/o and w/ mic of each L and 31 31 + minimum, impedance maximum, volume, DC offset w/o and w/ mic of each L and 32 32 R channel accordingly. Example is shown as following. 33 33 < 0 300 7 0xffd160 0xffd1c0 0xff8a10 0xff8ab0 34 34 301 65535 4 0xffe470 0xffe470 0xffb8e0 0xffb8e0>

+1 -1

Documentation/devicetree/bindings/sound/serial-midi.yaml

reviewed

··· 20 20 parent serial device. If the standard MIDI baud of 31.25 kBaud is needed 21 21 (as would be the case if interfacing with arbitrary external MIDI devices), 22 22 configure the clocks of the parent serial device so that a requested baud of 38.4 kBaud 23 23 - resuts in the standard MIDI baud rate, and set the 'current-speed' property to 38400 (default) 23 23 + results in the standard MIDI baud rate, and set the 'current-speed' property to 38400 (default) 24 24 25 25 properties: 26 26 compatible:

+1 -1

Documentation/devicetree/bindings/sound/sprd-pcm.txt

reviewed

··· 1 1 - * Spreadtrum DMA platfrom bindings 1 1 + * Spreadtrum DMA platform bindings 2 2 3 3 Required properties: 4 4 - compatible: Should be "sprd,pcm-platform".

+1 -1

Documentation/devicetree/bindings/sound/st,stm32-sai.yaml

reviewed

··· 63 63 additionalProperties: false 64 64 description: 65 65 Two subnodes corresponding to SAI sub-block instances A et B 66 66 - can be defined. Subnode can be omitted for unsused sub-block. 66 66 + can be defined. Subnode can be omitted for unused sub-block. 67 67 68 68 properties: 69 69 compatible:

+1 -1

Documentation/devicetree/bindings/sound/ti,j721e-cpb-ivi-audio.yaml

reviewed

··· 13 13 14 14 description: | 15 15 The Infotainment board plugs into the Common Processor Board, the support of the 16 16 - extension board is extending the CPB audio support, decribed in: 16 16 + extension board is extending the CPB audio support, described in: 17 17 sound/ti,j721e-cpb-audio.txt 18 18 19 19 The audio support on the Infotainment Expansion Board consists of McASP0

+1 -1

Documentation/devicetree/bindings/sound/ti,tas2781.yaml

reviewed

··· 29 29 reg: 30 30 description: 31 31 I2C address, in multiple tas2781s case, all the i2c address 32 32 - aggreate as one Audio Device to support multiple audio slots. 32 32 + aggregate as one Audio Device to support multiple audio slots. 33 33 maxItems: 8 34 34 minItems: 1 35 35 items:

+1 -1

Documentation/devicetree/bindings/sound/tlv320adcx140.yaml

reviewed

··· 32 32 reg: 33 33 maxItems: 1 34 34 description: | 35 35 - I2C addresss of the device can be one of these 0x4c, 0x4d, 0x4e or 0x4f 35 35 + I2C address of the device can be one of these 0x4c, 0x4d, 0x4e or 0x4f 36 36 37 37 reset-gpios: 38 38 maxItems: 1

+2 -2

Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml

reviewed

··· 159 159 qcom,ports-hstart: 160 160 $ref: /schemas/types.yaml#/definitions/uint8-array 161 161 description: 162 162 - Identifying lowerst numbered coloum in SoundWire Frame, 162 162 + Identifying lowerst numbered column in SoundWire Frame, 163 163 i.e. left edge of the Transport sub-frame for each port. 164 164 Out ports followed by In ports. 165 165 Value of 0xff indicates that this option is not implemented ··· 176 176 qcom,ports-hstop: 177 177 $ref: /schemas/types.yaml#/definitions/uint8-array 178 178 description: 179 179 - Identifying highest numbered coloum in SoundWire Frame, 179 179 + Identifying highest numbered column in SoundWire Frame, 180 180 i.e. the right edge of the Transport 181 181 sub-frame for each port. Out ports followed by In ports. 182 182 Value of 0xff indicates that this option is not implemented

+2 -2

Documentation/devicetree/bindings/spi/brcm,bcm2835-aux-spi.txt

reviewed

··· 1 1 - Broadcom BCM2835 auxiliar SPI1/2 controller 1 1 + Broadcom BCM2835 auxiliary SPI1/2 controller 2 2 3 3 The BCM2835 contains two forms of SPI master controller, one known simply as 4 4 SPI0, and the other known as the "Universal SPI Master"; part of the ··· 9 9 - reg: Should contain register location and length for the spi block 10 10 - interrupts: Should contain shared interrupt of the aux block 11 11 - clocks: The clock feeding the SPI controller - needs to 12 12 - point to the auxiliar clock driver of the bcm2835, 12 12 + point to the auxiliary clock driver of the bcm2835, 13 13 as this clock will enable the output gate for the specific 14 14 clock. 15 15 - cs-gpios: the cs-gpios (native cs is NOT supported)

+2 -2

Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.yaml

reviewed

··· 12 12 13 13 description: | 14 14 The Broadcom SPI controller is a SPI master found on various SOCs, including 15 15 - BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consits 15 15 + BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consists 16 16 of: 17 17 MSPI : SPI master controller can read and write to a SPI slave device 18 18 BSPI : Broadcom SPI in combination with the MSPI hw IP provides acceleration ··· 20 20 io with 3-byte and 4-byte addressing support. 21 21 22 22 Supported Broadcom SoCs have one instance of MSPI+BSPI controller IP. 23 23 - MSPI master can be used wihout BSPI. BRCMSTB SoCs have an additional instance 23 23 + MSPI master can be used without BSPI. BRCMSTB SoCs have an additional instance 24 24 of a MSPI master without the BSPI to use with non flash slave devices that 25 25 use SPI protocol. 26 26

+1 -1

Documentation/devicetree/bindings/spi/omap-spi.yaml

reviewed

··· 68 68 dma-names: 69 69 description: 70 70 List of DMA request names. These strings correspond 1:1 with 71 71 - the DMA sepecifiers listed in dmas. The string names is to be 71 71 + the DMA specifiers listed in dmas. The string names is to be 72 72 "rxN" and "txN" for RX and TX requests, respectively. Where N 73 73 is the chip select number. 74 74 minItems: 1

+1 -1

Documentation/devicetree/bindings/thermal/qcom-lmh.yaml

reviewed

··· 8 8 title: Qualcomm Limits Management Hardware(LMh) 9 9 10 10 maintainers: 11 11 - - Thara Gopinath <thara.gopinath@linaro.org> 11 11 + - Thara Gopinath <thara.gopinath@gmail.com> 12 12 13 13 description: 14 14 Limits Management Hardware(LMh) is a hardware infrastructure on some

+1 -1

Documentation/devicetree/bindings/timer/snps,arc-timer.txt

reviewed

··· 1 1 Synopsys ARC Local Timer with Interrupt Capabilities 2 2 - Found on all ARC CPUs (ARC700/ARCHS) 3 3 - Can be optionally programmed to interrupt on Limit 4 4 - - Two idential copies TIMER0 and TIMER1 exist in ARC cores and historically 4 4 + - Two identical copies TIMER0 and TIMER1 exist in ARC cores and historically 5 5 TIMER0 used as clockevent provider (true for all ARC cores) 6 6 TIMER1 used for clocksource (mandatory for ARC700, optional for ARC HS) 7 7

+4 -6

Documentation/devicetree/bindings/trivial-devices.yaml

reviewed

··· 197 197 - maxim,max1237 198 198 # Temperature Sensor, I2C interface 199 199 - maxim,max1619 200 200 - # 10-bit 10 kOhm linear programable voltage divider 200 200 + # 10-bit 10 kOhm linear programmable voltage divider 201 201 - maxim,max5481 202 202 - # 10-bit 50 kOhm linear programable voltage divider 202 202 + # 10-bit 50 kOhm linear programmable voltage divider 203 203 - maxim,max5482 204 204 - # 10-bit 10 kOhm linear programable variable resistor 204 204 + # 10-bit 10 kOhm linear programmable variable resistor 205 205 - maxim,max5483 206 206 - # 10-bit 50 kOhm linear programable variable resistor 206 206 + # 10-bit 50 kOhm linear programmable variable resistor 207 207 - maxim,max5484 208 208 # PECI-to-I2C translator for PECI-to-SMBus/I2C protocol conversion 209 209 - maxim,max6621 ··· 295 295 - miramems,da311 296 296 # Temperature sensor with integrated fan control 297 297 - national,lm63 298 298 - # I2C TEMP SENSOR 299 299 - - national,lm75 300 298 # Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor 301 299 - national,lm80 302 300 # Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor

+44

Documentation/devicetree/bindings/ufs/qcom,ufs.yaml

reviewed

··· 29 29 - qcom,sa8775p-ufshc 30 30 - qcom,sc8280xp-ufshc 31 31 - qcom,sdm845-ufshc 32 32 + - qcom,sm6115-ufshc 32 33 - qcom,sm6350-ufshc 33 34 - qcom,sm8150-ufshc 34 35 - qcom,sm8250-ufshc ··· 79 78 reg: 80 79 minItems: 1 81 80 maxItems: 2 81 81 + 82 82 + reg-names: 83 83 + items: 84 84 + - const: std 85 85 + - const: ice 82 86 83 87 required-opps: 84 88 maxItems: 1 ··· 140 134 reg: 141 135 minItems: 1 142 136 maxItems: 1 137 137 + reg-names: 138 138 + maxItems: 1 143 139 144 140 - if: 145 141 properties: ··· 170 162 reg: 171 163 minItems: 2 172 164 maxItems: 2 165 165 + reg-names: 166 166 + minItems: 2 167 167 + required: 168 168 + - reg-names 173 169 174 170 - if: 175 171 properties: ··· 202 190 reg: 203 191 minItems: 1 204 192 maxItems: 1 193 193 + reg-names: 194 194 + maxItems: 1 195 195 + 196 196 + - if: 197 197 + properties: 198 198 + compatible: 199 199 + contains: 200 200 + enum: 201 201 + - qcom,sm6115-ufshc 202 202 + then: 203 203 + properties: 204 204 + clocks: 205 205 + minItems: 8 206 206 + maxItems: 8 207 207 + clock-names: 208 208 + items: 209 209 + - const: core_clk 210 210 + - const: bus_aggr_clk 211 211 + - const: iface_clk 212 212 + - const: core_clk_unipro 213 213 + - const: ref_clk 214 214 + - const: tx_lane0_sync_clk 215 215 + - const: rx_lane0_sync_clk 216 216 + - const: ice_core_clk 217 217 + reg: 218 218 + minItems: 2 219 219 + maxItems: 2 220 220 + reg-names: 221 221 + minItems: 2 222 222 + required: 223 223 + - reg-names 205 224 206 225 # TODO: define clock bindings for qcom,msm8994-ufshc 207 226 ··· 317 274 <0 0>, 318 275 <0 0>, 319 276 <0 0>; 277 277 + qcom,ice = <&ice>; 320 278 }; 321 279 };

+1 -1

Documentation/devicetree/bindings/ufs/ufs-common.yaml

reviewed

··· 74 74 Specifies max. load that can be drawn from VCCQ2 supply. 75 75 76 76 dependencies: 77 77 - freq-table-hz: [ 'clocks' ] 77 77 + freq-table-hz: [ clocks ] 78 78 79 79 required: 80 80 - interrupts

+1 -1

Documentation/devicetree/bindings/usb/ci-hdrc-usb2.yaml

reviewed

··· 167 167 at RTL is 0, so this property only affects siTD. 168 168 169 169 If this property is not set, the max packet size is 1023 bytes, and 170 170 - if the total of packet size for pervious transactions are more than 170 170 + if the total of packet size for previous transactions are more than 171 171 256 bytes, it can't accept any transactions within this frame. The 172 172 use case is single transaction, but higher frame rate. 173 173

+2 -4

Documentation/devicetree/bindings/usb/cypress,cypd4226.yaml

reviewed

··· 43 43 patternProperties: 44 44 '^connector@[01]$': 45 45 $ref: /schemas/connector/usb-connector.yaml# 46 46 - unevaluatedProperties: false 47 47 - properties: 48 48 - reg: 49 49 - maxItems: 1 46 46 + required: 47 47 + - reg 50 48 51 49 required: 52 50 - compatible

+1 -1

Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml

reviewed

··· 52 52 fsl,permanently-attached: 53 53 type: boolean 54 54 description: 55 55 - Indicates if the device atached to a downstream port is 55 55 + Indicates if the device attached to a downstream port is 56 56 permanently attached. 57 57 58 58 fsl,disable-port-power-control:

+1

Documentation/devicetree/bindings/usb/generic-ehci.yaml

reviewed

··· 38 38 - allwinner,sun8i-a83t-ehci 39 39 - allwinner,sun8i-h3-ehci 40 40 - allwinner,sun8i-r40-ehci 41 41 + - allwinner,sun8i-v3s-ehci 41 42 - allwinner,sun9i-a80-ehci 42 43 - allwinner,sun20i-d1-ehci 43 44 - aspeed,ast2400-ehci

+1

Documentation/devicetree/bindings/usb/generic-ohci.yaml

reviewed

··· 25 25 - allwinner,sun8i-a83t-ohci 26 26 - allwinner,sun8i-h3-ohci 27 27 - allwinner,sun8i-r40-ohci 28 28 + - allwinner,sun8i-v3s-ohci 28 29 - allwinner,sun9i-a80-ohci 29 30 - allwinner,sun20i-d1-ohci 30 31 - brcm,bcm3384-ohci

+1 -1

Documentation/devicetree/bindings/usb/genesys,gl850g.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/usb/genesys,gl850g.yaml#

+1 -1

Documentation/devicetree/bindings/usb/msm-hsusb.txt

reviewed

··· 53 53 - dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg" 54 54 55 55 - switch-gpio: A phandle + gpio-specifier pair. Some boards are using Dual 56 56 - SPDT USB Switch, witch is cotrolled by GPIO to de/multiplex 56 56 + SPDT USB Switch, witch is controlled by GPIO to de/multiplex 57 57 D+/D- USB lines between connectors. 58 58 59 59 - qcom,phy-init-sequence: PHY configuration sequence values. This is related to Device

+1 -1

Documentation/devicetree/bindings/usb/realtek,rts5411.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/usb/realtek,rts5411.yaml#

+1 -1

Documentation/devicetree/bindings/usb/richtek,rt1719.yaml

reviewed

··· 10 10 - ChiYuan Huang <cy_huang@richtek.com> 11 11 12 12 description: | 13 13 - The RT1719 is a sink-only USB Type-C contoller that complies with the latest 13 13 + The RT1719 is a sink-only USB Type-C controller that complies with the latest 14 14 USB Type-C and PD standards. It does the USB Type-C detection including attach 15 15 and orientation. It integrates the physical layer of the USB BMC power 16 16 delivery protocol to allow up to 100W of power. The BMC PD block enables full

-38

Documentation/devicetree/bindings/usb/samsung-hsotg.txt

reviewed

··· 1 1 - Samsung High Speed USB OTG controller 2 2 - ----------------------------- 3 3 - 4 4 - The Samsung HSOTG IP can be found on Samsung SoCs, from S3C6400 onwards. 5 5 - It gives functionality of OTG-compliant USB 2.0 host and device with 6 6 - support for USB 2.0 high-speed (480Mbps) and full-speed (12 Mbps) 7 7 - operation. 8 8 - 9 9 - Currently only device mode is supported. 10 10 - 11 11 - Binding details 12 12 - ----- 13 13 - 14 14 - Required properties: 15 15 - - compatible: "samsung,s3c6400-hsotg" should be used for all currently 16 16 - supported SoC, 17 17 - - interrupts: specifier of interrupt signal of interrupt controller, 18 18 - according to bindings of interrupt controller, 19 19 - - clocks: contains an array of clock specifiers: 20 20 - - first entry: OTG clock 21 21 - - clock-names: contains array of clock names: 22 22 - - first entry: must be "otg" 23 23 - - vusb_d-supply: phandle to voltage regulator of digital section, 24 24 - - vusb_a-supply: phandle to voltage regulator of analog section. 25 25 - 26 26 - Example 27 27 - ----- 28 28 - 29 29 - hsotg@12480000 { 30 30 - compatible = "samsung,s3c6400-hsotg"; 31 31 - reg = <0x12480000 0x20000>; 32 32 - interrupts = <0 71 0>; 33 33 - clocks = <&clock 305>; 34 34 - clock-names = "otg"; 35 35 - vusb_d-supply = <&vusb_reg>; 36 36 - vusb_a-supply = <&vusbdac_reg>; 37 37 - }; 38 38 -

+1 -1

Documentation/devicetree/bindings/usb/ti,usb8041.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/usb/ti,usb8041.yaml#

+1 -1

Documentation/devicetree/bindings/usb/vialab,vl817.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 %YAML 1.2 3 3 --- 4 4 $id: http://devicetree.org/schemas/usb/vialab,vl817.yaml#

+2

Documentation/devicetree/bindings/vendor-prefixes.yaml

reviewed

··· 1157 1157 description: Shenzhen Roofull Technology Co, Ltd 1158 1158 "^roseapplepi,.*": 1159 1159 description: RoseapplePi.org 1160 1160 + "^saef,.*": 1161 1161 + description: Saef Technology Limited 1160 1162 "^samsung,.*": 1161 1163 description: Samsung Semiconductor 1162 1164 "^samtec,.*":

+2 -2

Documentation/devicetree/bindings/watchdog/toshiba,visconti-wdt.yaml

reviewed

··· 2 2 # Copyright 2020 Toshiba Electronic Devices & Storage Corporation 3 3 %YAML 1.2 4 4 --- 5 5 - $id: "http://devicetree.org/schemas/watchdog/toshiba,visconti-wdt.yaml#" 6 6 - $schema: "http://devicetree.org/meta-schemas/core.yaml#" 5 5 + $id: http://devicetree.org/schemas/watchdog/toshiba,visconti-wdt.yaml# 6 6 + $schema: http://devicetree.org/meta-schemas/core.yaml# 7 7 8 8 title: Toshiba Visconti SoCs PIUWDT Watchdog timer 9 9

+1 -1

MAINTAINERS

reviewed

··· 17123 17123 S: Maintained 17124 17124 W: http://wiki.enneenne.com/index.php/LinuxPPS_support 17125 17125 F: Documentation/ABI/testing/sysfs-pps 17126 17126 - F: Documentation/devicetree/bindings/pps/pps-gpio.txt 17126 17126 + F: Documentation/devicetree/bindings/pps/pps-gpio.yaml 17127 17127 F: Documentation/driver-api/pps.rst 17128 17128 F: drivers/pps/ 17129 17129 F: include/linux/pps*.h

+1 -1

drivers/base/platform.c

reviewed

··· 1528 1528 error = bus_register(&platform_bus_type); 1529 1529 if (error) 1530 1530 device_unregister(&platform_bus); 1531 1531 - of_platform_register_reconfig_notifier(); 1531 1531 + 1532 1532 return error; 1533 1533 }

+53 -37

drivers/of/base.c

reviewed

··· 167 167 { 168 168 struct device_node *np; 169 169 170 170 + of_platform_register_reconfig_notifier(); 170 171 171 172 /* Create the kset, and register existing nodes */ 172 173 mutex_lock(&of_mutex); ··· 1530 1529 } 1531 1530 EXPORT_SYMBOL(of_count_phandle_with_args); 1532 1531 1532 1532 + static struct property *__of_remove_property_from_list(struct property **list, struct property *prop) 1533 1533 + { 1534 1534 + struct property **next; 1535 1535 + 1536 1536 + for (next = list; *next; next = &(*next)->next) { 1537 1537 + if (*next == prop) { 1538 1538 + *next = prop->next; 1539 1539 + prop->next = NULL; 1540 1540 + return prop; 1541 1541 + } 1542 1542 + } 1543 1543 + return NULL; 1544 1544 + } 1545 1545 + 1533 1546 /** 1534 1547 * __of_add_property - Add a property to a node without lock operations 1535 1548 * @np: Caller's Device Node ··· 1551 1536 */ 1552 1537 int __of_add_property(struct device_node *np, struct property *prop) 1553 1538 { 1539 1539 + int rc = 0; 1540 1540 + unsigned long flags; 1554 1541 struct property **next; 1542 1542 + 1543 1543 + raw_spin_lock_irqsave(&devtree_lock, flags); 1544 1544 + 1545 1545 + __of_remove_property_from_list(&np->deadprops, prop); 1555 1546 1556 1547 prop->next = NULL; 1557 1548 next = &np->properties; 1558 1549 while (*next) { 1559 1559 - if (strcmp(prop->name, (*next)->name) == 0) 1550 1550 + if (strcmp(prop->name, (*next)->name) == 0) { 1560 1551 /* duplicate ! don't insert it */ 1561 1561 - return -EEXIST; 1562 1562 - 1552 1552 + rc = -EEXIST; 1553 1553 + goto out_unlock; 1554 1554 + } 1563 1555 next = &(*next)->next; 1564 1556 } 1565 1557 *next = prop; 1566 1558 1559 1559 + out_unlock: 1560 1560 + raw_spin_unlock_irqrestore(&devtree_lock, flags); 1561 1561 + if (rc) 1562 1562 + return rc; 1563 1563 + 1564 1564 + __of_add_property_sysfs(np, prop); 1567 1565 return 0; 1568 1566 } 1569 1567 ··· 1587 1559 */ 1588 1560 int of_add_property(struct device_node *np, struct property *prop) 1589 1561 { 1590 1590 - unsigned long flags; 1591 1562 int rc; 1592 1563 1593 1564 mutex_lock(&of_mutex); 1594 1594 - 1595 1595 - raw_spin_lock_irqsave(&devtree_lock, flags); 1596 1565 rc = __of_add_property(np, prop); 1597 1597 - raw_spin_unlock_irqrestore(&devtree_lock, flags); 1598 1598 - 1599 1599 - if (!rc) 1600 1600 - __of_add_property_sysfs(np, prop); 1601 1601 - 1602 1566 mutex_unlock(&of_mutex); 1603 1567 1604 1568 if (!rc) ··· 1602 1582 1603 1583 int __of_remove_property(struct device_node *np, struct property *prop) 1604 1584 { 1605 1605 - struct property **next; 1585 1585 + unsigned long flags; 1586 1586 + int rc = -ENODEV; 1606 1587 1607 1607 - for (next = &np->properties; *next; next = &(*next)->next) { 1608 1608 - if (*next == prop) 1609 1609 - break; 1588 1588 + raw_spin_lock_irqsave(&devtree_lock, flags); 1589 1589 + 1590 1590 + if (__of_remove_property_from_list(&np->properties, prop)) { 1591 1591 + /* Found the property, add it to deadprops list */ 1592 1592 + prop->next = np->deadprops; 1593 1593 + np->deadprops = prop; 1594 1594 + rc = 0; 1610 1595 } 1611 1611 - if (*next == NULL) 1612 1612 - return -ENODEV; 1613 1596 1614 1614 - /* found the node */ 1615 1615 - *next = prop->next; 1616 1616 - prop->next = np->deadprops; 1617 1617 - np->deadprops = prop; 1597 1597 + raw_spin_unlock_irqrestore(&devtree_lock, flags); 1598 1598 + if (rc) 1599 1599 + return rc; 1618 1600 1601 1601 + __of_remove_property_sysfs(np, prop); 1619 1602 return 0; 1620 1603 } 1621 1604 ··· 1634 1611 */ 1635 1612 int of_remove_property(struct device_node *np, struct property *prop) 1636 1613 { 1637 1637 - unsigned long flags; 1638 1614 int rc; 1639 1615 1640 1616 if (!prop) 1641 1617 return -ENODEV; 1642 1618 1643 1619 mutex_lock(&of_mutex); 1644 1644 - 1645 1645 - raw_spin_lock_irqsave(&devtree_lock, flags); 1646 1620 rc = __of_remove_property(np, prop); 1647 1647 - raw_spin_unlock_irqrestore(&devtree_lock, flags); 1648 1648 - 1649 1649 - if (!rc) 1650 1650 - __of_remove_property_sysfs(np, prop); 1651 1651 - 1652 1621 mutex_unlock(&of_mutex); 1653 1622 1654 1623 if (!rc) ··· 1654 1639 struct property **oldpropp) 1655 1640 { 1656 1641 struct property **next, *oldprop; 1642 1642 + unsigned long flags; 1643 1643 + 1644 1644 + raw_spin_lock_irqsave(&devtree_lock, flags); 1645 1645 + 1646 1646 + __of_remove_property_from_list(&np->deadprops, newprop); 1657 1647 1658 1648 for (next = &np->properties; *next; next = &(*next)->next) { 1659 1649 if (of_prop_cmp((*next)->name, newprop->name) == 0) ··· 1678 1658 *next = newprop; 1679 1659 } 1680 1660 1661 1661 + raw_spin_unlock_irqrestore(&devtree_lock, flags); 1662 1662 + 1663 1663 + __of_update_property_sysfs(np, newprop, oldprop); 1664 1664 + 1681 1665 return 0; 1682 1666 } 1683 1667 ··· 1697 1673 int of_update_property(struct device_node *np, struct property *newprop) 1698 1674 { 1699 1675 struct property *oldprop; 1700 1700 - unsigned long flags; 1701 1676 int rc; 1702 1677 1703 1678 if (!newprop->name) 1704 1679 return -EINVAL; 1705 1680 1706 1681 mutex_lock(&of_mutex); 1707 1707 - 1708 1708 - raw_spin_lock_irqsave(&devtree_lock, flags); 1709 1682 rc = __of_update_property(np, newprop, &oldprop); 1710 1710 - raw_spin_unlock_irqrestore(&devtree_lock, flags); 1711 1711 - 1712 1712 - if (!rc) 1713 1713 - __of_update_property_sysfs(np, newprop, oldprop); 1714 1714 - 1715 1683 mutex_unlock(&of_mutex); 1716 1684 1717 1685 if (!rc)

-32

drivers/of/device.c

reviewed

··· 32 32 } 33 33 EXPORT_SYMBOL(of_match_device); 34 34 35 35 - int of_device_add(struct platform_device *ofdev) 36 36 - { 37 37 - BUG_ON(ofdev->dev.of_node == NULL); 38 38 - 39 39 - /* name and id have to be set so that the platform bus doesn't get 40 40 - * confused on matching */ 41 41 - ofdev->name = dev_name(&ofdev->dev); 42 42 - ofdev->id = PLATFORM_DEVID_NONE; 43 43 - 44 44 - /* 45 45 - * If this device has not binding numa node in devicetree, that is 46 46 - * of_node_to_nid returns NUMA_NO_NODE. device_add will assume that this 47 47 - * device is on the same node as the parent. 48 48 - */ 49 49 - set_dev_node(&ofdev->dev, of_node_to_nid(ofdev->dev.of_node)); 50 50 - 51 51 - return device_add(&ofdev->dev); 52 52 - } 53 53 - 54 35 static void 55 36 of_dma_set_restricted_buffer(struct device *dev, struct device_node *np) 56 37 { ··· 201 220 return 0; 202 221 } 203 222 EXPORT_SYMBOL_GPL(of_dma_configure_id); 204 204 - 205 205 - int of_device_register(struct platform_device *pdev) 206 206 - { 207 207 - device_initialize(&pdev->dev); 208 208 - return of_device_add(pdev); 209 209 - } 210 210 - EXPORT_SYMBOL(of_device_register); 211 211 - 212 212 - void of_device_unregister(struct platform_device *ofdev) 213 213 - { 214 214 - device_unregister(&ofdev->dev); 215 215 - } 216 216 - EXPORT_SYMBOL(of_device_unregister); 217 223 218 224 const void *of_device_get_match_data(const struct device *dev) 219 225 {

+192 -100

drivers/of/dynamic.c

reviewed

··· 72 72 [OF_RECONFIG_UPDATE_PROPERTY] = "UPDATE_PROPERTY", 73 73 }; 74 74 75 75 + #define _do_print(func, prefix, action, node, prop, ...) ({ \ 76 76 + func("changeset: " prefix "%-15s %pOF%s%s\n", \ 77 77 + ##__VA_ARGS__, action_names[action], node, \ 78 78 + prop ? ":" : "", prop ? prop->name : ""); \ 79 79 + }) 80 80 + #define of_changeset_action_err(...) _do_print(pr_err, __VA_ARGS__) 81 81 + #define of_changeset_action_debug(...) _do_print(pr_debug, __VA_ARGS__) 82 82 + 75 83 int of_reconfig_notify(unsigned long action, struct of_reconfig_data *p) 76 84 { 77 85 int rc; 78 78 - #ifdef DEBUG 79 86 struct of_reconfig_data *pr = p; 80 87 81 81 - switch (action) { 82 82 - case OF_RECONFIG_ATTACH_NODE: 83 83 - case OF_RECONFIG_DETACH_NODE: 84 84 - pr_debug("notify %-15s %pOF\n", action_names[action], 85 85 - pr->dn); 86 86 - break; 87 87 - case OF_RECONFIG_ADD_PROPERTY: 88 88 - case OF_RECONFIG_REMOVE_PROPERTY: 89 89 - case OF_RECONFIG_UPDATE_PROPERTY: 90 90 - pr_debug("notify %-15s %pOF:%s\n", action_names[action], 91 91 - pr->dn, pr->prop->name); 92 92 - break; 88 88 + of_changeset_action_debug("notify: ", action, pr->dn, pr->prop); 93 89 94 94 - } 95 95 - #endif 96 90 rc = blocking_notifier_call_chain(&of_reconfig_chain, action, p); 97 91 return notifier_to_errno(rc); 98 92 } ··· 198 204 { 199 205 const __be32 *phandle; 200 206 int sz; 207 207 + unsigned long flags; 208 208 + 209 209 + raw_spin_lock_irqsave(&devtree_lock, flags); 201 210 202 211 if (!of_node_check_flag(np, OF_OVERLAY)) { 203 212 np->name = __of_get_property(np, "name", NULL); ··· 223 226 np->parent->child = np; 224 227 of_node_clear_flag(np, OF_DETACHED); 225 228 np->fwnode.flags |= FWNODE_FLAG_NOT_DEVICE; 229 229 + 230 230 + raw_spin_unlock_irqrestore(&devtree_lock, flags); 231 231 + 232 232 + __of_attach_node_sysfs(np); 226 233 } 227 234 228 235 /** ··· 236 235 int of_attach_node(struct device_node *np) 237 236 { 238 237 struct of_reconfig_data rd; 239 239 - unsigned long flags; 240 238 241 239 memset(&rd, 0, sizeof(rd)); 242 240 rd.dn = np; 243 241 244 242 mutex_lock(&of_mutex); 245 245 - raw_spin_lock_irqsave(&devtree_lock, flags); 246 243 __of_attach_node(np); 247 247 - raw_spin_unlock_irqrestore(&devtree_lock, flags); 248 248 - 249 249 - __of_attach_node_sysfs(np); 250 244 mutex_unlock(&of_mutex); 251 245 252 246 of_reconfig_notify(OF_RECONFIG_ATTACH_NODE, &rd); ··· 252 256 void __of_detach_node(struct device_node *np) 253 257 { 254 258 struct device_node *parent; 259 259 + unsigned long flags; 255 260 256 256 - if (WARN_ON(of_node_check_flag(np, OF_DETACHED))) 257 257 - return; 261 261 + raw_spin_lock_irqsave(&devtree_lock, flags); 258 262 259 263 parent = np->parent; 260 260 - if (WARN_ON(!parent)) 264 264 + if (WARN_ON(of_node_check_flag(np, OF_DETACHED) || !parent)) { 265 265 + raw_spin_unlock_irqrestore(&devtree_lock, flags); 261 266 return; 267 267 + } 262 268 263 269 if (parent->child == np) 264 270 parent->child = np->sibling; ··· 277 279 278 280 /* race with of_find_node_by_phandle() prevented by devtree_lock */ 279 281 __of_phandle_cache_inv_entry(np->phandle); 282 282 + 283 283 + raw_spin_unlock_irqrestore(&devtree_lock, flags); 284 284 + 285 285 + __of_detach_node_sysfs(np); 280 286 } 281 287 282 288 /** ··· 290 288 int of_detach_node(struct device_node *np) 291 289 { 292 290 struct of_reconfig_data rd; 293 293 - unsigned long flags; 294 291 295 292 memset(&rd, 0, sizeof(rd)); 296 293 rd.dn = np; 297 294 298 295 mutex_lock(&of_mutex); 299 299 - raw_spin_lock_irqsave(&devtree_lock, flags); 300 296 __of_detach_node(np); 301 301 - raw_spin_unlock_irqrestore(&devtree_lock, flags); 302 302 - 303 303 - __of_detach_node_sysfs(np); 304 297 mutex_unlock(&of_mutex); 305 298 306 299 of_reconfig_notify(OF_RECONFIG_DETACH_NODE, &rd); ··· 483 486 return NULL; 484 487 } 485 488 489 489 + /** 490 490 + * of_changeset_create_node - Dynamically create a device node and attach to 491 491 + * a given changeset. 492 492 + * 493 493 + * @ocs: Pointer to changeset 494 494 + * @parent: Pointer to parent device node 495 495 + * @full_name: Node full name 496 496 + * 497 497 + * Return: Pointer to the created device node or NULL in case of an error. 498 498 + */ 499 499 + struct device_node *of_changeset_create_node(struct of_changeset *ocs, 500 500 + struct device_node *parent, 501 501 + const char *full_name) 502 502 + { 503 503 + struct device_node *np; 504 504 + int ret; 505 505 + 506 506 + np = __of_node_dup(NULL, full_name); 507 507 + if (!np) 508 508 + return NULL; 509 509 + np->parent = parent; 510 510 + 511 511 + ret = of_changeset_attach_node(ocs, np); 512 512 + if (ret) { 513 513 + of_node_put(np); 514 514 + return NULL; 515 515 + } 516 516 + 517 517 + return np; 518 518 + } 519 519 + EXPORT_SYMBOL(of_changeset_create_node); 520 520 + 486 521 static void __of_changeset_entry_destroy(struct of_changeset_entry *ce) 487 522 { 488 523 if (ce->action == OF_RECONFIG_ATTACH_NODE && ··· 531 502 list_del(&ce->node); 532 503 kfree(ce); 533 504 } 534 534 - 535 535 - #ifdef DEBUG 536 536 - static void __of_changeset_entry_dump(struct of_changeset_entry *ce) 537 537 - { 538 538 - switch (ce->action) { 539 539 - case OF_RECONFIG_ADD_PROPERTY: 540 540 - case OF_RECONFIG_REMOVE_PROPERTY: 541 541 - case OF_RECONFIG_UPDATE_PROPERTY: 542 542 - pr_debug("cset<%p> %-15s %pOF/%s\n", ce, action_names[ce->action], 543 543 - ce->np, ce->prop->name); 544 544 - break; 545 545 - case OF_RECONFIG_ATTACH_NODE: 546 546 - case OF_RECONFIG_DETACH_NODE: 547 547 - pr_debug("cset<%p> %-15s %pOF\n", ce, action_names[ce->action], 548 548 - ce->np); 549 549 - break; 550 550 - } 551 551 - } 552 552 - #else 553 553 - static inline void __of_changeset_entry_dump(struct of_changeset_entry *ce) 554 554 - { 555 555 - /* empty */ 556 556 - } 557 557 - #endif 558 505 559 506 static void __of_changeset_entry_invert(struct of_changeset_entry *ce, 560 507 struct of_changeset_entry *rce) ··· 599 594 600 595 static int __of_changeset_entry_apply(struct of_changeset_entry *ce) 601 596 { 602 602 - struct property *old_prop, **propp; 603 603 - unsigned long flags; 604 597 int ret = 0; 605 598 606 606 - __of_changeset_entry_dump(ce); 599 599 + of_changeset_action_debug("apply: ", ce->action, ce->np, ce->prop); 607 600 608 608 - raw_spin_lock_irqsave(&devtree_lock, flags); 609 601 switch (ce->action) { 610 602 case OF_RECONFIG_ATTACH_NODE: 611 603 __of_attach_node(ce->np); ··· 611 609 __of_detach_node(ce->np); 612 610 break; 613 611 case OF_RECONFIG_ADD_PROPERTY: 614 614 - /* If the property is in deadprops then it must be removed */ 615 615 - for (propp = &ce->np->deadprops; *propp; propp = &(*propp)->next) { 616 616 - if (*propp == ce->prop) { 617 617 - *propp = ce->prop->next; 618 618 - ce->prop->next = NULL; 619 619 - break; 620 620 - } 621 621 - } 622 622 - 623 612 ret = __of_add_property(ce->np, ce->prop); 624 613 break; 625 614 case OF_RECONFIG_REMOVE_PROPERTY: ··· 618 625 break; 619 626 620 627 case OF_RECONFIG_UPDATE_PROPERTY: 621 621 - /* If the property is in deadprops then it must be removed */ 622 622 - for (propp = &ce->np->deadprops; *propp; propp = &(*propp)->next) { 623 623 - if (*propp == ce->prop) { 624 624 - *propp = ce->prop->next; 625 625 - ce->prop->next = NULL; 626 626 - break; 627 627 - } 628 628 - } 629 629 - 630 630 - ret = __of_update_property(ce->np, ce->prop, &old_prop); 628 628 + ret = __of_update_property(ce->np, ce->prop, &ce->old_prop); 631 629 break; 632 630 default: 633 631 ret = -EINVAL; 634 632 } 635 635 - raw_spin_unlock_irqrestore(&devtree_lock, flags); 636 633 637 634 if (ret) { 638 638 - pr_err("changeset: apply failed: %-15s %pOF:%s\n", 639 639 - action_names[ce->action], ce->np, ce->prop->name); 635 635 + of_changeset_action_err("apply failed: ", ce->action, ce->np, ce->prop); 640 636 return ret; 641 641 - } 642 642 - 643 643 - switch (ce->action) { 644 644 - case OF_RECONFIG_ATTACH_NODE: 645 645 - __of_attach_node_sysfs(ce->np); 646 646 - break; 647 647 - case OF_RECONFIG_DETACH_NODE: 648 648 - __of_detach_node_sysfs(ce->np); 649 649 - break; 650 650 - case OF_RECONFIG_ADD_PROPERTY: 651 651 - /* ignore duplicate names */ 652 652 - __of_add_property_sysfs(ce->np, ce->prop); 653 653 - break; 654 654 - case OF_RECONFIG_REMOVE_PROPERTY: 655 655 - __of_remove_property_sysfs(ce->np, ce->prop); 656 656 - break; 657 657 - case OF_RECONFIG_UPDATE_PROPERTY: 658 658 - __of_update_property_sysfs(ce->np, ce->prop, ce->old_prop); 659 659 - break; 660 637 } 661 638 662 639 return 0; ··· 902 939 ce->np = of_node_get(np); 903 940 ce->prop = prop; 904 941 905 905 - if (action == OF_RECONFIG_UPDATE_PROPERTY && prop) 906 906 - ce->old_prop = of_find_property(np, prop->name, NULL); 907 907 - 908 942 /* add it to the list */ 909 943 list_add_tail(&ce->node, &ocs->entries); 910 944 return 0; 911 945 } 912 946 EXPORT_SYMBOL_GPL(of_changeset_action); 947 947 + 948 948 + static int of_changeset_add_prop_helper(struct of_changeset *ocs, 949 949 + struct device_node *np, 950 950 + const struct property *pp) 951 951 + { 952 952 + struct property *new_pp; 953 953 + int ret; 954 954 + 955 955 + new_pp = __of_prop_dup(pp, GFP_KERNEL); 956 956 + if (!new_pp) 957 957 + return -ENOMEM; 958 958 + 959 959 + ret = of_changeset_add_property(ocs, np, new_pp); 960 960 + if (ret) { 961 961 + kfree(new_pp->name); 962 962 + kfree(new_pp->value); 963 963 + kfree(new_pp); 964 964 + } 965 965 + 966 966 + return ret; 967 967 + } 968 968 + 969 969 + /** 970 970 + * of_changeset_add_prop_string - Add a string property to a changeset 971 971 + * 972 972 + * @ocs: changeset pointer 973 973 + * @np: device node pointer 974 974 + * @prop_name: name of the property to be added 975 975 + * @str: pointer to null terminated string 976 976 + * 977 977 + * Create a string property and add it to a changeset. 978 978 + * 979 979 + * Return: 0 on success, a negative error value in case of an error. 980 980 + */ 981 981 + int of_changeset_add_prop_string(struct of_changeset *ocs, 982 982 + struct device_node *np, 983 983 + const char *prop_name, const char *str) 984 984 + { 985 985 + struct property prop; 986 986 + 987 987 + prop.name = (char *)prop_name; 988 988 + prop.length = strlen(str) + 1; 989 989 + prop.value = (void *)str; 990 990 + 991 991 + return of_changeset_add_prop_helper(ocs, np, &prop); 992 992 + } 993 993 + EXPORT_SYMBOL_GPL(of_changeset_add_prop_string); 994 994 + 995 995 + /** 996 996 + * of_changeset_add_prop_string_array - Add a string list property to 997 997 + * a changeset 998 998 + * 999 999 + * @ocs: changeset pointer 1000 1000 + * @np: device node pointer 1001 1001 + * @prop_name: name of the property to be added 1002 1002 + * @str_array: pointer to an array of null terminated strings 1003 1003 + * @sz: number of string array elements 1004 1004 + * 1005 1005 + * Create a string list property and add it to a changeset. 1006 1006 + * 1007 1007 + * Return: 0 on success, a negative error value in case of an error. 1008 1008 + */ 1009 1009 + int of_changeset_add_prop_string_array(struct of_changeset *ocs, 1010 1010 + struct device_node *np, 1011 1011 + const char *prop_name, 1012 1012 + const char **str_array, size_t sz) 1013 1013 + { 1014 1014 + struct property prop; 1015 1015 + int i, ret; 1016 1016 + char *vp; 1017 1017 + 1018 1018 + prop.name = (char *)prop_name; 1019 1019 + 1020 1020 + prop.length = 0; 1021 1021 + for (i = 0; i < sz; i++) 1022 1022 + prop.length += strlen(str_array[i]) + 1; 1023 1023 + 1024 1024 + prop.value = kmalloc(prop.length, GFP_KERNEL); 1025 1025 + if (!prop.value) 1026 1026 + return -ENOMEM; 1027 1027 + 1028 1028 + vp = prop.value; 1029 1029 + for (i = 0; i < sz; i++) { 1030 1030 + vp += snprintf(vp, (char *)prop.value + prop.length - vp, "%s", 1031 1031 + str_array[i]) + 1; 1032 1032 + } 1033 1033 + ret = of_changeset_add_prop_helper(ocs, np, &prop); 1034 1034 + kfree(prop.value); 1035 1035 + 1036 1036 + return ret; 1037 1037 + } 1038 1038 + EXPORT_SYMBOL_GPL(of_changeset_add_prop_string_array); 1039 1039 + 1040 1040 + /** 1041 1041 + * of_changeset_add_prop_u32_array - Add a property of 32 bit integers 1042 1042 + * property to a changeset 1043 1043 + * 1044 1044 + * @ocs: changeset pointer 1045 1045 + * @np: device node pointer 1046 1046 + * @prop_name: name of the property to be added 1047 1047 + * @array: pointer to an array of 32 bit integers 1048 1048 + * @sz: number of array elements 1049 1049 + * 1050 1050 + * Create a property of 32 bit integers and add it to a changeset. 1051 1051 + * 1052 1052 + * Return: 0 on success, a negative error value in case of an error. 1053 1053 + */ 1054 1054 + int of_changeset_add_prop_u32_array(struct of_changeset *ocs, 1055 1055 + struct device_node *np, 1056 1056 + const char *prop_name, 1057 1057 + const u32 *array, size_t sz) 1058 1058 + { 1059 1059 + struct property prop; 1060 1060 + __be32 *val; 1061 1061 + int i, ret; 1062 1062 + 1063 1063 + val = kcalloc(sz, sizeof(__be32), GFP_KERNEL); 1064 1064 + if (!val) 1065 1065 + return -ENOMEM; 1066 1066 + 1067 1067 + for (i = 0; i < sz; i++) 1068 1068 + val[i] = cpu_to_be32(array[i]); 1069 1069 + prop.name = (char *)prop_name; 1070 1070 + prop.length = sizeof(u32) * sz; 1071 1071 + prop.value = (void *)val; 1072 1072 + 1073 1073 + ret = of_changeset_add_prop_helper(ocs, np, &prop); 1074 1074 + kfree(val); 1075 1075 + 1076 1076 + return ret; 1077 1077 + } 1078 1078 + EXPORT_SYMBOL_GPL(of_changeset_add_prop_u32_array);

+6

drivers/of/of_private.h

reviewed

··· 60 60 } 61 61 #endif /* CONFIG_OF_DYNAMIC */ 62 62 63 63 + #if defined(CONFIG_OF_DYNAMIC) && defined(CONFIG_OF_ADDRESS) 64 64 + void of_platform_register_reconfig_notifier(void); 65 65 + #else 66 66 + static inline void of_platform_register_reconfig_notifier(void) { } 67 67 + #endif 68 68 + 63 69 #if defined(CONFIG_OF_KOBJ) 64 70 int of_node_is_attached(const struct device_node *node); 65 71 int __of_add_property_sysfs(struct device_node *np, struct property *pp);

+32 -13

drivers/of/overlay.c

reviewed

··· 682 682 * 1) "target" property containing the phandle of the target 683 683 * 2) "target-path" property containing the path of the target 684 684 */ 685 685 - static struct device_node *find_target(struct device_node *info_node) 685 685 + static struct device_node *find_target(struct device_node *info_node, 686 686 + struct device_node *target_base) 686 687 { 687 688 struct device_node *node; 689 689 + char *target_path; 688 690 const char *path; 689 691 u32 val; 690 692 int ret; ··· 702 700 703 701 ret = of_property_read_string(info_node, "target-path", &path); 704 702 if (!ret) { 705 705 - node = of_find_node_by_path(path); 706 706 - if (!node) 707 707 - pr_err("find target, node: %pOF, path '%s' not found\n", 708 708 - info_node, path); 703 703 + if (target_base) { 704 704 + target_path = kasprintf(GFP_KERNEL, "%pOF%s", target_base, path); 705 705 + if (!target_path) 706 706 + return NULL; 707 707 + node = of_find_node_by_path(target_path); 708 708 + if (!node) { 709 709 + pr_err("find target, node: %pOF, path '%s' not found\n", 710 710 + info_node, target_path); 711 711 + } 712 712 + kfree(target_path); 713 713 + } else { 714 714 + node = of_find_node_by_path(path); 715 715 + if (!node) { 716 716 + pr_err("find target, node: %pOF, path '%s' not found\n", 717 717 + info_node, path); 718 718 + } 719 719 + } 709 720 return node; 710 721 } 711 722 ··· 730 715 /** 731 716 * init_overlay_changeset() - initialize overlay changeset from overlay tree 732 717 * @ovcs: Overlay changeset to build 718 718 + * @target_base: Point to the target node to apply overlay 733 719 * 734 720 * Initialize @ovcs. Populate @ovcs->fragments with node information from 735 721 * the top level of @overlay_root. The relevant top level nodes are the ··· 741 725 * detected in @overlay_root. On error return, the caller of 742 726 * init_overlay_changeset() must call free_overlay_changeset(). 743 727 */ 744 744 - static int init_overlay_changeset(struct overlay_changeset *ovcs) 728 728 + static int init_overlay_changeset(struct overlay_changeset *ovcs, 729 729 + struct device_node *target_base) 745 730 { 746 731 struct device_node *node, *overlay_node; 747 732 struct fragment *fragment; ··· 768 751 769 752 if (!of_node_is_root(ovcs->overlay_root)) 770 753 pr_debug("%s() ovcs->overlay_root is not root\n", __func__); 771 771 - 772 772 - of_changeset_init(&ovcs->cset); 773 754 774 755 cnt = 0; 775 756 ··· 801 786 802 787 fragment = &fragments[cnt]; 803 788 fragment->overlay = overlay_node; 804 804 - fragment->target = find_target(node); 789 789 + fragment->target = find_target(node, target_base); 805 790 if (!fragment->target) { 806 791 of_node_put(fragment->overlay); 807 792 ret = -EINVAL; ··· 892 877 * 893 878 * of_overlay_apply() - Create and apply an overlay changeset 894 879 * @ovcs: overlay changeset 880 880 + * @base: point to the target node to apply overlay 895 881 * 896 882 * Creates and applies an overlay changeset. 897 883 * ··· 916 900 * the caller of of_overlay_apply() must call free_overlay_changeset(). 917 901 */ 918 902 919 919 - static int of_overlay_apply(struct overlay_changeset *ovcs) 903 903 + static int of_overlay_apply(struct overlay_changeset *ovcs, 904 904 + struct device_node *base) 920 905 { 921 906 int ret = 0, ret_revert, ret_tmp; 922 907 ··· 925 908 if (ret) 926 909 goto out; 927 910 928 928 - ret = init_overlay_changeset(ovcs); 911 911 + ret = init_overlay_changeset(ovcs, base); 929 912 if (ret) 930 913 goto out; 931 914 ··· 969 952 * @overlay_fdt: pointer to overlay FDT 970 953 * @overlay_fdt_size: number of bytes in @overlay_fdt 971 954 * @ret_ovcs_id: pointer for returning created changeset id 955 955 + * @base: pointer for the target node to apply overlay 972 956 * 973 957 * Creates and applies an overlay changeset. 974 958 * ··· 985 967 */ 986 968 987 969 int of_overlay_fdt_apply(const void *overlay_fdt, u32 overlay_fdt_size, 988 988 - int *ret_ovcs_id) 970 970 + int *ret_ovcs_id, struct device_node *base) 989 971 { 990 972 void *new_fdt; 991 973 void *new_fdt_align; ··· 1031 1013 1032 1014 INIT_LIST_HEAD(&ovcs->ovcs_list); 1033 1015 list_add_tail(&ovcs->ovcs_list, &ovcs_list); 1016 1016 + of_changeset_init(&ovcs->cset); 1034 1017 1035 1018 /* 1036 1019 * Must create permanent copy of FDT because of_fdt_unflatten_tree() ··· 1056 1037 } 1057 1038 ovcs->overlay_mem = overlay_mem; 1058 1039 1059 1059 - ret = of_overlay_apply(ovcs); 1040 1040 + ret = of_overlay_apply(ovcs, base); 1060 1041 /* 1061 1042 * If of_overlay_apply() error, calling free_overlay_changeset() may 1062 1043 * result in a memory leak if the apply partly succeeded, so do NOT

+39 -5

drivers/of/platform.c

reviewed

··· 21 21 #include <linux/of_platform.h> 22 22 #include <linux/platform_device.h> 23 23 24 24 + #include "of_private.h" 25 25 + 24 26 const struct of_device_id of_default_bus_match_table[] = { 25 27 { .compatible = "simple-bus", }, 26 28 { .compatible = "simple-mfd", }, ··· 30 28 #ifdef CONFIG_ARM_AMBA 31 29 { .compatible = "arm,amba-bus", }, 32 30 #endif /* CONFIG_ARM_AMBA */ 33 33 - {} /* Empty terminated list */ 34 34 - }; 35 35 - 36 36 - static const struct of_device_id of_skipped_node_table[] = { 37 37 - { .compatible = "operating-points-v2", }, 38 31 {} /* Empty terminated list */ 39 32 }; 40 33 ··· 51 54 } 52 55 EXPORT_SYMBOL(of_find_device_by_node); 53 56 57 57 + int of_device_add(struct platform_device *ofdev) 58 58 + { 59 59 + BUG_ON(ofdev->dev.of_node == NULL); 60 60 + 61 61 + /* name and id have to be set so that the platform bus doesn't get 62 62 + * confused on matching */ 63 63 + ofdev->name = dev_name(&ofdev->dev); 64 64 + ofdev->id = PLATFORM_DEVID_NONE; 65 65 + 66 66 + /* 67 67 + * If this device has not binding numa node in devicetree, that is 68 68 + * of_node_to_nid returns NUMA_NO_NODE. device_add will assume that this 69 69 + * device is on the same node as the parent. 70 70 + */ 71 71 + set_dev_node(&ofdev->dev, of_node_to_nid(ofdev->dev.of_node)); 72 72 + 73 73 + return device_add(&ofdev->dev); 74 74 + } 75 75 + 76 76 + int of_device_register(struct platform_device *pdev) 77 77 + { 78 78 + device_initialize(&pdev->dev); 79 79 + return of_device_add(pdev); 80 80 + } 81 81 + EXPORT_SYMBOL(of_device_register); 82 82 + 83 83 + void of_device_unregister(struct platform_device *ofdev) 84 84 + { 85 85 + device_unregister(&ofdev->dev); 86 86 + } 87 87 + EXPORT_SYMBOL(of_device_unregister); 88 88 + 54 89 #ifdef CONFIG_OF_ADDRESS 90 90 + static const struct of_device_id of_skipped_node_table[] = { 91 91 + { .compatible = "operating-points-v2", }, 92 92 + {} /* Empty terminated list */ 93 93 + }; 94 94 + 55 95 /* 56 96 * The following routines scan a subtree and registers a device for 57 97 * each applicable node.

+3 -1

drivers/of/unittest-data/Makefile

reviewed

··· 32 32 overlay_gpio_02b.dtbo.o \ 33 33 overlay_gpio_03.dtbo.o \ 34 34 overlay_gpio_04a.dtbo.o \ 35 35 - overlay_gpio_04b.dtbo.o 35 35 + overlay_gpio_04b.dtbo.o \ 36 36 + overlay_pci_node.dtbo.o \ 37 37 + overlay_bad_unresolved.dtbo.o 36 38 37 39 # enable creation of __symbols__ node 38 40 DTC_FLAGS_overlay += -@

+15 -17

drivers/of/unittest-data/overlay.dtso

reviewed

··· 3 3 /plugin/; 4 4 5 5 &electric_1 { 6 6 - 7 6 status = "okay"; 8 7 9 8 hvac_2: hvac-large-1 { 10 9 compatible = "ot,hvac-large"; 11 11 - heat-range = < 40 75 >; 12 12 - cool-range = < 65 80 >; 10 10 + heat-range = <40 75>; 11 11 + cool-range = <65 80>; 13 12 }; 14 13 }; 15 14 ··· 23 24 #size-cells = <1>; 24 25 25 26 track@30 { 26 26 - incline-up = < 48 32 16 >; 27 27 + incline-up = <48 32 16>; 27 28 }; 28 29 29 30 track@40 { 30 30 - incline-up = < 47 31 15 >; 31 31 + incline-up = <47 31 15>; 31 32 }; 32 33 }; 33 34 ··· 35 36 #address-cells = <1>; 36 37 #size-cells = <1>; 37 38 compatible = "ot,ferris-wheel"; 38 38 - reg = < 0x00000200 0x100 >; 39 39 - hvac-provider = < &hvac_2 >; 40 40 - hvac-thermostat = < 27 32 > ; 41 41 - hvac-zones = < 12 5 >; 39 39 + reg = <0x00000200 0x100>; 40 40 + hvac-provider = <&hvac_2>; 41 41 + hvac-thermostat = <27 32> ; 42 42 + hvac-zones = <12 5>; 42 43 hvac-zone-names = "operator", "snack-bar"; 43 43 - spin-controller = < &spin_ctrl_1 3 >; 44 44 - spin-rph = < 30 >; 45 45 - gondolas = < 16 >; 46 46 - gondola-capacity = < 6 >; 44 44 + spin-controller = <&spin_ctrl_1 3>; 45 45 + spin-rph = <30>; 46 46 + gondolas = <16>; 47 47 + gondola-capacity = <6>; 47 48 48 49 ride_200_left: track@10 { 49 49 - reg = < 0x00000010 0x10 >; 50 50 + reg = <0x00000010 0x10>; 50 51 }; 51 52 52 53 ride_200_right: track@20 { 53 53 - reg = < 0x00000020 0x10 >; 54 54 + reg = <0x00000020 0x10>; 54 55 }; 55 56 }; 56 57 }; 57 58 58 59 &lights_2 { 59 59 - 60 60 status = "okay"; 61 61 color = "purple", "white", "red", "green"; 62 62 - rate = < 3 256 >; 62 62 + rate = <3 256>; 63 63 };

+3 -8

drivers/of/unittest-data/overlay_0.dtso

reviewed

··· 2 2 /dts-v1/; 3 3 /plugin/; 4 4 5 5 - / { 6 6 - /* overlay_0 - enable using absolute target path */ 5 5 + /* overlay_0 - enable using absolute target path */ 7 6 8 8 - fragment@0 { 9 9 - target-path = "/testcase-data/overlay-node/test-bus/test-unittest0"; 10 10 - __overlay__ { 11 11 - status = "okay"; 12 12 - }; 13 13 - }; 7 7 + &{/testcase-data/overlay-node/test-bus/test-unittest0} { 8 8 + status = "okay"; 14 9 };

+3 -8

drivers/of/unittest-data/overlay_1.dtso

reviewed

··· 2 2 /dts-v1/; 3 3 /plugin/; 4 4 5 5 - / { 6 6 - /* overlay_1 - disable using absolute target path */ 5 5 + /* overlay_1 - disable using absolute target path */ 7 6 8 8 - fragment@0 { 9 9 - target-path = "/testcase-data/overlay-node/test-bus/test-unittest1"; 10 10 - __overlay__ { 11 11 - status = "disabled"; 12 12 - }; 13 13 - }; 7 7 + &{/testcase-data/overlay-node/test-bus/test-unittest1} { 8 8 + status = "disabled"; 14 9 };

-1

drivers/of/unittest-data/overlay_11.dtso

reviewed

··· 23 23 status = "okay"; 24 24 reg = <1>; 25 25 }; 26 26 - 27 26 }; 28 27 };

+3 -8

drivers/of/unittest-data/overlay_12.dtso

reviewed

··· 2 2 /dts-v1/; 3 3 /plugin/; 4 4 5 5 - / { 6 6 - /* overlay_12 - enable using absolute target path (i2c) */ 5 5 + /* overlay_12 - enable using absolute target path (i2c) */ 7 6 8 8 - fragment@0 { 9 9 - target-path = "/testcase-data/overlay-node/test-bus/i2c-test-bus/test-unittest12"; 10 10 - __overlay__ { 11 11 - status = "okay"; 12 12 - }; 13 13 - }; 7 7 + &{/testcase-data/overlay-node/test-bus/i2c-test-bus/test-unittest12} { 8 8 + status = "okay"; 14 9 };

+3 -8

drivers/of/unittest-data/overlay_13.dtso

reviewed

··· 2 2 /dts-v1/; 3 3 /plugin/; 4 4 5 5 - / { 6 6 - /* overlay_13 - disable using absolute target path (i2c) */ 5 5 + /* overlay_13 - disable using absolute target path (i2c) */ 7 6 8 8 - fragment@0 { 9 9 - target-path = "/testcase-data/overlay-node/test-bus/i2c-test-bus/test-unittest13"; 10 10 - __overlay__ { 11 11 - status = "disabled"; 12 12 - }; 13 13 - }; 7 7 + &{/testcase-data/overlay-node/test-bus/i2c-test-bus/test-unittest13} { 8 8 + status = "disabled"; 14 9 };

+1

drivers/of/unittest-data/overlay_15.dtso

reviewed

··· 7 7 &unittest_i2c_test_bus { 8 8 #address-cells = <1>; 9 9 #size-cells = <0>; 10 10 + 10 11 test-unittest15 { 11 12 reg = <11>; 12 13 compatible = "unittest-i2c-mux";

-1

drivers/of/unittest-data/overlay_4.dtso

reviewed

··· 5 5 /* overlay_4 - test insertion of a full node */ 6 6 7 7 &unittest_test_bus { 8 8 - 9 8 /* suppress DTC warning */ 10 9 #address-cells = <1>; 11 10 #size-cells = <0>;

+4 -5

drivers/of/unittest-data/overlay_bad_add_dup_node.dtso

reviewed

··· 13 13 */ 14 14 15 15 &electric_1 { 16 16 - 17 16 motor-1 { 18 17 controller { 19 19 - power_bus = < 0x1 0x2 >; 18 18 + power_bus = <0x1 0x2>; 20 19 }; 21 20 }; 22 21 }; 23 22 24 23 &spin_ctrl_1 { 25 25 - controller { 26 26 - power_bus_emergency = < 0x101 0x102 >; 27 27 - }; 24 24 + controller { 25 25 + power_bus_emergency = <0x101 0x102>; 26 26 + }; 28 27 };

+4 -5

drivers/of/unittest-data/overlay_bad_add_dup_prop.dtso

reviewed

··· 24 24 */ 25 25 26 26 &electric_1 { 27 27 - 28 27 motor-1 { 29 28 electric { 30 30 - rpm_avail = < 100 >; 29 29 + rpm_avail = <100>; 31 30 }; 32 31 }; 33 32 }; 34 33 35 34 &spin_ctrl_1 { 36 36 - electric { 37 37 - rpm_avail = < 100 200 >; 38 38 - }; 35 35 + electric { 36 36 + rpm_avail = <100 200>; 37 37 + }; 39 38 };

+2 -3

drivers/of/unittest-data/overlay_bad_phandle.dtso

reviewed

··· 3 3 /plugin/; 4 4 5 5 &electric_1 { 6 6 - 7 6 // This label should cause an error when the overlay 8 7 // is applied. There is already a phandle value 9 8 // in the base tree for motor-1. 10 9 spin_ctrl_1_conflict: motor-1 { 11 11 - accelerate = < 3 >; 12 12 - decelerate = < 5 >; 10 10 + accelerate = <3>; 11 11 + decelerate = <5>; 13 12 }; 14 13 };

+2 -3

drivers/of/unittest-data/overlay_bad_symbol.dtso

reviewed

··· 3 3 /plugin/; 4 4 5 5 &electric_1 { 6 6 - 7 6 // This label should cause an error when the overlay 8 7 // is applied. There is already a symbol hvac_1 9 8 // in the base tree 10 9 hvac_1: hvac-medium-2 { 11 10 compatible = "ot,hvac-medium"; 12 12 - heat-range = < 50 75 >; 13 13 - cool-range = < 60 80 >; 11 11 + heat-range = <50 75>; 12 12 + cool-range = <60 80>; 14 13 }; 15 14 16 15 };

+7

drivers/of/unittest-data/overlay_bad_unresolved.dtso

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /dts-v1/; 3 3 + /plugin/; 4 4 + 5 5 + &this_label_does_not_exist { 6 6 + status = "ok"; 7 7 + };

+17 -19

drivers/of/unittest-data/overlay_common.dtsi

reviewed

··· 16 16 17 17 electric_1: substation@100 { 18 18 compatible = "ot,big-volts-control"; 19 19 - reg = < 0x00000100 0x100 >; 19 19 + reg = <0x00000100 0x100>; 20 20 status = "disabled"; 21 21 22 22 hvac_1: hvac-medium-1 { 23 23 compatible = "ot,hvac-medium"; 24 24 - heat-range = < 50 75 >; 25 25 - cool-range = < 60 80 >; 24 24 + heat-range = <50 75>; 25 25 + cool-range = <60 80>; 26 26 }; 27 27 28 28 spin_ctrl_1: motor-1 { 29 29 compatible = "ot,ferris-wheel-motor"; 30 30 spin = "clockwise"; 31 31 - rpm_avail = < 50 >; 31 31 + rpm_avail = <50>; 32 32 }; 33 33 34 34 spin_ctrl_2: motor-8 { ··· 41 41 #size-cells = <1>; 42 42 compatible = "ot,rides"; 43 43 status = "disabled"; 44 44 - orientation = < 127 >; 44 44 + orientation = <127>; 45 45 46 46 ride@100 { 47 47 #address-cells = <1>; 48 48 #size-cells = <1>; 49 49 compatible = "ot,roller-coaster"; 50 50 - reg = < 0x00000100 0x100 >; 51 51 - hvac-provider = < &hvac_1 >; 52 52 - hvac-thermostat = < 29 > ; 53 53 - hvac-zones = < 14 >; 50 50 + reg = <0x00000100 0x100>; 51 51 + hvac-provider = <&hvac_1>; 52 52 + hvac-thermostat = <29> ; 53 53 + hvac-zones = <14>; 54 54 hvac-zone-names = "operator"; 55 55 - spin-controller = < &spin_ctrl_2 5 &spin_ctrl_2 7 >; 55 55 + spin-controller = <&spin_ctrl_2 5 &spin_ctrl_2 7>; 56 56 spin-controller-names = "track_1", "track_2"; 57 57 - queues = < 2 >; 57 57 + queues = <2>; 58 58 59 59 track@30 { 60 60 - reg = < 0x00000030 0x10 >; 60 60 + reg = <0x00000030 0x10>; 61 61 }; 62 62 63 63 track@40 { 64 64 - reg = < 0x00000040 0x10 >; 64 64 + reg = <0x00000040 0x10>; 65 65 }; 66 66 67 67 }; ··· 69 69 70 70 lights_1: lights@30000 { 71 71 compatible = "ot,work-lights"; 72 72 - reg = < 0x00030000 0x1000 >; 72 72 + reg = <0x00030000 0x1000>; 73 73 status = "disabled"; 74 74 }; 75 75 76 76 lights_2: lights@40000 { 77 77 compatible = "ot,show-lights"; 78 78 - reg = < 0x00040000 0x1000 >; 78 78 + reg = <0x00040000 0x1000>; 79 79 status = "disabled"; 80 80 - rate = < 13 138 >; 80 80 + rate = <13 138>; 81 81 }; 82 82 83 83 retail_1: vending@50000 { 84 84 - reg = < 0x00050000 0x1000 >; 84 84 + reg = <0x00050000 0x1000>; 85 85 compatible = "ot,tickets"; 86 86 status = "disabled"; 87 87 }; 88 88 - 89 88 }; 90 89 }; 91 91 -

+1

drivers/of/unittest-data/overlay_gpio_01.dtso

reviewed

··· 5 5 &unittest_test_bus { 6 6 #address-cells = <1>; 7 7 #size-cells = <0>; 8 8 + 8 9 gpio@0 { 9 10 compatible = "unittest-gpio"; 10 11 reg = <0>;

+1

drivers/of/unittest-data/overlay_gpio_02a.dtso

reviewed

··· 5 5 &unittest_test_bus { 6 6 #address-cells = <1>; 7 7 #size-cells = <0>; 8 8 + 8 9 gpio@2 { 9 10 compatible = "unittest-gpio"; 10 11 reg = <2>;

+1

drivers/of/unittest-data/overlay_gpio_02b.dtso

reviewed

··· 5 5 &unittest_test_bus { 6 6 #address-cells = <1>; 7 7 #size-cells = <0>; 8 8 + 8 9 gpio@2 { 9 10 line-a { 10 11 gpio-hog;

+1

drivers/of/unittest-data/overlay_gpio_03.dtso

reviewed

··· 5 5 &unittest_test_bus { 6 6 #address-cells = <1>; 7 7 #size-cells = <0>; 8 8 + 8 9 gpio@3 { 9 10 compatible = "unittest-gpio"; 10 11 reg = <3>;

+1

drivers/of/unittest-data/overlay_gpio_04a.dtso

reviewed

··· 5 5 &unittest_test_bus { 6 6 #address-cells = <1>; 7 7 #size-cells = <0>; 8 8 + 8 9 gpio@4 { 9 10 compatible = "unittest-gpio"; 10 11 reg = <4>;

+1

drivers/of/unittest-data/overlay_gpio_04b.dtso

reviewed

··· 5 5 &unittest_test_bus { 6 6 #address-cells = <1>; 7 7 #size-cells = <0>; 8 8 + 8 9 gpio@4 { 9 10 line-c { 10 11 gpio-hog;

+22

drivers/of/unittest-data/overlay_pci_node.dtso

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /dts-v1/; 3 3 + / { 4 4 + fragment@0 { 5 5 + target-path=""; 6 6 + __overlay__ { 7 7 + #address-cells = <3>; 8 8 + #size-cells = <2>; 9 9 + pci-ep-bus@0 { 10 10 + compatible = "simple-bus"; 11 11 + #address-cells = <1>; 12 12 + #size-cells = <1>; 13 13 + ranges = <0x0 0x0 0x0 0x0 0x1000>; 14 14 + reg = <0 0 0 0 0>; 15 15 + unittest-pci@100 { 16 16 + compatible = "unittest-pci"; 17 17 + reg = <0x100 0x200>; 18 18 + }; 19 19 + }; 20 20 + }; 21 21 + }; 22 22 + };

+1

drivers/of/unittest-data/testcases_common.dtsi

reviewed

··· 5 5 changeset { 6 6 prop-update = "hello"; 7 7 prop-remove = "world"; 8 8 + 8 9 node-remove { 9 10 }; 10 11 };

+1

drivers/of/unittest-data/tests-interrupts.dtsi

reviewed

··· 5 5 interrupts { 6 6 #address-cells = <1>; 7 7 #size-cells = <1>; 8 8 + 8 9 test_intc0: intc0 { 9 10 interrupt-controller; 10 11 #interrupt-cells = <1>;

-1

drivers/of/unittest-data/tests-overlay.dtsi

reviewed

··· 3 3 / { 4 4 testcase-data { 5 5 overlay-node { 6 6 - 7 6 /* test bus */ 8 7 unittest_test_bus: test-bus { 9 8 compatible = "simple-bus";

+2

drivers/of/unittest-data/tests-phandle.dtsi

reviewed

··· 8 8 testcase: testcase-data { 9 9 security-password = "password"; 10 10 duplicate-name = "duplicate"; 11 11 + 11 12 duplicate-name { }; 13 13 + 12 14 phandle-tests { 13 15 provider0: provider0 { 14 16 #phandle-cells = <0>;

+377 -99

drivers/of/unittest.c

reviewed

··· 22 22 #include <linux/slab.h> 23 23 #include <linux/device.h> 24 24 #include <linux/platform_device.h> 25 25 + #include <linux/pci.h> 25 26 #include <linux/kernel.h> 26 27 27 28 #include <linux/i2c.h> ··· 78 77 79 78 np = of_find_node_by_path("/testcase-data"); 80 79 name = kasprintf(GFP_KERNEL, "%pOF", np); 81 81 - unittest(np && !strcmp("/testcase-data", name), 80 80 + unittest(np && name && !strcmp("/testcase-data", name), 82 81 "find /testcase-data failed\n"); 83 82 of_node_put(np); 84 83 kfree(name); ··· 89 88 90 89 np = of_find_node_by_path("/testcase-data/phandle-tests/consumer-a"); 91 90 name = kasprintf(GFP_KERNEL, "%pOF", np); 92 92 - unittest(np && !strcmp("/testcase-data/phandle-tests/consumer-a", name), 91 91 + unittest(np && name && !strcmp("/testcase-data/phandle-tests/consumer-a", name), 93 92 "find /testcase-data/phandle-tests/consumer-a failed\n"); 94 93 of_node_put(np); 95 94 kfree(name); 96 95 97 96 np = of_find_node_by_path("testcase-alias"); 98 97 name = kasprintf(GFP_KERNEL, "%pOF", np); 99 99 - unittest(np && !strcmp("/testcase-data", name), 98 98 + unittest(np && name && !strcmp("/testcase-data", name), 100 99 "find testcase-alias failed\n"); 101 100 of_node_put(np); 102 101 kfree(name); ··· 107 106 108 107 np = of_find_node_by_path("testcase-alias/phandle-tests/consumer-a"); 109 108 name = kasprintf(GFP_KERNEL, "%pOF", np); 110 110 - unittest(np && !strcmp("/testcase-data/phandle-tests/consumer-a", name), 109 109 + unittest(np && name && !strcmp("/testcase-data/phandle-tests/consumer-a", name), 111 110 "find testcase-alias/phandle-tests/consumer-a failed\n"); 112 111 of_node_put(np); 113 112 kfree(name); ··· 797 796 static void __init of_unittest_changeset(void) 798 797 { 799 798 #ifdef CONFIG_OF_DYNAMIC 799 799 + int ret; 800 800 struct property *ppadd, padd = { .name = "prop-add", .length = 1, .value = "" }; 801 801 struct property *ppname_n1, pname_n1 = { .name = "name", .length = 3, .value = "n1" }; 802 802 struct property *ppname_n2, pname_n2 = { .name = "name", .length = 3, .value = "n2" }; 803 803 struct property *ppname_n21, pname_n21 = { .name = "name", .length = 3, .value = "n21" }; 804 804 struct property *ppupdate, pupdate = { .name = "prop-update", .length = 5, .value = "abcd" }; 805 805 struct property *ppremove; 806 806 - struct device_node *n1, *n2, *n21, *nchangeset, *nremove, *parent, *np; 806 806 + struct device_node *n1, *n2, *n21, *n22, *nchangeset, *nremove, *parent, *np; 807 807 + static const char * const str_array[] = { "str1", "str2", "str3" }; 808 808 + const u32 u32_array[] = { 1, 2, 3 }; 807 809 struct of_changeset chgset; 810 810 + const char *propstr = NULL; 808 811 809 812 n1 = __of_node_dup(NULL, "n1"); 810 813 unittest(n1, "testcase setup failure\n"); ··· 862 857 unittest(!of_changeset_add_property(&chgset, parent, ppadd), "fail add prop prop-add\n"); 863 858 unittest(!of_changeset_update_property(&chgset, parent, ppupdate), "fail update prop\n"); 864 859 unittest(!of_changeset_remove_property(&chgset, parent, ppremove), "fail remove prop\n"); 860 860 + n22 = of_changeset_create_node(&chgset, n2, "n22"); 861 861 + unittest(n22, "fail create n22\n"); 862 862 + unittest(!of_changeset_add_prop_string(&chgset, n22, "prop-str", "abcd"), 863 863 + "fail add prop prop-str"); 864 864 + unittest(!of_changeset_add_prop_string_array(&chgset, n22, "prop-str-array", 865 865 + (const char **)str_array, 866 866 + ARRAY_SIZE(str_array)), 867 867 + "fail add prop prop-str-array"); 868 868 + unittest(!of_changeset_add_prop_u32_array(&chgset, n22, "prop-u32-array", 869 869 + u32_array, ARRAY_SIZE(u32_array)), 870 870 + "fail add prop prop-u32-array"); 865 871 866 872 unittest(!of_changeset_apply(&chgset), "apply failed\n"); 867 873 ··· 882 866 unittest((np = of_find_node_by_path("/testcase-data/changeset/n2/n21")), 883 867 "'%pOF' not added\n", n21); 884 868 of_node_put(np); 869 869 + unittest((np = of_find_node_by_path("/testcase-data/changeset/n2/n22")), 870 870 + "'%pOF' not added\n", n22); 871 871 + of_node_put(np); 885 872 886 873 unittest(!of_changeset_revert(&chgset), "revert failed\n"); 874 874 + 875 875 + unittest(!of_find_node_by_path("/testcase-data/changeset/n2/n21"), 876 876 + "'%pOF' still present after revert\n", n21); 877 877 + 878 878 + ppremove = of_find_property(parent, "prop-remove", NULL); 879 879 + unittest(ppremove, "failed to find removed prop after revert\n"); 880 880 + 881 881 + ret = of_property_read_string(parent, "prop-update", &propstr); 882 882 + unittest(!ret, "failed to find updated prop after revert\n"); 883 883 + if (!ret) 884 884 + unittest(strcmp(propstr, "hello") == 0, "original value not in updated property after revert"); 887 885 888 886 of_changeset_destroy(&chgset); 889 887 890 888 of_node_put(n1); 891 889 of_node_put(n2); 892 890 of_node_put(n21); 891 891 + of_node_put(n22); 893 892 #endif 894 893 } 895 894 ··· 1564 1533 const char *full_name; 1565 1534 1566 1535 full_name = kasprintf(GFP_KERNEL, "%pOF", np); 1536 1536 + if (!full_name) 1537 1537 + return; 1567 1538 1568 1539 if (!strcmp(full_name, "/__local_fixups__") || 1569 1540 !strcmp(full_name, "/__fixups__")) { ··· 1727 1694 .remove_new = unittest_remove, 1728 1695 .driver = { 1729 1696 .name = "unittest", 1730 1730 - .of_match_table = of_match_ptr(unittest_match), 1697 1697 + .of_match_table = unittest_match, 1731 1698 }, 1732 1699 }; 1733 1700 ··· 1828 1795 .remove_new = unittest_gpio_remove, 1829 1796 .driver = { 1830 1797 .name = "unittest-gpio", 1831 1831 - .of_match_table = of_match_ptr(unittest_gpio_id), 1798 1798 + .of_match_table = unittest_gpio_id, 1832 1799 }, 1833 1800 }; 1834 1801 ··· 2134 2101 return 0; 2135 2102 } 2136 2103 2137 2137 - /* apply an overlay while checking before and after states */ 2138 2138 - static int __init of_unittest_apply_overlay_check(int overlay_nr, 2104 2104 + static int __init __of_unittest_apply_overlay_check(int overlay_nr, 2139 2105 int unittest_nr, int before, int after, 2140 2106 enum overlay_type ovtype) 2141 2107 { 2142 2108 int ret, ovcs_id; 2143 2143 - 2144 2144 - /* unittest device must not be in before state */ 2145 2145 - if (of_unittest_device_exists(unittest_nr, ovtype) != before) { 2146 2146 - unittest(0, "%s with device @\"%s\" %s\n", 2147 2147 - overlay_name_from_nr(overlay_nr), 2148 2148 - unittest_path(unittest_nr, ovtype), 2149 2149 - !before ? "enabled" : "disabled"); 2150 2150 - return -EINVAL; 2151 2151 - } 2152 2152 - 2153 2153 - ovcs_id = 0; 2154 2154 - ret = of_unittest_apply_overlay(overlay_nr, &ovcs_id); 2155 2155 - if (ret != 0) { 2156 2156 - /* of_unittest_apply_overlay already called unittest() */ 2157 2157 - return ret; 2158 2158 - } 2159 2159 - 2160 2160 - /* unittest device must be to set to after state */ 2161 2161 - if (of_unittest_device_exists(unittest_nr, ovtype) != after) { 2162 2162 - unittest(0, "%s failed to create @\"%s\" %s\n", 2163 2163 - overlay_name_from_nr(overlay_nr), 2164 2164 - unittest_path(unittest_nr, ovtype), 2165 2165 - !after ? "enabled" : "disabled"); 2166 2166 - return -EINVAL; 2167 2167 - } 2168 2168 - 2169 2169 - return 0; 2170 2170 - } 2171 2171 - 2172 2172 - /* apply an overlay and then revert it while checking before, after states */ 2173 2173 - static int __init of_unittest_apply_revert_overlay_check(int overlay_nr, 2174 2174 - int unittest_nr, int before, int after, 2175 2175 - enum overlay_type ovtype) 2176 2176 - { 2177 2177 - int ret, ovcs_id, save_ovcs_id; 2178 2109 2179 2110 /* unittest device must be in before state */ 2180 2111 if (of_unittest_device_exists(unittest_nr, ovtype) != before) { ··· 2159 2162 2160 2163 /* unittest device must be in after state */ 2161 2164 if (of_unittest_device_exists(unittest_nr, ovtype) != after) { 2162 2162 - unittest(0, "%s failed to create @\"%s\" %s\n", 2165 2165 + unittest(0, "%s with device @\"%s\" %s\n", 2163 2166 overlay_name_from_nr(overlay_nr), 2164 2167 unittest_path(unittest_nr, ovtype), 2165 2168 !after ? "enabled" : "disabled"); 2166 2169 return -EINVAL; 2167 2170 } 2168 2171 2172 2172 + return ovcs_id; 2173 2173 + } 2174 2174 + 2175 2175 + /* apply an overlay while checking before and after states */ 2176 2176 + static int __init of_unittest_apply_overlay_check(int overlay_nr, 2177 2177 + int unittest_nr, int before, int after, 2178 2178 + enum overlay_type ovtype) 2179 2179 + { 2180 2180 + int ovcs_id = __of_unittest_apply_overlay_check(overlay_nr, 2181 2181 + unittest_nr, before, after, ovtype); 2182 2182 + if (ovcs_id < 0) 2183 2183 + return ovcs_id; 2184 2184 + 2185 2185 + return 0; 2186 2186 + } 2187 2187 + 2188 2188 + /* apply an overlay and then revert it while checking before, after states */ 2189 2189 + static int __init of_unittest_apply_revert_overlay_check(int overlay_nr, 2190 2190 + int unittest_nr, int before, int after, 2191 2191 + enum overlay_type ovtype) 2192 2192 + { 2193 2193 + int ret, ovcs_id, save_ovcs_id; 2194 2194 + 2195 2195 + ovcs_id = __of_unittest_apply_overlay_check(overlay_nr, unittest_nr, 2196 2196 + before, after, ovtype); 2197 2197 + if (ovcs_id < 0) 2198 2198 + return ovcs_id; 2199 2199 + 2200 2200 + /* remove the overlay */ 2169 2201 save_ovcs_id = ovcs_id; 2170 2202 ret = of_overlay_remove(&ovcs_id); 2171 2203 if (ret != 0) { ··· 2206 2180 of_unittest_untrack_overlay(save_ovcs_id); 2207 2181 2208 2182 /* unittest device must be again in before state */ 2209 2209 - if (of_unittest_device_exists(unittest_nr, PDEV_OVERLAY) != before) { 2183 2183 + if (of_unittest_device_exists(unittest_nr, ovtype) != before) { 2210 2184 unittest(0, "%s with device @\"%s\" %s\n", 2211 2185 overlay_name_from_nr(overlay_nr), 2212 2186 unittest_path(unittest_nr, ovtype), ··· 2648 2622 .remove_new = unittest_i2c_bus_remove, 2649 2623 .driver = { 2650 2624 .name = "unittest-i2c-bus", 2651 2651 - .of_match_table = of_match_ptr(unittest_i2c_bus_match), 2625 2625 + .of_match_table = unittest_i2c_bus_match, 2652 2626 }, 2653 2627 }; 2654 2628 ··· 2997 2971 2998 2972 unittest(ovcs_id, "ovcs_id not created for overlay_17\n"); 2999 2973 3000 3000 - if (ovcs_id) { 3001 3001 - ret = of_overlay_remove(&ovcs_id); 3002 3002 - unittest(!ret, 3003 3003 - "overlay_17 of_overlay_remove(), ret = %d\n", ret); 3004 3004 - } 3005 3005 - 3006 2974 /* --- overlay 18 --- */ 3007 2975 3008 2976 unittest(overlay_data_apply("overlay_18", &ovcs_id), ··· 3066 3046 static void __init of_unittest_overlay(void) 3067 3047 { 3068 3048 struct device_node *bus_np = NULL; 3049 3049 + unsigned int i; 3069 3050 3070 3051 if (platform_driver_register(&unittest_driver)) { 3071 3052 unittest(0, "could not register unittest driver\n"); ··· 3104 3083 of_unittest_overlay_2(); 3105 3084 of_unittest_overlay_3(); 3106 3085 of_unittest_overlay_4(); 3107 3107 - of_unittest_overlay_5(); 3086 3086 + for (i = 0; i < 3; i++) 3087 3087 + of_unittest_overlay_5(); 3108 3088 of_unittest_overlay_6(); 3109 3089 of_unittest_overlay_8(); 3110 3090 ··· 3286 3264 extern uint8_t __dtbo_##overlay_name##_begin[]; \ 3287 3265 extern uint8_t __dtbo_##overlay_name##_end[] 3288 3266 3289 3289 - #define OVERLAY_INFO(overlay_name, expected) \ 3290 3290 - { .dtbo_begin = __dtbo_##overlay_name##_begin, \ 3291 3291 - .dtbo_end = __dtbo_##overlay_name##_end, \ 3292 3292 - .expected_result = expected, \ 3293 3293 - .name = #overlay_name, \ 3267 3267 + #define OVERLAY_INFO(overlay_name, expected, expected_remove) \ 3268 3268 + { .dtbo_begin = __dtbo_##overlay_name##_begin, \ 3269 3269 + .dtbo_end = __dtbo_##overlay_name##_end, \ 3270 3270 + .expected_result = expected, \ 3271 3271 + .expected_result_remove = expected_remove, \ 3272 3272 + .name = #overlay_name, \ 3294 3273 } 3295 3274 3296 3275 struct overlay_info { 3297 3276 uint8_t *dtbo_begin; 3298 3277 uint8_t *dtbo_end; 3299 3278 int expected_result; 3279 3279 + int expected_result_remove; /* if apply failed */ 3300 3280 int ovcs_id; 3301 3281 char *name; 3302 3282 }; ··· 3331 3307 OVERLAY_INFO_EXTERN(overlay_gpio_03); 3332 3308 OVERLAY_INFO_EXTERN(overlay_gpio_04a); 3333 3309 OVERLAY_INFO_EXTERN(overlay_gpio_04b); 3310 3310 + OVERLAY_INFO_EXTERN(overlay_pci_node); 3334 3311 OVERLAY_INFO_EXTERN(overlay_bad_add_dup_node); 3335 3312 OVERLAY_INFO_EXTERN(overlay_bad_add_dup_prop); 3336 3313 OVERLAY_INFO_EXTERN(overlay_bad_phandle); 3337 3314 OVERLAY_INFO_EXTERN(overlay_bad_symbol); 3315 3315 + OVERLAY_INFO_EXTERN(overlay_bad_unresolved); 3338 3316 3339 3317 /* entries found by name */ 3340 3318 static struct overlay_info overlays[] = { 3341 3341 - OVERLAY_INFO(overlay_base, -9999), 3342 3342 - OVERLAY_INFO(overlay, 0), 3343 3343 - OVERLAY_INFO(overlay_0, 0), 3344 3344 - OVERLAY_INFO(overlay_1, 0), 3345 3345 - OVERLAY_INFO(overlay_2, 0), 3346 3346 - OVERLAY_INFO(overlay_3, 0), 3347 3347 - OVERLAY_INFO(overlay_4, 0), 3348 3348 - OVERLAY_INFO(overlay_5, 0), 3349 3349 - OVERLAY_INFO(overlay_6, 0), 3350 3350 - OVERLAY_INFO(overlay_7, 0), 3351 3351 - OVERLAY_INFO(overlay_8, 0), 3352 3352 - OVERLAY_INFO(overlay_9, 0), 3353 3353 - OVERLAY_INFO(overlay_10, 0), 3354 3354 - OVERLAY_INFO(overlay_11, 0), 3355 3355 - OVERLAY_INFO(overlay_12, 0), 3356 3356 - OVERLAY_INFO(overlay_13, 0), 3357 3357 - OVERLAY_INFO(overlay_15, 0), 3358 3358 - OVERLAY_INFO(overlay_16, -EBUSY), 3359 3359 - OVERLAY_INFO(overlay_17, -EEXIST), 3360 3360 - OVERLAY_INFO(overlay_18, 0), 3361 3361 - OVERLAY_INFO(overlay_19, 0), 3362 3362 - OVERLAY_INFO(overlay_20, 0), 3363 3363 - OVERLAY_INFO(overlay_gpio_01, 0), 3364 3364 - OVERLAY_INFO(overlay_gpio_02a, 0), 3365 3365 - OVERLAY_INFO(overlay_gpio_02b, 0), 3366 3366 - OVERLAY_INFO(overlay_gpio_03, 0), 3367 3367 - OVERLAY_INFO(overlay_gpio_04a, 0), 3368 3368 - OVERLAY_INFO(overlay_gpio_04b, 0), 3369 3369 - OVERLAY_INFO(overlay_bad_add_dup_node, -EINVAL), 3370 3370 - OVERLAY_INFO(overlay_bad_add_dup_prop, -EINVAL), 3371 3371 - OVERLAY_INFO(overlay_bad_phandle, -EINVAL), 3372 3372 - OVERLAY_INFO(overlay_bad_symbol, -EINVAL), 3319 3319 + OVERLAY_INFO(overlay_base, -9999, 0), 3320 3320 + OVERLAY_INFO(overlay, 0, 0), 3321 3321 + OVERLAY_INFO(overlay_0, 0, 0), 3322 3322 + OVERLAY_INFO(overlay_1, 0, 0), 3323 3323 + OVERLAY_INFO(overlay_2, 0, 0), 3324 3324 + OVERLAY_INFO(overlay_3, 0, 0), 3325 3325 + OVERLAY_INFO(overlay_4, 0, 0), 3326 3326 + OVERLAY_INFO(overlay_5, 0, 0), 3327 3327 + OVERLAY_INFO(overlay_6, 0, 0), 3328 3328 + OVERLAY_INFO(overlay_7, 0, 0), 3329 3329 + OVERLAY_INFO(overlay_8, 0, 0), 3330 3330 + OVERLAY_INFO(overlay_9, 0, 0), 3331 3331 + OVERLAY_INFO(overlay_10, 0, 0), 3332 3332 + OVERLAY_INFO(overlay_11, 0, 0), 3333 3333 + OVERLAY_INFO(overlay_12, 0, 0), 3334 3334 + OVERLAY_INFO(overlay_13, 0, 0), 3335 3335 + OVERLAY_INFO(overlay_15, 0, 0), 3336 3336 + OVERLAY_INFO(overlay_16, -EBUSY, 0), 3337 3337 + OVERLAY_INFO(overlay_17, -EEXIST, 0), 3338 3338 + OVERLAY_INFO(overlay_18, 0, 0), 3339 3339 + OVERLAY_INFO(overlay_19, 0, 0), 3340 3340 + OVERLAY_INFO(overlay_20, 0, 0), 3341 3341 + OVERLAY_INFO(overlay_gpio_01, 0, 0), 3342 3342 + OVERLAY_INFO(overlay_gpio_02a, 0, 0), 3343 3343 + OVERLAY_INFO(overlay_gpio_02b, 0, 0), 3344 3344 + OVERLAY_INFO(overlay_gpio_03, 0, 0), 3345 3345 + OVERLAY_INFO(overlay_gpio_04a, 0, 0), 3346 3346 + OVERLAY_INFO(overlay_gpio_04b, 0, 0), 3347 3347 + OVERLAY_INFO(overlay_pci_node, 0, 0), 3348 3348 + OVERLAY_INFO(overlay_bad_add_dup_node, -EINVAL, -ENODEV), 3349 3349 + OVERLAY_INFO(overlay_bad_add_dup_prop, -EINVAL, -ENODEV), 3350 3350 + OVERLAY_INFO(overlay_bad_phandle, -EINVAL, 0), 3351 3351 + OVERLAY_INFO(overlay_bad_symbol, -EINVAL, -ENODEV), 3352 3352 + OVERLAY_INFO(overlay_bad_unresolved, -EINVAL, 0), 3373 3353 /* end marker */ 3374 3374 - {.dtbo_begin = NULL, .dtbo_end = NULL, .expected_result = 0, .name = NULL} 3354 3354 + { } 3375 3355 }; 3376 3356 3377 3357 static struct device_node *overlay_base_root; ··· 3470 3442 static int __init overlay_data_apply(const char *overlay_name, int *ovcs_id) 3471 3443 { 3472 3444 struct overlay_info *info; 3445 3445 + int passed = 1; 3473 3446 int found = 0; 3474 3474 - int ret; 3447 3447 + int ret, ret2; 3475 3448 u32 size; 3476 3449 3477 3450 for (info = overlays; info && info->name; info++) { ··· 3490 3461 if (!size) 3491 3462 pr_err("no overlay data for %s\n", overlay_name); 3492 3463 3493 3493 - ret = of_overlay_fdt_apply(info->dtbo_begin, size, &info->ovcs_id); 3464 3464 + ret = of_overlay_fdt_apply(info->dtbo_begin, size, &info->ovcs_id, 3465 3465 + NULL); 3494 3466 if (ovcs_id) 3495 3467 *ovcs_id = info->ovcs_id; 3496 3468 if (ret < 0) ··· 3500 3470 pr_debug("%s applied\n", overlay_name); 3501 3471 3502 3472 out: 3503 3503 - if (ret != info->expected_result) 3473 3473 + if (ret != info->expected_result) { 3504 3474 pr_err("of_overlay_fdt_apply() expected %d, ret=%d, %s\n", 3505 3475 info->expected_result, ret, overlay_name); 3476 3476 + passed = 0; 3477 3477 + } 3506 3478 3507 3507 - return (ret == info->expected_result); 3479 3479 + if (ret < 0) { 3480 3480 + /* changeset may be partially applied */ 3481 3481 + ret2 = of_overlay_remove(&info->ovcs_id); 3482 3482 + if (ret2 != info->expected_result_remove) { 3483 3483 + pr_err("of_overlay_remove() expected %d, ret=%d, %s\n", 3484 3484 + info->expected_result_remove, ret2, 3485 3485 + overlay_name); 3486 3486 + passed = 0; 3487 3487 + } 3488 3488 + } 3489 3489 + 3490 3490 + return passed; 3508 3491 } 3509 3492 3510 3493 /* ··· 3656 3613 3657 3614 /* now do the normal overlay usage test */ 3658 3615 3616 3616 + /* --- overlay --- */ 3617 3617 + 3659 3618 EXPECT_BEGIN(KERN_ERR, 3660 3619 "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data-2/substation@100/status"); 3661 3620 EXPECT_BEGIN(KERN_ERR, ··· 3708 3663 3709 3664 unittest(ret, "Adding overlay 'overlay' failed\n"); 3710 3665 3666 3666 + /* --- overlay_bad_add_dup_node --- */ 3667 3667 + 3711 3668 EXPECT_BEGIN(KERN_ERR, 3712 3669 "OF: overlay: ERROR: multiple fragments add and/or delete node /testcase-data-2/substation@100/motor-1/controller"); 3713 3670 EXPECT_BEGIN(KERN_ERR, 3714 3671 "OF: overlay: ERROR: multiple fragments add, update, and/or delete property /testcase-data-2/substation@100/motor-1/controller/name"); 3672 3672 + EXPECT_BEGIN(KERN_ERR, 3673 3673 + "OF: changeset: apply failed: REMOVE_PROPERTY /testcase-data-2/substation@100/motor-1/controller:name"); 3674 3674 + EXPECT_BEGIN(KERN_ERR, 3675 3675 + "OF: Error reverting changeset (-19)"); 3715 3676 3716 3677 unittest(overlay_data_apply("overlay_bad_add_dup_node", NULL), 3717 3678 "Adding overlay 'overlay_bad_add_dup_node' failed\n"); 3718 3679 3719 3680 EXPECT_END(KERN_ERR, 3681 3681 + "OF: Error reverting changeset (-19)"); 3682 3682 + EXPECT_END(KERN_ERR, 3683 3683 + "OF: changeset: apply failed: REMOVE_PROPERTY /testcase-data-2/substation@100/motor-1/controller:name"); 3684 3684 + EXPECT_END(KERN_ERR, 3720 3685 "OF: overlay: ERROR: multiple fragments add, update, and/or delete property /testcase-data-2/substation@100/motor-1/controller/name"); 3721 3686 EXPECT_END(KERN_ERR, 3722 3687 "OF: overlay: ERROR: multiple fragments add and/or delete node /testcase-data-2/substation@100/motor-1/controller"); 3688 3688 + 3689 3689 + /* --- overlay_bad_add_dup_prop --- */ 3723 3690 3724 3691 EXPECT_BEGIN(KERN_ERR, 3725 3692 "OF: overlay: ERROR: multiple fragments add and/or delete node /testcase-data-2/substation@100/motor-1/electric"); ··· 3739 3682 "OF: overlay: ERROR: multiple fragments add, update, and/or delete property /testcase-data-2/substation@100/motor-1/electric/rpm_avail"); 3740 3683 EXPECT_BEGIN(KERN_ERR, 3741 3684 "OF: overlay: ERROR: multiple fragments add, update, and/or delete property /testcase-data-2/substation@100/motor-1/electric/name"); 3685 3685 + EXPECT_BEGIN(KERN_ERR, 3686 3686 + "OF: changeset: apply failed: REMOVE_PROPERTY /testcase-data-2/substation@100/motor-1/electric:name"); 3687 3687 + EXPECT_BEGIN(KERN_ERR, 3688 3688 + "OF: Error reverting changeset (-19)"); 3742 3689 3743 3690 unittest(overlay_data_apply("overlay_bad_add_dup_prop", NULL), 3744 3691 "Adding overlay 'overlay_bad_add_dup_prop' failed\n"); 3745 3692 3746 3693 EXPECT_END(KERN_ERR, 3747 3747 - "OF: overlay: ERROR: multiple fragments add, update, and/or delete property /testcase-data-2/substation@100/motor-1/electric/name"); 3694 3694 + "OF: Error reverting changeset (-19)"); 3748 3695 EXPECT_END(KERN_ERR, 3749 3749 - "OF: overlay: ERROR: multiple fragments add, update, and/or delete property /testcase-data-2/substation@100/motor-1/electric/rpm_avail"); 3696 3696 + "OF: changeset: apply failed: REMOVE_PROPERTY /testcase-data-2/substation@100/motor-1/electric:name"); 3750 3697 EXPECT_END(KERN_ERR, 3751 3751 - "OF: overlay: ERROR: multiple fragments add and/or delete node /testcase-data-2/substation@100/motor-1/electric"); 3698 3698 + "OF: overlay: ERROR: multiple fragments add, update, and/or delete property /testcase-data-2/substation@100/motor-1/electric/name"); 3699 3699 + EXPECT_END(KERN_ERR, 3700 3700 + "OF: overlay: ERROR: multiple fragments add, update, and/or delete property /testcase-data-2/substation@100/motor-1/electric/rpm_avail"); 3701 3701 + EXPECT_END(KERN_ERR, 3702 3702 + "OF: overlay: ERROR: multiple fragments add and/or delete node /testcase-data-2/substation@100/motor-1/electric"); 3703 3703 + 3704 3704 + /* --- overlay_bad_phandle --- */ 3752 3705 3753 3706 unittest(overlay_data_apply("overlay_bad_phandle", NULL), 3754 3707 "Adding overlay 'overlay_bad_phandle' failed\n"); 3755 3708 3709 3709 + /* --- overlay_bad_symbol --- */ 3710 3710 + 3711 3711 + EXPECT_BEGIN(KERN_ERR, 3712 3712 + "OF: changeset: apply failed: REMOVE_PROPERTY /testcase-data-2/substation@100/hvac-medium-2:name"); 3713 3713 + EXPECT_BEGIN(KERN_ERR, 3714 3714 + "OF: Error reverting changeset (-19)"); 3715 3715 + 3756 3716 unittest(overlay_data_apply("overlay_bad_symbol", NULL), 3757 3717 "Adding overlay 'overlay_bad_symbol' failed\n"); 3718 3718 + 3719 3719 + EXPECT_END(KERN_ERR, 3720 3720 + "OF: Error reverting changeset (-19)"); 3721 3721 + EXPECT_END(KERN_ERR, 3722 3722 + "OF: changeset: apply failed: REMOVE_PROPERTY /testcase-data-2/substation@100/hvac-medium-2:name"); 3723 3723 + 3724 3724 + /* --- overlay_bad_unresolved --- */ 3725 3725 + 3726 3726 + EXPECT_BEGIN(KERN_ERR, 3727 3727 + "OF: resolver: node label 'this_label_does_not_exist' not found in live devicetree symbols table"); 3728 3728 + EXPECT_BEGIN(KERN_ERR, 3729 3729 + "OF: resolver: overlay phandle fixup failed: -22"); 3730 3730 + 3731 3731 + unittest(overlay_data_apply("overlay_bad_unresolved", NULL), 3732 3732 + "Adding overlay 'overlay_bad_unresolved' failed\n"); 3733 3733 + 3734 3734 + EXPECT_END(KERN_ERR, 3735 3735 + "OF: resolver: overlay phandle fixup failed: -22"); 3736 3736 + EXPECT_END(KERN_ERR, 3737 3737 + "OF: resolver: node label 'this_label_does_not_exist' not found in live devicetree symbols table"); 3758 3738 3759 3739 return; 3760 3740 ··· 3799 3705 mutex_unlock(&of_mutex); 3800 3706 } 3801 3707 3708 3708 + static int of_unittest_pci_dev_num; 3709 3709 + static int of_unittest_pci_child_num; 3710 3710 + 3711 3711 + /* 3712 3712 + * PCI device tree node test driver 3713 3713 + */ 3714 3714 + static const struct pci_device_id testdrv_pci_ids[] = { 3715 3715 + { PCI_DEVICE(PCI_VENDOR_ID_REDHAT, 0x5), }, /* PCI_VENDOR_ID_REDHAT */ 3716 3716 + { 0, } 3717 3717 + }; 3718 3718 + 3719 3719 + static int testdrv_probe(struct pci_dev *pdev, const struct pci_device_id *id) 3720 3720 + { 3721 3721 + struct overlay_info *info; 3722 3722 + struct device_node *dn; 3723 3723 + int ret, ovcs_id; 3724 3724 + u32 size; 3725 3725 + 3726 3726 + dn = pdev->dev.of_node; 3727 3727 + if (!dn) { 3728 3728 + dev_err(&pdev->dev, "does not find bus endpoint"); 3729 3729 + return -EINVAL; 3730 3730 + } 3731 3731 + 3732 3732 + for (info = overlays; info && info->name; info++) { 3733 3733 + if (!strcmp(info->name, "overlay_pci_node")) 3734 3734 + break; 3735 3735 + } 3736 3736 + if (!info || !info->name) { 3737 3737 + dev_err(&pdev->dev, "no overlay data for overlay_pci_node"); 3738 3738 + return -ENODEV; 3739 3739 + } 3740 3740 + 3741 3741 + size = info->dtbo_end - info->dtbo_begin; 3742 3742 + ret = of_overlay_fdt_apply(info->dtbo_begin, size, &ovcs_id, dn); 3743 3743 + of_node_put(dn); 3744 3744 + if (ret) 3745 3745 + return ret; 3746 3746 + 3747 3747 + of_platform_default_populate(dn, NULL, &pdev->dev); 3748 3748 + pci_set_drvdata(pdev, (void *)(uintptr_t)ovcs_id); 3749 3749 + 3750 3750 + return 0; 3751 3751 + } 3752 3752 + 3753 3753 + static void testdrv_remove(struct pci_dev *pdev) 3754 3754 + { 3755 3755 + int ovcs_id = (int)(uintptr_t)pci_get_drvdata(pdev); 3756 3756 + 3757 3757 + of_platform_depopulate(&pdev->dev); 3758 3758 + of_overlay_remove(&ovcs_id); 3759 3759 + } 3760 3760 + 3761 3761 + static struct pci_driver testdrv_driver = { 3762 3762 + .name = "pci_dt_testdrv", 3763 3763 + .id_table = testdrv_pci_ids, 3764 3764 + .probe = testdrv_probe, 3765 3765 + .remove = testdrv_remove, 3766 3766 + }; 3767 3767 + 3768 3768 + static int unittest_pci_probe(struct platform_device *pdev) 3769 3769 + { 3770 3770 + struct resource *res; 3771 3771 + struct device *dev; 3772 3772 + u64 exp_addr; 3773 3773 + 3774 3774 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3775 3775 + if (!res) 3776 3776 + return -ENODEV; 3777 3777 + 3778 3778 + dev = &pdev->dev; 3779 3779 + while (dev && !dev_is_pci(dev)) 3780 3780 + dev = dev->parent; 3781 3781 + if (!dev) { 3782 3782 + pr_err("unable to find parent device\n"); 3783 3783 + return -ENODEV; 3784 3784 + } 3785 3785 + 3786 3786 + exp_addr = pci_resource_start(to_pci_dev(dev), 0) + 0x100; 3787 3787 + unittest(res->start == exp_addr, "Incorrect translated address %llx, expected %llx\n", 3788 3788 + (u64)res->start, exp_addr); 3789 3789 + 3790 3790 + of_unittest_pci_child_num++; 3791 3791 + 3792 3792 + return 0; 3793 3793 + } 3794 3794 + 3795 3795 + static const struct of_device_id unittest_pci_of_match[] = { 3796 3796 + { .compatible = "unittest-pci" }, 3797 3797 + { } 3798 3798 + }; 3799 3799 + 3800 3800 + static struct platform_driver unittest_pci_driver = { 3801 3801 + .probe = unittest_pci_probe, 3802 3802 + .driver = { 3803 3803 + .name = "unittest-pci", 3804 3804 + .of_match_table = unittest_pci_of_match, 3805 3805 + }, 3806 3806 + }; 3807 3807 + 3808 3808 + static int of_unittest_pci_node_verify(struct pci_dev *pdev, bool add) 3809 3809 + { 3810 3810 + struct device_node *pnp, *np = NULL; 3811 3811 + struct device *child_dev; 3812 3812 + char *path = NULL; 3813 3813 + const __be32 *reg; 3814 3814 + int rc = 0; 3815 3815 + 3816 3816 + pnp = pdev->dev.of_node; 3817 3817 + unittest(pnp, "Failed creating PCI dt node\n"); 3818 3818 + if (!pnp) 3819 3819 + return -ENODEV; 3820 3820 + 3821 3821 + if (add) { 3822 3822 + path = kasprintf(GFP_KERNEL, "%pOF/pci-ep-bus@0/unittest-pci@100", pnp); 3823 3823 + np = of_find_node_by_path(path); 3824 3824 + unittest(np, "Failed to get unittest-pci node under PCI node\n"); 3825 3825 + if (!np) { 3826 3826 + rc = -ENODEV; 3827 3827 + goto failed; 3828 3828 + } 3829 3829 + 3830 3830 + reg = of_get_property(np, "reg", NULL); 3831 3831 + unittest(reg, "Failed to get reg property\n"); 3832 3832 + if (!reg) 3833 3833 + rc = -ENODEV; 3834 3834 + } else { 3835 3835 + path = kasprintf(GFP_KERNEL, "%pOF/pci-ep-bus@0", pnp); 3836 3836 + np = of_find_node_by_path(path); 3837 3837 + unittest(!np, "Child device tree node is not removed\n"); 3838 3838 + child_dev = device_find_any_child(&pdev->dev); 3839 3839 + unittest(!child_dev, "Child device is not removed\n"); 3840 3840 + } 3841 3841 + 3842 3842 + failed: 3843 3843 + kfree(path); 3844 3844 + if (np) 3845 3845 + of_node_put(np); 3846 3846 + 3847 3847 + return rc; 3848 3848 + } 3849 3849 + 3850 3850 + static void __init of_unittest_pci_node(void) 3851 3851 + { 3852 3852 + struct pci_dev *pdev = NULL; 3853 3853 + int rc; 3854 3854 + 3855 3855 + if (!IS_ENABLED(CONFIG_PCI_DYNAMIC_OF_NODES)) 3856 3856 + return; 3857 3857 + 3858 3858 + rc = pci_register_driver(&testdrv_driver); 3859 3859 + unittest(!rc, "Failed to register pci test driver; rc = %d\n", rc); 3860 3860 + if (rc) 3861 3861 + return; 3862 3862 + 3863 3863 + rc = platform_driver_register(&unittest_pci_driver); 3864 3864 + if (unittest(!rc, "Failed to register unittest pci driver\n")) { 3865 3865 + pci_unregister_driver(&testdrv_driver); 3866 3866 + return; 3867 3867 + } 3868 3868 + 3869 3869 + while ((pdev = pci_get_device(PCI_VENDOR_ID_REDHAT, 0x5, pdev)) != NULL) { 3870 3870 + of_unittest_pci_node_verify(pdev, true); 3871 3871 + of_unittest_pci_dev_num++; 3872 3872 + } 3873 3873 + if (pdev) 3874 3874 + pci_dev_put(pdev); 3875 3875 + 3876 3876 + unittest(of_unittest_pci_dev_num, 3877 3877 + "No test PCI device been found. Please run QEMU with '-device pci-testdev'\n"); 3878 3878 + unittest(of_unittest_pci_dev_num == of_unittest_pci_child_num, 3879 3879 + "Child device number %d is not expected %d", of_unittest_pci_child_num, 3880 3880 + of_unittest_pci_dev_num); 3881 3881 + 3882 3882 + platform_driver_unregister(&unittest_pci_driver); 3883 3883 + pci_unregister_driver(&testdrv_driver); 3884 3884 + 3885 3885 + while ((pdev = pci_get_device(PCI_VENDOR_ID_REDHAT, 0x5, pdev)) != NULL) 3886 3886 + of_unittest_pci_node_verify(pdev, false); 3887 3887 + if (pdev) 3888 3888 + pci_dev_put(pdev); 3889 3889 + } 3802 3890 #else 3803 3891 3804 3892 static inline __init void of_unittest_overlay_high_level(void) {} 3893 3893 + static inline __init void of_unittest_pci_node(void) { } 3805 3894 3806 3895 #endif 3807 3896 ··· 4038 3761 of_unittest_platform_populate(); 4039 3762 of_unittest_overlay(); 4040 3763 of_unittest_lifecycle(); 3764 3764 + of_unittest_pci_node(); 4041 3765 4042 3766 /* Double check linkage after removing testcase data */ 4043 3767 of_unittest_check_tree_linkage();

+12

drivers/pci/Kconfig

reviewed

··· 194 194 The PCI device frontend driver allows the kernel to import arbitrary 195 195 PCI devices from a PCI backend to support PCI driver domains. 196 196 197 197 + config PCI_DYNAMIC_OF_NODES 198 198 + bool "Create Device tree nodes for PCI devices" 199 199 + depends on OF 200 200 + select OF_DYNAMIC 201 201 + help 202 202 + This option enables support for generating device tree nodes for some 203 203 + PCI devices. Thus, the driver of this kind can load and overlay 204 204 + flattened device tree for its downstream devices. 205 205 + 206 206 + Once this option is selected, the device tree nodes will be generated 207 207 + for all PCI bridges. 208 208 + 197 209 choice 198 210 prompt "PCI Express hierarchy optimization setting" 199 211 default PCIE_BUS_DEFAULT

+1

drivers/pci/Makefile

reviewed

··· 32 32 obj-$(CONFIG_XEN_PCIDEV_FRONTEND) += xen-pcifront.o 33 33 obj-$(CONFIG_VGA_ARB) += vgaarb.o 34 34 obj-$(CONFIG_PCI_DOE) += doe.o 35 35 + obj-$(CONFIG_PCI_DYNAMIC_OF_NODES) += of_property.o 35 36 36 37 # Endpoint library must be initialized before its users 37 38 obj-$(CONFIG_PCI_ENDPOINT) += endpoint/

+2

drivers/pci/bus.c

reviewed

··· 342 342 */ 343 343 pcibios_bus_add_device(dev); 344 344 pci_fixup_device(pci_fixup_final, dev); 345 345 + if (pci_is_bridge(dev)) 346 346 + of_pci_make_dev_node(dev); 345 347 pci_create_sysfs_dev_files(dev); 346 348 pci_proc_attach_device(dev); 347 349 pci_bridge_d3_update(dev);

+79

drivers/pci/of.c

reviewed

··· 606 606 return pci_parse_request_of_pci_ranges(dev, bridge); 607 607 } 608 608 609 609 + #ifdef CONFIG_PCI_DYNAMIC_OF_NODES 610 610 + 611 611 + void of_pci_remove_node(struct pci_dev *pdev) 612 612 + { 613 613 + struct device_node *np; 614 614 + 615 615 + np = pci_device_to_OF_node(pdev); 616 616 + if (!np || !of_node_check_flag(np, OF_DYNAMIC)) 617 617 + return; 618 618 + pdev->dev.of_node = NULL; 619 619 + 620 620 + of_changeset_revert(np->data); 621 621 + of_changeset_destroy(np->data); 622 622 + of_node_put(np); 623 623 + } 624 624 + 625 625 + void of_pci_make_dev_node(struct pci_dev *pdev) 626 626 + { 627 627 + struct device_node *ppnode, *np = NULL; 628 628 + const char *pci_type; 629 629 + struct of_changeset *cset; 630 630 + const char *name; 631 631 + int ret; 632 632 + 633 633 + /* 634 634 + * If there is already a device tree node linked to this device, 635 635 + * return immediately. 636 636 + */ 637 637 + if (pci_device_to_OF_node(pdev)) 638 638 + return; 639 639 + 640 640 + /* Check if there is device tree node for parent device */ 641 641 + if (!pdev->bus->self) 642 642 + ppnode = pdev->bus->dev.of_node; 643 643 + else 644 644 + ppnode = pdev->bus->self->dev.of_node; 645 645 + if (!ppnode) 646 646 + return; 647 647 + 648 648 + if (pci_is_bridge(pdev)) 649 649 + pci_type = "pci"; 650 650 + else 651 651 + pci_type = "dev"; 652 652 + 653 653 + name = kasprintf(GFP_KERNEL, "%s@%x,%x", pci_type, 654 654 + PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); 655 655 + if (!name) 656 656 + return; 657 657 + 658 658 + cset = kmalloc(sizeof(*cset), GFP_KERNEL); 659 659 + if (!cset) 660 660 + goto failed; 661 661 + of_changeset_init(cset); 662 662 + 663 663 + np = of_changeset_create_node(cset, ppnode, name); 664 664 + if (!np) 665 665 + goto failed; 666 666 + np->data = cset; 667 667 + 668 668 + ret = of_pci_add_properties(pdev, cset, np); 669 669 + if (ret) 670 670 + goto failed; 671 671 + 672 672 + ret = of_changeset_apply(cset); 673 673 + if (ret) 674 674 + goto failed; 675 675 + 676 676 + pdev->dev.of_node = np; 677 677 + kfree(name); 678 678 + 679 679 + return; 680 680 + 681 681 + failed: 682 682 + if (np) 683 683 + of_node_put(np); 684 684 + kfree(name); 685 685 + } 686 686 + #endif 687 687 + 609 688 #endif /* CONFIG_PCI */ 610 689 611 690 /**

+355

drivers/pci/of_property.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0+ 2 2 + /* 3 3 + * Copyright (C) 2022-2023, Advanced Micro Devices, Inc. 4 4 + */ 5 5 + 6 6 + #include <linux/pci.h> 7 7 + #include <linux/of.h> 8 8 + #include <linux/of_irq.h> 9 9 + #include <linux/bitfield.h> 10 10 + #include <linux/bits.h> 11 11 + #include "pci.h" 12 12 + 13 13 + #define OF_PCI_ADDRESS_CELLS 3 14 14 + #define OF_PCI_SIZE_CELLS 2 15 15 + #define OF_PCI_MAX_INT_PIN 4 16 16 + 17 17 + struct of_pci_addr_pair { 18 18 + u32 phys_addr[OF_PCI_ADDRESS_CELLS]; 19 19 + u32 size[OF_PCI_SIZE_CELLS]; 20 20 + }; 21 21 + 22 22 + /* 23 23 + * Each entry in the ranges table is a tuple containing the child address, 24 24 + * the parent address, and the size of the region in the child address space. 25 25 + * Thus, for PCI, in each entry parent address is an address on the primary 26 26 + * side and the child address is the corresponding address on the secondary 27 27 + * side. 28 28 + */ 29 29 + struct of_pci_range { 30 30 + u32 child_addr[OF_PCI_ADDRESS_CELLS]; 31 31 + u32 parent_addr[OF_PCI_ADDRESS_CELLS]; 32 32 + u32 size[OF_PCI_SIZE_CELLS]; 33 33 + }; 34 34 + 35 35 + #define OF_PCI_ADDR_SPACE_IO 0x1 36 36 + #define OF_PCI_ADDR_SPACE_MEM32 0x2 37 37 + #define OF_PCI_ADDR_SPACE_MEM64 0x3 38 38 + 39 39 + #define OF_PCI_ADDR_FIELD_NONRELOC BIT(31) 40 40 + #define OF_PCI_ADDR_FIELD_SS GENMASK(25, 24) 41 41 + #define OF_PCI_ADDR_FIELD_PREFETCH BIT(30) 42 42 + #define OF_PCI_ADDR_FIELD_BUS GENMASK(23, 16) 43 43 + #define OF_PCI_ADDR_FIELD_DEV GENMASK(15, 11) 44 44 + #define OF_PCI_ADDR_FIELD_FUNC GENMASK(10, 8) 45 45 + #define OF_PCI_ADDR_FIELD_REG GENMASK(7, 0) 46 46 + 47 47 + enum of_pci_prop_compatible { 48 48 + PROP_COMPAT_PCI_VVVV_DDDD, 49 49 + PROP_COMPAT_PCICLASS_CCSSPP, 50 50 + PROP_COMPAT_PCICLASS_CCSS, 51 51 + PROP_COMPAT_NUM, 52 52 + }; 53 53 + 54 54 + static void of_pci_set_address(struct pci_dev *pdev, u32 *prop, u64 addr, 55 55 + u32 reg_num, u32 flags, bool reloc) 56 56 + { 57 57 + prop[0] = FIELD_PREP(OF_PCI_ADDR_FIELD_BUS, pdev->bus->number) | 58 58 + FIELD_PREP(OF_PCI_ADDR_FIELD_DEV, PCI_SLOT(pdev->devfn)) | 59 59 + FIELD_PREP(OF_PCI_ADDR_FIELD_FUNC, PCI_FUNC(pdev->devfn)); 60 60 + prop[0] |= flags | reg_num; 61 61 + if (!reloc) { 62 62 + prop[0] |= OF_PCI_ADDR_FIELD_NONRELOC; 63 63 + prop[1] = upper_32_bits(addr); 64 64 + prop[2] = lower_32_bits(addr); 65 65 + } 66 66 + } 67 67 + 68 68 + static int of_pci_get_addr_flags(struct resource *res, u32 *flags) 69 69 + { 70 70 + u32 ss; 71 71 + 72 72 + if (res->flags & IORESOURCE_IO) 73 73 + ss = OF_PCI_ADDR_SPACE_IO; 74 74 + else if (res->flags & IORESOURCE_MEM_64) 75 75 + ss = OF_PCI_ADDR_SPACE_MEM64; 76 76 + else if (res->flags & IORESOURCE_MEM) 77 77 + ss = OF_PCI_ADDR_SPACE_MEM32; 78 78 + else 79 79 + return -EINVAL; 80 80 + 81 81 + *flags = 0; 82 82 + if (res->flags & IORESOURCE_PREFETCH) 83 83 + *flags |= OF_PCI_ADDR_FIELD_PREFETCH; 84 84 + 85 85 + *flags |= FIELD_PREP(OF_PCI_ADDR_FIELD_SS, ss); 86 86 + 87 87 + return 0; 88 88 + } 89 89 + 90 90 + static int of_pci_prop_bus_range(struct pci_dev *pdev, 91 91 + struct of_changeset *ocs, 92 92 + struct device_node *np) 93 93 + { 94 94 + u32 bus_range[] = { pdev->subordinate->busn_res.start, 95 95 + pdev->subordinate->busn_res.end }; 96 96 + 97 97 + return of_changeset_add_prop_u32_array(ocs, np, "bus-range", bus_range, 98 98 + ARRAY_SIZE(bus_range)); 99 99 + } 100 100 + 101 101 + static int of_pci_prop_ranges(struct pci_dev *pdev, struct of_changeset *ocs, 102 102 + struct device_node *np) 103 103 + { 104 104 + struct of_pci_range *rp; 105 105 + struct resource *res; 106 106 + int i, j, ret; 107 107 + u32 flags, num; 108 108 + u64 val64; 109 109 + 110 110 + if (pci_is_bridge(pdev)) { 111 111 + num = PCI_BRIDGE_RESOURCE_NUM; 112 112 + res = &pdev->resource[PCI_BRIDGE_RESOURCES]; 113 113 + } else { 114 114 + num = PCI_STD_NUM_BARS; 115 115 + res = &pdev->resource[PCI_STD_RESOURCES]; 116 116 + } 117 117 + 118 118 + rp = kcalloc(num, sizeof(*rp), GFP_KERNEL); 119 119 + if (!rp) 120 120 + return -ENOMEM; 121 121 + 122 122 + for (i = 0, j = 0; j < num; j++) { 123 123 + if (!resource_size(&res[j])) 124 124 + continue; 125 125 + 126 126 + if (of_pci_get_addr_flags(&res[j], &flags)) 127 127 + continue; 128 128 + 129 129 + val64 = res[j].start; 130 130 + of_pci_set_address(pdev, rp[i].parent_addr, val64, 0, flags, 131 131 + false); 132 132 + if (pci_is_bridge(pdev)) { 133 133 + memcpy(rp[i].child_addr, rp[i].parent_addr, 134 134 + sizeof(rp[i].child_addr)); 135 135 + } else { 136 136 + /* 137 137 + * For endpoint device, the lower 64-bits of child 138 138 + * address is always zero. 139 139 + */ 140 140 + rp[i].child_addr[0] = j; 141 141 + } 142 142 + 143 143 + val64 = resource_size(&res[j]); 144 144 + rp[i].size[0] = upper_32_bits(val64); 145 145 + rp[i].size[1] = lower_32_bits(val64); 146 146 + 147 147 + i++; 148 148 + } 149 149 + 150 150 + ret = of_changeset_add_prop_u32_array(ocs, np, "ranges", (u32 *)rp, 151 151 + i * sizeof(*rp) / sizeof(u32)); 152 152 + kfree(rp); 153 153 + 154 154 + return ret; 155 155 + } 156 156 + 157 157 + static int of_pci_prop_reg(struct pci_dev *pdev, struct of_changeset *ocs, 158 158 + struct device_node *np) 159 159 + { 160 160 + struct of_pci_addr_pair reg = { 0 }; 161 161 + 162 162 + /* configuration space */ 163 163 + of_pci_set_address(pdev, reg.phys_addr, 0, 0, 0, true); 164 164 + 165 165 + return of_changeset_add_prop_u32_array(ocs, np, "reg", (u32 *)&reg, 166 166 + sizeof(reg) / sizeof(u32)); 167 167 + } 168 168 + 169 169 + static int of_pci_prop_interrupts(struct pci_dev *pdev, 170 170 + struct of_changeset *ocs, 171 171 + struct device_node *np) 172 172 + { 173 173 + int ret; 174 174 + u8 pin; 175 175 + 176 176 + ret = pci_read_config_byte(pdev, PCI_INTERRUPT_PIN, &pin); 177 177 + if (ret != 0) 178 178 + return ret; 179 179 + 180 180 + if (!pin) 181 181 + return 0; 182 182 + 183 183 + return of_changeset_add_prop_u32(ocs, np, "interrupts", (u32)pin); 184 184 + } 185 185 + 186 186 + static int of_pci_prop_intr_map(struct pci_dev *pdev, struct of_changeset *ocs, 187 187 + struct device_node *np) 188 188 + { 189 189 + struct of_phandle_args out_irq[OF_PCI_MAX_INT_PIN]; 190 190 + u32 i, addr_sz[OF_PCI_MAX_INT_PIN], map_sz = 0; 191 191 + __be32 laddr[OF_PCI_ADDRESS_CELLS] = { 0 }; 192 192 + u32 int_map_mask[] = { 0xffff00, 0, 0, 7 }; 193 193 + struct device_node *pnode; 194 194 + struct pci_dev *child; 195 195 + u32 *int_map, *mapp; 196 196 + int ret; 197 197 + u8 pin; 198 198 + 199 199 + pnode = pci_device_to_OF_node(pdev->bus->self); 200 200 + if (!pnode) 201 201 + pnode = pci_bus_to_OF_node(pdev->bus); 202 202 + 203 203 + if (!pnode) { 204 204 + pci_err(pdev, "failed to get parent device node"); 205 205 + return -EINVAL; 206 206 + } 207 207 + 208 208 + laddr[0] = cpu_to_be32((pdev->bus->number << 16) | (pdev->devfn << 8)); 209 209 + for (pin = 1; pin <= OF_PCI_MAX_INT_PIN; pin++) { 210 210 + i = pin - 1; 211 211 + out_irq[i].np = pnode; 212 212 + out_irq[i].args_count = 1; 213 213 + out_irq[i].args[0] = pin; 214 214 + ret = of_irq_parse_raw(laddr, &out_irq[i]); 215 215 + if (ret) { 216 216 + pci_err(pdev, "parse irq %d failed, ret %d", pin, ret); 217 217 + continue; 218 218 + } 219 219 + ret = of_property_read_u32(out_irq[i].np, "#address-cells", 220 220 + &addr_sz[i]); 221 221 + if (ret) 222 222 + addr_sz[i] = 0; 223 223 + } 224 224 + 225 225 + list_for_each_entry(child, &pdev->subordinate->devices, bus_list) { 226 226 + for (pin = 1; pin <= OF_PCI_MAX_INT_PIN; pin++) { 227 227 + i = pci_swizzle_interrupt_pin(child, pin) - 1; 228 228 + map_sz += 5 + addr_sz[i] + out_irq[i].args_count; 229 229 + } 230 230 + } 231 231 + 232 232 + int_map = kcalloc(map_sz, sizeof(u32), GFP_KERNEL); 233 233 + mapp = int_map; 234 234 + 235 235 + list_for_each_entry(child, &pdev->subordinate->devices, bus_list) { 236 236 + for (pin = 1; pin <= OF_PCI_MAX_INT_PIN; pin++) { 237 237 + *mapp = (child->bus->number << 16) | 238 238 + (child->devfn << 8); 239 239 + mapp += OF_PCI_ADDRESS_CELLS; 240 240 + *mapp = pin; 241 241 + mapp++; 242 242 + i = pci_swizzle_interrupt_pin(child, pin) - 1; 243 243 + *mapp = out_irq[i].np->phandle; 244 244 + mapp++; 245 245 + if (addr_sz[i]) { 246 246 + ret = of_property_read_u32_array(out_irq[i].np, 247 247 + "reg", mapp, 248 248 + addr_sz[i]); 249 249 + if (ret) 250 250 + goto failed; 251 251 + } 252 252 + mapp += addr_sz[i]; 253 253 + memcpy(mapp, out_irq[i].args, 254 254 + out_irq[i].args_count * sizeof(u32)); 255 255 + mapp += out_irq[i].args_count; 256 256 + } 257 257 + } 258 258 + 259 259 + ret = of_changeset_add_prop_u32_array(ocs, np, "interrupt-map", int_map, 260 260 + map_sz); 261 261 + if (ret) 262 262 + goto failed; 263 263 + 264 264 + ret = of_changeset_add_prop_u32(ocs, np, "#interrupt-cells", 1); 265 265 + if (ret) 266 266 + goto failed; 267 267 + 268 268 + ret = of_changeset_add_prop_u32_array(ocs, np, "interrupt-map-mask", 269 269 + int_map_mask, 270 270 + ARRAY_SIZE(int_map_mask)); 271 271 + if (ret) 272 272 + goto failed; 273 273 + 274 274 + kfree(int_map); 275 275 + return 0; 276 276 + 277 277 + failed: 278 278 + kfree(int_map); 279 279 + return ret; 280 280 + } 281 281 + 282 282 + static int of_pci_prop_compatible(struct pci_dev *pdev, 283 283 + struct of_changeset *ocs, 284 284 + struct device_node *np) 285 285 + { 286 286 + const char *compat_strs[PROP_COMPAT_NUM] = { 0 }; 287 287 + int i, ret; 288 288 + 289 289 + compat_strs[PROP_COMPAT_PCI_VVVV_DDDD] = 290 290 + kasprintf(GFP_KERNEL, "pci%x,%x", pdev->vendor, pdev->device); 291 291 + compat_strs[PROP_COMPAT_PCICLASS_CCSSPP] = 292 292 + kasprintf(GFP_KERNEL, "pciclass,%06x", pdev->class); 293 293 + compat_strs[PROP_COMPAT_PCICLASS_CCSS] = 294 294 + kasprintf(GFP_KERNEL, "pciclass,%04x", pdev->class >> 8); 295 295 + 296 296 + ret = of_changeset_add_prop_string_array(ocs, np, "compatible", 297 297 + compat_strs, PROP_COMPAT_NUM); 298 298 + for (i = 0; i < PROP_COMPAT_NUM; i++) 299 299 + kfree(compat_strs[i]); 300 300 + 301 301 + return ret; 302 302 + } 303 303 + 304 304 + int of_pci_add_properties(struct pci_dev *pdev, struct of_changeset *ocs, 305 305 + struct device_node *np) 306 306 + { 307 307 + int ret; 308 308 + 309 309 + /* 310 310 + * The added properties will be released when the 311 311 + * changeset is destroyed. 312 312 + */ 313 313 + if (pci_is_bridge(pdev)) { 314 314 + ret = of_changeset_add_prop_string(ocs, np, "device_type", 315 315 + "pci"); 316 316 + if (ret) 317 317 + return ret; 318 318 + 319 319 + ret = of_pci_prop_bus_range(pdev, ocs, np); 320 320 + if (ret) 321 321 + return ret; 322 322 + 323 323 + ret = of_pci_prop_intr_map(pdev, ocs, np); 324 324 + if (ret) 325 325 + return ret; 326 326 + } 327 327 + 328 328 + ret = of_pci_prop_ranges(pdev, ocs, np); 329 329 + if (ret) 330 330 + return ret; 331 331 + 332 332 + ret = of_changeset_add_prop_u32(ocs, np, "#address-cells", 333 333 + OF_PCI_ADDRESS_CELLS); 334 334 + if (ret) 335 335 + return ret; 336 336 + 337 337 + ret = of_changeset_add_prop_u32(ocs, np, "#size-cells", 338 338 + OF_PCI_SIZE_CELLS); 339 339 + if (ret) 340 340 + return ret; 341 341 + 342 342 + ret = of_pci_prop_reg(pdev, ocs, np); 343 343 + if (ret) 344 344 + return ret; 345 345 + 346 346 + ret = of_pci_prop_compatible(pdev, ocs, np); 347 347 + if (ret) 348 348 + return ret; 349 349 + 350 350 + ret = of_pci_prop_interrupts(pdev, ocs, np); 351 351 + if (ret) 352 352 + return ret; 353 353 + 354 354 + return 0; 355 355 + }

+12

drivers/pci/pci.h

reviewed

··· 679 679 680 680 #endif /* CONFIG_OF */ 681 681 682 682 + struct of_changeset; 683 683 + 684 684 + #ifdef CONFIG_PCI_DYNAMIC_OF_NODES 685 685 + void of_pci_make_dev_node(struct pci_dev *pdev); 686 686 + void of_pci_remove_node(struct pci_dev *pdev); 687 687 + int of_pci_add_properties(struct pci_dev *pdev, struct of_changeset *ocs, 688 688 + struct device_node *np); 689 689 + #else 690 690 + static inline void of_pci_make_dev_node(struct pci_dev *pdev) { } 691 691 + static inline void of_pci_remove_node(struct pci_dev *pdev) { } 692 692 + #endif 693 693 + 682 694 #ifdef CONFIG_PCIEAER 683 695 void pci_no_aer(void); 684 696 void pci_aer_init(struct pci_dev *dev);

+12

drivers/pci/quirks.c

reviewed

··· 6138 6138 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2f, dpc_log_size); 6139 6139 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a31, dpc_log_size); 6140 6140 #endif 6141 6141 + 6142 6142 + /* 6143 6143 + * For a PCI device with multiple downstream devices, its driver may use 6144 6144 + * a flattened device tree to describe the downstream devices. 6145 6145 + * To overlay the flattened device tree, the PCI device and all its ancestor 6146 6146 + * devices need to have device tree nodes on system base device tree. Thus, 6147 6147 + * before driver probing, it might need to add a device tree node as the final 6148 6148 + * fixup. 6149 6149 + */ 6150 6150 + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5020, of_pci_make_dev_node); 6151 6151 + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5021, of_pci_make_dev_node); 6152 6152 + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REDHAT, 0x0005, of_pci_make_dev_node);

+1

drivers/pci/remove.c

reviewed

··· 22 22 device_release_driver(&dev->dev); 23 23 pci_proc_detach_device(dev); 24 24 pci_remove_sysfs_dev_files(dev); 25 25 + of_pci_remove_node(dev); 25 26 26 27 pci_dev_assign_added(dev, false); 27 28 }

+1 -1

include/dt-bindings/ata/ahci.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ 2 2 /* 3 3 * This header provides constants for most AHCI bindings. 4 4 */

+1 -1

include/dt-bindings/clock/hi3559av100-clock.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0-or-later or BSD-2-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause */ 2 2 /* 3 3 * Copyright (c) 2019-2020, Huawei Tech. Co., Ltd. 4 4 *

+1 -1

include/dt-bindings/clock/r8a779f0-cpg-mssr.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: (GPL-2.0 or MIT) */ 1 1 + /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 2 /* 3 3 * Copyright (C) 2021 Renesas Electronics Corp. 4 4 */

+1 -1

include/dt-bindings/clock/rockchip,rk3588-cru.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: (GPL-2.0 or MIT) */ 1 1 + /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 2 /* 3 3 * Copyright (c) 2021 Rockchip Electronics Co. Ltd. 4 4 * Copyright (c) 2022 Collabora Ltd.

+1 -1

include/dt-bindings/clock/stm32mp1-clks.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved 4 4 * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.

+1 -1

include/dt-bindings/clock/sun20i-d1-ccu.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ 1 1 + /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 2 /* 3 3 * Copyright (C) 2020 huangzhenwei@allwinnertech.com 4 4 * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>

+1 -1

include/dt-bindings/clock/sun20i-d1-r-ccu.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ 1 1 + /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 2 /* 3 3 * Copyright (C) 2021 Samuel Holland <samuel@sholland.org> 4 4 */

+1 -1

include/dt-bindings/clock/sun50i-a100-ccu.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ 1 1 + /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 2 /* 3 3 * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com> 4 4 */

+1 -1

include/dt-bindings/clock/sun50i-h6-ccu.h

reviewed

··· 1 1 - // SPDX-License-Identifier: (GPL-2.0+ or MIT) 1 1 + /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 2 /* 3 3 * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> 4 4 */

+1 -1

include/dt-bindings/clock/sun50i-h616-ccu.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ 1 1 + /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 2 /* 3 3 * Copyright (C) 2020 Arm Ltd. 4 4 */

+1 -1

include/dt-bindings/clock/sun6i-rtc.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ 1 1 + /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 2 3 3 #ifndef _DT_BINDINGS_CLK_SUN6I_RTC_H_ 4 4 #define _DT_BINDINGS_CLK_SUN6I_RTC_H_

+1 -1

include/dt-bindings/display/sdtv-standards.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0-only or X11 */ 1 1 + /* SPDX-License-Identifier: GPL-2.0-only OR X11 */ 2 2 /* 3 3 * Copyright 2019 Pengutronix, Marco Felsch <kernel@pengutronix.de> 4 4 */

+1 -1

include/dt-bindings/gpio/meson-g12a-gpio.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ 1 1 + /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 2 /* 3 3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 4 4 * Author: Xingyu Chen <xingyu.chen@amlogic.com>

+1 -1

include/dt-bindings/power/meson-a1-power.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ 1 1 + /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 2 /* 3 3 * Copyright (c) 2019 Amlogic, Inc. 4 4 * Author: Jianxin Pan <jianxin.pan@amlogic.com>

+1 -1

include/dt-bindings/power/meson-axg-power.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ 1 1 + /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 2 /* 3 3 * Copyright (c) 2020 BayLibre, SAS 4 4 * Author: Neil Armstrong <narmstrong@baylibre.com>

+1 -1

include/dt-bindings/power/meson-g12a-power.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ 1 1 + /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 2 /* 3 3 * Copyright (c) 2019 BayLibre, SAS 4 4 * Author: Neil Armstrong <narmstrong@baylibre.com>

+1 -1

include/dt-bindings/power/meson-gxbb-power.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ 1 1 + /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 2 /* 3 3 * Copyright (c) 2019 BayLibre, SAS 4 4 * Author: Neil Armstrong <narmstrong@baylibre.com>

+1 -1

include/dt-bindings/power/meson-s4-power.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ 1 1 + /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 2 /* 3 3 * Copyright (c) 2021 Amlogic, Inc. 4 4 * Author: Shunzhou Jiang <shunzhou.jiang@amlogic.com>

+1 -1

include/dt-bindings/power/meson-sm1-power.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ 1 1 + /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 2 /* 3 3 * Copyright (c) 2019 BayLibre, SAS 4 4 * Author: Neil Armstrong <narmstrong@baylibre.com>

+1 -1

include/dt-bindings/power/meson8-power.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ 1 1 + /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 2 /* 3 3 * Copyright (c) 2019 Martin Blumenstingl <martin.blumenstingl@googlemail.com> 4 4 */

+1 -1

include/dt-bindings/power/r8a779f0-sysc.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: (GPL-2.0 or MIT) */ 1 1 + /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 2 /* 3 3 * Copyright (C) 2021 Renesas Electronics Corp. 4 4 */

+1 -1

include/dt-bindings/power/rk3588-power.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: (GPL-2.0 or MIT) */ 1 1 + /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 2 #ifndef __DT_BINDINGS_POWER_RK3588_POWER_H__ 3 3 #define __DT_BINDINGS_POWER_RK3588_POWER_H__ 4 4

+1 -1

include/dt-bindings/power/summit,smb347-charger.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: (GPL-2.0-or-later or MIT) */ 1 1 + /* SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) */ 2 2 /* 3 3 * Author: David Heidelberg <david@ixit.cz> 4 4 */

+1 -1

include/dt-bindings/reset/rockchip,rk3588-cru.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: (GPL-2.0 or MIT) */ 1 1 + /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 2 /* 3 3 * Copyright (c) 2021 Rockchip Electronics Co. Ltd. 4 4 * Copyright (c) 2022 Collabora Ltd.

+1 -1

include/dt-bindings/reset/stm32mp1-resets.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 2 /* 3 3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved 4 4 * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.

+1 -1

include/dt-bindings/reset/sun20i-d1-ccu.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ 1 1 + /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 2 /* 3 3 * Copyright (c) 2020 huangzhenwei@allwinnertech.com 4 4 * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>

+1 -1

include/dt-bindings/reset/sun20i-d1-r-ccu.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ 1 1 + /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 2 /* 3 3 * Copyright (C) 2021 Samuel Holland <samuel@sholland.org> 4 4 */

+1 -1

include/dt-bindings/reset/sun50i-a100-ccu.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ 1 1 + /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 2 /* 3 3 * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com> 4 4 */

+1 -1

include/dt-bindings/reset/sun50i-a100-r-ccu.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ 1 1 + /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 2 /* 3 3 * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com> 4 4 */

+1 -1

include/dt-bindings/reset/sun50i-h6-ccu.h

reviewed

··· 1 1 - // SPDX-License-Identifier: (GPL-2.0+ or MIT) 1 1 + /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 2 /* 3 3 * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> 4 4 */

+1 -1

include/dt-bindings/reset/sun50i-h6-r-ccu.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ 1 1 + /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 2 /* 3 3 * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> 4 4 */

+1 -1

include/dt-bindings/reset/sun50i-h616-ccu.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ 1 1 + /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 2 /* 3 3 * Copyright (C) 2020 Arm Ltd. 4 4 */

+27 -5

include/linux/of.h

reviewed

··· 96 96 struct property *old_prop; 97 97 }; 98 98 99 99 + extern const struct kobj_type of_node_ktype; 100 100 + extern const struct fwnode_operations of_fwnode_ops; 101 101 + 99 102 /** 100 103 * of_node_init - initialize a devicetree node 101 104 * @node: Pointer to device node that has been created by kzalloc() 102 102 - * @phandle_name: Name of property holding a phandle value 103 105 * 104 106 * On return the device_node refcount is set to one. Use of_node_put() 105 107 * on @node when done to free the memory allocated for it. If the node ··· 109 107 * whether to free the memory will be done by node->release(), which is 110 108 * of_node_release(). 111 109 */ 112 112 - /* initialize a node */ 113 113 - extern const struct kobj_type of_node_ktype; 114 114 - extern const struct fwnode_operations of_fwnode_ops; 115 110 static inline void of_node_init(struct device_node *node) 116 111 { 117 112 #if defined(CONFIG_OF_KOBJ) ··· 1579 1580 { 1580 1581 return of_changeset_action(ocs, OF_RECONFIG_UPDATE_PROPERTY, np, prop); 1581 1582 } 1583 1583 + 1584 1584 + struct device_node *of_changeset_create_node(struct of_changeset *ocs, 1585 1585 + struct device_node *parent, 1586 1586 + const char *full_name); 1587 1587 + int of_changeset_add_prop_string(struct of_changeset *ocs, 1588 1588 + struct device_node *np, 1589 1589 + const char *prop_name, const char *str); 1590 1590 + int of_changeset_add_prop_string_array(struct of_changeset *ocs, 1591 1591 + struct device_node *np, 1592 1592 + const char *prop_name, 1593 1593 + const char **str_array, size_t sz); 1594 1594 + int of_changeset_add_prop_u32_array(struct of_changeset *ocs, 1595 1595 + struct device_node *np, 1596 1596 + const char *prop_name, 1597 1597 + const u32 *array, size_t sz); 1598 1598 + static inline int of_changeset_add_prop_u32(struct of_changeset *ocs, 1599 1599 + struct device_node *np, 1600 1600 + const char *prop_name, 1601 1601 + const u32 val) 1602 1602 + { 1603 1603 + return of_changeset_add_prop_u32_array(ocs, np, prop_name, &val, 1); 1604 1604 + } 1605 1605 + 1582 1606 #else /* CONFIG_OF_DYNAMIC */ 1583 1607 static inline int of_reconfig_notifier_register(struct notifier_block *nb) 1584 1608 { ··· 1667 1645 #ifdef CONFIG_OF_OVERLAY 1668 1646 1669 1647 int of_overlay_fdt_apply(const void *overlay_fdt, u32 overlay_fdt_size, 1670 1670 - int *ovcs_id); 1648 1648 + int *ovcs_id, struct device_node *target_base); 1671 1649 int of_overlay_remove(int *ovcs_id); 1672 1650 int of_overlay_remove_all(void); 1673 1651

-6

include/linux/of_platform.h

reviewed

··· 127 127 static inline void devm_of_platform_depopulate(struct device *dev) { } 128 128 #endif 129 129 130 130 - #if defined(CONFIG_OF_DYNAMIC) && defined(CONFIG_OF_ADDRESS) 131 131 - extern void of_platform_register_reconfig_notifier(void); 132 132 - #else 133 133 - static inline void of_platform_register_reconfig_notifier(void) { } 134 134 - #endif 135 135 - 136 130 #endif /* _LINUX_OF_PLATFORM_H */

+2 -2

scripts/dtc/dt-extract-compatibles

reviewed

··· 25 25 def parse_of_device_id(data): 26 26 """ Find all compatible strings in of_device_id structs """ 27 27 compat_list = [] 28 28 - for m in re.finditer(r'of_device_id\s+[a-zA-Z0-9_]+\[\]\s*=\s*({.*?);', data): 29 29 - compat_list += re.findall(r'\.compatible\s+=\s+"([a-zA-Z0-9_\-,]+)"', m[1]) 28 28 + for m in re.finditer(r'of_device_id(\s+\S+)?\s+\S+\[\](\s+\S+)?\s*=\s*({.*?);', data): 29 29 + compat_list += re.findall(r'\.compatible\s+=\s+"(\S+)"', m[3]) 30 30 31 31 return compat_list 32 32