memory: tegra: Group register and fields

The current register definitions are not in sorted order. Sort these
registers according to their address. Put bit fields and masks of the
corresponding registers below the register definitions to clearly
identify which fields belongs to which registers.

Signed-off-by: Ketan Patil <ketanp@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Link: https://patch.msgid.link/20260226163115.1152181-3-ketanp@nvidia.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

authored by

Ketan Patil and committed by

Krzysztof Kozlowski 3 months ago 95b714bd b8a177f1

+33 -29

1 changed file

expand all

drivers

memory

tegra

mc.h

+33 -29

drivers/memory/tegra/mc.h

··· 13 13 #include <soc/tegra/mc.h> 14 14 15 15 #define MC_INTSTATUS 0x00 16 + /* Bit field of MC_INTSTATUS register */ 17 + #define MC_INT_DECERR_EMEM BIT(6) 18 + #define MC_INT_INVALID_GART_PAGE BIT(7) 19 + #define MC_INT_SECURITY_VIOLATION BIT(8) 20 + #define MC_INT_ARBITRATION_EMEM BIT(9) 21 + #define MC_INT_INVALID_SMMU_PAGE BIT(10) 22 + #define MC_INT_INVALID_APB_ASID_UPDATE BIT(11) 23 + #define MC_INT_DECERR_VPR BIT(12) 24 + #define MC_INT_SECERR_SEC BIT(13) 25 + #define MC_INT_DECERR_MTS BIT(16) 26 + #define MC_INT_DECERR_GENERALIZED_CARVEOUT BIT(17) 27 + #define MC_INT_DECERR_ROUTE_SANITY BIT(20) 28 + 16 29 #define MC_INTMASK 0x04 17 30 #define MC_GART_ERROR_REQ 0x30 18 31 #define MC_EMEM_ADR_CFG 0x54 32 + #define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0) 33 + 19 34 #define MC_DECERR_EMEM_OTHERS_STATUS 0x58 20 35 #define MC_SECURITY_VIOLATION_STATUS 0x74 21 36 #define MC_EMEM_ARB_CFG 0x90 37 + #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x) ((x) & 0x1ff) 38 + #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff 39 + 22 40 #define MC_EMEM_ARB_OUTSTANDING_REQ 0x94 41 + #define MC_EMEM_ARB_OUTSTANDING_REQ_HOLDOFF_OVERRIDE BIT(30) 42 + #define MC_EMEM_ARB_OUTSTANDING_REQ_LIMIT_ENABLE BIT(31) 43 + #define MC_EMEM_ARB_OUTSTANDING_REQ_MAX_MASK 0x1ff 44 + 23 45 #define MC_EMEM_ARB_TIMING_RCD 0x98 24 46 #define MC_EMEM_ARB_TIMING_RP 0x9c 25 47 #define MC_EMEM_ARB_TIMING_RC 0xa0 ··· 61 39 #define MC_EMEM_ARB_MISC1 0xdc 62 40 #define MC_EMEM_ARB_RING1_THROTTLE 0xe0 63 41 #define MC_EMEM_ARB_OVERRIDE 0xe8 42 + #define MC_EMEM_ARB_OVERRIDE_EACK_MASK 0x3 43 + 64 44 #define MC_TIMING_CONTROL_DBG 0xf8 65 45 #define MC_TIMING_CONTROL 0xfc 46 + #define MC_TIMING_UPDATE BIT(0) 47 + 66 48 #define MC_GLOBAL_INTSTATUS 0xf24 67 49 68 - #define MC_INT_DECERR_ROUTE_SANITY BIT(20) 69 - #define MC_INT_DECERR_GENERALIZED_CARVEOUT BIT(17) 70 - #define MC_INT_DECERR_MTS BIT(16) 71 - #define MC_INT_SECERR_SEC BIT(13) 72 - #define MC_INT_DECERR_VPR BIT(12) 73 - #define MC_INT_INVALID_APB_ASID_UPDATE BIT(11) 74 - #define MC_INT_INVALID_SMMU_PAGE BIT(10) 75 - #define MC_INT_ARBITRATION_EMEM BIT(9) 76 - #define MC_INT_SECURITY_VIOLATION BIT(8) 77 - #define MC_INT_INVALID_GART_PAGE BIT(7) 78 - #define MC_INT_DECERR_EMEM BIT(6) 50 + /* Bit field of MC_ERR_STATUS_0 register */ 51 + #define MC_ERR_STATUS_RW BIT(16) 52 + #define MC_ERR_STATUS_SECURITY BIT(17) 53 + #define MC_ERR_STATUS_NONSECURE BIT(25) 54 + #define MC_ERR_STATUS_WRITABLE BIT(26) 55 + #define MC_ERR_STATUS_READABLE BIT(27) 79 56 80 57 #define MC_ERR_STATUS_TYPE_SHIFT 28 81 58 #define MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE (0x6 << 28) 82 59 #define MC_ERR_STATUS_TYPE_MASK (0x7 << 28) 83 - #define MC_ERR_STATUS_READABLE BIT(27) 84 - #define MC_ERR_STATUS_WRITABLE BIT(26) 85 - #define MC_ERR_STATUS_NONSECURE BIT(25) 60 + 86 61 #define MC_ERR_STATUS_ADR_HI_SHIFT 20 87 62 #define MC_ERR_STATUS_ADR_HI_MASK 0x3 88 - #define MC_ERR_STATUS_SECURITY BIT(17) 89 - #define MC_ERR_STATUS_RW BIT(16) 90 - 91 - #define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0) 92 - 93 - #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x) ((x) & 0x1ff) 94 - #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff 95 - 96 - #define MC_EMEM_ARB_OUTSTANDING_REQ_MAX_MASK 0x1ff 97 - #define MC_EMEM_ARB_OUTSTANDING_REQ_HOLDOFF_OVERRIDE BIT(30) 98 - #define MC_EMEM_ARB_OUTSTANDING_REQ_LIMIT_ENABLE BIT(31) 99 - 100 - #define MC_EMEM_ARB_OVERRIDE_EACK_MASK 0x3 101 - 102 - #define MC_TIMING_UPDATE BIT(0) 103 63 104 64 #define MC_BROADCAST_CHANNEL ~0 105 65

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