Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'icc-qdu1000-immutable' of https://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into HEAD
Merge DT binding to gain interconnect defines.
+1341
+70
Documentation/devicetree/bindings/interconnect/qcom,qdu1000-rpmh.yaml
+70
Documentation/devicetree/bindings/interconnect/qcom,qdu1000-rpmh.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/interconnect/qcom,qdu1000-rpmh.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm RPMh Network-On-Chip Interconnect on QDU1000
8
+
9
+
maintainers:
10
+
- Georgi Djakov <djakov@kernel.org>
11
+
- Odelu Kukatla <quic_okukatla@quicinc.com>
12
+
13
+
description: |
14
+
RPMh interconnect providers support system bandwidth requirements through
15
+
RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
16
+
able to communicate with the BCM through the Resource State Coordinator (RSC)
17
+
associated with each execution environment. Provider nodes must point to at
18
+
least one RPMh device child node pertaining to their RSC and each provider
19
+
can map to multiple RPMh resources.
20
+
21
+
properties:
22
+
compatible:
23
+
enum:
24
+
- qcom,qdu1000-clk-virt
25
+
- qcom,qdu1000-gem-noc
26
+
- qcom,qdu1000-mc-virt
27
+
- qcom,qdu1000-system-noc
28
+
29
+
'#interconnect-cells': true
30
+
31
+
reg:
32
+
maxItems: 1
33
+
34
+
allOf:
35
+
- $ref: qcom,rpmh-common.yaml#
36
+
- if:
37
+
properties:
38
+
compatible:
39
+
contains:
40
+
enum:
41
+
- qcom,qdu1000-clk-virt
42
+
- qcom,qdu1000-mc-virt
43
+
then:
44
+
properties:
45
+
reg: false
46
+
else:
47
+
required:
48
+
- reg
49
+
50
+
required:
51
+
- compatible
52
+
53
+
unevaluatedProperties: false
54
+
55
+
examples:
56
+
- |
57
+
#include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h>
58
+
59
+
system_noc: interconnect@1640000 {
60
+
compatible = "qcom,qdu1000-system-noc";
61
+
reg = <0x1640000 0x45080>;
62
+
#interconnect-cells = <2>;
63
+
qcom,bcm-voters = <&apps_bcm_voter>;
64
+
};
65
+
66
+
clk_virt: interconnect-0 {
67
+
compatible = "qcom,qdu1000-clk-virt";
68
+
#interconnect-cells = <2>;
69
+
qcom,bcm-voters = <&apps_bcm_voter>;
70
+
};
+9
drivers/interconnect/qcom/Kconfig
+9
drivers/interconnect/qcom/Kconfig
···
69
69
This is a driver for the Qualcomm Network-on-Chip on qcs404-based
70
70
platforms.
71
71
72
+
config INTERCONNECT_QCOM_QDU1000
73
+
tristate "Qualcomm QDU1000/QRU1000 interconnect driver"
74
+
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
75
+
select INTERCONNECT_QCOM_RPMH
76
+
select INTERCONNECT_QCOM_BCM_VOTER
77
+
help
78
+
This is a driver for the Qualcomm Network-on-Chip on QDU1000-based
79
+
and QRU1000-based platforms.
80
+
72
81
config INTERCONNECT_QCOM_RPMH_POSSIBLE
73
82
tristate
74
83
default INTERCONNECT_QCOM
+2
drivers/interconnect/qcom/Makefile
+2
drivers/interconnect/qcom/Makefile
···
11
11
icc-osm-l3-objs := osm-l3.o
12
12
qnoc-qcm2290-objs := qcm2290.o
13
13
qnoc-qcs404-objs := qcs404.o
14
+
qnoc-qdu1000-objs := qdu1000.o
14
15
icc-rpmh-obj := icc-rpmh.o
15
16
qnoc-sc7180-objs := sc7180.o
16
17
qnoc-sc7280-objs := sc7280.o
···
37
36
obj-$(CONFIG_INTERCONNECT_QCOM_OSM_L3) += icc-osm-l3.o
38
37
obj-$(CONFIG_INTERCONNECT_QCOM_QCM2290) += qnoc-qcm2290.o
39
38
obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) += qnoc-qcs404.o
39
+
obj-$(CONFIG_INTERCONNECT_QCOM_QDU1000) += qnoc-qdu1000.o
40
40
obj-$(CONFIG_INTERCONNECT_QCOM_RPMH) += icc-rpmh.o
41
41
obj-$(CONFIG_INTERCONNECT_QCOM_SC7180) += qnoc-sc7180.o
42
42
obj-$(CONFIG_INTERCONNECT_QCOM_SC7280) += qnoc-sc7280.o
+1067
drivers/interconnect/qcom/qdu1000.c
+1067
drivers/interconnect/qcom/qdu1000.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*
5
+
*/
6
+
7
+
#include <linux/device.h>
8
+
#include <linux/interconnect.h>
9
+
#include <linux/interconnect-provider.h>
10
+
#include <linux/module.h>
11
+
#include <linux/of_platform.h>
12
+
#include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h>
13
+
14
+
#include "bcm-voter.h"
15
+
#include "icc-common.h"
16
+
#include "icc-rpmh.h"
17
+
#include "qdu1000.h"
18
+
19
+
static struct qcom_icc_node qup0_core_master = {
20
+
.name = "qup0_core_master",
21
+
.id = QDU1000_MASTER_QUP_CORE_0,
22
+
.channels = 1,
23
+
.buswidth = 4,
24
+
.num_links = 1,
25
+
.links = { QDU1000_SLAVE_QUP_CORE_0 },
26
+
};
27
+
28
+
static struct qcom_icc_node qup1_core_master = {
29
+
.name = "qup1_core_master",
30
+
.id = QDU1000_MASTER_QUP_CORE_1,
31
+
.channels = 1,
32
+
.buswidth = 4,
33
+
.num_links = 1,
34
+
.links = { QDU1000_SLAVE_QUP_CORE_1 },
35
+
};
36
+
37
+
static struct qcom_icc_node alm_sys_tcu = {
38
+
.name = "alm_sys_tcu",
39
+
.id = QDU1000_MASTER_SYS_TCU,
40
+
.channels = 1,
41
+
.buswidth = 8,
42
+
.num_links = 2,
43
+
.links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC },
44
+
};
45
+
46
+
static struct qcom_icc_node chm_apps = {
47
+
.name = "chm_apps",
48
+
.id = QDU1000_MASTER_APPSS_PROC,
49
+
.channels = 1,
50
+
.buswidth = 16,
51
+
.num_links = 4,
52
+
.links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC,
53
+
QDU1000_SLAVE_GEMNOC_MODEM_CNOC, QDU1000_SLAVE_MEM_NOC_PCIE_SNOC
54
+
},
55
+
};
56
+
57
+
static struct qcom_icc_node qnm_ecpri_dma = {
58
+
.name = "qnm_ecpri_dma",
59
+
.id = QDU1000_MASTER_GEMNOC_ECPRI_DMA,
60
+
.channels = 2,
61
+
.buswidth = 32,
62
+
.num_links = 2,
63
+
.links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC },
64
+
};
65
+
66
+
static struct qcom_icc_node qnm_fec_2_gemnoc = {
67
+
.name = "qnm_fec_2_gemnoc",
68
+
.id = QDU1000_MASTER_FEC_2_GEMNOC,
69
+
.channels = 2,
70
+
.buswidth = 32,
71
+
.num_links = 2,
72
+
.links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC },
73
+
};
74
+
75
+
static struct qcom_icc_node qnm_pcie = {
76
+
.name = "qnm_pcie",
77
+
.id = QDU1000_MASTER_ANOC_PCIE_GEM_NOC,
78
+
.channels = 1,
79
+
.buswidth = 64,
80
+
.num_links = 3,
81
+
.links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC,
82
+
QDU1000_SLAVE_GEMNOC_MODEM_CNOC
83
+
},
84
+
};
85
+
86
+
static struct qcom_icc_node qnm_snoc_gc = {
87
+
.name = "qnm_snoc_gc",
88
+
.id = QDU1000_MASTER_SNOC_GC_MEM_NOC,
89
+
.channels = 1,
90
+
.buswidth = 8,
91
+
.num_links = 1,
92
+
.links = { QDU1000_SLAVE_LLCC },
93
+
};
94
+
95
+
static struct qcom_icc_node qnm_snoc_sf = {
96
+
.name = "qnm_snoc_sf",
97
+
.id = QDU1000_MASTER_SNOC_SF_MEM_NOC,
98
+
.channels = 1,
99
+
.buswidth = 16,
100
+
.num_links = 4,
101
+
.links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC,
102
+
QDU1000_SLAVE_GEMNOC_MODEM_CNOC, QDU1000_SLAVE_MEM_NOC_PCIE_SNOC
103
+
},
104
+
};
105
+
106
+
static struct qcom_icc_node qxm_mdsp = {
107
+
.name = "qxm_mdsp",
108
+
.id = QDU1000_MASTER_MSS_PROC,
109
+
.channels = 1,
110
+
.buswidth = 16,
111
+
.num_links = 3,
112
+
.links = { QDU1000_SLAVE_GEM_NOC_CNOC, QDU1000_SLAVE_LLCC,
113
+
QDU1000_SLAVE_MEM_NOC_PCIE_SNOC
114
+
},
115
+
};
116
+
117
+
static struct qcom_icc_node llcc_mc = {
118
+
.name = "llcc_mc",
119
+
.id = QDU1000_MASTER_LLCC,
120
+
.channels = 8,
121
+
.buswidth = 4,
122
+
.num_links = 1,
123
+
.links = { QDU1000_SLAVE_EBI1 },
124
+
};
125
+
126
+
static struct qcom_icc_node qhm_gic = {
127
+
.name = "qhm_gic",
128
+
.id = QDU1000_MASTER_GIC_AHB,
129
+
.channels = 1,
130
+
.buswidth = 4,
131
+
.num_links = 1,
132
+
.links = { QDU1000_SLAVE_SNOC_GEM_NOC_SF },
133
+
};
134
+
135
+
static struct qcom_icc_node qhm_qdss_bam = {
136
+
.name = "qhm_qdss_bam",
137
+
.id = QDU1000_MASTER_QDSS_BAM,
138
+
.channels = 1,
139
+
.buswidth = 4,
140
+
.num_links = 1,
141
+
.links = { QDU1000_SLAVE_SNOC_GEM_NOC_SF },
142
+
};
143
+
144
+
static struct qcom_icc_node qhm_qpic = {
145
+
.name = "qhm_qpic",
146
+
.id = QDU1000_MASTER_QPIC,
147
+
.channels = 1,
148
+
.buswidth = 4,
149
+
.num_links = 1,
150
+
.links = { QDU1000_SLAVE_A1NOC_SNOC },
151
+
};
152
+
153
+
static struct qcom_icc_node qhm_qspi = {
154
+
.name = "qhm_qspi",
155
+
.id = QDU1000_MASTER_QSPI_0,
156
+
.channels = 1,
157
+
.buswidth = 4,
158
+
.num_links = 1,
159
+
.links = { QDU1000_SLAVE_A1NOC_SNOC },
160
+
};
161
+
162
+
static struct qcom_icc_node qhm_qup0 = {
163
+
.name = "qhm_qup0",
164
+
.id = QDU1000_MASTER_QUP_0,
165
+
.channels = 1,
166
+
.buswidth = 4,
167
+
.num_links = 1,
168
+
.links = { QDU1000_SLAVE_A1NOC_SNOC },
169
+
};
170
+
171
+
static struct qcom_icc_node qhm_qup1 = {
172
+
.name = "qhm_qup1",
173
+
.id = QDU1000_MASTER_QUP_1,
174
+
.channels = 1,
175
+
.buswidth = 4,
176
+
.num_links = 1,
177
+
.links = { QDU1000_SLAVE_A1NOC_SNOC },
178
+
};
179
+
180
+
static struct qcom_icc_node qhm_system_noc_cfg = {
181
+
.name = "qhm_system_noc_cfg",
182
+
.id = QDU1000_MASTER_SNOC_CFG,
183
+
.channels = 1,
184
+
.buswidth = 4,
185
+
.num_links = 1,
186
+
.links = { QDU1000_SLAVE_SERVICE_SNOC },
187
+
};
188
+
189
+
static struct qcom_icc_node qnm_aggre_noc = {
190
+
.name = "qnm_aggre_noc",
191
+
.id = QDU1000_MASTER_ANOC_SNOC,
192
+
.channels = 1,
193
+
.buswidth = 8,
194
+
.num_links = 1,
195
+
.links = { QDU1000_SLAVE_SNOC_GEM_NOC_SF },
196
+
};
197
+
198
+
static struct qcom_icc_node qnm_aggre_noc_gsi = {
199
+
.name = "qnm_aggre_noc_gsi",
200
+
.id = QDU1000_MASTER_ANOC_GSI,
201
+
.channels = 1,
202
+
.buswidth = 8,
203
+
.num_links = 1,
204
+
.links = { QDU1000_SLAVE_SNOC_GEM_NOC_GC },
205
+
};
206
+
207
+
static struct qcom_icc_node qnm_gemnoc_cnoc = {
208
+
.name = "qnm_gemnoc_cnoc",
209
+
.id = QDU1000_MASTER_GEM_NOC_CNOC,
210
+
.channels = 1,
211
+
.buswidth = 16,
212
+
.num_links = 36,
213
+
.links = { QDU1000_SLAVE_AHB2PHY_SOUTH, QDU1000_SLAVE_AHB2PHY_NORTH,
214
+
QDU1000_SLAVE_AHB2PHY_EAST, QDU1000_SLAVE_AOSS,
215
+
QDU1000_SLAVE_CLK_CTL, QDU1000_SLAVE_RBCPR_CX_CFG,
216
+
QDU1000_SLAVE_RBCPR_MX_CFG, QDU1000_SLAVE_CRYPTO_0_CFG,
217
+
QDU1000_SLAVE_ECPRI_CFG, QDU1000_SLAVE_IMEM_CFG,
218
+
QDU1000_SLAVE_IPC_ROUTER_CFG, QDU1000_SLAVE_CNOC_MSS,
219
+
QDU1000_SLAVE_PCIE_CFG, QDU1000_SLAVE_PDM,
220
+
QDU1000_SLAVE_PIMEM_CFG, QDU1000_SLAVE_PRNG,
221
+
QDU1000_SLAVE_QDSS_CFG, QDU1000_SLAVE_QPIC,
222
+
QDU1000_SLAVE_QSPI_0, QDU1000_SLAVE_QUP_0,
223
+
QDU1000_SLAVE_QUP_1, QDU1000_SLAVE_SDCC_2,
224
+
QDU1000_SLAVE_SMBUS_CFG, QDU1000_SLAVE_SNOC_CFG,
225
+
QDU1000_SLAVE_TCSR, QDU1000_SLAVE_TLMM,
226
+
QDU1000_SLAVE_TME_CFG, QDU1000_SLAVE_TSC_CFG,
227
+
QDU1000_SLAVE_USB3_0, QDU1000_SLAVE_VSENSE_CTRL_CFG,
228
+
QDU1000_SLAVE_DDRSS_CFG, QDU1000_SLAVE_IMEM,
229
+
QDU1000_SLAVE_PIMEM, QDU1000_SLAVE_ETHERNET_SS,
230
+
QDU1000_SLAVE_QDSS_STM, QDU1000_SLAVE_TCU
231
+
},
232
+
};
233
+
234
+
static struct qcom_icc_node qnm_gemnoc_modem_slave = {
235
+
.name = "qnm_gemnoc_modem_slave",
236
+
.id = QDU1000_MASTER_GEMNOC_MODEM_CNOC,
237
+
.channels = 1,
238
+
.buswidth = 16,
239
+
.num_links = 1,
240
+
.links = { QDU1000_SLAVE_MODEM_OFFLINE },
241
+
};
242
+
243
+
static struct qcom_icc_node qnm_gemnoc_pcie = {
244
+
.name = "qnm_gemnoc_pcie",
245
+
.id = QDU1000_MASTER_GEM_NOC_PCIE_SNOC,
246
+
.channels = 1,
247
+
.buswidth = 16,
248
+
.num_links = 1,
249
+
.links = { QDU1000_SLAVE_PCIE_0 },
250
+
};
251
+
252
+
static struct qcom_icc_node qxm_crypto = {
253
+
.name = "qxm_crypto",
254
+
.id = QDU1000_MASTER_CRYPTO,
255
+
.channels = 1,
256
+
.buswidth = 8,
257
+
.num_links = 1,
258
+
.links = { QDU1000_SLAVE_A1NOC_SNOC },
259
+
};
260
+
261
+
static struct qcom_icc_node qxm_ecpri_gsi = {
262
+
.name = "qxm_ecpri_gsi",
263
+
.id = QDU1000_MASTER_ECPRI_GSI,
264
+
.channels = 1,
265
+
.buswidth = 8,
266
+
.num_links = 2,
267
+
.links = { QDU1000_SLAVE_ANOC_SNOC_GSI, QDU1000_SLAVE_PCIE_0 },
268
+
};
269
+
270
+
static struct qcom_icc_node qxm_pimem = {
271
+
.name = "qxm_pimem",
272
+
.id = QDU1000_MASTER_PIMEM,
273
+
.channels = 1,
274
+
.buswidth = 8,
275
+
.num_links = 1,
276
+
.links = { QDU1000_SLAVE_SNOC_GEM_NOC_GC },
277
+
};
278
+
279
+
static struct qcom_icc_node xm_ecpri_dma = {
280
+
.name = "xm_ecpri_dma",
281
+
.id = QDU1000_MASTER_SNOC_ECPRI_DMA,
282
+
.channels = 2,
283
+
.buswidth = 32,
284
+
.num_links = 2,
285
+
.links = { QDU1000_SLAVE_ECPRI_GEMNOC, QDU1000_SLAVE_PCIE_0 },
286
+
};
287
+
288
+
static struct qcom_icc_node xm_gic = {
289
+
.name = "xm_gic",
290
+
.id = QDU1000_MASTER_GIC,
291
+
.channels = 1,
292
+
.buswidth = 8,
293
+
.num_links = 1,
294
+
.links = { QDU1000_SLAVE_SNOC_GEM_NOC_GC },
295
+
};
296
+
297
+
static struct qcom_icc_node xm_pcie = {
298
+
.name = "xm_pcie",
299
+
.id = QDU1000_MASTER_PCIE,
300
+
.channels = 1,
301
+
.buswidth = 64,
302
+
.num_links = 1,
303
+
.links = { QDU1000_SLAVE_ANOC_PCIE_GEM_NOC },
304
+
};
305
+
306
+
static struct qcom_icc_node xm_qdss_etr0 = {
307
+
.name = "xm_qdss_etr0",
308
+
.id = QDU1000_MASTER_QDSS_ETR,
309
+
.channels = 1,
310
+
.buswidth = 8,
311
+
.num_links = 1,
312
+
.links = { QDU1000_SLAVE_SNOC_GEM_NOC_SF },
313
+
};
314
+
315
+
static struct qcom_icc_node xm_qdss_etr1 = {
316
+
.name = "xm_qdss_etr1",
317
+
.id = QDU1000_MASTER_QDSS_ETR_1,
318
+
.channels = 1,
319
+
.buswidth = 8,
320
+
.num_links = 1,
321
+
.links = { QDU1000_SLAVE_SNOC_GEM_NOC_SF },
322
+
};
323
+
324
+
static struct qcom_icc_node xm_sdc = {
325
+
.name = "xm_sdc",
326
+
.id = QDU1000_MASTER_SDCC_1,
327
+
.channels = 1,
328
+
.buswidth = 8,
329
+
.num_links = 1,
330
+
.links = { QDU1000_SLAVE_A1NOC_SNOC },
331
+
};
332
+
333
+
static struct qcom_icc_node xm_usb3 = {
334
+
.name = "xm_usb3",
335
+
.id = QDU1000_MASTER_USB3,
336
+
.channels = 1,
337
+
.buswidth = 8,
338
+
.num_links = 1,
339
+
.links = { QDU1000_SLAVE_A1NOC_SNOC },
340
+
};
341
+
342
+
static struct qcom_icc_node qup0_core_slave = {
343
+
.name = "qup0_core_slave",
344
+
.id = QDU1000_SLAVE_QUP_CORE_0,
345
+
.channels = 1,
346
+
.buswidth = 4,
347
+
.num_links = 0,
348
+
};
349
+
350
+
static struct qcom_icc_node qup1_core_slave = {
351
+
.name = "qup1_core_slave",
352
+
.id = QDU1000_SLAVE_QUP_CORE_1,
353
+
.channels = 1,
354
+
.buswidth = 4,
355
+
.num_links = 0,
356
+
};
357
+
358
+
static struct qcom_icc_node qns_gem_noc_cnoc = {
359
+
.name = "qns_gem_noc_cnoc",
360
+
.id = QDU1000_SLAVE_GEM_NOC_CNOC,
361
+
.channels = 1,
362
+
.buswidth = 16,
363
+
.num_links = 1,
364
+
.links = { QDU1000_MASTER_GEM_NOC_CNOC },
365
+
};
366
+
367
+
static struct qcom_icc_node qns_llcc = {
368
+
.name = "qns_llcc",
369
+
.id = QDU1000_SLAVE_LLCC,
370
+
.channels = 8,
371
+
.buswidth = 16,
372
+
.num_links = 1,
373
+
.links = { QDU1000_MASTER_LLCC },
374
+
};
375
+
376
+
static struct qcom_icc_node qns_modem_slave = {
377
+
.name = "qns_modem_slave",
378
+
.id = QDU1000_SLAVE_GEMNOC_MODEM_CNOC,
379
+
.channels = 1,
380
+
.buswidth = 16,
381
+
.num_links = 1,
382
+
.links = { QDU1000_MASTER_GEMNOC_MODEM_CNOC },
383
+
};
384
+
385
+
static struct qcom_icc_node qns_pcie = {
386
+
.name = "qns_pcie",
387
+
.id = QDU1000_SLAVE_MEM_NOC_PCIE_SNOC,
388
+
.channels = 1,
389
+
.buswidth = 16,
390
+
.num_links = 1,
391
+
.links = { QDU1000_MASTER_GEM_NOC_PCIE_SNOC },
392
+
};
393
+
394
+
static struct qcom_icc_node ebi = {
395
+
.name = "ebi",
396
+
.id = QDU1000_SLAVE_EBI1,
397
+
.channels = 8,
398
+
.buswidth = 4,
399
+
.num_links = 0,
400
+
};
401
+
402
+
static struct qcom_icc_node qhs_ahb2phy0_south = {
403
+
.name = "qhs_ahb2phy0_south",
404
+
.id = QDU1000_SLAVE_AHB2PHY_SOUTH,
405
+
.channels = 1,
406
+
.buswidth = 4,
407
+
.num_links = 0,
408
+
};
409
+
410
+
static struct qcom_icc_node qhs_ahb2phy1_north = {
411
+
.name = "qhs_ahb2phy1_north",
412
+
.id = QDU1000_SLAVE_AHB2PHY_NORTH,
413
+
.channels = 1,
414
+
.buswidth = 4,
415
+
.num_links = 0,
416
+
};
417
+
418
+
static struct qcom_icc_node qhs_ahb2phy2_east = {
419
+
.name = "qhs_ahb2phy2_east",
420
+
.id = QDU1000_SLAVE_AHB2PHY_EAST,
421
+
.channels = 1,
422
+
.buswidth = 4,
423
+
.num_links = 0,
424
+
};
425
+
426
+
static struct qcom_icc_node qhs_aoss = {
427
+
.name = "qhs_aoss",
428
+
.id = QDU1000_SLAVE_AOSS,
429
+
.channels = 1,
430
+
.buswidth = 4,
431
+
.num_links = 0,
432
+
};
433
+
434
+
static struct qcom_icc_node qhs_clk_ctl = {
435
+
.name = "qhs_clk_ctl",
436
+
.id = QDU1000_SLAVE_CLK_CTL,
437
+
.channels = 1,
438
+
.buswidth = 4,
439
+
.num_links = 0,
440
+
};
441
+
442
+
static struct qcom_icc_node qhs_cpr_cx = {
443
+
.name = "qhs_cpr_cx",
444
+
.id = QDU1000_SLAVE_RBCPR_CX_CFG,
445
+
.channels = 1,
446
+
.buswidth = 4,
447
+
.num_links = 0,
448
+
};
449
+
450
+
static struct qcom_icc_node qhs_cpr_mx = {
451
+
.name = "qhs_cpr_mx",
452
+
.id = QDU1000_SLAVE_RBCPR_MX_CFG,
453
+
.channels = 1,
454
+
.buswidth = 4,
455
+
.num_links = 0,
456
+
};
457
+
458
+
static struct qcom_icc_node qhs_crypto_cfg = {
459
+
.name = "qhs_crypto_cfg",
460
+
.id = QDU1000_SLAVE_CRYPTO_0_CFG,
461
+
.channels = 1,
462
+
.buswidth = 4,
463
+
.num_links = 0,
464
+
};
465
+
466
+
static struct qcom_icc_node qhs_ecpri_cfg = {
467
+
.name = "qhs_ecpri_cfg",
468
+
.id = QDU1000_SLAVE_ECPRI_CFG,
469
+
.channels = 1,
470
+
.buswidth = 4,
471
+
.num_links = 0,
472
+
};
473
+
474
+
static struct qcom_icc_node qhs_imem_cfg = {
475
+
.name = "qhs_imem_cfg",
476
+
.id = QDU1000_SLAVE_IMEM_CFG,
477
+
.channels = 1,
478
+
.buswidth = 4,
479
+
.num_links = 0,
480
+
};
481
+
482
+
static struct qcom_icc_node qhs_ipc_router = {
483
+
.name = "qhs_ipc_router",
484
+
.id = QDU1000_SLAVE_IPC_ROUTER_CFG,
485
+
.channels = 1,
486
+
.buswidth = 4,
487
+
.num_links = 0,
488
+
};
489
+
490
+
static struct qcom_icc_node qhs_mss_cfg = {
491
+
.name = "qhs_mss_cfg",
492
+
.id = QDU1000_SLAVE_CNOC_MSS,
493
+
.channels = 1,
494
+
.buswidth = 4,
495
+
.num_links = 0,
496
+
};
497
+
498
+
static struct qcom_icc_node qhs_pcie_cfg = {
499
+
.name = "qhs_pcie_cfg",
500
+
.id = QDU1000_SLAVE_PCIE_CFG,
501
+
.channels = 1,
502
+
.buswidth = 4,
503
+
.num_links = 0,
504
+
};
505
+
506
+
static struct qcom_icc_node qhs_pdm = {
507
+
.name = "qhs_pdm",
508
+
.id = QDU1000_SLAVE_PDM,
509
+
.channels = 1,
510
+
.buswidth = 4,
511
+
.num_links = 0,
512
+
};
513
+
514
+
static struct qcom_icc_node qhs_pimem_cfg = {
515
+
.name = "qhs_pimem_cfg",
516
+
.id = QDU1000_SLAVE_PIMEM_CFG,
517
+
.channels = 1,
518
+
.buswidth = 4,
519
+
.num_links = 0,
520
+
};
521
+
522
+
static struct qcom_icc_node qhs_prng = {
523
+
.name = "qhs_prng",
524
+
.id = QDU1000_SLAVE_PRNG,
525
+
.channels = 1,
526
+
.buswidth = 4,
527
+
.num_links = 0,
528
+
};
529
+
530
+
static struct qcom_icc_node qhs_qdss_cfg = {
531
+
.name = "qhs_qdss_cfg",
532
+
.id = QDU1000_SLAVE_QDSS_CFG,
533
+
.channels = 1,
534
+
.buswidth = 4,
535
+
.num_links = 0,
536
+
};
537
+
538
+
static struct qcom_icc_node qhs_qpic = {
539
+
.name = "qhs_qpic",
540
+
.id = QDU1000_SLAVE_QPIC,
541
+
.channels = 1,
542
+
.buswidth = 4,
543
+
.num_links = 0,
544
+
};
545
+
546
+
static struct qcom_icc_node qhs_qspi = {
547
+
.name = "qhs_qspi",
548
+
.id = QDU1000_SLAVE_QSPI_0,
549
+
.channels = 1,
550
+
.buswidth = 4,
551
+
.num_links = 0,
552
+
};
553
+
554
+
static struct qcom_icc_node qhs_qup0 = {
555
+
.name = "qhs_qup0",
556
+
.id = QDU1000_SLAVE_QUP_0,
557
+
.channels = 1,
558
+
.buswidth = 4,
559
+
.num_links = 0,
560
+
};
561
+
562
+
static struct qcom_icc_node qhs_qup1 = {
563
+
.name = "qhs_qup1",
564
+
.id = QDU1000_SLAVE_QUP_1,
565
+
.channels = 1,
566
+
.buswidth = 4,
567
+
.num_links = 0,
568
+
};
569
+
570
+
static struct qcom_icc_node qhs_sdc2 = {
571
+
.name = "qhs_sdc2",
572
+
.id = QDU1000_SLAVE_SDCC_2,
573
+
.channels = 1,
574
+
.buswidth = 4,
575
+
.num_links = 0,
576
+
};
577
+
578
+
static struct qcom_icc_node qhs_smbus_cfg = {
579
+
.name = "qhs_smbus_cfg",
580
+
.id = QDU1000_SLAVE_SMBUS_CFG,
581
+
.channels = 1,
582
+
.buswidth = 4,
583
+
.num_links = 0,
584
+
};
585
+
586
+
static struct qcom_icc_node qhs_system_noc_cfg = {
587
+
.name = "qhs_system_noc_cfg",
588
+
.id = QDU1000_SLAVE_SNOC_CFG,
589
+
.channels = 1,
590
+
.buswidth = 4,
591
+
.num_links = 1,
592
+
.links = { QDU1000_MASTER_SNOC_CFG },
593
+
};
594
+
595
+
static struct qcom_icc_node qhs_tcsr = {
596
+
.name = "qhs_tcsr",
597
+
.id = QDU1000_SLAVE_TCSR,
598
+
.channels = 1,
599
+
.buswidth = 4,
600
+
.num_links = 0,
601
+
};
602
+
603
+
static struct qcom_icc_node qhs_tlmm = {
604
+
.name = "qhs_tlmm",
605
+
.id = QDU1000_SLAVE_TLMM,
606
+
.channels = 1,
607
+
.buswidth = 4,
608
+
.num_links = 0,
609
+
};
610
+
611
+
static struct qcom_icc_node qhs_tme_cfg = {
612
+
.name = "qhs_tme_cfg",
613
+
.id = QDU1000_SLAVE_TME_CFG,
614
+
.channels = 1,
615
+
.buswidth = 4,
616
+
.num_links = 0,
617
+
};
618
+
619
+
static struct qcom_icc_node qhs_tsc_cfg = {
620
+
.name = "qhs_tsc_cfg",
621
+
.id = QDU1000_SLAVE_TSC_CFG,
622
+
.channels = 1,
623
+
.buswidth = 4,
624
+
.num_links = 0,
625
+
};
626
+
627
+
static struct qcom_icc_node qhs_usb3 = {
628
+
.name = "qhs_usb3",
629
+
.id = QDU1000_SLAVE_USB3_0,
630
+
.channels = 1,
631
+
.buswidth = 4,
632
+
.num_links = 0,
633
+
};
634
+
635
+
static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
636
+
.name = "qhs_vsense_ctrl_cfg",
637
+
.id = QDU1000_SLAVE_VSENSE_CTRL_CFG,
638
+
.channels = 1,
639
+
.buswidth = 4,
640
+
.num_links = 0,
641
+
};
642
+
643
+
static struct qcom_icc_node qns_a1noc_snoc = {
644
+
.name = "qns_a1noc_snoc",
645
+
.id = QDU1000_SLAVE_A1NOC_SNOC,
646
+
.channels = 1,
647
+
.buswidth = 8,
648
+
.num_links = 1,
649
+
.links = { QDU1000_MASTER_ANOC_SNOC },
650
+
};
651
+
652
+
static struct qcom_icc_node qns_anoc_snoc_gsi = {
653
+
.name = "qns_anoc_snoc_gsi",
654
+
.id = QDU1000_SLAVE_ANOC_SNOC_GSI,
655
+
.channels = 1,
656
+
.buswidth = 8,
657
+
.num_links = 1,
658
+
.links = { QDU1000_MASTER_ANOC_GSI },
659
+
};
660
+
661
+
static struct qcom_icc_node qns_ddrss_cfg = {
662
+
.name = "qns_ddrss_cfg",
663
+
.id = QDU1000_SLAVE_DDRSS_CFG,
664
+
.channels = 1,
665
+
.buswidth = 4,
666
+
.num_links = 0,
667
+
};
668
+
669
+
static struct qcom_icc_node qns_ecpri_gemnoc = {
670
+
.name = "qns_ecpri_gemnoc",
671
+
.id = QDU1000_SLAVE_ECPRI_GEMNOC,
672
+
.channels = 2,
673
+
.buswidth = 32,
674
+
.num_links = 1,
675
+
.links = { QDU1000_MASTER_GEMNOC_ECPRI_DMA },
676
+
};
677
+
678
+
static struct qcom_icc_node qns_gemnoc_gc = {
679
+
.name = "qns_gemnoc_gc",
680
+
.id = QDU1000_SLAVE_SNOC_GEM_NOC_GC,
681
+
.channels = 1,
682
+
.buswidth = 8,
683
+
.num_links = 1,
684
+
.links = { QDU1000_MASTER_SNOC_GC_MEM_NOC },
685
+
};
686
+
687
+
static struct qcom_icc_node qns_gemnoc_sf = {
688
+
.name = "qns_gemnoc_sf",
689
+
.id = QDU1000_SLAVE_SNOC_GEM_NOC_SF,
690
+
.channels = 1,
691
+
.buswidth = 16,
692
+
.num_links = 1,
693
+
.links = { QDU1000_MASTER_SNOC_SF_MEM_NOC },
694
+
};
695
+
696
+
static struct qcom_icc_node qns_modem = {
697
+
.name = "qns_modem",
698
+
.id = QDU1000_SLAVE_MODEM_OFFLINE,
699
+
.channels = 1,
700
+
.buswidth = 32,
701
+
.num_links = 0,
702
+
};
703
+
704
+
static struct qcom_icc_node qns_pcie_gemnoc = {
705
+
.name = "qns_pcie_gemnoc",
706
+
.id = QDU1000_SLAVE_ANOC_PCIE_GEM_NOC,
707
+
.channels = 1,
708
+
.buswidth = 64,
709
+
.num_links = 1,
710
+
.links = { QDU1000_MASTER_ANOC_PCIE_GEM_NOC },
711
+
};
712
+
713
+
static struct qcom_icc_node qxs_imem = {
714
+
.name = "qxs_imem",
715
+
.id = QDU1000_SLAVE_IMEM,
716
+
.channels = 1,
717
+
.buswidth = 8,
718
+
.num_links = 0,
719
+
};
720
+
721
+
static struct qcom_icc_node qxs_pimem = {
722
+
.name = "qxs_pimem",
723
+
.id = QDU1000_SLAVE_PIMEM,
724
+
.channels = 1,
725
+
.buswidth = 8,
726
+
.num_links = 0,
727
+
};
728
+
729
+
static struct qcom_icc_node srvc_system_noc = {
730
+
.name = "srvc_system_noc",
731
+
.id = QDU1000_SLAVE_SERVICE_SNOC,
732
+
.channels = 1,
733
+
.buswidth = 4,
734
+
.num_links = 0,
735
+
};
736
+
737
+
static struct qcom_icc_node xs_ethernet_ss = {
738
+
.name = "xs_ethernet_ss",
739
+
.id = QDU1000_SLAVE_ETHERNET_SS,
740
+
.channels = 1,
741
+
.buswidth = 32,
742
+
.num_links = 0,
743
+
};
744
+
745
+
static struct qcom_icc_node xs_pcie = {
746
+
.name = "xs_pcie",
747
+
.id = QDU1000_SLAVE_PCIE_0,
748
+
.channels = 1,
749
+
.buswidth = 64,
750
+
.num_links = 0,
751
+
};
752
+
753
+
static struct qcom_icc_node xs_qdss_stm = {
754
+
.name = "xs_qdss_stm",
755
+
.id = QDU1000_SLAVE_QDSS_STM,
756
+
.channels = 1,
757
+
.buswidth = 4,
758
+
.num_links = 0,
759
+
};
760
+
761
+
static struct qcom_icc_node xs_sys_tcu_cfg = {
762
+
.name = "xs_sys_tcu_cfg",
763
+
.id = QDU1000_SLAVE_TCU,
764
+
.channels = 1,
765
+
.buswidth = 8,
766
+
.num_links = 0,
767
+
};
768
+
769
+
static struct qcom_icc_bcm bcm_acv = {
770
+
.name = "ACV",
771
+
.num_nodes = 1,
772
+
.nodes = { &ebi },
773
+
};
774
+
775
+
static struct qcom_icc_bcm bcm_ce0 = {
776
+
.name = "CE0",
777
+
.num_nodes = 1,
778
+
.nodes = { &qxm_crypto },
779
+
};
780
+
781
+
static struct qcom_icc_bcm bcm_cn0 = {
782
+
.name = "CN0",
783
+
.num_nodes = 44,
784
+
.nodes = { &qhm_qpic, &qhm_qspi,
785
+
&qnm_gemnoc_cnoc, &qnm_gemnoc_modem_slave,
786
+
&qnm_gemnoc_pcie, &xm_sdc,
787
+
&xm_usb3, &qhs_ahb2phy0_south,
788
+
&qhs_ahb2phy1_north, &qhs_ahb2phy2_east,
789
+
&qhs_aoss, &qhs_clk_ctl,
790
+
&qhs_cpr_cx, &qhs_cpr_mx,
791
+
&qhs_crypto_cfg, &qhs_ecpri_cfg,
792
+
&qhs_imem_cfg, &qhs_ipc_router,
793
+
&qhs_mss_cfg, &qhs_pcie_cfg,
794
+
&qhs_pdm, &qhs_pimem_cfg,
795
+
&qhs_prng, &qhs_qdss_cfg,
796
+
&qhs_qpic, &qhs_qspi,
797
+
&qhs_qup0, &qhs_qup1,
798
+
&qhs_sdc2, &qhs_smbus_cfg,
799
+
&qhs_system_noc_cfg, &qhs_tcsr,
800
+
&qhs_tlmm, &qhs_tme_cfg,
801
+
&qhs_tsc_cfg, &qhs_usb3,
802
+
&qhs_vsense_ctrl_cfg, &qns_ddrss_cfg,
803
+
&qns_modem, &qxs_imem,
804
+
&qxs_pimem, &xs_ethernet_ss,
805
+
&xs_qdss_stm, &xs_sys_tcu_cfg
806
+
},
807
+
};
808
+
809
+
static struct qcom_icc_bcm bcm_mc0 = {
810
+
.name = "MC0",
811
+
.num_nodes = 1,
812
+
.nodes = { &ebi },
813
+
};
814
+
815
+
static struct qcom_icc_bcm bcm_qup0 = {
816
+
.name = "QUP0",
817
+
.num_nodes = 2,
818
+
.nodes = { &qup0_core_slave, &qup1_core_slave },
819
+
};
820
+
821
+
static struct qcom_icc_bcm bcm_sh0 = {
822
+
.name = "SH0",
823
+
.num_nodes = 1,
824
+
.nodes = { &qns_llcc },
825
+
};
826
+
827
+
static struct qcom_icc_bcm bcm_sh1 = {
828
+
.name = "SH1",
829
+
.num_nodes = 11,
830
+
.nodes = { &alm_sys_tcu, &chm_apps,
831
+
&qnm_ecpri_dma, &qnm_fec_2_gemnoc,
832
+
&qnm_pcie, &qnm_snoc_gc,
833
+
&qnm_snoc_sf, &qxm_mdsp,
834
+
&qns_gem_noc_cnoc, &qns_modem_slave,
835
+
&qns_pcie
836
+
},
837
+
};
838
+
839
+
static struct qcom_icc_bcm bcm_sn0 = {
840
+
.name = "SN0",
841
+
.num_nodes = 1,
842
+
.nodes = { &qns_gemnoc_sf },
843
+
};
844
+
845
+
static struct qcom_icc_bcm bcm_sn1 = {
846
+
.name = "SN1",
847
+
.num_nodes = 6,
848
+
.nodes = { &qhm_gic, &qxm_pimem,
849
+
&xm_gic, &xm_qdss_etr0,
850
+
&xm_qdss_etr1, &qns_gemnoc_gc
851
+
},
852
+
};
853
+
854
+
static struct qcom_icc_bcm bcm_sn2 = {
855
+
.name = "SN2",
856
+
.num_nodes = 5,
857
+
.nodes = { &qnm_aggre_noc, &qxm_ecpri_gsi,
858
+
&xm_ecpri_dma, &qns_anoc_snoc_gsi,
859
+
&qns_ecpri_gemnoc
860
+
},
861
+
};
862
+
863
+
static struct qcom_icc_bcm bcm_sn7 = {
864
+
.name = "SN7",
865
+
.num_nodes = 2,
866
+
.nodes = { &qns_pcie_gemnoc, &xs_pcie },
867
+
};
868
+
869
+
static struct qcom_icc_bcm * const clk_virt_bcms[] = {
870
+
&bcm_qup0,
871
+
};
872
+
873
+
static struct qcom_icc_node * const clk_virt_nodes[] = {
874
+
[MASTER_QUP_CORE_0] = &qup0_core_master,
875
+
[MASTER_QUP_CORE_1] = &qup1_core_master,
876
+
[SLAVE_QUP_CORE_0] = &qup0_core_slave,
877
+
[SLAVE_QUP_CORE_1] = &qup1_core_slave,
878
+
};
879
+
880
+
static const struct qcom_icc_desc qdu1000_clk_virt = {
881
+
.nodes = clk_virt_nodes,
882
+
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
883
+
.bcms = clk_virt_bcms,
884
+
.num_bcms = ARRAY_SIZE(clk_virt_bcms),
885
+
};
886
+
887
+
static struct qcom_icc_bcm * const gem_noc_bcms[] = {
888
+
&bcm_sh0,
889
+
&bcm_sh1,
890
+
};
891
+
892
+
static struct qcom_icc_node * const gem_noc_nodes[] = {
893
+
[MASTER_SYS_TCU] = &alm_sys_tcu,
894
+
[MASTER_APPSS_PROC] = &chm_apps,
895
+
[MASTER_GEMNOC_ECPRI_DMA] = &qnm_ecpri_dma,
896
+
[MASTER_FEC_2_GEMNOC] = &qnm_fec_2_gemnoc,
897
+
[MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
898
+
[MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
899
+
[MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
900
+
[MASTER_MSS_PROC] = &qxm_mdsp,
901
+
[SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
902
+
[SLAVE_LLCC] = &qns_llcc,
903
+
[SLAVE_GEMNOC_MODEM_CNOC] = &qns_modem_slave,
904
+
[SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
905
+
};
906
+
907
+
static const struct qcom_icc_desc qdu1000_gem_noc = {
908
+
.nodes = gem_noc_nodes,
909
+
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
910
+
.bcms = gem_noc_bcms,
911
+
.num_bcms = ARRAY_SIZE(gem_noc_bcms),
912
+
};
913
+
914
+
static struct qcom_icc_bcm * const mc_virt_bcms[] = {
915
+
&bcm_acv,
916
+
&bcm_mc0,
917
+
};
918
+
919
+
static struct qcom_icc_node * const mc_virt_nodes[] = {
920
+
[MASTER_LLCC] = &llcc_mc,
921
+
[SLAVE_EBI1] = &ebi,
922
+
};
923
+
924
+
static const struct qcom_icc_desc qdu1000_mc_virt = {
925
+
.nodes = mc_virt_nodes,
926
+
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
927
+
.bcms = mc_virt_bcms,
928
+
.num_bcms = ARRAY_SIZE(mc_virt_bcms),
929
+
};
930
+
931
+
static struct qcom_icc_bcm * const system_noc_bcms[] = {
932
+
&bcm_ce0,
933
+
&bcm_cn0,
934
+
&bcm_sn0,
935
+
&bcm_sn1,
936
+
&bcm_sn2,
937
+
&bcm_sn7,
938
+
};
939
+
940
+
static struct qcom_icc_node * const system_noc_nodes[] = {
941
+
[MASTER_GIC_AHB] = &qhm_gic,
942
+
[MASTER_QDSS_BAM] = &qhm_qdss_bam,
943
+
[MASTER_QPIC] = &qhm_qpic,
944
+
[MASTER_QSPI_0] = &qhm_qspi,
945
+
[MASTER_QUP_0] = &qhm_qup0,
946
+
[MASTER_QUP_1] = &qhm_qup1,
947
+
[MASTER_SNOC_CFG] = &qhm_system_noc_cfg,
948
+
[MASTER_ANOC_SNOC] = &qnm_aggre_noc,
949
+
[MASTER_ANOC_GSI] = &qnm_aggre_noc_gsi,
950
+
[MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
951
+
[MASTER_GEMNOC_MODEM_CNOC] = &qnm_gemnoc_modem_slave,
952
+
[MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
953
+
[MASTER_CRYPTO] = &qxm_crypto,
954
+
[MASTER_ECPRI_GSI] = &qxm_ecpri_gsi,
955
+
[MASTER_PIMEM] = &qxm_pimem,
956
+
[MASTER_SNOC_ECPRI_DMA] = &xm_ecpri_dma,
957
+
[MASTER_GIC] = &xm_gic,
958
+
[MASTER_PCIE] = &xm_pcie,
959
+
[MASTER_QDSS_ETR] = &xm_qdss_etr0,
960
+
[MASTER_QDSS_ETR_1] = &xm_qdss_etr1,
961
+
[MASTER_SDCC_1] = &xm_sdc,
962
+
[MASTER_USB3] = &xm_usb3,
963
+
[SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0_south,
964
+
[SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1_north,
965
+
[SLAVE_AHB2PHY_EAST] = &qhs_ahb2phy2_east,
966
+
[SLAVE_AOSS] = &qhs_aoss,
967
+
[SLAVE_CLK_CTL] = &qhs_clk_ctl,
968
+
[SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
969
+
[SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
970
+
[SLAVE_CRYPTO_0_CFG] = &qhs_crypto_cfg,
971
+
[SLAVE_ECPRI_CFG] = &qhs_ecpri_cfg,
972
+
[SLAVE_IMEM_CFG] = &qhs_imem_cfg,
973
+
[SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
974
+
[SLAVE_CNOC_MSS] = &qhs_mss_cfg,
975
+
[SLAVE_PCIE_CFG] = &qhs_pcie_cfg,
976
+
[SLAVE_PDM] = &qhs_pdm,
977
+
[SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
978
+
[SLAVE_PRNG] = &qhs_prng,
979
+
[SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
980
+
[SLAVE_QPIC] = &qhs_qpic,
981
+
[SLAVE_QSPI_0] = &qhs_qspi,
982
+
[SLAVE_QUP_0] = &qhs_qup0,
983
+
[SLAVE_QUP_1] = &qhs_qup1,
984
+
[SLAVE_SDCC_2] = &qhs_sdc2,
985
+
[SLAVE_SMBUS_CFG] = &qhs_smbus_cfg,
986
+
[SLAVE_SNOC_CFG] = &qhs_system_noc_cfg,
987
+
[SLAVE_TCSR] = &qhs_tcsr,
988
+
[SLAVE_TLMM] = &qhs_tlmm,
989
+
[SLAVE_TME_CFG] = &qhs_tme_cfg,
990
+
[SLAVE_TSC_CFG] = &qhs_tsc_cfg,
991
+
[SLAVE_USB3_0] = &qhs_usb3,
992
+
[SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
993
+
[SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
994
+
[SLAVE_ANOC_SNOC_GSI] = &qns_anoc_snoc_gsi,
995
+
[SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
996
+
[SLAVE_ECPRI_GEMNOC] = &qns_ecpri_gemnoc,
997
+
[SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
998
+
[SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
999
+
[SLAVE_MODEM_OFFLINE] = &qns_modem,
1000
+
[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_gemnoc,
1001
+
[SLAVE_IMEM] = &qxs_imem,
1002
+
[SLAVE_PIMEM] = &qxs_pimem,
1003
+
[SLAVE_SERVICE_SNOC] = &srvc_system_noc,
1004
+
[SLAVE_ETHERNET_SS] = &xs_ethernet_ss,
1005
+
[SLAVE_PCIE_0] = &xs_pcie,
1006
+
[SLAVE_QDSS_STM] = &xs_qdss_stm,
1007
+
[SLAVE_TCU] = &xs_sys_tcu_cfg,
1008
+
};
1009
+
1010
+
static const struct qcom_icc_desc qdu1000_system_noc = {
1011
+
.nodes = system_noc_nodes,
1012
+
.num_nodes = ARRAY_SIZE(system_noc_nodes),
1013
+
.bcms = system_noc_bcms,
1014
+
.num_bcms = ARRAY_SIZE(system_noc_bcms),
1015
+
};
1016
+
1017
+
static int qnoc_probe(struct platform_device *pdev)
1018
+
{
1019
+
int ret;
1020
+
1021
+
ret = qcom_icc_rpmh_probe(pdev);
1022
+
if (ret)
1023
+
dev_err(&pdev->dev, "failed to register ICC provider\n");
1024
+
1025
+
return ret;
1026
+
}
1027
+
1028
+
static const struct of_device_id qnoc_of_match[] = {
1029
+
{ .compatible = "qcom,qdu1000-clk-virt",
1030
+
.data = &qdu1000_clk_virt
1031
+
},
1032
+
{ .compatible = "qcom,qdu1000-gem-noc",
1033
+
.data = &qdu1000_gem_noc
1034
+
},
1035
+
{ .compatible = "qcom,qdu1000-mc-virt",
1036
+
.data = &qdu1000_mc_virt
1037
+
},
1038
+
{ .compatible = "qcom,qdu1000-system-noc",
1039
+
.data = &qdu1000_system_noc
1040
+
},
1041
+
{ }
1042
+
};
1043
+
MODULE_DEVICE_TABLE(of, qnoc_of_match);
1044
+
1045
+
static struct platform_driver qnoc_driver = {
1046
+
.probe = qnoc_probe,
1047
+
.remove = qcom_icc_rpmh_remove,
1048
+
.driver = {
1049
+
.name = "qnoc-qdu1000",
1050
+
.of_match_table = qnoc_of_match,
1051
+
},
1052
+
};
1053
+
1054
+
static int __init qnoc_driver_init(void)
1055
+
{
1056
+
return platform_driver_register(&qnoc_driver);
1057
+
}
1058
+
core_initcall(qnoc_driver_init);
1059
+
1060
+
static void __exit qnoc_driver_exit(void)
1061
+
{
1062
+
platform_driver_unregister(&qnoc_driver);
1063
+
}
1064
+
module_exit(qnoc_driver_exit);
1065
+
1066
+
MODULE_DESCRIPTION("QDU1000 NoC driver");
1067
+
MODULE_LICENSE("GPL");
+95
drivers/interconnect/qcom/qdu1000.h
+95
drivers/interconnect/qcom/qdu1000.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#ifndef __DRIVERS_INTERCONNECT_QCOM_QDU1000_H
7
+
#define __DRIVERS_INTERCONNECT_QCOM_QDU1000_H
8
+
9
+
#define QDU1000_MASTER_SYS_TCU 0
10
+
#define QDU1000_MASTER_APPSS_PROC 1
11
+
#define QDU1000_MASTER_LLCC 2
12
+
#define QDU1000_MASTER_GIC_AHB 3
13
+
#define QDU1000_MASTER_QDSS_BAM 4
14
+
#define QDU1000_MASTER_QPIC 5
15
+
#define QDU1000_MASTER_QSPI_0 6
16
+
#define QDU1000_MASTER_QUP_0 7
17
+
#define QDU1000_MASTER_QUP_1 8
18
+
#define QDU1000_MASTER_SNOC_CFG 9
19
+
#define QDU1000_MASTER_ANOC_SNOC 10
20
+
#define QDU1000_MASTER_ANOC_GSI 11
21
+
#define QDU1000_MASTER_GEMNOC_ECPRI_DMA 12
22
+
#define QDU1000_MASTER_FEC_2_GEMNOC 13
23
+
#define QDU1000_MASTER_GEM_NOC_CNOC 14
24
+
#define QDU1000_MASTER_GEMNOC_MODEM_CNOC 15
25
+
#define QDU1000_MASTER_GEM_NOC_PCIE_SNOC 16
26
+
#define QDU1000_MASTER_ANOC_PCIE_GEM_NOC 17
27
+
#define QDU1000_MASTER_SNOC_GC_MEM_NOC 18
28
+
#define QDU1000_MASTER_SNOC_SF_MEM_NOC 19
29
+
#define QDU1000_MASTER_QUP_CORE_0 20
30
+
#define QDU1000_MASTER_QUP_CORE_1 21
31
+
#define QDU1000_MASTER_CRYPTO 22
32
+
#define QDU1000_MASTER_ECPRI_GSI 23
33
+
#define QDU1000_MASTER_MSS_PROC 24
34
+
#define QDU1000_MASTER_PIMEM 25
35
+
#define QDU1000_MASTER_SNOC_ECPRI_DMA 26
36
+
#define QDU1000_MASTER_GIC 27
37
+
#define QDU1000_MASTER_PCIE 28
38
+
#define QDU1000_MASTER_QDSS_ETR 29
39
+
#define QDU1000_MASTER_QDSS_ETR_1 30
40
+
#define QDU1000_MASTER_SDCC_1 31
41
+
#define QDU1000_MASTER_USB3 32
42
+
#define QDU1000_SLAVE_EBI1 512
43
+
#define QDU1000_SLAVE_AHB2PHY_SOUTH 513
44
+
#define QDU1000_SLAVE_AHB2PHY_NORTH 514
45
+
#define QDU1000_SLAVE_AHB2PHY_EAST 515
46
+
#define QDU1000_SLAVE_AOSS 516
47
+
#define QDU1000_SLAVE_CLK_CTL 517
48
+
#define QDU1000_SLAVE_RBCPR_CX_CFG 518
49
+
#define QDU1000_SLAVE_RBCPR_MX_CFG 519
50
+
#define QDU1000_SLAVE_CRYPTO_0_CFG 520
51
+
#define QDU1000_SLAVE_ECPRI_CFG 521
52
+
#define QDU1000_SLAVE_IMEM_CFG 522
53
+
#define QDU1000_SLAVE_IPC_ROUTER_CFG 523
54
+
#define QDU1000_SLAVE_CNOC_MSS 524
55
+
#define QDU1000_SLAVE_PCIE_CFG 525
56
+
#define QDU1000_SLAVE_PDM 526
57
+
#define QDU1000_SLAVE_PIMEM_CFG 527
58
+
#define QDU1000_SLAVE_PRNG 528
59
+
#define QDU1000_SLAVE_QDSS_CFG 529
60
+
#define QDU1000_SLAVE_QPIC 530
61
+
#define QDU1000_SLAVE_QSPI_0 531
62
+
#define QDU1000_SLAVE_QUP_0 532
63
+
#define QDU1000_SLAVE_QUP_1 533
64
+
#define QDU1000_SLAVE_SDCC_2 534
65
+
#define QDU1000_SLAVE_SMBUS_CFG 535
66
+
#define QDU1000_SLAVE_SNOC_CFG 536
67
+
#define QDU1000_SLAVE_TCSR 537
68
+
#define QDU1000_SLAVE_TLMM 538
69
+
#define QDU1000_SLAVE_TME_CFG 539
70
+
#define QDU1000_SLAVE_TSC_CFG 540
71
+
#define QDU1000_SLAVE_USB3_0 541
72
+
#define QDU1000_SLAVE_VSENSE_CTRL_CFG 542
73
+
#define QDU1000_SLAVE_A1NOC_SNOC 543
74
+
#define QDU1000_SLAVE_ANOC_SNOC_GSI 544
75
+
#define QDU1000_SLAVE_DDRSS_CFG 545
76
+
#define QDU1000_SLAVE_ECPRI_GEMNOC 546
77
+
#define QDU1000_SLAVE_GEM_NOC_CNOC 547
78
+
#define QDU1000_SLAVE_SNOC_GEM_NOC_GC 548
79
+
#define QDU1000_SLAVE_SNOC_GEM_NOC_SF 549
80
+
#define QDU1000_SLAVE_LLCC 550
81
+
#define QDU1000_SLAVE_MODEM_OFFLINE 551
82
+
#define QDU1000_SLAVE_GEMNOC_MODEM_CNOC 552
83
+
#define QDU1000_SLAVE_MEM_NOC_PCIE_SNOC 553
84
+
#define QDU1000_SLAVE_ANOC_PCIE_GEM_NOC 554
85
+
#define QDU1000_SLAVE_QUP_CORE_0 555
86
+
#define QDU1000_SLAVE_QUP_CORE_1 556
87
+
#define QDU1000_SLAVE_IMEM 557
88
+
#define QDU1000_SLAVE_PIMEM 558
89
+
#define QDU1000_SLAVE_SERVICE_SNOC 559
90
+
#define QDU1000_SLAVE_ETHERNET_SS 560
91
+
#define QDU1000_SLAVE_PCIE_0 561
92
+
#define QDU1000_SLAVE_QDSS_STM 562
93
+
#define QDU1000_SLAVE_TCU 563
94
+
95
+
#endif
+98
include/dt-bindings/interconnect/qcom,qdu1000-rpmh.h
+98
include/dt-bindings/interconnect/qcom,qdu1000-rpmh.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
2
+
/*
3
+
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_QDU1000_H
7
+
#define __DT_BINDINGS_INTERCONNECT_QCOM_QDU1000_H
8
+
9
+
#define MASTER_QUP_CORE_0 0
10
+
#define MASTER_QUP_CORE_1 1
11
+
#define SLAVE_QUP_CORE_0 2
12
+
#define SLAVE_QUP_CORE_1 3
13
+
14
+
#define MASTER_SYS_TCU 0
15
+
#define MASTER_APPSS_PROC 1
16
+
#define MASTER_GEMNOC_ECPRI_DMA 2
17
+
#define MASTER_FEC_2_GEMNOC 3
18
+
#define MASTER_ANOC_PCIE_GEM_NOC 4
19
+
#define MASTER_SNOC_GC_MEM_NOC 5
20
+
#define MASTER_SNOC_SF_MEM_NOC 6
21
+
#define MASTER_MSS_PROC 7
22
+
#define SLAVE_GEM_NOC_CNOC 8
23
+
#define SLAVE_LLCC 9
24
+
#define SLAVE_GEMNOC_MODEM_CNOC 10
25
+
#define SLAVE_MEM_NOC_PCIE_SNOC 11
26
+
27
+
#define MASTER_LLCC 0
28
+
#define SLAVE_EBI1 1
29
+
30
+
#define MASTER_GIC_AHB 0
31
+
#define MASTER_QDSS_BAM 1
32
+
#define MASTER_QPIC 2
33
+
#define MASTER_QSPI_0 3
34
+
#define MASTER_QUP_0 4
35
+
#define MASTER_QUP_1 5
36
+
#define MASTER_SNOC_CFG 6
37
+
#define MASTER_ANOC_SNOC 7
38
+
#define MASTER_ANOC_GSI 8
39
+
#define MASTER_GEM_NOC_CNOC 9
40
+
#define MASTER_GEMNOC_MODEM_CNOC 10
41
+
#define MASTER_GEM_NOC_PCIE_SNOC 11
42
+
#define MASTER_CRYPTO 12
43
+
#define MASTER_ECPRI_GSI 13
44
+
#define MASTER_PIMEM 14
45
+
#define MASTER_SNOC_ECPRI_DMA 15
46
+
#define MASTER_GIC 16
47
+
#define MASTER_PCIE 17
48
+
#define MASTER_QDSS_ETR 18
49
+
#define MASTER_QDSS_ETR_1 19
50
+
#define MASTER_SDCC_1 20
51
+
#define MASTER_USB3 21
52
+
#define SLAVE_AHB2PHY_SOUTH 22
53
+
#define SLAVE_AHB2PHY_NORTH 23
54
+
#define SLAVE_AHB2PHY_EAST 24
55
+
#define SLAVE_AOSS 25
56
+
#define SLAVE_CLK_CTL 26
57
+
#define SLAVE_RBCPR_CX_CFG 27
58
+
#define SLAVE_RBCPR_MX_CFG 28
59
+
#define SLAVE_CRYPTO_0_CFG 29
60
+
#define SLAVE_ECPRI_CFG 30
61
+
#define SLAVE_IMEM_CFG 31
62
+
#define SLAVE_IPC_ROUTER_CFG 32
63
+
#define SLAVE_CNOC_MSS 33
64
+
#define SLAVE_PCIE_CFG 34
65
+
#define SLAVE_PDM 35
66
+
#define SLAVE_PIMEM_CFG 36
67
+
#define SLAVE_PRNG 37
68
+
#define SLAVE_QDSS_CFG 38
69
+
#define SLAVE_QPIC 40
70
+
#define SLAVE_QSPI_0 41
71
+
#define SLAVE_QUP_0 42
72
+
#define SLAVE_QUP_1 43
73
+
#define SLAVE_SDCC_2 44
74
+
#define SLAVE_SMBUS_CFG 45
75
+
#define SLAVE_SNOC_CFG 46
76
+
#define SLAVE_TCSR 47
77
+
#define SLAVE_TLMM 48
78
+
#define SLAVE_TME_CFG 49
79
+
#define SLAVE_TSC_CFG 50
80
+
#define SLAVE_USB3_0 51
81
+
#define SLAVE_VSENSE_CTRL_CFG 52
82
+
#define SLAVE_A1NOC_SNOC 53
83
+
#define SLAVE_ANOC_SNOC_GSI 54
84
+
#define SLAVE_DDRSS_CFG 55
85
+
#define SLAVE_ECPRI_GEMNOC 56
86
+
#define SLAVE_SNOC_GEM_NOC_GC 57
87
+
#define SLAVE_SNOC_GEM_NOC_SF 58
88
+
#define SLAVE_MODEM_OFFLINE 59
89
+
#define SLAVE_ANOC_PCIE_GEM_NOC 60
90
+
#define SLAVE_IMEM 61
91
+
#define SLAVE_PIMEM 62
92
+
#define SLAVE_SERVICE_SNOC 63
93
+
#define SLAVE_ETHERNET_SS 64
94
+
#define SLAVE_PCIE_0 65
95
+
#define SLAVE_QDSS_STM 66
96
+
#define SLAVE_TCU 67
97
+
98
+
#endif