Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
mfd: cs42l43: Add support for cs42l43 core driver
The CS42L43 is an audio CODEC with integrated MIPI SoundWire interface
(Version 1.2.1 compliant), I2C, SPI, and I2S/TDM interfaces designed
for portable applications. It provides a high dynamic range, stereo
DAC for headphone output, two integrated Class D amplifiers for
loudspeakers, and two ADCs for wired headset microphone input or
stereo line input. PDM inputs are provided for digital microphones.
The MFD component registers and initialises the device and provides
PM/system power management.
Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20230804104602.395892-4-ckeepax@opensource.cirrus.com
Signed-off-by: Lee Jones <lee@kernel.org>
authored by
Charles Keepax
and committed by
Lee Jones
ace6d144
ec77cad8
+2867
+2
MAINTAINERS
+2
MAINTAINERS
···
4879
4879
L: patches@opensource.cirrus.com
4880
4880
S: Maintained
4881
4881
F: Documentation/devicetree/bindings/sound/cirrus,cs*
4882
+
F: drivers/mfd/cs42l43*
4882
4883
F: include/dt-bindings/sound/cs*
4884
+
F: include/linux/mfd/cs42l43*
4883
4885
F: include/sound/cs*
4884
4886
F: sound/pci/hda/cs*
4885
4887
F: sound/pci/hda/hda_cs_dsp_ctl.*
+23
drivers/mfd/Kconfig
+23
drivers/mfd/Kconfig
···
237
237
To compile this driver as a module, choose M here: the module will be
238
238
called cros-ec-dev.
239
239
240
+
config MFD_CS42L43
241
+
tristate
242
+
select MFD_CORE
243
+
select REGMAP
244
+
245
+
config MFD_CS42L43_I2C
246
+
tristate "Cirrus Logic CS42L43 (I2C)"
247
+
depends on I2C
248
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select REGMAP_I2C
249
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select MFD_CS42L43
250
+
help
251
+
Select this to support the Cirrus Logic CS42L43 PC CODEC with
252
+
headphone and class D speaker drivers over I2C.
253
+
254
+
config MFD_CS42L43_SDW
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tristate "Cirrus Logic CS42L43 (SoundWire)"
256
+
depends on SOUNDWIRE
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select REGMAP_SOUNDWIRE
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select MFD_CS42L43
259
+
help
260
+
Select this to support the Cirrus Logic CS42L43 PC CODEC with
261
+
headphone and class D speaker drivers over SoundWire.
262
+
240
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config MFD_MADERA
241
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tristate "Cirrus Logic Madera codecs"
242
265
select MFD_CORE
+3
drivers/mfd/Makefile
+3
drivers/mfd/Makefile
···
13
13
obj-$(CONFIG_MFD_BCM590XX) += bcm590xx.o
14
14
obj-$(CONFIG_MFD_BD9571MWV) += bd9571mwv.o
15
15
obj-$(CONFIG_MFD_CROS_EC_DEV) += cros_ec_dev.o
16
+
obj-$(CONFIG_MFD_CS42L43) += cs42l43.o
17
+
obj-$(CONFIG_MFD_CS42L43_I2C) += cs42l43-i2c.o
18
+
obj-$(CONFIG_MFD_CS42L43_SDW) += cs42l43-sdw.o
16
19
obj-$(CONFIG_MFD_ENE_KB3930) += ene-kb3930.o
17
20
obj-$(CONFIG_MFD_EXYNOS_LPASS) += exynos-lpass.o
18
21
obj-$(CONFIG_MFD_GATEWORKS_GSC) += gateworks-gsc.o
+98
drivers/mfd/cs42l43-i2c.c
+98
drivers/mfd/cs42l43-i2c.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* CS42L43 I2C driver
4
+
*
5
+
* Copyright (C) 2022-2023 Cirrus Logic, Inc. and
6
+
* Cirrus Logic International Semiconductor Ltd.
7
+
*/
8
+
9
+
#include <linux/err.h>
10
+
#include <linux/errno.h>
11
+
#include <linux/i2c.h>
12
+
#include <linux/mfd/cs42l43-regs.h>
13
+
#include <linux/module.h>
14
+
15
+
#include "cs42l43.h"
16
+
17
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static const struct regmap_config cs42l43_i2c_regmap = {
18
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.reg_bits = 32,
19
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.reg_stride = 4,
20
+
.val_bits = 32,
21
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.reg_format_endian = REGMAP_ENDIAN_BIG,
22
+
.val_format_endian = REGMAP_ENDIAN_BIG,
23
+
24
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.max_register = CS42L43_MCU_RAM_MAX,
25
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.readable_reg = cs42l43_readable_register,
26
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.volatile_reg = cs42l43_volatile_register,
27
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.precious_reg = cs42l43_precious_register,
28
+
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.cache_type = REGCACHE_MAPLE,
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.reg_defaults = cs42l43_reg_default,
31
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.num_reg_defaults = ARRAY_SIZE(cs42l43_reg_default),
32
+
};
33
+
34
+
static int cs42l43_i2c_probe(struct i2c_client *i2c)
35
+
{
36
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struct cs42l43 *cs42l43;
37
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int ret;
38
+
39
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cs42l43 = devm_kzalloc(&i2c->dev, sizeof(*cs42l43), GFP_KERNEL);
40
+
if (!cs42l43)
41
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return -ENOMEM;
42
+
43
+
cs42l43->dev = &i2c->dev;
44
+
cs42l43->irq = i2c->irq;
45
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/* A device on an I2C is always attached by definition. */
46
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cs42l43->attached = true;
47
+
48
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cs42l43->regmap = devm_regmap_init_i2c(i2c, &cs42l43_i2c_regmap);
49
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if (IS_ERR(cs42l43->regmap)) {
50
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ret = PTR_ERR(cs42l43->regmap);
51
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dev_err(cs42l43->dev, "Failed to allocate regmap: %d\n", ret);
52
+
return ret;
53
+
}
54
+
55
+
return cs42l43_dev_probe(cs42l43);
56
+
}
57
+
58
+
static void cs42l43_i2c_remove(struct i2c_client *i2c)
59
+
{
60
+
struct cs42l43 *cs42l43 = dev_get_drvdata(&i2c->dev);
61
+
62
+
cs42l43_dev_remove(cs42l43);
63
+
}
64
+
65
+
#if IS_ENABLED(CONFIG_OF)
66
+
static const struct of_device_id cs42l43_of_match[] = {
67
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{ .compatible = "cirrus,cs42l43", },
68
+
{}
69
+
};
70
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MODULE_DEVICE_TABLE(of, cs42l43_of_match);
71
+
#endif
72
+
73
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#if IS_ENABLED(CONFIG_ACPI)
74
+
static const struct acpi_device_id cs42l43_acpi_match[] = {
75
+
{ "CSC4243", 0 },
76
+
{}
77
+
};
78
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MODULE_DEVICE_TABLE(acpi, cs42l43_acpi_match);
79
+
#endif
80
+
81
+
static struct i2c_driver cs42l43_i2c_driver = {
82
+
.driver = {
83
+
.name = "cs42l43",
84
+
.pm = pm_ptr(&cs42l43_pm_ops),
85
+
.of_match_table = of_match_ptr(cs42l43_of_match),
86
+
.acpi_match_table = ACPI_PTR(cs42l43_acpi_match),
87
+
},
88
+
89
+
.probe = cs42l43_i2c_probe,
90
+
.remove = cs42l43_i2c_remove,
91
+
};
92
+
module_i2c_driver(cs42l43_i2c_driver);
93
+
94
+
MODULE_IMPORT_NS(MFD_CS42L43);
95
+
96
+
MODULE_DESCRIPTION("CS42L43 I2C Driver");
97
+
MODULE_AUTHOR("Charles Keepax <ckeepax@opensource.cirrus.com>");
98
+
MODULE_LICENSE("GPL");
+239
drivers/mfd/cs42l43-sdw.c
+239
drivers/mfd/cs42l43-sdw.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* CS42L43 SoundWire driver
4
+
*
5
+
* Copyright (C) 2022-2023 Cirrus Logic, Inc. and
6
+
* Cirrus Logic International Semiconductor Ltd.
7
+
*/
8
+
9
+
#include <linux/err.h>
10
+
#include <linux/errno.h>
11
+
#include <linux/mfd/cs42l43-regs.h>
12
+
#include <linux/module.h>
13
+
#include <linux/device.h>
14
+
#include <linux/soundwire/sdw.h>
15
+
#include <linux/soundwire/sdw_registers.h>
16
+
#include <linux/soundwire/sdw_type.h>
17
+
18
+
#include "cs42l43.h"
19
+
20
+
enum cs42l43_sdw_ports {
21
+
CS42L43_DMIC_DEC_ASP_PORT = 1,
22
+
CS42L43_SPK_TX_PORT,
23
+
CS42L43_SPDIF_HP_PORT,
24
+
CS42L43_SPK_RX_PORT,
25
+
CS42L43_ASP_PORT,
26
+
};
27
+
28
+
static const struct regmap_config cs42l43_sdw_regmap = {
29
+
.reg_bits = 32,
30
+
.reg_stride = 4,
31
+
.val_bits = 32,
32
+
.reg_format_endian = REGMAP_ENDIAN_LITTLE,
33
+
.val_format_endian = REGMAP_ENDIAN_LITTLE,
34
+
35
+
.max_register = CS42L43_MCU_RAM_MAX,
36
+
.readable_reg = cs42l43_readable_register,
37
+
.volatile_reg = cs42l43_volatile_register,
38
+
.precious_reg = cs42l43_precious_register,
39
+
40
+
.cache_type = REGCACHE_MAPLE,
41
+
.reg_defaults = cs42l43_reg_default,
42
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.num_reg_defaults = ARRAY_SIZE(cs42l43_reg_default),
43
+
};
44
+
45
+
static int cs42l43_read_prop(struct sdw_slave *sdw)
46
+
{
47
+
struct sdw_slave_prop *prop = &sdw->prop;
48
+
struct device *dev = &sdw->dev;
49
+
struct sdw_dpn_prop *dpn;
50
+
unsigned long addr;
51
+
int nval;
52
+
int i;
53
+
u32 bit;
54
+
55
+
prop->use_domain_irq = true;
56
+
prop->paging_support = true;
57
+
prop->wake_capable = true;
58
+
prop->source_ports = BIT(CS42L43_DMIC_DEC_ASP_PORT) | BIT(CS42L43_SPK_TX_PORT);
59
+
prop->sink_ports = BIT(CS42L43_SPDIF_HP_PORT) |
60
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BIT(CS42L43_SPK_RX_PORT) | BIT(CS42L43_ASP_PORT);
61
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prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
62
+
prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY |
63
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SDW_SCP_INT1_IMPL_DEF;
64
+
65
+
nval = hweight32(prop->source_ports);
66
+
prop->src_dpn_prop = devm_kcalloc(dev, nval, sizeof(*prop->src_dpn_prop),
67
+
GFP_KERNEL);
68
+
if (!prop->src_dpn_prop)
69
+
return -ENOMEM;
70
+
71
+
i = 0;
72
+
dpn = prop->src_dpn_prop;
73
+
addr = prop->source_ports;
74
+
for_each_set_bit(bit, &addr, 32) {
75
+
dpn[i].num = bit;
76
+
dpn[i].max_ch = 2;
77
+
dpn[i].type = SDW_DPN_FULL;
78
+
dpn[i].max_word = 24;
79
+
i++;
80
+
}
81
+
/*
82
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* All ports are 2 channels max, except the first one,
83
+
* CS42L43_DMIC_DEC_ASP_PORT.
84
+
*/
85
+
dpn[CS42L43_DMIC_DEC_ASP_PORT].max_ch = 4;
86
+
87
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nval = hweight32(prop->sink_ports);
88
+
prop->sink_dpn_prop = devm_kcalloc(dev, nval, sizeof(*prop->sink_dpn_prop),
89
+
GFP_KERNEL);
90
+
if (!prop->sink_dpn_prop)
91
+
return -ENOMEM;
92
+
93
+
i = 0;
94
+
dpn = prop->sink_dpn_prop;
95
+
addr = prop->sink_ports;
96
+
for_each_set_bit(bit, &addr, 32) {
97
+
dpn[i].num = bit;
98
+
dpn[i].max_ch = 2;
99
+
dpn[i].type = SDW_DPN_FULL;
100
+
dpn[i].max_word = 24;
101
+
i++;
102
+
}
103
+
104
+
return 0;
105
+
}
106
+
107
+
static int cs42l43_sdw_update_status(struct sdw_slave *sdw, enum sdw_slave_status status)
108
+
{
109
+
struct cs42l43 *cs42l43 = dev_get_drvdata(&sdw->dev);
110
+
111
+
switch (status) {
112
+
case SDW_SLAVE_ATTACHED:
113
+
dev_dbg(cs42l43->dev, "Device attach\n");
114
+
115
+
sdw_write_no_pm(sdw, CS42L43_GEN_INT_MASK_1,
116
+
CS42L43_INT_STAT_GEN1_MASK);
117
+
118
+
cs42l43->attached = true;
119
+
120
+
complete(&cs42l43->device_attach);
121
+
break;
122
+
case SDW_SLAVE_UNATTACHED:
123
+
dev_dbg(cs42l43->dev, "Device detach\n");
124
+
125
+
cs42l43->attached = false;
126
+
127
+
reinit_completion(&cs42l43->device_attach);
128
+
complete(&cs42l43->device_detach);
129
+
break;
130
+
default:
131
+
break;
132
+
}
133
+
134
+
return 0;
135
+
}
136
+
137
+
static int cs42l43_sdw_interrupt(struct sdw_slave *sdw,
138
+
struct sdw_slave_intr_status *status)
139
+
{
140
+
/*
141
+
* The IRQ itself was handled through the regmap_irq handler, this is
142
+
* just clearing up the additional Cirrus SoundWire registers that are
143
+
* not covered by the SoundWire framework or the IRQ handler itself.
144
+
* There is only a single bit in GEN_INT_STAT_1 and it doesn't clear if
145
+
* IRQs are still pending so doing a read/write here after handling the
146
+
* IRQ is fine.
147
+
*/
148
+
sdw_read_no_pm(sdw, CS42L43_GEN_INT_STAT_1);
149
+
sdw_write_no_pm(sdw, CS42L43_GEN_INT_STAT_1, CS42L43_INT_STAT_GEN1_MASK);
150
+
151
+
return 0;
152
+
}
153
+
154
+
static int cs42l43_sdw_bus_config(struct sdw_slave *sdw,
155
+
struct sdw_bus_params *params)
156
+
{
157
+
struct cs42l43 *cs42l43 = dev_get_drvdata(&sdw->dev);
158
+
int ret = 0;
159
+
160
+
mutex_lock(&cs42l43->pll_lock);
161
+
162
+
if (cs42l43->sdw_freq != params->curr_dr_freq / 2) {
163
+
if (cs42l43->sdw_pll_active) {
164
+
dev_err(cs42l43->dev,
165
+
"PLL active can't change SoundWire bus clock\n");
166
+
ret = -EBUSY;
167
+
} else {
168
+
cs42l43->sdw_freq = params->curr_dr_freq / 2;
169
+
}
170
+
}
171
+
172
+
mutex_unlock(&cs42l43->pll_lock);
173
+
174
+
return ret;
175
+
}
176
+
177
+
static const struct sdw_slave_ops cs42l43_sdw_ops = {
178
+
.read_prop = cs42l43_read_prop,
179
+
.update_status = cs42l43_sdw_update_status,
180
+
.interrupt_callback = cs42l43_sdw_interrupt,
181
+
.bus_config = cs42l43_sdw_bus_config,
182
+
};
183
+
184
+
static int cs42l43_sdw_probe(struct sdw_slave *sdw, const struct sdw_device_id *id)
185
+
{
186
+
struct cs42l43 *cs42l43;
187
+
struct device *dev = &sdw->dev;
188
+
int ret;
189
+
190
+
cs42l43 = devm_kzalloc(dev, sizeof(*cs42l43), GFP_KERNEL);
191
+
if (!cs42l43)
192
+
return -ENOMEM;
193
+
194
+
cs42l43->dev = dev;
195
+
cs42l43->sdw = sdw;
196
+
197
+
cs42l43->regmap = devm_regmap_init_sdw(sdw, &cs42l43_sdw_regmap);
198
+
if (IS_ERR(cs42l43->regmap)) {
199
+
ret = PTR_ERR(cs42l43->regmap);
200
+
dev_err(cs42l43->dev, "Failed to allocate regmap: %d\n", ret);
201
+
return ret;
202
+
}
203
+
204
+
return cs42l43_dev_probe(cs42l43);
205
+
}
206
+
207
+
static int cs42l43_sdw_remove(struct sdw_slave *sdw)
208
+
{
209
+
struct cs42l43 *cs42l43 = dev_get_drvdata(&sdw->dev);
210
+
211
+
cs42l43_dev_remove(cs42l43);
212
+
213
+
return 0;
214
+
}
215
+
216
+
static const struct sdw_device_id cs42l43_sdw_id[] = {
217
+
SDW_SLAVE_ENTRY(0x01FA, 0x4243, 0),
218
+
{}
219
+
};
220
+
MODULE_DEVICE_TABLE(sdw, cs42l43_sdw_id);
221
+
222
+
static struct sdw_driver cs42l43_sdw_driver = {
223
+
.driver = {
224
+
.name = "cs42l43",
225
+
.pm = pm_ptr(&cs42l43_pm_ops),
226
+
},
227
+
228
+
.probe = cs42l43_sdw_probe,
229
+
.remove = cs42l43_sdw_remove,
230
+
.id_table = cs42l43_sdw_id,
231
+
.ops = &cs42l43_sdw_ops,
232
+
};
233
+
module_sdw_driver(cs42l43_sdw_driver);
234
+
235
+
MODULE_IMPORT_NS(MFD_CS42L43);
236
+
237
+
MODULE_DESCRIPTION("CS42L43 SoundWire Driver");
238
+
MODULE_AUTHOR("Lucas Tanure <tanureal@opensource.cirrus.com>");
239
+
MODULE_LICENSE("GPL");
+1188
drivers/mfd/cs42l43.c
+1188
drivers/mfd/cs42l43.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* CS42L43 core driver
4
+
*
5
+
* Copyright (C) 2022-2023 Cirrus Logic, Inc. and
6
+
* Cirrus Logic International Semiconductor Ltd.
7
+
*/
8
+
9
+
#include <linux/bitops.h>
10
+
#include <linux/build_bug.h>
11
+
#include <linux/delay.h>
12
+
#include <linux/err.h>
13
+
#include <linux/errno.h>
14
+
#include <linux/firmware.h>
15
+
#include <linux/jiffies.h>
16
+
#include <linux/mfd/core.h>
17
+
#include <linux/mfd/cs42l43-regs.h>
18
+
#include <linux/module.h>
19
+
#include <linux/pm_runtime.h>
20
+
#include <linux/soundwire/sdw.h>
21
+
22
+
#include "cs42l43.h"
23
+
24
+
#define CS42L43_RESET_DELAY 20
25
+
26
+
#define CS42L43_SDW_ATTACH_TIMEOUT 500
27
+
#define CS42L43_SDW_DETACH_TIMEOUT 100
28
+
29
+
#define CS42L43_MCU_BOOT_STAGE1 1
30
+
#define CS42L43_MCU_BOOT_STAGE2 2
31
+
#define CS42L43_MCU_BOOT_STAGE3 3
32
+
#define CS42L43_MCU_BOOT_STAGE4 4
33
+
#define CS42L43_MCU_POLL 5000
34
+
#define CS42L43_MCU_CMD_TIMEOUT 20000
35
+
#define CS42L43_MCU_UPDATE_FORMAT 3
36
+
#define CS42L43_MCU_UPDATE_OFFSET 0x100000
37
+
#define CS42L43_MCU_UPDATE_TIMEOUT 500000
38
+
#define CS42L43_MCU_UPDATE_RETRIES 5
39
+
40
+
#define CS42L43_MCU_SUPPORTED_REV 0x2105
41
+
#define CS42L43_MCU_SHADOW_REGS_REQUIRED_REV 0x2200
42
+
#define CS42L43_MCU_SUPPORTED_BIOS_REV 0x0001
43
+
44
+
#define CS42L43_VDDP_DELAY 50
45
+
#define CS42L43_VDDD_DELAY 1000
46
+
47
+
#define CS42L43_AUTOSUSPEND_TIME 250
48
+
49
+
struct cs42l43_patch_header {
50
+
__le16 version;
51
+
__le16 size;
52
+
u8 reserved;
53
+
u8 secure;
54
+
__le16 bss_size;
55
+
__le32 apply_addr;
56
+
__le32 checksum;
57
+
__le32 sha;
58
+
__le16 swrev;
59
+
__le16 patchid;
60
+
__le16 ipxid;
61
+
__le16 romver;
62
+
__le32 load_addr;
63
+
} __packed;
64
+
65
+
static const struct reg_sequence cs42l43_reva_patch[] = {
66
+
{ 0x4000, 0x00000055 },
67
+
{ 0x4000, 0x000000AA },
68
+
{ 0x10084, 0x00000000 },
69
+
{ 0x1741C, 0x00CD2000 },
70
+
{ 0x1718C, 0x00000003 },
71
+
{ 0x4000, 0x00000000 },
72
+
{ CS42L43_CCM_BLK_CLK_CONTROL, 0x00000002 },
73
+
{ CS42L43_HPPATHVOL, 0x011B011B },
74
+
{ CS42L43_OSC_DIV_SEL, 0x00000001 },
75
+
{ CS42L43_DACCNFG2, 0x00000005 },
76
+
{ CS42L43_MIC_DETECT_CONTROL_ANDROID, 0x80790079 },
77
+
{ CS42L43_RELID, 0x0000000F },
78
+
};
79
+
80
+
const struct reg_default cs42l43_reg_default[CS42L43_N_DEFAULTS] = {
81
+
{ CS42L43_DRV_CTRL1, 0x000186C0 },
82
+
{ CS42L43_DRV_CTRL3, 0x286DB018 },
83
+
{ CS42L43_DRV_CTRL4, 0x000006D8 },
84
+
{ CS42L43_DRV_CTRL_5, 0x136C00C0 },
85
+
{ CS42L43_GPIO_CTRL1, 0x00000707 },
86
+
{ CS42L43_GPIO_CTRL2, 0x00000000 },
87
+
{ CS42L43_GPIO_FN_SEL, 0x00000000 },
88
+
{ CS42L43_MCLK_SRC_SEL, 0x00000000 },
89
+
{ CS42L43_SAMPLE_RATE1, 0x00000003 },
90
+
{ CS42L43_SAMPLE_RATE2, 0x00000003 },
91
+
{ CS42L43_SAMPLE_RATE3, 0x00000003 },
92
+
{ CS42L43_SAMPLE_RATE4, 0x00000003 },
93
+
{ CS42L43_PLL_CONTROL, 0x00000000 },
94
+
{ CS42L43_FS_SELECT1, 0x00000000 },
95
+
{ CS42L43_FS_SELECT2, 0x00000000 },
96
+
{ CS42L43_FS_SELECT3, 0x00000000 },
97
+
{ CS42L43_FS_SELECT4, 0x00000000 },
98
+
{ CS42L43_PDM_CONTROL, 0x00000000 },
99
+
{ CS42L43_ASP_CLK_CONFIG1, 0x00010001 },
100
+
{ CS42L43_ASP_CLK_CONFIG2, 0x00000000 },
101
+
{ CS42L43_OSC_DIV_SEL, 0x00000001 },
102
+
{ CS42L43_ADC_B_CTRL1, 0x00000000 },
103
+
{ CS42L43_ADC_B_CTRL2, 0x00000000 },
104
+
{ CS42L43_DECIM_HPF_WNF_CTRL1, 0x00000001 },
105
+
{ CS42L43_DECIM_HPF_WNF_CTRL2, 0x00000001 },
106
+
{ CS42L43_DECIM_HPF_WNF_CTRL3, 0x00000001 },
107
+
{ CS42L43_DECIM_HPF_WNF_CTRL4, 0x00000001 },
108
+
{ CS42L43_DMIC_PDM_CTRL, 0x00000000 },
109
+
{ CS42L43_DECIM_VOL_CTRL_CH1_CH2, 0x20122012 },
110
+
{ CS42L43_DECIM_VOL_CTRL_CH3_CH4, 0x20122012 },
111
+
{ CS42L43_INTP_VOLUME_CTRL1, 0x00000180 },
112
+
{ CS42L43_INTP_VOLUME_CTRL2, 0x00000180 },
113
+
{ CS42L43_AMP1_2_VOL_RAMP, 0x00000022 },
114
+
{ CS42L43_ASP_CTRL, 0x00000004 },
115
+
{ CS42L43_ASP_FSYNC_CTRL1, 0x000000FA },
116
+
{ CS42L43_ASP_FSYNC_CTRL2, 0x00000001 },
117
+
{ CS42L43_ASP_FSYNC_CTRL3, 0x00000000 },
118
+
{ CS42L43_ASP_FSYNC_CTRL4, 0x000001F4 },
119
+
{ CS42L43_ASP_DATA_CTRL, 0x0000003A },
120
+
{ CS42L43_ASP_RX_EN, 0x00000000 },
121
+
{ CS42L43_ASP_TX_EN, 0x00000000 },
122
+
{ CS42L43_ASP_RX_CH1_CTRL, 0x00170001 },
123
+
{ CS42L43_ASP_RX_CH2_CTRL, 0x00170031 },
124
+
{ CS42L43_ASP_RX_CH3_CTRL, 0x00170061 },
125
+
{ CS42L43_ASP_RX_CH4_CTRL, 0x00170091 },
126
+
{ CS42L43_ASP_RX_CH5_CTRL, 0x001700C1 },
127
+
{ CS42L43_ASP_RX_CH6_CTRL, 0x001700F1 },
128
+
{ CS42L43_ASP_TX_CH1_CTRL, 0x00170001 },
129
+
{ CS42L43_ASP_TX_CH2_CTRL, 0x00170031 },
130
+
{ CS42L43_ASP_TX_CH3_CTRL, 0x00170061 },
131
+
{ CS42L43_ASP_TX_CH4_CTRL, 0x00170091 },
132
+
{ CS42L43_ASP_TX_CH5_CTRL, 0x001700C1 },
133
+
{ CS42L43_ASP_TX_CH6_CTRL, 0x001700F1 },
134
+
{ CS42L43_ASPTX1_INPUT, 0x00800000 },
135
+
{ CS42L43_ASPTX2_INPUT, 0x00800000 },
136
+
{ CS42L43_ASPTX3_INPUT, 0x00800000 },
137
+
{ CS42L43_ASPTX4_INPUT, 0x00800000 },
138
+
{ CS42L43_ASPTX5_INPUT, 0x00800000 },
139
+
{ CS42L43_ASPTX6_INPUT, 0x00800000 },
140
+
{ CS42L43_SWIRE_DP1_CH1_INPUT, 0x00800000 },
141
+
{ CS42L43_SWIRE_DP1_CH2_INPUT, 0x00800000 },
142
+
{ CS42L43_SWIRE_DP1_CH3_INPUT, 0x00800000 },
143
+
{ CS42L43_SWIRE_DP1_CH4_INPUT, 0x00800000 },
144
+
{ CS42L43_SWIRE_DP2_CH1_INPUT, 0x00800000 },
145
+
{ CS42L43_SWIRE_DP2_CH2_INPUT, 0x00800000 },
146
+
{ CS42L43_SWIRE_DP3_CH1_INPUT, 0x00800000 },
147
+
{ CS42L43_SWIRE_DP3_CH2_INPUT, 0x00800000 },
148
+
{ CS42L43_SWIRE_DP4_CH1_INPUT, 0x00800000 },
149
+
{ CS42L43_SWIRE_DP4_CH2_INPUT, 0x00800000 },
150
+
{ CS42L43_ASRC_INT1_INPUT1, 0x00800000 },
151
+
{ CS42L43_ASRC_INT2_INPUT1, 0x00800000 },
152
+
{ CS42L43_ASRC_INT3_INPUT1, 0x00800000 },
153
+
{ CS42L43_ASRC_INT4_INPUT1, 0x00800000 },
154
+
{ CS42L43_ASRC_DEC1_INPUT1, 0x00800000 },
155
+
{ CS42L43_ASRC_DEC2_INPUT1, 0x00800000 },
156
+
{ CS42L43_ASRC_DEC3_INPUT1, 0x00800000 },
157
+
{ CS42L43_ASRC_DEC4_INPUT1, 0x00800000 },
158
+
{ CS42L43_ISRC1INT1_INPUT1, 0x00800000 },
159
+
{ CS42L43_ISRC1INT2_INPUT1, 0x00800000 },
160
+
{ CS42L43_ISRC1DEC1_INPUT1, 0x00800000 },
161
+
{ CS42L43_ISRC1DEC2_INPUT1, 0x00800000 },
162
+
{ CS42L43_ISRC2INT1_INPUT1, 0x00800000 },
163
+
{ CS42L43_ISRC2INT2_INPUT1, 0x00800000 },
164
+
{ CS42L43_ISRC2DEC1_INPUT1, 0x00800000 },
165
+
{ CS42L43_ISRC2DEC2_INPUT1, 0x00800000 },
166
+
{ CS42L43_EQ1MIX_INPUT1, 0x00800000 },
167
+
{ CS42L43_EQ1MIX_INPUT2, 0x00800000 },
168
+
{ CS42L43_EQ1MIX_INPUT3, 0x00800000 },
169
+
{ CS42L43_EQ1MIX_INPUT4, 0x00800000 },
170
+
{ CS42L43_EQ2MIX_INPUT1, 0x00800000 },
171
+
{ CS42L43_EQ2MIX_INPUT2, 0x00800000 },
172
+
{ CS42L43_EQ2MIX_INPUT3, 0x00800000 },
173
+
{ CS42L43_EQ2MIX_INPUT4, 0x00800000 },
174
+
{ CS42L43_SPDIF1_INPUT1, 0x00800000 },
175
+
{ CS42L43_SPDIF2_INPUT1, 0x00800000 },
176
+
{ CS42L43_AMP1MIX_INPUT1, 0x00800000 },
177
+
{ CS42L43_AMP1MIX_INPUT2, 0x00800000 },
178
+
{ CS42L43_AMP1MIX_INPUT3, 0x00800000 },
179
+
{ CS42L43_AMP1MIX_INPUT4, 0x00800000 },
180
+
{ CS42L43_AMP2MIX_INPUT1, 0x00800000 },
181
+
{ CS42L43_AMP2MIX_INPUT2, 0x00800000 },
182
+
{ CS42L43_AMP2MIX_INPUT3, 0x00800000 },
183
+
{ CS42L43_AMP2MIX_INPUT4, 0x00800000 },
184
+
{ CS42L43_AMP3MIX_INPUT1, 0x00800000 },
185
+
{ CS42L43_AMP3MIX_INPUT2, 0x00800000 },
186
+
{ CS42L43_AMP3MIX_INPUT3, 0x00800000 },
187
+
{ CS42L43_AMP3MIX_INPUT4, 0x00800000 },
188
+
{ CS42L43_AMP4MIX_INPUT1, 0x00800000 },
189
+
{ CS42L43_AMP4MIX_INPUT2, 0x00800000 },
190
+
{ CS42L43_AMP4MIX_INPUT3, 0x00800000 },
191
+
{ CS42L43_AMP4MIX_INPUT4, 0x00800000 },
192
+
{ CS42L43_ASRC_INT_ENABLES, 0x00000100 },
193
+
{ CS42L43_ASRC_DEC_ENABLES, 0x00000100 },
194
+
{ CS42L43_PDNCNTL, 0x00000000 },
195
+
{ CS42L43_RINGSENSE_DEB_CTRL, 0x0000001B },
196
+
{ CS42L43_TIPSENSE_DEB_CTRL, 0x0000001B },
197
+
{ CS42L43_HS2, 0x050106F3 },
198
+
{ CS42L43_STEREO_MIC_CTRL, 0x00000000 },
199
+
{ CS42L43_STEREO_MIC_CLAMP_CTRL, 0x00000001 },
200
+
{ CS42L43_BLOCK_EN2, 0x00000000 },
201
+
{ CS42L43_BLOCK_EN3, 0x00000000 },
202
+
{ CS42L43_BLOCK_EN4, 0x00000000 },
203
+
{ CS42L43_BLOCK_EN5, 0x00000000 },
204
+
{ CS42L43_BLOCK_EN6, 0x00000000 },
205
+
{ CS42L43_BLOCK_EN7, 0x00000000 },
206
+
{ CS42L43_BLOCK_EN8, 0x00000000 },
207
+
{ CS42L43_BLOCK_EN9, 0x00000000 },
208
+
{ CS42L43_BLOCK_EN10, 0x00000000 },
209
+
{ CS42L43_BLOCK_EN11, 0x00000000 },
210
+
{ CS42L43_TONE_CH1_CTRL, 0x00000000 },
211
+
{ CS42L43_TONE_CH2_CTRL, 0x00000000 },
212
+
{ CS42L43_MIC_DETECT_CONTROL_1, 0x00000003 },
213
+
{ CS42L43_HS_BIAS_SENSE_AND_CLAMP_AUTOCONTROL, 0x02000003 },
214
+
{ CS42L43_MIC_DETECT_CONTROL_ANDROID, 0x80790079 },
215
+
{ CS42L43_ISRC1_CTRL, 0x00000000 },
216
+
{ CS42L43_ISRC2_CTRL, 0x00000000 },
217
+
{ CS42L43_CTRL_REG, 0x00000006 },
218
+
{ CS42L43_FDIV_FRAC, 0x40000000 },
219
+
{ CS42L43_CAL_RATIO, 0x00000080 },
220
+
{ CS42L43_SPI_CLK_CONFIG1, 0x00000000 },
221
+
{ CS42L43_SPI_CONFIG1, 0x00000000 },
222
+
{ CS42L43_SPI_CONFIG2, 0x00000000 },
223
+
{ CS42L43_SPI_CONFIG3, 0x00000001 },
224
+
{ CS42L43_SPI_CONFIG4, 0x00000000 },
225
+
{ CS42L43_TRAN_CONFIG3, 0x00000000 },
226
+
{ CS42L43_TRAN_CONFIG4, 0x00000000 },
227
+
{ CS42L43_TRAN_CONFIG5, 0x00000000 },
228
+
{ CS42L43_TRAN_CONFIG6, 0x00000000 },
229
+
{ CS42L43_TRAN_CONFIG7, 0x00000000 },
230
+
{ CS42L43_TRAN_CONFIG8, 0x00000000 },
231
+
{ CS42L43_DACCNFG1, 0x00000008 },
232
+
{ CS42L43_DACCNFG2, 0x00000005 },
233
+
{ CS42L43_HPPATHVOL, 0x011B011B },
234
+
{ CS42L43_PGAVOL, 0x00003470 },
235
+
{ CS42L43_LOADDETENA, 0x00000000 },
236
+
{ CS42L43_CTRL, 0x00000037 },
237
+
{ CS42L43_COEFF_DATA_IN0, 0x00000000 },
238
+
{ CS42L43_COEFF_RD_WR0, 0x00000000 },
239
+
{ CS42L43_START_EQZ0, 0x00000000 },
240
+
{ CS42L43_MUTE_EQ_IN0, 0x00000000 },
241
+
{ CS42L43_DECIM_MASK, 0x0000000F },
242
+
{ CS42L43_EQ_MIX_MASK, 0x0000000F },
243
+
{ CS42L43_ASP_MASK, 0x000000FF },
244
+
{ CS42L43_PLL_MASK, 0x00000003 },
245
+
{ CS42L43_SOFT_MASK, 0x0000FFFF },
246
+
{ CS42L43_SWIRE_MASK, 0x00007FFF },
247
+
{ CS42L43_MSM_MASK, 0x00000FFF },
248
+
{ CS42L43_ACC_DET_MASK, 0x00000FFF },
249
+
{ CS42L43_I2C_TGT_MASK, 0x00000003 },
250
+
{ CS42L43_SPI_MSTR_MASK, 0x00000007 },
251
+
{ CS42L43_SW_TO_SPI_BRIDGE_MASK, 0x00000001 },
252
+
{ CS42L43_OTP_MASK, 0x00000007 },
253
+
{ CS42L43_CLASS_D_AMP_MASK, 0x00003FFF },
254
+
{ CS42L43_GPIO_INT_MASK, 0x0000003F },
255
+
{ CS42L43_ASRC_MASK, 0x0000000F },
256
+
{ CS42L43_HPOUT_MASK, 0x00000003 },
257
+
};
258
+
EXPORT_SYMBOL_NS_GPL(cs42l43_reg_default, MFD_CS42L43);
259
+
260
+
bool cs42l43_readable_register(struct device *dev, unsigned int reg)
261
+
{
262
+
switch (reg) {
263
+
case CS42L43_DEVID:
264
+
case CS42L43_REVID:
265
+
case CS42L43_RELID:
266
+
case CS42L43_SFT_RESET:
267
+
case CS42L43_DRV_CTRL1:
268
+
case CS42L43_DRV_CTRL3:
269
+
case CS42L43_DRV_CTRL4:
270
+
case CS42L43_DRV_CTRL_5:
271
+
case CS42L43_GPIO_CTRL1:
272
+
case CS42L43_GPIO_CTRL2:
273
+
case CS42L43_GPIO_STS:
274
+
case CS42L43_GPIO_FN_SEL:
275
+
case CS42L43_MCLK_SRC_SEL:
276
+
case CS42L43_SAMPLE_RATE1 ... CS42L43_SAMPLE_RATE4:
277
+
case CS42L43_PLL_CONTROL:
278
+
case CS42L43_FS_SELECT1 ... CS42L43_FS_SELECT4:
279
+
case CS42L43_PDM_CONTROL:
280
+
case CS42L43_ASP_CLK_CONFIG1 ... CS42L43_ASP_CLK_CONFIG2:
281
+
case CS42L43_OSC_DIV_SEL:
282
+
case CS42L43_ADC_B_CTRL1 ... CS42L43_ADC_B_CTRL2:
283
+
case CS42L43_DECIM_HPF_WNF_CTRL1 ... CS42L43_DECIM_HPF_WNF_CTRL4:
284
+
case CS42L43_DMIC_PDM_CTRL:
285
+
case CS42L43_DECIM_VOL_CTRL_CH1_CH2 ... CS42L43_DECIM_VOL_CTRL_CH3_CH4:
286
+
case CS42L43_INTP_VOLUME_CTRL1 ... CS42L43_INTP_VOLUME_CTRL2:
287
+
case CS42L43_AMP1_2_VOL_RAMP:
288
+
case CS42L43_ASP_CTRL:
289
+
case CS42L43_ASP_FSYNC_CTRL1 ... CS42L43_ASP_FSYNC_CTRL4:
290
+
case CS42L43_ASP_DATA_CTRL:
291
+
case CS42L43_ASP_RX_EN ... CS42L43_ASP_TX_EN:
292
+
case CS42L43_ASP_RX_CH1_CTRL ... CS42L43_ASP_RX_CH6_CTRL:
293
+
case CS42L43_ASP_TX_CH1_CTRL ... CS42L43_ASP_TX_CH6_CTRL:
294
+
case CS42L43_OTP_REVISION_ID:
295
+
case CS42L43_ASPTX1_INPUT:
296
+
case CS42L43_ASPTX2_INPUT:
297
+
case CS42L43_ASPTX3_INPUT:
298
+
case CS42L43_ASPTX4_INPUT:
299
+
case CS42L43_ASPTX5_INPUT:
300
+
case CS42L43_ASPTX6_INPUT:
301
+
case CS42L43_SWIRE_DP1_CH1_INPUT:
302
+
case CS42L43_SWIRE_DP1_CH2_INPUT:
303
+
case CS42L43_SWIRE_DP1_CH3_INPUT:
304
+
case CS42L43_SWIRE_DP1_CH4_INPUT:
305
+
case CS42L43_SWIRE_DP2_CH1_INPUT:
306
+
case CS42L43_SWIRE_DP2_CH2_INPUT:
307
+
case CS42L43_SWIRE_DP3_CH1_INPUT:
308
+
case CS42L43_SWIRE_DP3_CH2_INPUT:
309
+
case CS42L43_SWIRE_DP4_CH1_INPUT:
310
+
case CS42L43_SWIRE_DP4_CH2_INPUT:
311
+
case CS42L43_ASRC_INT1_INPUT1:
312
+
case CS42L43_ASRC_INT2_INPUT1:
313
+
case CS42L43_ASRC_INT3_INPUT1:
314
+
case CS42L43_ASRC_INT4_INPUT1:
315
+
case CS42L43_ASRC_DEC1_INPUT1:
316
+
case CS42L43_ASRC_DEC2_INPUT1:
317
+
case CS42L43_ASRC_DEC3_INPUT1:
318
+
case CS42L43_ASRC_DEC4_INPUT1:
319
+
case CS42L43_ISRC1INT1_INPUT1:
320
+
case CS42L43_ISRC1INT2_INPUT1:
321
+
case CS42L43_ISRC1DEC1_INPUT1:
322
+
case CS42L43_ISRC1DEC2_INPUT1:
323
+
case CS42L43_ISRC2INT1_INPUT1:
324
+
case CS42L43_ISRC2INT2_INPUT1:
325
+
case CS42L43_ISRC2DEC1_INPUT1:
326
+
case CS42L43_ISRC2DEC2_INPUT1:
327
+
case CS42L43_EQ1MIX_INPUT1 ... CS42L43_EQ1MIX_INPUT4:
328
+
case CS42L43_EQ2MIX_INPUT1 ... CS42L43_EQ2MIX_INPUT4:
329
+
case CS42L43_SPDIF1_INPUT1:
330
+
case CS42L43_SPDIF2_INPUT1:
331
+
case CS42L43_AMP1MIX_INPUT1 ... CS42L43_AMP1MIX_INPUT4:
332
+
case CS42L43_AMP2MIX_INPUT1 ... CS42L43_AMP2MIX_INPUT4:
333
+
case CS42L43_AMP3MIX_INPUT1 ... CS42L43_AMP3MIX_INPUT4:
334
+
case CS42L43_AMP4MIX_INPUT1 ... CS42L43_AMP4MIX_INPUT4:
335
+
case CS42L43_ASRC_INT_ENABLES ... CS42L43_ASRC_DEC_ENABLES:
336
+
case CS42L43_PDNCNTL:
337
+
case CS42L43_RINGSENSE_DEB_CTRL:
338
+
case CS42L43_TIPSENSE_DEB_CTRL:
339
+
case CS42L43_TIP_RING_SENSE_INTERRUPT_STATUS:
340
+
case CS42L43_HS2:
341
+
case CS42L43_HS_STAT:
342
+
case CS42L43_MCU_SW_INTERRUPT:
343
+
case CS42L43_STEREO_MIC_CTRL:
344
+
case CS42L43_STEREO_MIC_CLAMP_CTRL:
345
+
case CS42L43_BLOCK_EN2 ... CS42L43_BLOCK_EN11:
346
+
case CS42L43_TONE_CH1_CTRL ... CS42L43_TONE_CH2_CTRL:
347
+
case CS42L43_MIC_DETECT_CONTROL_1:
348
+
case CS42L43_DETECT_STATUS_1:
349
+
case CS42L43_HS_BIAS_SENSE_AND_CLAMP_AUTOCONTROL:
350
+
case CS42L43_MIC_DETECT_CONTROL_ANDROID:
351
+
case CS42L43_ISRC1_CTRL:
352
+
case CS42L43_ISRC2_CTRL:
353
+
case CS42L43_CTRL_REG:
354
+
case CS42L43_FDIV_FRAC:
355
+
case CS42L43_CAL_RATIO:
356
+
case CS42L43_SPI_CLK_CONFIG1:
357
+
case CS42L43_SPI_CONFIG1 ... CS42L43_SPI_CONFIG4:
358
+
case CS42L43_SPI_STATUS1 ... CS42L43_SPI_STATUS2:
359
+
case CS42L43_TRAN_CONFIG1 ... CS42L43_TRAN_CONFIG8:
360
+
case CS42L43_TRAN_STATUS1 ... CS42L43_TRAN_STATUS3:
361
+
case CS42L43_TX_DATA:
362
+
case CS42L43_RX_DATA:
363
+
case CS42L43_DACCNFG1 ... CS42L43_DACCNFG2:
364
+
case CS42L43_HPPATHVOL:
365
+
case CS42L43_PGAVOL:
366
+
case CS42L43_LOADDETRESULTS:
367
+
case CS42L43_LOADDETENA:
368
+
case CS42L43_CTRL:
369
+
case CS42L43_COEFF_DATA_IN0:
370
+
case CS42L43_COEFF_RD_WR0:
371
+
case CS42L43_INIT_DONE0:
372
+
case CS42L43_START_EQZ0:
373
+
case CS42L43_MUTE_EQ_IN0:
374
+
case CS42L43_DECIM_INT ... CS42L43_HPOUT_INT:
375
+
case CS42L43_DECIM_MASK ... CS42L43_HPOUT_MASK:
376
+
case CS42L43_DECIM_INT_SHADOW ... CS42L43_HP_OUT_SHADOW:
377
+
case CS42L43_BOOT_CONTROL:
378
+
case CS42L43_BLOCK_EN:
379
+
case CS42L43_SHUTTER_CONTROL:
380
+
case CS42L43_MCU_SW_REV ... CS42L43_MCU_RAM_MAX:
381
+
return true;
382
+
default:
383
+
return false;
384
+
}
385
+
}
386
+
EXPORT_SYMBOL_NS_GPL(cs42l43_readable_register, MFD_CS42L43);
387
+
388
+
bool cs42l43_precious_register(struct device *dev, unsigned int reg)
389
+
{
390
+
switch (reg) {
391
+
case CS42L43_SFT_RESET:
392
+
case CS42L43_TX_DATA:
393
+
case CS42L43_RX_DATA:
394
+
case CS42L43_DECIM_INT ... CS42L43_HPOUT_INT:
395
+
case CS42L43_MCU_SW_REV ... CS42L43_MCU_RAM_MAX:
396
+
return true;
397
+
default:
398
+
return false;
399
+
}
400
+
}
401
+
EXPORT_SYMBOL_NS_GPL(cs42l43_precious_register, MFD_CS42L43);
402
+
403
+
bool cs42l43_volatile_register(struct device *dev, unsigned int reg)
404
+
{
405
+
switch (reg) {
406
+
case CS42L43_DEVID:
407
+
case CS42L43_REVID:
408
+
case CS42L43_RELID:
409
+
case CS42L43_GPIO_STS:
410
+
case CS42L43_OTP_REVISION_ID:
411
+
case CS42L43_TIP_RING_SENSE_INTERRUPT_STATUS:
412
+
case CS42L43_HS_STAT:
413
+
case CS42L43_MCU_SW_INTERRUPT:
414
+
case CS42L43_DETECT_STATUS_1:
415
+
case CS42L43_SPI_STATUS1 ... CS42L43_SPI_STATUS2:
416
+
case CS42L43_TRAN_CONFIG1 ... CS42L43_TRAN_CONFIG2:
417
+
case CS42L43_TRAN_CONFIG8:
418
+
case CS42L43_TRAN_STATUS1 ... CS42L43_TRAN_STATUS3:
419
+
case CS42L43_LOADDETRESULTS:
420
+
case CS42L43_INIT_DONE0:
421
+
case CS42L43_DECIM_INT_SHADOW ... CS42L43_HP_OUT_SHADOW:
422
+
case CS42L43_BOOT_CONTROL:
423
+
case CS42L43_BLOCK_EN:
424
+
return true;
425
+
default:
426
+
return cs42l43_precious_register(dev, reg);
427
+
}
428
+
}
429
+
EXPORT_SYMBOL_NS_GPL(cs42l43_volatile_register, MFD_CS42L43);
430
+
431
+
#define CS42L43_IRQ_OFFSET(reg) ((CS42L43_##reg##_INT) - CS42L43_DECIM_INT)
432
+
433
+
#define CS42L43_IRQ_REG(name, reg) REGMAP_IRQ_REG(CS42L43_##name, \
434
+
CS42L43_IRQ_OFFSET(reg), \
435
+
CS42L43_##name##_INT_MASK)
436
+
437
+
static const struct regmap_irq cs42l43_regmap_irqs[] = {
438
+
CS42L43_IRQ_REG(PLL_LOST_LOCK, PLL),
439
+
CS42L43_IRQ_REG(PLL_READY, PLL),
440
+
441
+
CS42L43_IRQ_REG(HP_STARTUP_DONE, MSM),
442
+
CS42L43_IRQ_REG(HP_SHUTDOWN_DONE, MSM),
443
+
CS42L43_IRQ_REG(HSDET_DONE, MSM),
444
+
CS42L43_IRQ_REG(TIPSENSE_UNPLUG_DB, MSM),
445
+
CS42L43_IRQ_REG(TIPSENSE_PLUG_DB, MSM),
446
+
CS42L43_IRQ_REG(RINGSENSE_UNPLUG_DB, MSM),
447
+
CS42L43_IRQ_REG(RINGSENSE_PLUG_DB, MSM),
448
+
CS42L43_IRQ_REG(TIPSENSE_UNPLUG_PDET, MSM),
449
+
CS42L43_IRQ_REG(TIPSENSE_PLUG_PDET, MSM),
450
+
CS42L43_IRQ_REG(RINGSENSE_UNPLUG_PDET, MSM),
451
+
CS42L43_IRQ_REG(RINGSENSE_PLUG_PDET, MSM),
452
+
453
+
CS42L43_IRQ_REG(HS2_BIAS_SENSE, ACC_DET),
454
+
CS42L43_IRQ_REG(HS1_BIAS_SENSE, ACC_DET),
455
+
CS42L43_IRQ_REG(DC_DETECT1_FALSE, ACC_DET),
456
+
CS42L43_IRQ_REG(DC_DETECT1_TRUE, ACC_DET),
457
+
CS42L43_IRQ_REG(HSBIAS_CLAMPED, ACC_DET),
458
+
CS42L43_IRQ_REG(HS3_4_BIAS_SENSE, ACC_DET),
459
+
460
+
CS42L43_IRQ_REG(AMP2_CLK_STOP_FAULT, CLASS_D_AMP),
461
+
CS42L43_IRQ_REG(AMP1_CLK_STOP_FAULT, CLASS_D_AMP),
462
+
CS42L43_IRQ_REG(AMP2_VDDSPK_FAULT, CLASS_D_AMP),
463
+
CS42L43_IRQ_REG(AMP1_VDDSPK_FAULT, CLASS_D_AMP),
464
+
CS42L43_IRQ_REG(AMP2_SHUTDOWN_DONE, CLASS_D_AMP),
465
+
CS42L43_IRQ_REG(AMP1_SHUTDOWN_DONE, CLASS_D_AMP),
466
+
CS42L43_IRQ_REG(AMP2_STARTUP_DONE, CLASS_D_AMP),
467
+
CS42L43_IRQ_REG(AMP1_STARTUP_DONE, CLASS_D_AMP),
468
+
CS42L43_IRQ_REG(AMP2_THERM_SHDN, CLASS_D_AMP),
469
+
CS42L43_IRQ_REG(AMP1_THERM_SHDN, CLASS_D_AMP),
470
+
CS42L43_IRQ_REG(AMP2_THERM_WARN, CLASS_D_AMP),
471
+
CS42L43_IRQ_REG(AMP1_THERM_WARN, CLASS_D_AMP),
472
+
CS42L43_IRQ_REG(AMP2_SCDET, CLASS_D_AMP),
473
+
CS42L43_IRQ_REG(AMP1_SCDET, CLASS_D_AMP),
474
+
475
+
CS42L43_IRQ_REG(GPIO3_FALL, GPIO),
476
+
CS42L43_IRQ_REG(GPIO3_RISE, GPIO),
477
+
CS42L43_IRQ_REG(GPIO2_FALL, GPIO),
478
+
CS42L43_IRQ_REG(GPIO2_RISE, GPIO),
479
+
CS42L43_IRQ_REG(GPIO1_FALL, GPIO),
480
+
CS42L43_IRQ_REG(GPIO1_RISE, GPIO),
481
+
482
+
CS42L43_IRQ_REG(HP_ILIMIT, HPOUT),
483
+
CS42L43_IRQ_REG(HP_LOADDET_DONE, HPOUT),
484
+
};
485
+
486
+
static const struct regmap_irq_chip cs42l43_irq_chip = {
487
+
.name = "cs42l43",
488
+
489
+
.status_base = CS42L43_DECIM_INT,
490
+
.mask_base = CS42L43_DECIM_MASK,
491
+
.num_regs = 16,
492
+
493
+
.irqs = cs42l43_regmap_irqs,
494
+
.num_irqs = ARRAY_SIZE(cs42l43_regmap_irqs),
495
+
496
+
.runtime_pm = true,
497
+
};
498
+
499
+
static const char * const cs42l43_core_supplies[] = {
500
+
"vdd-a", "vdd-io", "vdd-cp",
501
+
};
502
+
503
+
static const char * const cs42l43_parent_supplies[] = { "vdd-amp" };
504
+
505
+
static const struct mfd_cell cs42l43_devs[] = {
506
+
{ .name = "cs42l43-pinctrl", },
507
+
{ .name = "cs42l43-spi", },
508
+
{
509
+
.name = "cs42l43-codec",
510
+
.parent_supplies = cs42l43_parent_supplies,
511
+
.num_parent_supplies = ARRAY_SIZE(cs42l43_parent_supplies),
512
+
},
513
+
};
514
+
515
+
/*
516
+
* If the device is connected over Soundwire, as well as soft resetting the
517
+
* device, this function will also way for the device to detach from the bus
518
+
* before returning.
519
+
*/
520
+
static int cs42l43_soft_reset(struct cs42l43 *cs42l43)
521
+
{
522
+
static const struct reg_sequence reset[] = {
523
+
{ CS42L43_SFT_RESET, CS42L43_SFT_RESET_VAL },
524
+
};
525
+
526
+
reinit_completion(&cs42l43->device_detach);
527
+
528
+
/*
529
+
* Apply cache only because the soft reset will cause the device to
530
+
* detach from the soundwire bus.
531
+
*/
532
+
regcache_cache_only(cs42l43->regmap, true);
533
+
regmap_multi_reg_write_bypassed(cs42l43->regmap, reset, ARRAY_SIZE(reset));
534
+
535
+
msleep(CS42L43_RESET_DELAY);
536
+
537
+
if (cs42l43->sdw) {
538
+
unsigned long timeout = msecs_to_jiffies(CS42L43_SDW_DETACH_TIMEOUT);
539
+
unsigned long time;
540
+
541
+
time = wait_for_completion_timeout(&cs42l43->device_detach, timeout);
542
+
if (!time) {
543
+
dev_err(cs42l43->dev, "Timed out waiting for device detach\n");
544
+
return -ETIMEDOUT;
545
+
}
546
+
}
547
+
548
+
return -EAGAIN;
549
+
}
550
+
551
+
/*
552
+
* This function is essentially a no-op on I2C, but will wait for the device to
553
+
* attach when the device is used on a SoundWire bus.
554
+
*/
555
+
static int cs42l43_wait_for_attach(struct cs42l43 *cs42l43)
556
+
{
557
+
if (!cs42l43->attached) {
558
+
unsigned long timeout = msecs_to_jiffies(CS42L43_SDW_ATTACH_TIMEOUT);
559
+
unsigned long time;
560
+
561
+
time = wait_for_completion_timeout(&cs42l43->device_attach, timeout);
562
+
if (!time) {
563
+
dev_err(cs42l43->dev, "Timed out waiting for device re-attach\n");
564
+
return -ETIMEDOUT;
565
+
}
566
+
}
567
+
568
+
regcache_cache_only(cs42l43->regmap, false);
569
+
570
+
/* The hardware requires enabling OSC_DIV before doing any SoundWire reads. */
571
+
if (cs42l43->sdw)
572
+
regmap_write(cs42l43->regmap, CS42L43_OSC_DIV_SEL,
573
+
CS42L43_OSC_DIV2_EN_MASK);
574
+
575
+
return 0;
576
+
}
577
+
578
+
/*
579
+
* This function will advance the firmware into boot stage 3 from boot stage 2.
580
+
* Boot stage 3 is required to send commands to the firmware. This is achieved
581
+
* by setting the firmware NEED configuration register to zero, this indicates
582
+
* no configuration is required forcing the firmware to advance to boot stage 3.
583
+
*
584
+
* Later revisions of the firmware require the use of an alternative register
585
+
* for this purpose, which is indicated through the shadow flag.
586
+
*/
587
+
static int cs42l43_mcu_stage_2_3(struct cs42l43 *cs42l43, bool shadow)
588
+
{
589
+
unsigned int need_reg = CS42L43_NEED_CONFIGS;
590
+
unsigned int val;
591
+
int ret;
592
+
593
+
if (shadow)
594
+
need_reg = CS42L43_FW_SH_BOOT_CFG_NEED_CONFIGS;
595
+
596
+
regmap_write(cs42l43->regmap, need_reg, 0);
597
+
598
+
ret = regmap_read_poll_timeout(cs42l43->regmap, CS42L43_BOOT_STATUS,
599
+
val, (val == CS42L43_MCU_BOOT_STAGE3),
600
+
CS42L43_MCU_POLL, CS42L43_MCU_CMD_TIMEOUT);
601
+
if (ret) {
602
+
dev_err(cs42l43->dev, "Failed to move to stage 3: %d, 0x%x\n", ret, val);
603
+
return ret;
604
+
}
605
+
606
+
return -EAGAIN;
607
+
}
608
+
609
+
/*
610
+
* This function will return the firmware to boot stage 2 from boot stage 3.
611
+
* Boot stage 2 is required to apply updates to the firmware. This is achieved
612
+
* by setting the firmware NEED configuration register to FW_PATCH_NEED_CFG,
613
+
* setting the HAVE configuration register to 0, and soft resetting. The
614
+
* firmware will see it is missing a patch configuration and will pause in boot
615
+
* stage 2.
616
+
*
617
+
* Note: Unlike cs42l43_mcu_stage_2_3 there is no need to consider the shadow
618
+
* register here as the driver will only return to boot stage 2 if the firmware
619
+
* requires update which means the revision does not include shadow register
620
+
* support.
621
+
*/
622
+
static int cs42l43_mcu_stage_3_2(struct cs42l43 *cs42l43)
623
+
{
624
+
regmap_write(cs42l43->regmap, CS42L43_FW_MISSION_CTRL_NEED_CONFIGS,
625
+
CS42L43_FW_PATCH_NEED_CFG_MASK);
626
+
regmap_write(cs42l43->regmap, CS42L43_FW_MISSION_CTRL_HAVE_CONFIGS, 0);
627
+
628
+
return cs42l43_soft_reset(cs42l43);
629
+
}
630
+
631
+
/*
632
+
* Disable the firmware running on the device such that the driver can access
633
+
* the registers without fear of the MCU changing them under it.
634
+
*/
635
+
static int cs42l43_mcu_disable(struct cs42l43 *cs42l43)
636
+
{
637
+
unsigned int val;
638
+
int ret;
639
+
640
+
regmap_write(cs42l43->regmap, CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_REG,
641
+
CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_DISABLE_VAL);
642
+
regmap_write(cs42l43->regmap, CS42L43_FW_MISSION_CTRL_MM_CTRL_SELECTION,
643
+
CS42L43_FW_MM_CTRL_MCU_SEL_MASK);
644
+
regmap_write(cs42l43->regmap, CS42L43_MCU_SW_INTERRUPT, CS42L43_CONTROL_IND_MASK);
645
+
regmap_write(cs42l43->regmap, CS42L43_MCU_SW_INTERRUPT, 0);
646
+
647
+
ret = regmap_read_poll_timeout(cs42l43->regmap, CS42L43_SOFT_INT_SHADOW, val,
648
+
(val & CS42L43_CONTROL_APPLIED_INT_MASK),
649
+
CS42L43_MCU_POLL, CS42L43_MCU_CMD_TIMEOUT);
650
+
if (ret) {
651
+
dev_err(cs42l43->dev, "Failed to disable firmware: %d, 0x%x\n", ret, val);
652
+
return ret;
653
+
}
654
+
655
+
/* Soft reset to clear any register state the firmware left behind. */
656
+
return cs42l43_soft_reset(cs42l43);
657
+
}
658
+
659
+
/*
660
+
* Callback to load firmware updates.
661
+
*/
662
+
static void cs42l43_mcu_load_firmware(const struct firmware *firmware, void *context)
663
+
{
664
+
struct cs42l43 *cs42l43 = context;
665
+
const struct cs42l43_patch_header *hdr;
666
+
unsigned int loadaddr, val;
667
+
int ret;
668
+
669
+
if (!firmware) {
670
+
dev_err(cs42l43->dev, "Failed to load firmware\n");
671
+
cs42l43->firmware_error = -ENODEV;
672
+
goto err;
673
+
}
674
+
675
+
hdr = (const struct cs42l43_patch_header *)&firmware->data[0];
676
+
loadaddr = le32_to_cpu(hdr->load_addr);
677
+
678
+
if (le16_to_cpu(hdr->version) != CS42L43_MCU_UPDATE_FORMAT) {
679
+
dev_err(cs42l43->dev, "Bad firmware file format: %d\n", hdr->version);
680
+
cs42l43->firmware_error = -EINVAL;
681
+
goto err_release;
682
+
}
683
+
684
+
regmap_write(cs42l43->regmap, CS42L43_PATCH_START_ADDR, loadaddr);
685
+
regmap_bulk_write(cs42l43->regmap, loadaddr + CS42L43_MCU_UPDATE_OFFSET,
686
+
&firmware->data[0], firmware->size / sizeof(u32));
687
+
688
+
regmap_write(cs42l43->regmap, CS42L43_MCU_SW_INTERRUPT, CS42L43_PATCH_IND_MASK);
689
+
regmap_write(cs42l43->regmap, CS42L43_MCU_SW_INTERRUPT, 0);
690
+
691
+
ret = regmap_read_poll_timeout(cs42l43->regmap, CS42L43_SOFT_INT_SHADOW, val,
692
+
(val & CS42L43_PATCH_APPLIED_INT_MASK),
693
+
CS42L43_MCU_POLL, CS42L43_MCU_UPDATE_TIMEOUT);
694
+
if (ret) {
695
+
dev_err(cs42l43->dev, "Failed to update firmware: %d, 0x%x\n", ret, val);
696
+
cs42l43->firmware_error = ret;
697
+
goto err_release;
698
+
}
699
+
700
+
err_release:
701
+
release_firmware(firmware);
702
+
err:
703
+
complete(&cs42l43->firmware_download);
704
+
}
705
+
706
+
/*
707
+
* The process of updating the firmware is split into a series of steps, at the
708
+
* end of each step a soft reset of the device might be required which will
709
+
* require the driver to wait for the device to re-attach on the SoundWire bus,
710
+
* if that control bus is being used.
711
+
*/
712
+
static int cs42l43_mcu_update_step(struct cs42l43 *cs42l43)
713
+
{
714
+
unsigned int mcu_rev, bios_rev, boot_status, secure_cfg;
715
+
bool patched, shadow;
716
+
int ret;
717
+
718
+
/* Clear any stale software interrupt bits. */
719
+
regmap_read(cs42l43->regmap, CS42L43_SOFT_INT, &mcu_rev);
720
+
721
+
ret = regmap_read(cs42l43->regmap, CS42L43_BOOT_STATUS, &boot_status);
722
+
if (ret) {
723
+
dev_err(cs42l43->dev, "Failed to read boot status: %d\n", ret);
724
+
return ret;
725
+
}
726
+
727
+
ret = regmap_read(cs42l43->regmap, CS42L43_MCU_SW_REV, &mcu_rev);
728
+
if (ret) {
729
+
dev_err(cs42l43->dev, "Failed to read firmware revision: %d\n", ret);
730
+
return ret;
731
+
}
732
+
733
+
bios_rev = (((mcu_rev & CS42L43_BIOS_MAJOR_REV_MASK) << 12) |
734
+
((mcu_rev & CS42L43_BIOS_MINOR_REV_MASK) << 4) |
735
+
((mcu_rev & CS42L43_BIOS_SUBMINOR_REV_MASK) >> 8)) >>
736
+
CS42L43_BIOS_MAJOR_REV_SHIFT;
737
+
mcu_rev = ((mcu_rev & CS42L43_FW_MAJOR_REV_MASK) << 12) |
738
+
((mcu_rev & CS42L43_FW_MINOR_REV_MASK) << 4) |
739
+
((mcu_rev & CS42L43_FW_SUBMINOR_REV_MASK) >> 8);
740
+
741
+
/*
742
+
* The firmware has two revision numbers bringing either of them up to a
743
+
* supported version will provide the features the driver requires.
744
+
*/
745
+
patched = mcu_rev >= CS42L43_MCU_SUPPORTED_REV ||
746
+
bios_rev >= CS42L43_MCU_SUPPORTED_BIOS_REV;
747
+
/*
748
+
* Later versions of the firmwware require the driver to access some
749
+
* features through a set of shadow registers.
750
+
*/
751
+
shadow = mcu_rev >= CS42L43_MCU_SHADOW_REGS_REQUIRED_REV;
752
+
753
+
ret = regmap_read(cs42l43->regmap, CS42L43_BOOT_CONTROL, &secure_cfg);
754
+
if (ret) {
755
+
dev_err(cs42l43->dev, "Failed to read security settings: %d\n", ret);
756
+
return ret;
757
+
}
758
+
759
+
cs42l43->hw_lock = secure_cfg & CS42L43_LOCK_HW_STS_MASK;
760
+
761
+
if (!patched && cs42l43->hw_lock) {
762
+
dev_err(cs42l43->dev, "Unpatched secure device\n");
763
+
return -EPERM;
764
+
}
765
+
766
+
dev_dbg(cs42l43->dev, "Firmware(0x%x, 0x%x) in boot stage %d\n",
767
+
mcu_rev, bios_rev, boot_status);
768
+
769
+
switch (boot_status) {
770
+
case CS42L43_MCU_BOOT_STAGE2:
771
+
if (!patched) {
772
+
ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_UEVENT,
773
+
"cs42l43.bin", cs42l43->dev,
774
+
GFP_KERNEL, cs42l43,
775
+
cs42l43_mcu_load_firmware);
776
+
if (ret) {
777
+
dev_err(cs42l43->dev, "Failed to request firmware: %d\n", ret);
778
+
return ret;
779
+
}
780
+
781
+
wait_for_completion(&cs42l43->firmware_download);
782
+
783
+
if (cs42l43->firmware_error)
784
+
return cs42l43->firmware_error;
785
+
786
+
return -EAGAIN;
787
+
} else {
788
+
return cs42l43_mcu_stage_2_3(cs42l43, shadow);
789
+
}
790
+
case CS42L43_MCU_BOOT_STAGE3:
791
+
if (patched)
792
+
return cs42l43_mcu_disable(cs42l43);
793
+
else
794
+
return cs42l43_mcu_stage_3_2(cs42l43);
795
+
case CS42L43_MCU_BOOT_STAGE4:
796
+
return 0;
797
+
default:
798
+
dev_err(cs42l43->dev, "Invalid boot status: %d\n", boot_status);
799
+
return -EINVAL;
800
+
}
801
+
}
802
+
803
+
/*
804
+
* Update the firmware running on the device.
805
+
*/
806
+
static int cs42l43_mcu_update(struct cs42l43 *cs42l43)
807
+
{
808
+
int i, ret;
809
+
810
+
for (i = 0; i < CS42L43_MCU_UPDATE_RETRIES; i++) {
811
+
ret = cs42l43_mcu_update_step(cs42l43);
812
+
if (ret != -EAGAIN)
813
+
return ret;
814
+
815
+
ret = cs42l43_wait_for_attach(cs42l43);
816
+
if (ret)
817
+
return ret;
818
+
}
819
+
820
+
dev_err(cs42l43->dev, "Failed retrying update\n");
821
+
return -ETIMEDOUT;
822
+
}
823
+
824
+
static int cs42l43_irq_config(struct cs42l43 *cs42l43)
825
+
{
826
+
struct irq_data *irq_data;
827
+
unsigned long irq_flags;
828
+
int ret;
829
+
830
+
if (cs42l43->sdw)
831
+
cs42l43->irq = cs42l43->sdw->irq;
832
+
833
+
cs42l43->irq_chip = cs42l43_irq_chip;
834
+
cs42l43->irq_chip.irq_drv_data = cs42l43;
835
+
836
+
irq_data = irq_get_irq_data(cs42l43->irq);
837
+
if (!irq_data) {
838
+
dev_err(cs42l43->dev, "Invalid IRQ: %d\n", cs42l43->irq);
839
+
return -EINVAL;
840
+
}
841
+
842
+
irq_flags = irqd_get_trigger_type(irq_data);
843
+
switch (irq_flags) {
844
+
case IRQF_TRIGGER_LOW:
845
+
case IRQF_TRIGGER_HIGH:
846
+
case IRQF_TRIGGER_RISING:
847
+
case IRQF_TRIGGER_FALLING:
848
+
break;
849
+
case IRQ_TYPE_NONE:
850
+
default:
851
+
irq_flags = IRQF_TRIGGER_LOW;
852
+
break;
853
+
}
854
+
855
+
irq_flags |= IRQF_ONESHOT;
856
+
857
+
ret = devm_regmap_add_irq_chip(cs42l43->dev, cs42l43->regmap,
858
+
cs42l43->irq, irq_flags, 0,
859
+
&cs42l43->irq_chip, &cs42l43->irq_data);
860
+
if (ret) {
861
+
dev_err(cs42l43->dev, "Failed to add IRQ chip: %d\n", ret);
862
+
return ret;
863
+
}
864
+
865
+
dev_dbg(cs42l43->dev, "Configured IRQ %d with flags 0x%lx\n",
866
+
cs42l43->irq, irq_flags);
867
+
868
+
return 0;
869
+
}
870
+
871
+
static void cs42l43_boot_work(struct work_struct *work)
872
+
{
873
+
struct cs42l43 *cs42l43 = container_of(work, struct cs42l43, boot_work);
874
+
unsigned int devid, revid, otp;
875
+
int ret;
876
+
877
+
ret = cs42l43_wait_for_attach(cs42l43);
878
+
if (ret)
879
+
goto err;
880
+
881
+
ret = regmap_read(cs42l43->regmap, CS42L43_DEVID, &devid);
882
+
if (ret) {
883
+
dev_err(cs42l43->dev, "Failed to read devid: %d\n", ret);
884
+
goto err;
885
+
}
886
+
887
+
switch (devid) {
888
+
case CS42L43_DEVID_VAL:
889
+
break;
890
+
default:
891
+
dev_err(cs42l43->dev, "Unrecognised devid: 0x%06x\n", devid);
892
+
goto err;
893
+
}
894
+
895
+
ret = regmap_read(cs42l43->regmap, CS42L43_REVID, &revid);
896
+
if (ret) {
897
+
dev_err(cs42l43->dev, "Failed to read rev: %d\n", ret);
898
+
goto err;
899
+
}
900
+
901
+
ret = regmap_read(cs42l43->regmap, CS42L43_OTP_REVISION_ID, &otp);
902
+
if (ret) {
903
+
dev_err(cs42l43->dev, "Failed to read otp rev: %d\n", ret);
904
+
goto err;
905
+
}
906
+
907
+
dev_info(cs42l43->dev,
908
+
"devid: 0x%06x, rev: 0x%02x, otp: 0x%02x\n", devid, revid, otp);
909
+
910
+
ret = cs42l43_mcu_update(cs42l43);
911
+
if (ret)
912
+
goto err;
913
+
914
+
ret = regmap_register_patch(cs42l43->regmap, cs42l43_reva_patch,
915
+
ARRAY_SIZE(cs42l43_reva_patch));
916
+
if (ret) {
917
+
dev_err(cs42l43->dev, "Failed to apply register patch: %d\n", ret);
918
+
goto err;
919
+
}
920
+
921
+
ret = cs42l43_irq_config(cs42l43);
922
+
if (ret)
923
+
goto err;
924
+
925
+
ret = devm_mfd_add_devices(cs42l43->dev, PLATFORM_DEVID_NONE,
926
+
cs42l43_devs, ARRAY_SIZE(cs42l43_devs),
927
+
NULL, 0, NULL);
928
+
if (ret) {
929
+
dev_err(cs42l43->dev, "Failed to add subdevices: %d\n", ret);
930
+
goto err;
931
+
}
932
+
933
+
pm_runtime_mark_last_busy(cs42l43->dev);
934
+
pm_runtime_put_autosuspend(cs42l43->dev);
935
+
936
+
return;
937
+
938
+
err:
939
+
pm_runtime_put_sync(cs42l43->dev);
940
+
cs42l43_dev_remove(cs42l43);
941
+
}
942
+
943
+
static int cs42l43_power_up(struct cs42l43 *cs42l43)
944
+
{
945
+
int ret;
946
+
947
+
ret = regulator_enable(cs42l43->vdd_p);
948
+
if (ret) {
949
+
dev_err(cs42l43->dev, "Failed to enable vdd-p: %d\n", ret);
950
+
return ret;
951
+
}
952
+
953
+
/* vdd-p must be on for 50uS before any other supply */
954
+
usleep_range(CS42L43_VDDP_DELAY, 2 * CS42L43_VDDP_DELAY);
955
+
956
+
gpiod_set_value_cansleep(cs42l43->reset, 1);
957
+
958
+
ret = regulator_bulk_enable(CS42L43_N_SUPPLIES, cs42l43->core_supplies);
959
+
if (ret) {
960
+
dev_err(cs42l43->dev, "Failed to enable core supplies: %d\n", ret);
961
+
goto err_reset;
962
+
}
963
+
964
+
ret = regulator_enable(cs42l43->vdd_d);
965
+
if (ret) {
966
+
dev_err(cs42l43->dev, "Failed to enable vdd-d: %d\n", ret);
967
+
goto err_core_supplies;
968
+
}
969
+
970
+
usleep_range(CS42L43_VDDD_DELAY, 2 * CS42L43_VDDD_DELAY);
971
+
972
+
return 0;
973
+
974
+
err_core_supplies:
975
+
regulator_bulk_disable(CS42L43_N_SUPPLIES, cs42l43->core_supplies);
976
+
err_reset:
977
+
gpiod_set_value_cansleep(cs42l43->reset, 0);
978
+
regulator_disable(cs42l43->vdd_p);
979
+
980
+
return ret;
981
+
}
982
+
983
+
static int cs42l43_power_down(struct cs42l43 *cs42l43)
984
+
{
985
+
int ret;
986
+
987
+
ret = regulator_disable(cs42l43->vdd_d);
988
+
if (ret) {
989
+
dev_err(cs42l43->dev, "Failed to disable vdd-d: %d\n", ret);
990
+
return ret;
991
+
}
992
+
993
+
ret = regulator_bulk_disable(CS42L43_N_SUPPLIES, cs42l43->core_supplies);
994
+
if (ret) {
995
+
dev_err(cs42l43->dev, "Failed to disable core supplies: %d\n", ret);
996
+
return ret;
997
+
}
998
+
999
+
gpiod_set_value_cansleep(cs42l43->reset, 0);
1000
+
1001
+
ret = regulator_disable(cs42l43->vdd_p);
1002
+
if (ret) {
1003
+
dev_err(cs42l43->dev, "Failed to disable vdd-p: %d\n", ret);
1004
+
return ret;
1005
+
}
1006
+
1007
+
return 0;
1008
+
}
1009
+
1010
+
int cs42l43_dev_probe(struct cs42l43 *cs42l43)
1011
+
{
1012
+
int i, ret;
1013
+
1014
+
dev_set_drvdata(cs42l43->dev, cs42l43);
1015
+
1016
+
mutex_init(&cs42l43->pll_lock);
1017
+
init_completion(&cs42l43->device_attach);
1018
+
init_completion(&cs42l43->device_detach);
1019
+
init_completion(&cs42l43->firmware_download);
1020
+
INIT_WORK(&cs42l43->boot_work, cs42l43_boot_work);
1021
+
1022
+
regcache_cache_only(cs42l43->regmap, true);
1023
+
1024
+
cs42l43->reset = devm_gpiod_get_optional(cs42l43->dev, "reset", GPIOD_OUT_LOW);
1025
+
if (IS_ERR(cs42l43->reset))
1026
+
return dev_err_probe(cs42l43->dev, PTR_ERR(cs42l43->reset),
1027
+
"Failed to get reset\n");
1028
+
1029
+
cs42l43->vdd_p = devm_regulator_get(cs42l43->dev, "vdd-p");
1030
+
if (IS_ERR(cs42l43->vdd_p))
1031
+
return dev_err_probe(cs42l43->dev, PTR_ERR(cs42l43->vdd_p),
1032
+
"Failed to get vdd-p\n");
1033
+
1034
+
cs42l43->vdd_d = devm_regulator_get(cs42l43->dev, "vdd-d");
1035
+
if (IS_ERR(cs42l43->vdd_d))
1036
+
return dev_err_probe(cs42l43->dev, PTR_ERR(cs42l43->vdd_d),
1037
+
"Failed to get vdd-d\n");
1038
+
1039
+
BUILD_BUG_ON(ARRAY_SIZE(cs42l43_core_supplies) != CS42L43_N_SUPPLIES);
1040
+
1041
+
for (i = 0; i < CS42L43_N_SUPPLIES; i++)
1042
+
cs42l43->core_supplies[i].supply = cs42l43_core_supplies[i];
1043
+
1044
+
ret = devm_regulator_bulk_get(cs42l43->dev, CS42L43_N_SUPPLIES,
1045
+
cs42l43->core_supplies);
1046
+
if (ret)
1047
+
return dev_err_probe(cs42l43->dev, ret,
1048
+
"Failed to get core supplies\n");
1049
+
1050
+
ret = cs42l43_power_up(cs42l43);
1051
+
if (ret)
1052
+
return ret;
1053
+
1054
+
pm_runtime_set_autosuspend_delay(cs42l43->dev, CS42L43_AUTOSUSPEND_TIME);
1055
+
pm_runtime_use_autosuspend(cs42l43->dev);
1056
+
pm_runtime_set_active(cs42l43->dev);
1057
+
/*
1058
+
* The device is already powered up, but keep it from suspending until
1059
+
* the boot work runs.
1060
+
*/
1061
+
pm_runtime_get_noresume(cs42l43->dev);
1062
+
devm_pm_runtime_enable(cs42l43->dev);
1063
+
1064
+
queue_work(system_long_wq, &cs42l43->boot_work);
1065
+
1066
+
return 0;
1067
+
}
1068
+
EXPORT_SYMBOL_NS_GPL(cs42l43_dev_probe, MFD_CS42L43);
1069
+
1070
+
void cs42l43_dev_remove(struct cs42l43 *cs42l43)
1071
+
{
1072
+
cs42l43_power_down(cs42l43);
1073
+
}
1074
+
EXPORT_SYMBOL_NS_GPL(cs42l43_dev_remove, MFD_CS42L43);
1075
+
1076
+
static int cs42l43_suspend(struct device *dev)
1077
+
{
1078
+
struct cs42l43 *cs42l43 = dev_get_drvdata(dev);
1079
+
int ret;
1080
+
1081
+
/*
1082
+
* Don't care about being resumed here, but the driver does want
1083
+
* force_resume to always trigger an actual resume, so that register
1084
+
* state for the MCU/GPIOs is returned as soon as possible after system
1085
+
* resume. force_resume will resume if the reference count is resumed on
1086
+
* suspend hence the get_noresume.
1087
+
*/
1088
+
pm_runtime_get_noresume(dev);
1089
+
1090
+
ret = pm_runtime_force_suspend(dev);
1091
+
if (ret) {
1092
+
dev_err(cs42l43->dev, "Failed to force suspend: %d\n", ret);
1093
+
pm_runtime_put_noidle(dev);
1094
+
return ret;
1095
+
}
1096
+
1097
+
pm_runtime_put_noidle(dev);
1098
+
1099
+
ret = cs42l43_power_down(cs42l43);
1100
+
if (ret)
1101
+
return ret;
1102
+
1103
+
return 0;
1104
+
}
1105
+
1106
+
static int cs42l43_resume(struct device *dev)
1107
+
{
1108
+
struct cs42l43 *cs42l43 = dev_get_drvdata(dev);
1109
+
int ret;
1110
+
1111
+
ret = cs42l43_power_up(cs42l43);
1112
+
if (ret)
1113
+
return ret;
1114
+
1115
+
ret = pm_runtime_force_resume(dev);
1116
+
if (ret) {
1117
+
dev_err(cs42l43->dev, "Failed to force resume: %d\n", ret);
1118
+
return ret;
1119
+
}
1120
+
1121
+
return 0;
1122
+
}
1123
+
1124
+
static int cs42l43_runtime_suspend(struct device *dev)
1125
+
{
1126
+
struct cs42l43 *cs42l43 = dev_get_drvdata(dev);
1127
+
1128
+
/*
1129
+
* Whilst the driver doesn't power the chip down here, going into runtime
1130
+
* suspend lets the SoundWire bus power down, which means the driver
1131
+
* can't communicate with the device any more.
1132
+
*/
1133
+
regcache_cache_only(cs42l43->regmap, true);
1134
+
1135
+
return 0;
1136
+
}
1137
+
1138
+
static int cs42l43_runtime_resume(struct device *dev)
1139
+
{
1140
+
struct cs42l43 *cs42l43 = dev_get_drvdata(dev);
1141
+
unsigned int reset_canary;
1142
+
int ret;
1143
+
1144
+
ret = cs42l43_wait_for_attach(cs42l43);
1145
+
if (ret)
1146
+
return ret;
1147
+
1148
+
ret = regmap_read(cs42l43->regmap, CS42L43_RELID, &reset_canary);
1149
+
if (ret) {
1150
+
dev_err(cs42l43->dev, "Failed to check reset canary: %d\n", ret);
1151
+
goto err;
1152
+
}
1153
+
1154
+
if (!reset_canary) {
1155
+
/*
1156
+
* If the canary has cleared the chip has reset, re-handle the
1157
+
* MCU and mark the cache as dirty to indicate the chip reset.
1158
+
*/
1159
+
ret = cs42l43_mcu_update(cs42l43);
1160
+
if (ret)
1161
+
goto err;
1162
+
1163
+
regcache_mark_dirty(cs42l43->regmap);
1164
+
}
1165
+
1166
+
ret = regcache_sync(cs42l43->regmap);
1167
+
if (ret) {
1168
+
dev_err(cs42l43->dev, "Failed to restore register cache: %d\n", ret);
1169
+
goto err;
1170
+
}
1171
+
1172
+
return 0;
1173
+
1174
+
err:
1175
+
regcache_cache_only(cs42l43->regmap, true);
1176
+
1177
+
return ret;
1178
+
}
1179
+
1180
+
EXPORT_NS_GPL_DEV_PM_OPS(cs42l43_pm_ops, MFD_CS42L43) = {
1181
+
SET_SYSTEM_SLEEP_PM_OPS(cs42l43_suspend, cs42l43_resume)
1182
+
SET_RUNTIME_PM_OPS(cs42l43_runtime_suspend, cs42l43_runtime_resume, NULL)
1183
+
};
1184
+
1185
+
MODULE_DESCRIPTION("CS42L43 Core Driver");
1186
+
MODULE_AUTHOR("Charles Keepax <ckeepax@opensource.cirrus.com>");
1187
+
MODULE_LICENSE("GPL");
1188
+
MODULE_FIRMWARE("cs42l43.bin");
+28
drivers/mfd/cs42l43.h
+28
drivers/mfd/cs42l43.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* CS42L43 core driver internal data
4
+
*
5
+
* Copyright (C) 2022-2023 Cirrus Logic, Inc. and
6
+
* Cirrus Logic International Semiconductor Ltd.
7
+
*/
8
+
9
+
#include <linux/mfd/cs42l43.h>
10
+
#include <linux/pm.h>
11
+
#include <linux/regmap.h>
12
+
13
+
#ifndef CS42L43_CORE_INT_H
14
+
#define CS42L43_CORE_INT_H
15
+
16
+
#define CS42L43_N_DEFAULTS 176
17
+
18
+
extern const struct dev_pm_ops cs42l43_pm_ops;
19
+
extern const struct reg_default cs42l43_reg_default[CS42L43_N_DEFAULTS];
20
+
21
+
bool cs42l43_readable_register(struct device *dev, unsigned int reg);
22
+
bool cs42l43_precious_register(struct device *dev, unsigned int reg);
23
+
bool cs42l43_volatile_register(struct device *dev, unsigned int reg);
24
+
25
+
int cs42l43_dev_probe(struct cs42l43 *cs42l43);
26
+
void cs42l43_dev_remove(struct cs42l43 *cs42l43);
27
+
28
+
#endif /* CS42L43_CORE_INT_H */
+1184
include/linux/mfd/cs42l43-regs.h
+1184
include/linux/mfd/cs42l43-regs.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* cs42l43 register definitions
4
+
*
5
+
* Copyright (c) 2022-2023 Cirrus Logic, Inc. and
6
+
* Cirrus Logic International Semiconductor Ltd.
7
+
*/
8
+
9
+
#ifndef CS42L43_CORE_REGS_H
10
+
#define CS42L43_CORE_REGS_H
11
+
12
+
/* Registers */
13
+
#define CS42L43_GEN_INT_STAT_1 0x000000C0
14
+
#define CS42L43_GEN_INT_MASK_1 0x000000C1
15
+
#define CS42L43_DEVID 0x00003000
16
+
#define CS42L43_REVID 0x00003004
17
+
#define CS42L43_RELID 0x0000300C
18
+
#define CS42L43_SFT_RESET 0x00003020
19
+
#define CS42L43_DRV_CTRL1 0x00006004
20
+
#define CS42L43_DRV_CTRL3 0x0000600C
21
+
#define CS42L43_DRV_CTRL4 0x00006010
22
+
#define CS42L43_DRV_CTRL_5 0x00006014
23
+
#define CS42L43_GPIO_CTRL1 0x00006034
24
+
#define CS42L43_GPIO_CTRL2 0x00006038
25
+
#define CS42L43_GPIO_STS 0x0000603C
26
+
#define CS42L43_GPIO_FN_SEL 0x00006040
27
+
#define CS42L43_MCLK_SRC_SEL 0x00007004
28
+
#define CS42L43_CCM_BLK_CLK_CONTROL 0x00007010
29
+
#define CS42L43_SAMPLE_RATE1 0x00007014
30
+
#define CS42L43_SAMPLE_RATE2 0x00007018
31
+
#define CS42L43_SAMPLE_RATE3 0x0000701C
32
+
#define CS42L43_SAMPLE_RATE4 0x00007020
33
+
#define CS42L43_PLL_CONTROL 0x00007034
34
+
#define CS42L43_FS_SELECT1 0x00007038
35
+
#define CS42L43_FS_SELECT2 0x0000703C
36
+
#define CS42L43_FS_SELECT3 0x00007040
37
+
#define CS42L43_FS_SELECT4 0x00007044
38
+
#define CS42L43_PDM_CONTROL 0x0000704C
39
+
#define CS42L43_ASP_CLK_CONFIG1 0x00007058
40
+
#define CS42L43_ASP_CLK_CONFIG2 0x0000705C
41
+
#define CS42L43_OSC_DIV_SEL 0x00007068
42
+
#define CS42L43_ADC_B_CTRL1 0x00008000
43
+
#define CS42L43_ADC_B_CTRL2 0x00008004
44
+
#define CS42L43_DECIM_HPF_WNF_CTRL1 0x0000803C
45
+
#define CS42L43_DECIM_HPF_WNF_CTRL2 0x00008040
46
+
#define CS42L43_DECIM_HPF_WNF_CTRL3 0x00008044
47
+
#define CS42L43_DECIM_HPF_WNF_CTRL4 0x00008048
48
+
#define CS42L43_DMIC_PDM_CTRL 0x0000804C
49
+
#define CS42L43_DECIM_VOL_CTRL_CH1_CH2 0x00008050
50
+
#define CS42L43_DECIM_VOL_CTRL_CH3_CH4 0x00008054
51
+
#define CS42L43_DECIM_VOL_CTRL_UPDATE 0x00008058
52
+
#define CS42L43_INTP_VOLUME_CTRL1 0x00009008
53
+
#define CS42L43_INTP_VOLUME_CTRL2 0x0000900C
54
+
#define CS42L43_AMP1_2_VOL_RAMP 0x00009010
55
+
#define CS42L43_ASP_CTRL 0x0000A000
56
+
#define CS42L43_ASP_FSYNC_CTRL1 0x0000A004
57
+
#define CS42L43_ASP_FSYNC_CTRL2 0x0000A008
58
+
#define CS42L43_ASP_FSYNC_CTRL3 0x0000A00C
59
+
#define CS42L43_ASP_FSYNC_CTRL4 0x0000A010
60
+
#define CS42L43_ASP_DATA_CTRL 0x0000A018
61
+
#define CS42L43_ASP_RX_EN 0x0000A020
62
+
#define CS42L43_ASP_TX_EN 0x0000A024
63
+
#define CS42L43_ASP_RX_CH1_CTRL 0x0000A028
64
+
#define CS42L43_ASP_RX_CH2_CTRL 0x0000A02C
65
+
#define CS42L43_ASP_RX_CH3_CTRL 0x0000A030
66
+
#define CS42L43_ASP_RX_CH4_CTRL 0x0000A034
67
+
#define CS42L43_ASP_RX_CH5_CTRL 0x0000A038
68
+
#define CS42L43_ASP_RX_CH6_CTRL 0x0000A03C
69
+
#define CS42L43_ASP_TX_CH1_CTRL 0x0000A068
70
+
#define CS42L43_ASP_TX_CH2_CTRL 0x0000A06C
71
+
#define CS42L43_ASP_TX_CH3_CTRL 0x0000A070
72
+
#define CS42L43_ASP_TX_CH4_CTRL 0x0000A074
73
+
#define CS42L43_ASP_TX_CH5_CTRL 0x0000A078
74
+
#define CS42L43_ASP_TX_CH6_CTRL 0x0000A07C
75
+
#define CS42L43_OTP_REVISION_ID 0x0000B02C
76
+
#define CS42L43_ASPTX1_INPUT 0x0000C200
77
+
#define CS42L43_ASPTX2_INPUT 0x0000C210
78
+
#define CS42L43_ASPTX3_INPUT 0x0000C220
79
+
#define CS42L43_ASPTX4_INPUT 0x0000C230
80
+
#define CS42L43_ASPTX5_INPUT 0x0000C240
81
+
#define CS42L43_ASPTX6_INPUT 0x0000C250
82
+
#define CS42L43_SWIRE_DP1_CH1_INPUT 0x0000C280
83
+
#define CS42L43_SWIRE_DP1_CH2_INPUT 0x0000C290
84
+
#define CS42L43_SWIRE_DP1_CH3_INPUT 0x0000C2A0
85
+
#define CS42L43_SWIRE_DP1_CH4_INPUT 0x0000C2B0
86
+
#define CS42L43_SWIRE_DP2_CH1_INPUT 0x0000C2C0
87
+
#define CS42L43_SWIRE_DP2_CH2_INPUT 0x0000C2D0
88
+
#define CS42L43_SWIRE_DP3_CH1_INPUT 0x0000C2E0
89
+
#define CS42L43_SWIRE_DP3_CH2_INPUT 0x0000C2F0
90
+
#define CS42L43_SWIRE_DP4_CH1_INPUT 0x0000C300
91
+
#define CS42L43_SWIRE_DP4_CH2_INPUT 0x0000C310
92
+
#define CS42L43_ASRC_INT1_INPUT1 0x0000C400
93
+
#define CS42L43_ASRC_INT2_INPUT1 0x0000C410
94
+
#define CS42L43_ASRC_INT3_INPUT1 0x0000C420
95
+
#define CS42L43_ASRC_INT4_INPUT1 0x0000C430
96
+
#define CS42L43_ASRC_DEC1_INPUT1 0x0000C440
97
+
#define CS42L43_ASRC_DEC2_INPUT1 0x0000C450
98
+
#define CS42L43_ASRC_DEC3_INPUT1 0x0000C460
99
+
#define CS42L43_ASRC_DEC4_INPUT1 0x0000C470
100
+
#define CS42L43_ISRC1INT1_INPUT1 0x0000C500
101
+
#define CS42L43_ISRC1INT2_INPUT1 0x0000C510
102
+
#define CS42L43_ISRC1DEC1_INPUT1 0x0000C520
103
+
#define CS42L43_ISRC1DEC2_INPUT1 0x0000C530
104
+
#define CS42L43_ISRC2INT1_INPUT1 0x0000C540
105
+
#define CS42L43_ISRC2INT2_INPUT1 0x0000C550
106
+
#define CS42L43_ISRC2DEC1_INPUT1 0x0000C560
107
+
#define CS42L43_ISRC2DEC2_INPUT1 0x0000C570
108
+
#define CS42L43_EQ1MIX_INPUT1 0x0000C580
109
+
#define CS42L43_EQ1MIX_INPUT2 0x0000C584
110
+
#define CS42L43_EQ1MIX_INPUT3 0x0000C588
111
+
#define CS42L43_EQ1MIX_INPUT4 0x0000C58C
112
+
#define CS42L43_EQ2MIX_INPUT1 0x0000C590
113
+
#define CS42L43_EQ2MIX_INPUT2 0x0000C594
114
+
#define CS42L43_EQ2MIX_INPUT3 0x0000C598
115
+
#define CS42L43_EQ2MIX_INPUT4 0x0000C59C
116
+
#define CS42L43_SPDIF1_INPUT1 0x0000C600
117
+
#define CS42L43_SPDIF2_INPUT1 0x0000C610
118
+
#define CS42L43_AMP1MIX_INPUT1 0x0000C620
119
+
#define CS42L43_AMP1MIX_INPUT2 0x0000C624
120
+
#define CS42L43_AMP1MIX_INPUT3 0x0000C628
121
+
#define CS42L43_AMP1MIX_INPUT4 0x0000C62C
122
+
#define CS42L43_AMP2MIX_INPUT1 0x0000C630
123
+
#define CS42L43_AMP2MIX_INPUT2 0x0000C634
124
+
#define CS42L43_AMP2MIX_INPUT3 0x0000C638
125
+
#define CS42L43_AMP2MIX_INPUT4 0x0000C63C
126
+
#define CS42L43_AMP3MIX_INPUT1 0x0000C640
127
+
#define CS42L43_AMP3MIX_INPUT2 0x0000C644
128
+
#define CS42L43_AMP3MIX_INPUT3 0x0000C648
129
+
#define CS42L43_AMP3MIX_INPUT4 0x0000C64C
130
+
#define CS42L43_AMP4MIX_INPUT1 0x0000C650
131
+
#define CS42L43_AMP4MIX_INPUT2 0x0000C654
132
+
#define CS42L43_AMP4MIX_INPUT3 0x0000C658
133
+
#define CS42L43_AMP4MIX_INPUT4 0x0000C65C
134
+
#define CS42L43_ASRC_INT_ENABLES 0x0000E000
135
+
#define CS42L43_ASRC_DEC_ENABLES 0x0000E004
136
+
#define CS42L43_PDNCNTL 0x00010000
137
+
#define CS42L43_RINGSENSE_DEB_CTRL 0x0001001C
138
+
#define CS42L43_TIPSENSE_DEB_CTRL 0x00010020
139
+
#define CS42L43_TIP_RING_SENSE_INTERRUPT_STATUS 0x00010028
140
+
#define CS42L43_HS2 0x00010040
141
+
#define CS42L43_HS_STAT 0x00010048
142
+
#define CS42L43_MCU_SW_INTERRUPT 0x00010094
143
+
#define CS42L43_STEREO_MIC_CTRL 0x000100A4
144
+
#define CS42L43_STEREO_MIC_CLAMP_CTRL 0x000100C4
145
+
#define CS42L43_BLOCK_EN2 0x00010104
146
+
#define CS42L43_BLOCK_EN3 0x00010108
147
+
#define CS42L43_BLOCK_EN4 0x0001010C
148
+
#define CS42L43_BLOCK_EN5 0x00010110
149
+
#define CS42L43_BLOCK_EN6 0x00010114
150
+
#define CS42L43_BLOCK_EN7 0x00010118
151
+
#define CS42L43_BLOCK_EN8 0x0001011C
152
+
#define CS42L43_BLOCK_EN9 0x00010120
153
+
#define CS42L43_BLOCK_EN10 0x00010124
154
+
#define CS42L43_BLOCK_EN11 0x00010128
155
+
#define CS42L43_TONE_CH1_CTRL 0x00010134
156
+
#define CS42L43_TONE_CH2_CTRL 0x00010138
157
+
#define CS42L43_MIC_DETECT_CONTROL_1 0x00011074
158
+
#define CS42L43_DETECT_STATUS_1 0x0001107C
159
+
#define CS42L43_HS_BIAS_SENSE_AND_CLAMP_AUTOCONTROL 0x00011090
160
+
#define CS42L43_MIC_DETECT_CONTROL_ANDROID 0x000110B0
161
+
#define CS42L43_ISRC1_CTRL 0x00012004
162
+
#define CS42L43_ISRC2_CTRL 0x00013004
163
+
#define CS42L43_CTRL_REG 0x00014000
164
+
#define CS42L43_FDIV_FRAC 0x00014004
165
+
#define CS42L43_CAL_RATIO 0x00014008
166
+
#define CS42L43_SPI_CLK_CONFIG1 0x00016004
167
+
#define CS42L43_SPI_CONFIG1 0x00016010
168
+
#define CS42L43_SPI_CONFIG2 0x00016014
169
+
#define CS42L43_SPI_CONFIG3 0x00016018
170
+
#define CS42L43_SPI_CONFIG4 0x00016024
171
+
#define CS42L43_SPI_STATUS1 0x00016100
172
+
#define CS42L43_SPI_STATUS2 0x00016104
173
+
#define CS42L43_TRAN_CONFIG1 0x00016200
174
+
#define CS42L43_TRAN_CONFIG2 0x00016204
175
+
#define CS42L43_TRAN_CONFIG3 0x00016208
176
+
#define CS42L43_TRAN_CONFIG4 0x0001620C
177
+
#define CS42L43_TRAN_CONFIG5 0x00016220
178
+
#define CS42L43_TRAN_CONFIG6 0x00016224
179
+
#define CS42L43_TRAN_CONFIG7 0x00016228
180
+
#define CS42L43_TRAN_CONFIG8 0x0001622C
181
+
#define CS42L43_TRAN_STATUS1 0x00016300
182
+
#define CS42L43_TRAN_STATUS2 0x00016304
183
+
#define CS42L43_TRAN_STATUS3 0x00016308
184
+
#define CS42L43_TX_DATA 0x00016400
185
+
#define CS42L43_RX_DATA 0x00016600
186
+
#define CS42L43_DACCNFG1 0x00017000
187
+
#define CS42L43_DACCNFG2 0x00017004
188
+
#define CS42L43_HPPATHVOL 0x0001700C
189
+
#define CS42L43_PGAVOL 0x00017014
190
+
#define CS42L43_LOADDETRESULTS 0x00017018
191
+
#define CS42L43_LOADDETENA 0x00017024
192
+
#define CS42L43_CTRL 0x00017028
193
+
#define CS42L43_COEFF_DATA_IN0 0x00018000
194
+
#define CS42L43_COEFF_RD_WR0 0x00018008
195
+
#define CS42L43_INIT_DONE0 0x00018010
196
+
#define CS42L43_START_EQZ0 0x00018014
197
+
#define CS42L43_MUTE_EQ_IN0 0x0001801C
198
+
#define CS42L43_DECIM_INT 0x0001B000
199
+
#define CS42L43_EQ_INT 0x0001B004
200
+
#define CS42L43_ASP_INT 0x0001B008
201
+
#define CS42L43_PLL_INT 0x0001B00C
202
+
#define CS42L43_SOFT_INT 0x0001B010
203
+
#define CS42L43_SWIRE_INT 0x0001B014
204
+
#define CS42L43_MSM_INT 0x0001B018
205
+
#define CS42L43_ACC_DET_INT 0x0001B01C
206
+
#define CS42L43_I2C_TGT_INT 0x0001B020
207
+
#define CS42L43_SPI_MSTR_INT 0x0001B024
208
+
#define CS42L43_SW_TO_SPI_BRIDGE_INT 0x0001B028
209
+
#define CS42L43_OTP_INT 0x0001B02C
210
+
#define CS42L43_CLASS_D_AMP_INT 0x0001B030
211
+
#define CS42L43_GPIO_INT 0x0001B034
212
+
#define CS42L43_ASRC_INT 0x0001B038
213
+
#define CS42L43_HPOUT_INT 0x0001B03C
214
+
#define CS42L43_DECIM_MASK 0x0001B0A0
215
+
#define CS42L43_EQ_MIX_MASK 0x0001B0A4
216
+
#define CS42L43_ASP_MASK 0x0001B0A8
217
+
#define CS42L43_PLL_MASK 0x0001B0AC
218
+
#define CS42L43_SOFT_MASK 0x0001B0B0
219
+
#define CS42L43_SWIRE_MASK 0x0001B0B4
220
+
#define CS42L43_MSM_MASK 0x0001B0B8
221
+
#define CS42L43_ACC_DET_MASK 0x0001B0BC
222
+
#define CS42L43_I2C_TGT_MASK 0x0001B0C0
223
+
#define CS42L43_SPI_MSTR_MASK 0x0001B0C4
224
+
#define CS42L43_SW_TO_SPI_BRIDGE_MASK 0x0001B0C8
225
+
#define CS42L43_OTP_MASK 0x0001B0CC
226
+
#define CS42L43_CLASS_D_AMP_MASK 0x0001B0D0
227
+
#define CS42L43_GPIO_INT_MASK 0x0001B0D4
228
+
#define CS42L43_ASRC_MASK 0x0001B0D8
229
+
#define CS42L43_HPOUT_MASK 0x0001B0DC
230
+
#define CS42L43_DECIM_INT_SHADOW 0x0001B300
231
+
#define CS42L43_EQ_MIX_INT_SHADOW 0x0001B304
232
+
#define CS42L43_ASP_INT_SHADOW 0x0001B308
233
+
#define CS42L43_PLL_INT_SHADOW 0x0001B30C
234
+
#define CS42L43_SOFT_INT_SHADOW 0x0001B310
235
+
#define CS42L43_SWIRE_INT_SHADOW 0x0001B314
236
+
#define CS42L43_MSM_INT_SHADOW 0x0001B318
237
+
#define CS42L43_ACC_DET_INT_SHADOW 0x0001B31C
238
+
#define CS42L43_I2C_TGT_INT_SHADOW 0x0001B320
239
+
#define CS42L43_SPI_MSTR_INT_SHADOW 0x0001B324
240
+
#define CS42L43_SW_TO_SPI_BRIDGE_SHADOW 0x0001B328
241
+
#define CS42L43_OTP_INT_SHADOW 0x0001B32C
242
+
#define CS42L43_CLASS_D_AMP_INT_SHADOW 0x0001B330
243
+
#define CS42L43_GPIO_SHADOW 0x0001B334
244
+
#define CS42L43_ASRC_SHADOW 0x0001B338
245
+
#define CS42L43_HP_OUT_SHADOW 0x0001B33C
246
+
#define CS42L43_BOOT_CONTROL 0x00101000
247
+
#define CS42L43_BLOCK_EN 0x00101008
248
+
#define CS42L43_SHUTTER_CONTROL 0x0010100C
249
+
#define CS42L43_MCU_SW_REV 0x00114000
250
+
#define CS42L43_PATCH_START_ADDR 0x00114004
251
+
#define CS42L43_NEED_CONFIGS 0x0011400C
252
+
#define CS42L43_BOOT_STATUS 0x0011401C
253
+
#define CS42L43_FW_SH_BOOT_CFG_NEED_CONFIGS 0x0011F8F8
254
+
#define CS42L43_FW_MISSION_CTRL_NEED_CONFIGS 0x0011FE00
255
+
#define CS42L43_FW_MISSION_CTRL_HAVE_CONFIGS 0x0011FE04
256
+
#define CS42L43_FW_MISSION_CTRL_MM_CTRL_SELECTION 0x0011FE0C
257
+
#define CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_REG 0x0011FE10
258
+
#define CS42L43_MCU_RAM_MAX 0x0011FFFF
259
+
260
+
/* CS42L43_DEVID */
261
+
#define CS42L43_DEVID_VAL 0x00042A43
262
+
263
+
/* CS42L43_GEN_INT_STAT_1 */
264
+
#define CS42L43_INT_STAT_GEN1_MASK 0x00000001
265
+
#define CS42L43_INT_STAT_GEN1_SHIFT 0
266
+
267
+
/* CS42L43_SFT_RESET */
268
+
#define CS42L43_SFT_RESET_MASK 0xFF000000
269
+
#define CS42L43_SFT_RESET_SHIFT 24
270
+
271
+
#define CS42L43_SFT_RESET_VAL 0x5A000000
272
+
273
+
/* CS42L43_DRV_CTRL1 */
274
+
#define CS42L43_ASP_DOUT_DRV_MASK 0x00038000
275
+
#define CS42L43_ASP_DOUT_DRV_SHIFT 15
276
+
#define CS42L43_ASP_FSYNC_DRV_MASK 0x00000E00
277
+
#define CS42L43_ASP_FSYNC_DRV_SHIFT 9
278
+
#define CS42L43_ASP_BCLK_DRV_MASK 0x000001C0
279
+
#define CS42L43_ASP_BCLK_DRV_SHIFT 6
280
+
281
+
/* CS42L43_DRV_CTRL3 */
282
+
#define CS42L43_I2C_ADDR_DRV_MASK 0x30000000
283
+
#define CS42L43_I2C_ADDR_DRV_SHIFT 28
284
+
#define CS42L43_I2C_SDA_DRV_MASK 0x0C000000
285
+
#define CS42L43_I2C_SDA_DRV_SHIFT 26
286
+
#define CS42L43_PDMOUT2_CLK_DRV_MASK 0x00E00000
287
+
#define CS42L43_PDMOUT2_CLK_DRV_SHIFT 21
288
+
#define CS42L43_PDMOUT2_DATA_DRV_MASK 0x001C0000
289
+
#define CS42L43_PDMOUT2_DATA_DRV_SHIFT 18
290
+
#define CS42L43_PDMOUT1_CLK_DRV_MASK 0x00038000
291
+
#define CS42L43_PDMOUT1_CLK_DRV_SHIFT 15
292
+
#define CS42L43_PDMOUT1_DATA_DRV_MASK 0x00007000
293
+
#define CS42L43_PDMOUT1_DATA_DRV_SHIFT 12
294
+
#define CS42L43_SPI_MISO_DRV_MASK 0x00000038
295
+
#define CS42L43_SPI_MISO_DRV_SHIFT 3
296
+
297
+
/* CS42L43_DRV_CTRL4 */
298
+
#define CS42L43_GPIO3_DRV_MASK 0x00000E00
299
+
#define CS42L43_GPIO3_DRV_SHIFT 9
300
+
#define CS42L43_GPIO2_DRV_MASK 0x000001C0
301
+
#define CS42L43_GPIO2_DRV_SHIFT 6
302
+
#define CS42L43_GPIO1_DRV_MASK 0x00000038
303
+
#define CS42L43_GPIO1_DRV_SHIFT 3
304
+
305
+
/* CS42L43_DRV_CTRL_5 */
306
+
#define CS42L43_I2C_SCL_DRV_MASK 0x18000000
307
+
#define CS42L43_I2C_SCL_DRV_SHIFT 27
308
+
#define CS42L43_SPI_SCK_DRV_MASK 0x07000000
309
+
#define CS42L43_SPI_SCK_DRV_SHIFT 24
310
+
#define CS42L43_SPI_MOSI_DRV_MASK 0x00E00000
311
+
#define CS42L43_SPI_MOSI_DRV_SHIFT 21
312
+
#define CS42L43_SPI_SSB_DRV_MASK 0x001C0000
313
+
#define CS42L43_SPI_SSB_DRV_SHIFT 18
314
+
#define CS42L43_ASP_DIN_DRV_MASK 0x000001C0
315
+
#define CS42L43_ASP_DIN_DRV_SHIFT 6
316
+
317
+
/* CS42L43_GPIO_CTRL1 */
318
+
#define CS42L43_GPIO3_POL_MASK 0x00040000
319
+
#define CS42L43_GPIO3_POL_SHIFT 18
320
+
#define CS42L43_GPIO2_POL_MASK 0x00020000
321
+
#define CS42L43_GPIO2_POL_SHIFT 17
322
+
#define CS42L43_GPIO1_POL_MASK 0x00010000
323
+
#define CS42L43_GPIO1_POL_SHIFT 16
324
+
#define CS42L43_GPIO3_LVL_MASK 0x00000400
325
+
#define CS42L43_GPIO3_LVL_SHIFT 10
326
+
#define CS42L43_GPIO2_LVL_MASK 0x00000200
327
+
#define CS42L43_GPIO2_LVL_SHIFT 9
328
+
#define CS42L43_GPIO1_LVL_MASK 0x00000100
329
+
#define CS42L43_GPIO1_LVL_SHIFT 8
330
+
#define CS42L43_GPIO3_DIR_MASK 0x00000004
331
+
#define CS42L43_GPIO3_DIR_SHIFT 2
332
+
#define CS42L43_GPIO2_DIR_MASK 0x00000002
333
+
#define CS42L43_GPIO2_DIR_SHIFT 1
334
+
#define CS42L43_GPIO1_DIR_MASK 0x00000001
335
+
#define CS42L43_GPIO1_DIR_SHIFT 0
336
+
337
+
/* CS42L43_GPIO_CTRL2 */
338
+
#define CS42L43_GPIO3_DEGLITCH_BYP_MASK 0x00000004
339
+
#define CS42L43_GPIO3_DEGLITCH_BYP_SHIFT 2
340
+
#define CS42L43_GPIO2_DEGLITCH_BYP_MASK 0x00000002
341
+
#define CS42L43_GPIO2_DEGLITCH_BYP_SHIFT 1
342
+
#define CS42L43_GPIO1_DEGLITCH_BYP_MASK 0x00000001
343
+
#define CS42L43_GPIO1_DEGLITCH_BYP_SHIFT 0
344
+
345
+
/* CS42L43_GPIO_STS */
346
+
#define CS42L43_GPIO3_STS_MASK 0x00000004
347
+
#define CS42L43_GPIO3_STS_SHIFT 2
348
+
#define CS42L43_GPIO2_STS_MASK 0x00000002
349
+
#define CS42L43_GPIO2_STS_SHIFT 1
350
+
#define CS42L43_GPIO1_STS_MASK 0x00000001
351
+
#define CS42L43_GPIO1_STS_SHIFT 0
352
+
353
+
/* CS42L43_GPIO_FN_SEL */
354
+
#define CS42L43_GPIO3_FN_SEL_MASK 0x00000004
355
+
#define CS42L43_GPIO3_FN_SEL_SHIFT 2
356
+
#define CS42L43_GPIO1_FN_SEL_MASK 0x00000001
357
+
#define CS42L43_GPIO1_FN_SEL_SHIFT 0
358
+
359
+
/* CS42L43_MCLK_SRC_SEL */
360
+
#define CS42L43_OSC_PLL_MCLK_SEL_MASK 0x00000001
361
+
#define CS42L43_OSC_PLL_MCLK_SEL_SHIFT 0
362
+
363
+
/* CS42L43_SAMPLE_RATE1..CS42L43_SAMPLE_RATE4 */
364
+
#define CS42L43_SAMPLE_RATE_MASK 0x0000001F
365
+
#define CS42L43_SAMPLE_RATE_SHIFT 0
366
+
367
+
/* CS42L43_PLL_CONTROL */
368
+
#define CS42L43_PLL_REFCLK_EN_MASK 0x00000008
369
+
#define CS42L43_PLL_REFCLK_EN_SHIFT 3
370
+
#define CS42L43_PLL_REFCLK_DIV_MASK 0x00000006
371
+
#define CS42L43_PLL_REFCLK_DIV_SHIFT 1
372
+
#define CS42L43_PLL_REFCLK_SRC_MASK 0x00000001
373
+
#define CS42L43_PLL_REFCLK_SRC_SHIFT 0
374
+
375
+
/* CS42L43_FS_SELECT1 */
376
+
#define CS42L43_ASP_RATE_MASK 0x00000003
377
+
#define CS42L43_ASP_RATE_SHIFT 0
378
+
379
+
/* CS42L43_FS_SELECT2 */
380
+
#define CS42L43_ASRC_DEC_OUT_RATE_MASK 0x000000C0
381
+
#define CS42L43_ASRC_DEC_OUT_RATE_SHIFT 6
382
+
#define CS42L43_ASRC_INT_OUT_RATE_MASK 0x00000030
383
+
#define CS42L43_ASRC_INT_OUT_RATE_SHIFT 4
384
+
#define CS42L43_ASRC_DEC_IN_RATE_MASK 0x0000000C
385
+
#define CS42L43_ASRC_DEC_IN_RATE_SHIFT 2
386
+
#define CS42L43_ASRC_INT_IN_RATE_MASK 0x00000003
387
+
#define CS42L43_ASRC_INT_IN_RATE_SHIFT 0
388
+
389
+
/* CS42L43_FS_SELECT3 */
390
+
#define CS42L43_HPOUT_RATE_MASK 0x0000C000
391
+
#define CS42L43_HPOUT_RATE_SHIFT 14
392
+
#define CS42L43_EQZ_RATE_MASK 0x00003000
393
+
#define CS42L43_EQZ_RATE_SHIFT 12
394
+
#define CS42L43_DIAGGEN_RATE_MASK 0x00000C00
395
+
#define CS42L43_DIAGGEN_RATE_SHIFT 10
396
+
#define CS42L43_DECIM_CH4_RATE_MASK 0x00000300
397
+
#define CS42L43_DECIM_CH4_RATE_SHIFT 8
398
+
#define CS42L43_DECIM_CH3_RATE_MASK 0x000000C0
399
+
#define CS42L43_DECIM_CH3_RATE_SHIFT 6
400
+
#define CS42L43_DECIM_CH2_RATE_MASK 0x00000030
401
+
#define CS42L43_DECIM_CH2_RATE_SHIFT 4
402
+
#define CS42L43_DECIM_CH1_RATE_MASK 0x0000000C
403
+
#define CS42L43_DECIM_CH1_RATE_SHIFT 2
404
+
#define CS42L43_AMP1_2_RATE_MASK 0x00000003
405
+
#define CS42L43_AMP1_2_RATE_SHIFT 0
406
+
407
+
/* CS42L43_FS_SELECT4 */
408
+
#define CS42L43_SW_DP7_RATE_MASK 0x00C00000
409
+
#define CS42L43_SW_DP7_RATE_SHIFT 22
410
+
#define CS42L43_SW_DP6_RATE_MASK 0x00300000
411
+
#define CS42L43_SW_DP6_RATE_SHIFT 20
412
+
#define CS42L43_SPDIF_RATE_MASK 0x000C0000
413
+
#define CS42L43_SPDIF_RATE_SHIFT 18
414
+
#define CS42L43_SW_DP5_RATE_MASK 0x00030000
415
+
#define CS42L43_SW_DP5_RATE_SHIFT 16
416
+
#define CS42L43_SW_DP4_RATE_MASK 0x0000C000
417
+
#define CS42L43_SW_DP4_RATE_SHIFT 14
418
+
#define CS42L43_SW_DP3_RATE_MASK 0x00003000
419
+
#define CS42L43_SW_DP3_RATE_SHIFT 12
420
+
#define CS42L43_SW_DP2_RATE_MASK 0x00000C00
421
+
#define CS42L43_SW_DP2_RATE_SHIFT 10
422
+
#define CS42L43_SW_DP1_RATE_MASK 0x00000300
423
+
#define CS42L43_SW_DP1_RATE_SHIFT 8
424
+
#define CS42L43_ISRC2_LOW_RATE_MASK 0x000000C0
425
+
#define CS42L43_ISRC2_LOW_RATE_SHIFT 6
426
+
#define CS42L43_ISRC2_HIGH_RATE_MASK 0x00000030
427
+
#define CS42L43_ISRC2_HIGH_RATE_SHIFT 4
428
+
#define CS42L43_ISRC1_LOW_RATE_MASK 0x0000000C
429
+
#define CS42L43_ISRC1_LOW_RATE_SHIFT 2
430
+
#define CS42L43_ISRC1_HIGH_RATE_MASK 0x00000003
431
+
#define CS42L43_ISRC1_HIGH_RATE_SHIFT 0
432
+
433
+
/* CS42L43_PDM_CONTROL */
434
+
#define CS42L43_PDM2_CLK_DIV_MASK 0x0000000C
435
+
#define CS42L43_PDM2_CLK_DIV_SHIFT 2
436
+
#define CS42L43_PDM1_CLK_DIV_MASK 0x00000003
437
+
#define CS42L43_PDM1_CLK_DIV_SHIFT 0
438
+
439
+
/* CS42L43_ASP_CLK_CONFIG1 */
440
+
#define CS42L43_ASP_BCLK_N_MASK 0x03FF0000
441
+
#define CS42L43_ASP_BCLK_N_SHIFT 16
442
+
#define CS42L43_ASP_BCLK_M_MASK 0x000003FF
443
+
#define CS42L43_ASP_BCLK_M_SHIFT 0
444
+
445
+
/* CS42L43_ASP_CLK_CONFIG2 */
446
+
#define CS42L43_ASP_MASTER_MODE_MASK 0x00000002
447
+
#define CS42L43_ASP_MASTER_MODE_SHIFT 1
448
+
#define CS42L43_ASP_BCLK_INV_MASK 0x00000001
449
+
#define CS42L43_ASP_BCLK_INV_SHIFT 0
450
+
451
+
/* CS42L43_OSC_DIV_SEL */
452
+
#define CS42L43_OSC_DIV2_EN_MASK 0x00000001
453
+
#define CS42L43_OSC_DIV2_EN_SHIFT 0
454
+
455
+
/* CS42L43_ADC_B_CTRL1..CS42L43_ADC_B_CTRL1 */
456
+
#define CS42L43_PGA_WIDESWING_MODE_EN_MASK 0x00000080
457
+
#define CS42L43_PGA_WIDESWING_MODE_EN_SHIFT 7
458
+
#define CS42L43_ADC_AIN_SEL_MASK 0x00000010
459
+
#define CS42L43_ADC_AIN_SEL_SHIFT 4
460
+
#define CS42L43_ADC_PGA_GAIN_MASK 0x0000000F
461
+
#define CS42L43_ADC_PGA_GAIN_SHIFT 0
462
+
463
+
/* CS42L43_DECIM_HPF_WNF_CTRL1..CS42L43_DECIM_HPF_WNF_CTRL4 */
464
+
#define CS42L43_DECIM_WNF_CF_MASK 0x00000070
465
+
#define CS42L43_DECIM_WNF_CF_SHIFT 4
466
+
#define CS42L43_DECIM_WNF_EN_MASK 0x00000008
467
+
#define CS42L43_DECIM_WNF_EN_SHIFT 3
468
+
#define CS42L43_DECIM_HPF_CF_MASK 0x00000006
469
+
#define CS42L43_DECIM_HPF_CF_SHIFT 1
470
+
#define CS42L43_DECIM_HPF_EN_MASK 0x00000001
471
+
#define CS42L43_DECIM_HPF_EN_SHIFT 0
472
+
473
+
/* CS42L43_DMIC_PDM_CTRL */
474
+
#define CS42L43_PDM2R_INV_MASK 0x00000020
475
+
#define CS42L43_PDM2R_INV_SHIFT 5
476
+
#define CS42L43_PDM2L_INV_MASK 0x00000010
477
+
#define CS42L43_PDM2L_INV_SHIFT 4
478
+
#define CS42L43_PDM1R_INV_MASK 0x00000008
479
+
#define CS42L43_PDM1R_INV_SHIFT 3
480
+
#define CS42L43_PDM1L_INV_MASK 0x00000004
481
+
#define CS42L43_PDM1L_INV_SHIFT 2
482
+
483
+
/* CS42L43_DECIM_VOL_CTRL_CH1_CH2 */
484
+
#define CS42L43_DECIM2_MUTE_MASK 0x80000000
485
+
#define CS42L43_DECIM2_MUTE_SHIFT 31
486
+
#define CS42L43_DECIM2_VOL_MASK 0x3FC00000
487
+
#define CS42L43_DECIM2_VOL_SHIFT 22
488
+
#define CS42L43_DECIM2_VD_RAMP_MASK 0x00380000
489
+
#define CS42L43_DECIM2_VD_RAMP_SHIFT 19
490
+
#define CS42L43_DECIM2_VI_RAMP_MASK 0x00070000
491
+
#define CS42L43_DECIM2_VI_RAMP_SHIFT 16
492
+
#define CS42L43_DECIM1_MUTE_MASK 0x00008000
493
+
#define CS42L43_DECIM1_MUTE_SHIFT 15
494
+
#define CS42L43_DECIM1_VOL_MASK 0x00003FC0
495
+
#define CS42L43_DECIM1_VOL_SHIFT 6
496
+
#define CS42L43_DECIM1_VD_RAMP_MASK 0x00000038
497
+
#define CS42L43_DECIM1_VD_RAMP_SHIFT 3
498
+
#define CS42L43_DECIM1_VI_RAMP_MASK 0x00000007
499
+
#define CS42L43_DECIM1_VI_RAMP_SHIFT 0
500
+
501
+
/* CS42L43_DECIM_VOL_CTRL_CH3_CH4 */
502
+
#define CS42L43_DECIM4_MUTE_MASK 0x80000000
503
+
#define CS42L43_DECIM4_MUTE_SHIFT 31
504
+
#define CS42L43_DECIM4_VOL_MASK 0x3FC00000
505
+
#define CS42L43_DECIM4_VOL_SHIFT 22
506
+
#define CS42L43_DECIM4_VD_RAMP_MASK 0x00380000
507
+
#define CS42L43_DECIM4_VD_RAMP_SHIFT 19
508
+
#define CS42L43_DECIM4_VI_RAMP_MASK 0x00070000
509
+
#define CS42L43_DECIM4_VI_RAMP_SHIFT 16
510
+
#define CS42L43_DECIM3_MUTE_MASK 0x00008000
511
+
#define CS42L43_DECIM3_MUTE_SHIFT 15
512
+
#define CS42L43_DECIM3_VOL_MASK 0x00003FC0
513
+
#define CS42L43_DECIM3_VOL_SHIFT 6
514
+
#define CS42L43_DECIM3_VD_RAMP_MASK 0x00000038
515
+
#define CS42L43_DECIM3_VD_RAMP_SHIFT 3
516
+
#define CS42L43_DECIM3_VI_RAMP_MASK 0x00000007
517
+
#define CS42L43_DECIM3_VI_RAMP_SHIFT 0
518
+
519
+
/* CS42L43_DECIM_VOL_CTRL_UPDATE */
520
+
#define CS42L43_DECIM4_VOL_UPDATE_MASK 0x00000008
521
+
#define CS42L43_DECIM4_VOL_UPDATE_SHIFT 3
522
+
#define CS42L43_DECIM3_VOL_UPDATE_MASK 0x00000004
523
+
#define CS42L43_DECIM3_VOL_UPDATE_SHIFT 2
524
+
#define CS42L43_DECIM2_VOL_UPDATE_MASK 0x00000002
525
+
#define CS42L43_DECIM2_VOL_UPDATE_SHIFT 1
526
+
#define CS42L43_DECIM1_VOL_UPDATE_MASK 0x00000001
527
+
#define CS42L43_DECIM1_VOL_UPDATE_SHIFT 0
528
+
529
+
/* CS42L43_INTP_VOLUME_CTRL1..CS42L43_INTP_VOLUME_CTRL2 */
530
+
#define CS42L43_AMP1_2_VU_MASK 0x00000200
531
+
#define CS42L43_AMP1_2_VU_SHIFT 9
532
+
#define CS42L43_AMP_MUTE_MASK 0x00000100
533
+
#define CS42L43_AMP_MUTE_SHIFT 8
534
+
#define CS42L43_AMP_VOL_MASK 0x000000FF
535
+
#define CS42L43_AMP_VOL_SHIFT 0
536
+
537
+
/* CS42L43_AMP1_2_VOL_RAMP */
538
+
#define CS42L43_AMP1_2_VD_RAMP_MASK 0x00000070
539
+
#define CS42L43_AMP1_2_VD_RAMP_SHIFT 4
540
+
#define CS42L43_AMP1_2_VI_RAMP_MASK 0x00000007
541
+
#define CS42L43_AMP1_2_VI_RAMP_SHIFT 0
542
+
543
+
/* CS42L43_ASP_CTRL */
544
+
#define CS42L43_ASP_FSYNC_MODE_MASK 0x00000004
545
+
#define CS42L43_ASP_FSYNC_MODE_SHIFT 2
546
+
#define CS42L43_ASP_BCLK_EN_MASK 0x00000002
547
+
#define CS42L43_ASP_BCLK_EN_SHIFT 1
548
+
#define CS42L43_ASP_FSYNC_EN_MASK 0x00000001
549
+
#define CS42L43_ASP_FSYNC_EN_SHIFT 0
550
+
551
+
/* CS42L43_ASP_FSYNC_CTRL1 */
552
+
#define CS42L43_ASP_FSYNC_M_MASK 0x0007FFFF
553
+
#define CS42L43_ASP_FSYNC_M_SHIFT 0
554
+
555
+
/* CS42L43_ASP_FSYNC_CTRL3 */
556
+
#define CS42L43_ASP_FSYNC_IN_INV_MASK 0x00000002
557
+
#define CS42L43_ASP_FSYNC_IN_INV_SHIFT 1
558
+
#define CS42L43_ASP_FSYNC_OUT_INV_MASK 0x00000001
559
+
#define CS42L43_ASP_FSYNC_OUT_INV_SHIFT 0
560
+
561
+
/* CS42L43_ASP_FSYNC_CTRL4 */
562
+
#define CS42L43_ASP_NUM_BCLKS_PER_FSYNC_MASK 0x00001FFE
563
+
#define CS42L43_ASP_NUM_BCLKS_PER_FSYNC_SHIFT 1
564
+
565
+
/* CS42L43_ASP_DATA_CTRL */
566
+
#define CS42L43_ASP_FSYNC_FRAME_START_PHASE_MASK 0x00000008
567
+
#define CS42L43_ASP_FSYNC_FRAME_START_PHASE_SHIFT 3
568
+
#define CS42L43_ASP_FSYNC_FRAME_START_DLY_MASK 0x00000007
569
+
#define CS42L43_ASP_FSYNC_FRAME_START_DLY_SHIFT 0
570
+
571
+
/* CS42L43_ASP_RX_EN */
572
+
#define CS42L43_ASP_RX_CH6_EN_MASK 0x00000020
573
+
#define CS42L43_ASP_RX_CH6_EN_SHIFT 5
574
+
#define CS42L43_ASP_RX_CH5_EN_MASK 0x00000010
575
+
#define CS42L43_ASP_RX_CH5_EN_SHIFT 4
576
+
#define CS42L43_ASP_RX_CH4_EN_MASK 0x00000008
577
+
#define CS42L43_ASP_RX_CH4_EN_SHIFT 3
578
+
#define CS42L43_ASP_RX_CH3_EN_MASK 0x00000004
579
+
#define CS42L43_ASP_RX_CH3_EN_SHIFT 2
580
+
#define CS42L43_ASP_RX_CH2_EN_MASK 0x00000002
581
+
#define CS42L43_ASP_RX_CH2_EN_SHIFT 1
582
+
#define CS42L43_ASP_RX_CH1_EN_MASK 0x00000001
583
+
#define CS42L43_ASP_RX_CH1_EN_SHIFT 0
584
+
585
+
/* CS42L43_ASP_TX_EN */
586
+
#define CS42L43_ASP_TX_CH6_EN_MASK 0x00000020
587
+
#define CS42L43_ASP_TX_CH6_EN_SHIFT 5
588
+
#define CS42L43_ASP_TX_CH5_EN_MASK 0x00000010
589
+
#define CS42L43_ASP_TX_CH5_EN_SHIFT 4
590
+
#define CS42L43_ASP_TX_CH4_EN_MASK 0x00000008
591
+
#define CS42L43_ASP_TX_CH4_EN_SHIFT 3
592
+
#define CS42L43_ASP_TX_CH3_EN_MASK 0x00000004
593
+
#define CS42L43_ASP_TX_CH3_EN_SHIFT 2
594
+
#define CS42L43_ASP_TX_CH2_EN_MASK 0x00000002
595
+
#define CS42L43_ASP_TX_CH2_EN_SHIFT 1
596
+
#define CS42L43_ASP_TX_CH1_EN_MASK 0x00000001
597
+
#define CS42L43_ASP_TX_CH1_EN_SHIFT 0
598
+
599
+
/* CS42L43_ASP_RX_CH1_CTRL..CS42L43_ASP_TX_CH6_CTRL */
600
+
#define CS42L43_ASP_CH_WIDTH_MASK 0x001F0000
601
+
#define CS42L43_ASP_CH_WIDTH_SHIFT 16
602
+
#define CS42L43_ASP_CH_SLOT_MASK 0x00001FFE
603
+
#define CS42L43_ASP_CH_SLOT_SHIFT 1
604
+
#define CS42L43_ASP_CH_SLOT_PHASE_MASK 0x00000001
605
+
#define CS42L43_ASP_CH_SLOT_PHASE_SHIFT 0
606
+
607
+
/* CS42L43_ASPTX1_INPUT..CS42L43_AMP4MIX_INPUT4 */
608
+
#define CS42L43_MIXER_VOL_MASK 0x00FE0000
609
+
#define CS42L43_MIXER_VOL_SHIFT 17
610
+
#define CS42L43_MIXER_SRC_MASK 0x000001FF
611
+
#define CS42L43_MIXER_SRC_SHIFT 0
612
+
613
+
/* CS42L43_ASRC_INT_ENABLES */
614
+
#define CS42L43_ASRC_INT4_EN_MASK 0x00000008
615
+
#define CS42L43_ASRC_INT4_EN_SHIFT 3
616
+
#define CS42L43_ASRC_INT3_EN_MASK 0x00000004
617
+
#define CS42L43_ASRC_INT3_EN_SHIFT 2
618
+
#define CS42L43_ASRC_INT2_EN_MASK 0x00000002
619
+
#define CS42L43_ASRC_INT2_EN_SHIFT 1
620
+
#define CS42L43_ASRC_INT1_EN_MASK 0x00000001
621
+
#define CS42L43_ASRC_INT1_EN_SHIFT 0
622
+
623
+
/* CS42L43_ASRC_DEC_ENABLES */
624
+
#define CS42L43_ASRC_DEC4_EN_MASK 0x00000008
625
+
#define CS42L43_ASRC_DEC4_EN_SHIFT 3
626
+
#define CS42L43_ASRC_DEC3_EN_MASK 0x00000004
627
+
#define CS42L43_ASRC_DEC3_EN_SHIFT 2
628
+
#define CS42L43_ASRC_DEC2_EN_MASK 0x00000002
629
+
#define CS42L43_ASRC_DEC2_EN_SHIFT 1
630
+
#define CS42L43_ASRC_DEC1_EN_MASK 0x00000001
631
+
#define CS42L43_ASRC_DEC1_EN_SHIFT 0
632
+
633
+
/* CS42L43_PDNCNTL */
634
+
#define CS42L43_RING_SENSE_EN_MASK 0x00000002
635
+
#define CS42L43_RING_SENSE_EN_SHIFT 1
636
+
637
+
/* CS42L43_RINGSENSE_DEB_CTRL */
638
+
#define CS42L43_RINGSENSE_INV_MASK 0x00000080
639
+
#define CS42L43_RINGSENSE_INV_SHIFT 7
640
+
#define CS42L43_RINGSENSE_PULLUP_PDNB_MASK 0x00000040
641
+
#define CS42L43_RINGSENSE_PULLUP_PDNB_SHIFT 6
642
+
#define CS42L43_RINGSENSE_FALLING_DB_TIME_MASK 0x00000038
643
+
#define CS42L43_RINGSENSE_FALLING_DB_TIME_SHIFT 3
644
+
#define CS42L43_RINGSENSE_RISING_DB_TIME_MASK 0x00000007
645
+
#define CS42L43_RINGSENSE_RISING_DB_TIME_SHIFT 0
646
+
647
+
/* CS42L43_TIPSENSE_DEB_CTRL */
648
+
#define CS42L43_TIPSENSE_INV_MASK 0x00000080
649
+
#define CS42L43_TIPSENSE_INV_SHIFT 7
650
+
#define CS42L43_TIPSENSE_FALLING_DB_TIME_MASK 0x00000038
651
+
#define CS42L43_TIPSENSE_FALLING_DB_TIME_SHIFT 3
652
+
#define CS42L43_TIPSENSE_RISING_DB_TIME_MASK 0x00000007
653
+
#define CS42L43_TIPSENSE_RISING_DB_TIME_SHIFT 0
654
+
655
+
/* CS42L43_TIP_RING_SENSE_INTERRUPT_STATUS */
656
+
#define CS42L43_TIPSENSE_UNPLUG_DB_STS_MASK 0x00000008
657
+
#define CS42L43_TIPSENSE_UNPLUG_DB_STS_SHIFT 3
658
+
#define CS42L43_TIPSENSE_PLUG_DB_STS_MASK 0x00000004
659
+
#define CS42L43_TIPSENSE_PLUG_DB_STS_SHIFT 2
660
+
#define CS42L43_RINGSENSE_UNPLUG_DB_STS_MASK 0x00000002
661
+
#define CS42L43_RINGSENSE_UNPLUG_DB_STS_SHIFT 1
662
+
#define CS42L43_RINGSENSE_PLUG_DB_STS_MASK 0x00000001
663
+
#define CS42L43_RINGSENSE_PLUG_DB_STS_SHIFT 0
664
+
665
+
/* CS42L43_HS2 */
666
+
#define CS42L43_HS_CLAMP_DISABLE_MASK 0x10000000
667
+
#define CS42L43_HS_CLAMP_DISABLE_SHIFT 28
668
+
#define CS42L43_HSBIAS_RAMP_MASK 0x0C000000
669
+
#define CS42L43_HSBIAS_RAMP_SHIFT 26
670
+
#define CS42L43_HSDET_MODE_MASK 0x00018000
671
+
#define CS42L43_HSDET_MODE_SHIFT 15
672
+
#define CS42L43_HSDET_MANUAL_MODE_MASK 0x00006000
673
+
#define CS42L43_HSDET_MANUAL_MODE_SHIFT 13
674
+
#define CS42L43_AUTO_HSDET_TIME_MASK 0x00000700
675
+
#define CS42L43_AUTO_HSDET_TIME_SHIFT 8
676
+
#define CS42L43_AMP3_4_GNDREF_HS3_SEL_MASK 0x00000080
677
+
#define CS42L43_AMP3_4_GNDREF_HS3_SEL_SHIFT 7
678
+
#define CS42L43_AMP3_4_GNDREF_HS4_SEL_MASK 0x00000040
679
+
#define CS42L43_AMP3_4_GNDREF_HS4_SEL_SHIFT 6
680
+
#define CS42L43_HSBIAS_GNDREF_HS3_SEL_MASK 0x00000020
681
+
#define CS42L43_HSBIAS_GNDREF_HS3_SEL_SHIFT 5
682
+
#define CS42L43_HSBIAS_GNDREF_HS4_SEL_MASK 0x00000010
683
+
#define CS42L43_HSBIAS_GNDREF_HS4_SEL_SHIFT 4
684
+
#define CS42L43_HSBIAS_OUT_HS3_SEL_MASK 0x00000008
685
+
#define CS42L43_HSBIAS_OUT_HS3_SEL_SHIFT 3
686
+
#define CS42L43_HSBIAS_OUT_HS4_SEL_MASK 0x00000004
687
+
#define CS42L43_HSBIAS_OUT_HS4_SEL_SHIFT 2
688
+
#define CS42L43_HSGND_HS3_SEL_MASK 0x00000002
689
+
#define CS42L43_HSGND_HS3_SEL_SHIFT 1
690
+
#define CS42L43_HSGND_HS4_SEL_MASK 0x00000001
691
+
#define CS42L43_HSGND_HS4_SEL_SHIFT 0
692
+
693
+
/* CS42L43_HS_STAT */
694
+
#define CS42L43_HSDET_TYPE_STS_MASK 0x00000007
695
+
#define CS42L43_HSDET_TYPE_STS_SHIFT 0
696
+
697
+
/* CS42L43_MCU_SW_INTERRUPT */
698
+
#define CS42L43_CONTROL_IND_MASK 0x00000004
699
+
#define CS42L43_CONTROL_IND_SHIFT 2
700
+
#define CS42L43_CONFIGS_IND_MASK 0x00000002
701
+
#define CS42L43_CONFIGS_IND_SHIFT 1
702
+
#define CS42L43_PATCH_IND_MASK 0x00000001
703
+
#define CS42L43_PATCH_IND_SHIFT 0
704
+
705
+
/* CS42L43_STEREO_MIC_CTRL */
706
+
#define CS42L43_HS2_BIAS_SENSE_EN_MASK 0x00000020
707
+
#define CS42L43_HS2_BIAS_SENSE_EN_SHIFT 5
708
+
#define CS42L43_HS1_BIAS_SENSE_EN_MASK 0x00000010
709
+
#define CS42L43_HS1_BIAS_SENSE_EN_SHIFT 4
710
+
#define CS42L43_HS2_BIAS_EN_MASK 0x00000008
711
+
#define CS42L43_HS2_BIAS_EN_SHIFT 3
712
+
#define CS42L43_HS1_BIAS_EN_MASK 0x00000004
713
+
#define CS42L43_HS1_BIAS_EN_SHIFT 2
714
+
#define CS42L43_JACK_STEREO_CONFIG_MASK 0x00000003
715
+
#define CS42L43_JACK_STEREO_CONFIG_SHIFT 0
716
+
717
+
/* CS42L43_STEREO_MIC_CLAMP_CTRL */
718
+
#define CS42L43_SMIC_HPAMP_CLAMP_DIS_FRC_VAL_MASK 0x00000002
719
+
#define CS42L43_SMIC_HPAMP_CLAMP_DIS_FRC_VAL_SHIFT 1
720
+
#define CS42L43_SMIC_HPAMP_CLAMP_DIS_FRC_MASK 0x00000001
721
+
#define CS42L43_SMIC_HPAMP_CLAMP_DIS_FRC_SHIFT 0
722
+
723
+
/* CS42L43_BLOCK_EN2 */
724
+
#define CS42L43_SPI_MSTR_EN_MASK 0x00000001
725
+
#define CS42L43_SPI_MSTR_EN_SHIFT 0
726
+
727
+
/* CS42L43_BLOCK_EN3 */
728
+
#define CS42L43_PDM2_DIN_R_EN_MASK 0x00000020
729
+
#define CS42L43_PDM2_DIN_R_EN_SHIFT 5
730
+
#define CS42L43_PDM2_DIN_L_EN_MASK 0x00000010
731
+
#define CS42L43_PDM2_DIN_L_EN_SHIFT 4
732
+
#define CS42L43_PDM1_DIN_R_EN_MASK 0x00000008
733
+
#define CS42L43_PDM1_DIN_R_EN_SHIFT 3
734
+
#define CS42L43_PDM1_DIN_L_EN_MASK 0x00000004
735
+
#define CS42L43_PDM1_DIN_L_EN_SHIFT 2
736
+
#define CS42L43_ADC2_EN_MASK 0x00000002
737
+
#define CS42L43_ADC2_EN_SHIFT 1
738
+
#define CS42L43_ADC1_EN_MASK 0x00000001
739
+
#define CS42L43_ADC1_EN_SHIFT 0
740
+
741
+
/* CS42L43_BLOCK_EN4 */
742
+
#define CS42L43_ASRC_DEC_BANK_EN_MASK 0x00000002
743
+
#define CS42L43_ASRC_DEC_BANK_EN_SHIFT 1
744
+
#define CS42L43_ASRC_INT_BANK_EN_MASK 0x00000001
745
+
#define CS42L43_ASRC_INT_BANK_EN_SHIFT 0
746
+
747
+
/* CS42L43_BLOCK_EN5 */
748
+
#define CS42L43_ISRC2_BANK_EN_MASK 0x00000002
749
+
#define CS42L43_ISRC2_BANK_EN_SHIFT 1
750
+
#define CS42L43_ISRC1_BANK_EN_MASK 0x00000001
751
+
#define CS42L43_ISRC1_BANK_EN_SHIFT 0
752
+
753
+
/* CS42L43_BLOCK_EN6 */
754
+
#define CS42L43_MIXER_EN_MASK 0x00000001
755
+
#define CS42L43_MIXER_EN_SHIFT 0
756
+
757
+
/* CS42L43_BLOCK_EN7 */
758
+
#define CS42L43_EQ_EN_MASK 0x00000001
759
+
#define CS42L43_EQ_EN_SHIFT 0
760
+
761
+
/* CS42L43_BLOCK_EN8 */
762
+
#define CS42L43_HP_EN_MASK 0x00000001
763
+
#define CS42L43_HP_EN_SHIFT 0
764
+
765
+
/* CS42L43_BLOCK_EN9 */
766
+
#define CS42L43_TONE_EN_MASK 0x00000001
767
+
#define CS42L43_TONE_EN_SHIFT 0
768
+
769
+
/* CS42L43_BLOCK_EN10 */
770
+
#define CS42L43_AMP2_EN_MASK 0x00000002
771
+
#define CS42L43_AMP2_EN_SHIFT 1
772
+
#define CS42L43_AMP1_EN_MASK 0x00000001
773
+
#define CS42L43_AMP1_EN_SHIFT 0
774
+
775
+
/* CS42L43_BLOCK_EN11 */
776
+
#define CS42L43_SPDIF_EN_MASK 0x00000001
777
+
#define CS42L43_SPDIF_EN_SHIFT 0
778
+
779
+
/* CS42L43_TONE_CH1_CTRL..CS42L43_TONE_CH2_CTRL */
780
+
#define CS42L43_TONE_FREQ_MASK 0x00000070
781
+
#define CS42L43_TONE_FREQ_SHIFT 4
782
+
#define CS42L43_TONE_SEL_MASK 0x0000000F
783
+
#define CS42L43_TONE_SEL_SHIFT 0
784
+
785
+
/* CS42L43_MIC_DETECT_CONTROL_1 */
786
+
#define CS42L43_BUTTON_DETECT_MODE_MASK 0x00000018
787
+
#define CS42L43_BUTTON_DETECT_MODE_SHIFT 3
788
+
#define CS42L43_HSBIAS_MODE_MASK 0x00000006
789
+
#define CS42L43_HSBIAS_MODE_SHIFT 1
790
+
#define CS42L43_MIC_LVL_DET_DISABLE_MASK 0x00000001
791
+
#define CS42L43_MIC_LVL_DET_DISABLE_SHIFT 0
792
+
793
+
/* CS42L43_DETECT_STATUS_1 */
794
+
#define CS42L43_HSDET_DC_STS_MASK 0x01FF0000
795
+
#define CS42L43_HSDET_DC_STS_SHIFT 16
796
+
#define CS42L43_JACKDET_STS_MASK 0x00000080
797
+
#define CS42L43_JACKDET_STS_SHIFT 7
798
+
#define CS42L43_HSBIAS_CLAMP_STS_MASK 0x00000040
799
+
#define CS42L43_HSBIAS_CLAMP_STS_SHIFT 6
800
+
801
+
/* CS42L43_HS_BIAS_SENSE_AND_CLAMP_AUTOCONTROL */
802
+
#define CS42L43_JACKDET_MODE_MASK 0xC0000000
803
+
#define CS42L43_JACKDET_MODE_SHIFT 30
804
+
#define CS42L43_JACKDET_INV_MASK 0x20000000
805
+
#define CS42L43_JACKDET_INV_SHIFT 29
806
+
#define CS42L43_JACKDET_DB_TIME_MASK 0x03000000
807
+
#define CS42L43_JACKDET_DB_TIME_SHIFT 24
808
+
#define CS42L43_S0_AUTO_ADCMUTE_DISABLE_MASK 0x00800000
809
+
#define CS42L43_S0_AUTO_ADCMUTE_DISABLE_SHIFT 23
810
+
#define CS42L43_HSBIAS_SENSE_EN_MASK 0x00000080
811
+
#define CS42L43_HSBIAS_SENSE_EN_SHIFT 7
812
+
#define CS42L43_AUTO_HSBIAS_CLAMP_EN_MASK 0x00000040
813
+
#define CS42L43_AUTO_HSBIAS_CLAMP_EN_SHIFT 6
814
+
#define CS42L43_JACKDET_SENSE_EN_MASK 0x00000020
815
+
#define CS42L43_JACKDET_SENSE_EN_SHIFT 5
816
+
#define CS42L43_HSBIAS_SENSE_TRIP_MASK 0x00000007
817
+
#define CS42L43_HSBIAS_SENSE_TRIP_SHIFT 0
818
+
819
+
/* CS42L43_MIC_DETECT_CONTROL_ANDROID */
820
+
#define CS42L43_HSDET_LVL_COMBWIDTH_MASK 0xC0000000
821
+
#define CS42L43_HSDET_LVL_COMBWIDTH_SHIFT 30
822
+
#define CS42L43_HSDET_LVL2_THRESH_MASK 0x01FF0000
823
+
#define CS42L43_HSDET_LVL2_THRESH_SHIFT 16
824
+
#define CS42L43_HSDET_LVL1_THRESH_MASK 0x000001FF
825
+
#define CS42L43_HSDET_LVL1_THRESH_SHIFT 0
826
+
827
+
/* CS42L43_ISRC1_CTRL..CS42L43_ISRC2_CTRL */
828
+
#define CS42L43_ISRC_INT2_EN_MASK 0x00000200
829
+
#define CS42L43_ISRC_INT2_EN_SHIFT 9
830
+
#define CS42L43_ISRC_INT1_EN_MASK 0x00000100
831
+
#define CS42L43_ISRC_INT1_EN_SHIFT 8
832
+
#define CS42L43_ISRC_DEC2_EN_MASK 0x00000002
833
+
#define CS42L43_ISRC_DEC2_EN_SHIFT 1
834
+
#define CS42L43_ISRC_DEC1_EN_MASK 0x00000001
835
+
#define CS42L43_ISRC_DEC1_EN_SHIFT 0
836
+
837
+
/* CS42L43_CTRL_REG */
838
+
#define CS42L43_PLL_MODE_BYPASS_500_MASK 0x00000004
839
+
#define CS42L43_PLL_MODE_BYPASS_500_SHIFT 2
840
+
#define CS42L43_PLL_MODE_BYPASS_1029_MASK 0x00000002
841
+
#define CS42L43_PLL_MODE_BYPASS_1029_SHIFT 1
842
+
#define CS42L43_PLL_EN_MASK 0x00000001
843
+
#define CS42L43_PLL_EN_SHIFT 0
844
+
845
+
/* CS42L43_FDIV_FRAC */
846
+
#define CS42L43_PLL_DIV_INT_MASK 0xFF000000
847
+
#define CS42L43_PLL_DIV_INT_SHIFT 24
848
+
#define CS42L43_PLL_DIV_FRAC_BYTE2_MASK 0x00FF0000
849
+
#define CS42L43_PLL_DIV_FRAC_BYTE2_SHIFT 16
850
+
#define CS42L43_PLL_DIV_FRAC_BYTE1_MASK 0x0000FF00
851
+
#define CS42L43_PLL_DIV_FRAC_BYTE1_SHIFT 8
852
+
#define CS42L43_PLL_DIV_FRAC_BYTE0_MASK 0x000000FF
853
+
#define CS42L43_PLL_DIV_FRAC_BYTE0_SHIFT 0
854
+
855
+
/* CS42L43_CAL_RATIO */
856
+
#define CS42L43_PLL_CAL_RATIO_MASK 0x000000FF
857
+
#define CS42L43_PLL_CAL_RATIO_SHIFT 0
858
+
859
+
/* CS42L43_SPI_CLK_CONFIG1 */
860
+
#define CS42L43_SCLK_DIV_MASK 0x0000000F
861
+
#define CS42L43_SCLK_DIV_SHIFT 0
862
+
863
+
/* CS42L43_SPI_CONFIG1 */
864
+
#define CS42L43_SPI_SS_IDLE_DUR_MASK 0x0F000000
865
+
#define CS42L43_SPI_SS_IDLE_DUR_SHIFT 24
866
+
#define CS42L43_SPI_SS_DELAY_DUR_MASK 0x000F0000
867
+
#define CS42L43_SPI_SS_DELAY_DUR_SHIFT 16
868
+
#define CS42L43_SPI_THREE_WIRE_MASK 0x00000100
869
+
#define CS42L43_SPI_THREE_WIRE_SHIFT 8
870
+
#define CS42L43_SPI_DPHA_MASK 0x00000040
871
+
#define CS42L43_SPI_DPHA_SHIFT 6
872
+
#define CS42L43_SPI_CPHA_MASK 0x00000020
873
+
#define CS42L43_SPI_CPHA_SHIFT 5
874
+
#define CS42L43_SPI_CPOL_MASK 0x00000010
875
+
#define CS42L43_SPI_CPOL_SHIFT 4
876
+
#define CS42L43_SPI_SS_SEL_MASK 0x00000007
877
+
#define CS42L43_SPI_SS_SEL_SHIFT 0
878
+
879
+
/* CS42L43_SPI_CONFIG2 */
880
+
#define CS42L43_SPI_SS_FRC_MASK 0x00000001
881
+
#define CS42L43_SPI_SS_FRC_SHIFT 0
882
+
883
+
/* CS42L43_SPI_CONFIG3 */
884
+
#define CS42L43_SPI_WDT_ENA_MASK 0x00000001
885
+
#define CS42L43_SPI_WDT_ENA_SHIFT 0
886
+
887
+
/* CS42L43_SPI_CONFIG4 */
888
+
#define CS42L43_SPI_STALL_ENA_MASK 0x00010000
889
+
#define CS42L43_SPI_STALL_ENA_SHIFT 16
890
+
891
+
/* CS42L43_SPI_STATUS1 */
892
+
#define CS42L43_SPI_ABORT_STS_MASK 0x00000002
893
+
#define CS42L43_SPI_ABORT_STS_SHIFT 1
894
+
#define CS42L43_SPI_DONE_STS_MASK 0x00000001
895
+
#define CS42L43_SPI_DONE_STS_SHIFT 0
896
+
897
+
/* CS42L43_SPI_STATUS2 */
898
+
#define CS42L43_SPI_RX_DONE_STS_MASK 0x00000010
899
+
#define CS42L43_SPI_RX_DONE_STS_SHIFT 4
900
+
#define CS42L43_SPI_TX_DONE_STS_MASK 0x00000001
901
+
#define CS42L43_SPI_TX_DONE_STS_SHIFT 0
902
+
903
+
/* CS42L43_TRAN_CONFIG1 */
904
+
#define CS42L43_SPI_START_MASK 0x00000001
905
+
#define CS42L43_SPI_START_SHIFT 0
906
+
907
+
/* CS42L43_TRAN_CONFIG2 */
908
+
#define CS42L43_SPI_ABORT_MASK 0x00000001
909
+
#define CS42L43_SPI_ABORT_SHIFT 0
910
+
911
+
/* CS42L43_TRAN_CONFIG3 */
912
+
#define CS42L43_SPI_WORD_SIZE_MASK 0x00070000
913
+
#define CS42L43_SPI_WORD_SIZE_SHIFT 16
914
+
#define CS42L43_SPI_CMD_MASK 0x00000003
915
+
#define CS42L43_SPI_CMD_SHIFT 0
916
+
917
+
/* CS42L43_TRAN_CONFIG4 */
918
+
#define CS42L43_SPI_TX_LENGTH_MASK 0x0000FFFF
919
+
#define CS42L43_SPI_TX_LENGTH_SHIFT 0
920
+
921
+
/* CS42L43_TRAN_CONFIG5 */
922
+
#define CS42L43_SPI_RX_LENGTH_MASK 0x0000FFFF
923
+
#define CS42L43_SPI_RX_LENGTH_SHIFT 0
924
+
925
+
/* CS42L43_TRAN_CONFIG6 */
926
+
#define CS42L43_SPI_TX_BLOCK_LENGTH_MASK 0x0000000F
927
+
#define CS42L43_SPI_TX_BLOCK_LENGTH_SHIFT 0
928
+
929
+
/* CS42L43_TRAN_CONFIG7 */
930
+
#define CS42L43_SPI_RX_BLOCK_LENGTH_MASK 0x0000000F
931
+
#define CS42L43_SPI_RX_BLOCK_LENGTH_SHIFT 0
932
+
933
+
/* CS42L43_TRAN_CONFIG8 */
934
+
#define CS42L43_SPI_RX_DONE_MASK 0x00000010
935
+
#define CS42L43_SPI_RX_DONE_SHIFT 4
936
+
#define CS42L43_SPI_TX_DONE_MASK 0x00000001
937
+
#define CS42L43_SPI_TX_DONE_SHIFT 0
938
+
939
+
/* CS42L43_TRAN_STATUS1 */
940
+
#define CS42L43_SPI_BUSY_STS_MASK 0x00000100
941
+
#define CS42L43_SPI_BUSY_STS_SHIFT 8
942
+
#define CS42L43_SPI_RX_REQUEST_MASK 0x00000010
943
+
#define CS42L43_SPI_RX_REQUEST_SHIFT 4
944
+
#define CS42L43_SPI_TX_REQUEST_MASK 0x00000001
945
+
#define CS42L43_SPI_TX_REQUEST_SHIFT 0
946
+
947
+
/* CS42L43_TRAN_STATUS2 */
948
+
#define CS42L43_SPI_TX_BYTE_COUNT_MASK 0x0000FFFF
949
+
#define CS42L43_SPI_TX_BYTE_COUNT_SHIFT 0
950
+
951
+
/* CS42L43_TRAN_STATUS3 */
952
+
#define CS42L43_SPI_RX_BYTE_COUNT_MASK 0x0000FFFF
953
+
#define CS42L43_SPI_RX_BYTE_COUNT_SHIFT 0
954
+
955
+
/* CS42L43_TX_DATA */
956
+
#define CS42L43_SPI_TX_DATA_MASK 0xFFFFFFFF
957
+
#define CS42L43_SPI_TX_DATA_SHIFT 0
958
+
959
+
/* CS42L43_RX_DATA */
960
+
#define CS42L43_SPI_RX_DATA_MASK 0xFFFFFFFF
961
+
#define CS42L43_SPI_RX_DATA_SHIFT 0
962
+
963
+
/* CS42L43_DACCNFG1 */
964
+
#define CS42L43_HP_MSTR_VOL_CTRL_EN_MASK 0x00000008
965
+
#define CS42L43_HP_MSTR_VOL_CTRL_EN_SHIFT 3
966
+
#define CS42L43_AMP4_INV_MASK 0x00000002
967
+
#define CS42L43_AMP4_INV_SHIFT 1
968
+
#define CS42L43_AMP3_INV_MASK 0x00000001
969
+
#define CS42L43_AMP3_INV_SHIFT 0
970
+
971
+
/* CS42L43_DACCNFG2 */
972
+
#define CS42L43_HP_AUTO_CLAMP_DISABLE_MASK 0x00000002
973
+
#define CS42L43_HP_AUTO_CLAMP_DISABLE_SHIFT 1
974
+
#define CS42L43_HP_HPF_EN_MASK 0x00000001
975
+
#define CS42L43_HP_HPF_EN_SHIFT 0
976
+
977
+
/* CS42L43_HPPATHVOL */
978
+
#define CS42L43_AMP4_PATH_VOL_MASK 0x01FF0000
979
+
#define CS42L43_AMP4_PATH_VOL_SHIFT 16
980
+
#define CS42L43_AMP3_PATH_VOL_MASK 0x000001FF
981
+
#define CS42L43_AMP3_PATH_VOL_SHIFT 0
982
+
983
+
/* CS42L43_PGAVOL */
984
+
#define CS42L43_HP_PATH_VOL_RAMP_MASK 0x0003C000
985
+
#define CS42L43_HP_PATH_VOL_RAMP_SHIFT 14
986
+
#define CS42L43_HP_PATH_VOL_ZC_MASK 0x00002000
987
+
#define CS42L43_HP_PATH_VOL_ZC_SHIFT 13
988
+
#define CS42L43_HP_PATH_VOL_SFT_MASK 0x00001000
989
+
#define CS42L43_HP_PATH_VOL_SFT_SHIFT 12
990
+
#define CS42L43_HP_DIG_VOL_RAMP_MASK 0x00000F00
991
+
#define CS42L43_HP_DIG_VOL_RAMP_SHIFT 8
992
+
#define CS42L43_HP_ANA_VOL_RAMP_MASK 0x0000000F
993
+
#define CS42L43_HP_ANA_VOL_RAMP_SHIFT 0
994
+
995
+
/* CS42L43_LOADDETRESULTS */
996
+
#define CS42L43_AMP3_RES_DET_MASK 0x00000003
997
+
#define CS42L43_AMP3_RES_DET_SHIFT 0
998
+
999
+
/* CS42L43_LOADDETENA */
1000
+
#define CS42L43_HPLOAD_DET_EN_MASK 0x00000001
1001
+
#define CS42L43_HPLOAD_DET_EN_SHIFT 0
1002
+
1003
+
/* CS42L43_CTRL */
1004
+
#define CS42L43_ADPTPWR_MODE_MASK 0x00000007
1005
+
#define CS42L43_ADPTPWR_MODE_SHIFT 0
1006
+
1007
+
/* CS42L43_COEFF_RD_WR0 */
1008
+
#define CS42L43_WRITE_MODE_MASK 0x00000002
1009
+
#define CS42L43_WRITE_MODE_SHIFT 1
1010
+
1011
+
/* CS42L43_INIT_DONE0 */
1012
+
#define CS42L43_INITIALIZE_DONE_MASK 0x00000001
1013
+
#define CS42L43_INITIALIZE_DONE_SHIFT 0
1014
+
1015
+
/* CS42L43_START_EQZ0 */
1016
+
#define CS42L43_START_FILTER_MASK 0x00000001
1017
+
#define CS42L43_START_FILTER_SHIFT 0
1018
+
1019
+
/* CS42L43_MUTE_EQ_IN0 */
1020
+
#define CS42L43_MUTE_EQ_CH2_MASK 0x00000002
1021
+
#define CS42L43_MUTE_EQ_CH2_SHIFT 1
1022
+
#define CS42L43_MUTE_EQ_CH1_MASK 0x00000001
1023
+
#define CS42L43_MUTE_EQ_CH1_SHIFT 0
1024
+
1025
+
/* CS42L43_PLL_INT */
1026
+
#define CS42L43_PLL_LOST_LOCK_INT_MASK 0x00000002
1027
+
#define CS42L43_PLL_LOST_LOCK_INT_SHIFT 1
1028
+
#define CS42L43_PLL_READY_INT_MASK 0x00000001
1029
+
#define CS42L43_PLL_READY_INT_SHIFT 0
1030
+
1031
+
/* CS42L43_SOFT_INT */
1032
+
#define CS42L43_CONTROL_APPLIED_INT_MASK 0x00000010
1033
+
#define CS42L43_CONTROL_APPLIED_INT_SHIFT 4
1034
+
#define CS42L43_CONTROL_WARN_INT_MASK 0x00000008
1035
+
#define CS42L43_CONTROL_WARN_INT_SHIFT 3
1036
+
#define CS42L43_PATCH_WARN_INT_MASK 0x00000002
1037
+
#define CS42L43_PATCH_WARN_INT_SHIFT 1
1038
+
#define CS42L43_PATCH_APPLIED_INT_MASK 0x00000001
1039
+
#define CS42L43_PATCH_APPLIED_INT_SHIFT 0
1040
+
1041
+
/* CS42L43_MSM_INT */
1042
+
#define CS42L43_HP_STARTUP_DONE_INT_MASK 0x00000800
1043
+
#define CS42L43_HP_STARTUP_DONE_INT_SHIFT 11
1044
+
#define CS42L43_HP_SHUTDOWN_DONE_INT_MASK 0x00000400
1045
+
#define CS42L43_HP_SHUTDOWN_DONE_INT_SHIFT 10
1046
+
#define CS42L43_HSDET_DONE_INT_MASK 0x00000200
1047
+
#define CS42L43_HSDET_DONE_INT_SHIFT 9
1048
+
#define CS42L43_TIPSENSE_UNPLUG_DB_INT_MASK 0x00000080
1049
+
#define CS42L43_TIPSENSE_UNPLUG_DB_INT_SHIFT 7
1050
+
#define CS42L43_TIPSENSE_PLUG_DB_INT_MASK 0x00000040
1051
+
#define CS42L43_TIPSENSE_PLUG_DB_INT_SHIFT 6
1052
+
#define CS42L43_RINGSENSE_UNPLUG_DB_INT_MASK 0x00000020
1053
+
#define CS42L43_RINGSENSE_UNPLUG_DB_INT_SHIFT 5
1054
+
#define CS42L43_RINGSENSE_PLUG_DB_INT_MASK 0x00000010
1055
+
#define CS42L43_RINGSENSE_PLUG_DB_INT_SHIFT 4
1056
+
#define CS42L43_TIPSENSE_UNPLUG_PDET_INT_MASK 0x00000008
1057
+
#define CS42L43_TIPSENSE_UNPLUG_PDET_INT_SHIFT 3
1058
+
#define CS42L43_TIPSENSE_PLUG_PDET_INT_MASK 0x00000004
1059
+
#define CS42L43_TIPSENSE_PLUG_PDET_INT_SHIFT 2
1060
+
#define CS42L43_RINGSENSE_UNPLUG_PDET_INT_MASK 0x00000002
1061
+
#define CS42L43_RINGSENSE_UNPLUG_PDET_INT_SHIFT 1
1062
+
#define CS42L43_RINGSENSE_PLUG_PDET_INT_MASK 0x00000001
1063
+
#define CS42L43_RINGSENSE_PLUG_PDET_INT_SHIFT 0
1064
+
1065
+
/* CS42L43_ACC_DET_INT */
1066
+
#define CS42L43_HS2_BIAS_SENSE_INT_MASK 0x00000800
1067
+
#define CS42L43_HS2_BIAS_SENSE_INT_SHIFT 11
1068
+
#define CS42L43_HS1_BIAS_SENSE_INT_MASK 0x00000400
1069
+
#define CS42L43_HS1_BIAS_SENSE_INT_SHIFT 10
1070
+
#define CS42L43_DC_DETECT1_FALSE_INT_MASK 0x00000080
1071
+
#define CS42L43_DC_DETECT1_FALSE_INT_SHIFT 7
1072
+
#define CS42L43_DC_DETECT1_TRUE_INT_MASK 0x00000040
1073
+
#define CS42L43_DC_DETECT1_TRUE_INT_SHIFT 6
1074
+
#define CS42L43_HSBIAS_CLAMPED_INT_MASK 0x00000008
1075
+
#define CS42L43_HSBIAS_CLAMPED_INT_SHIFT 3
1076
+
#define CS42L43_HS3_4_BIAS_SENSE_INT_MASK 0x00000001
1077
+
#define CS42L43_HS3_4_BIAS_SENSE_INT_SHIFT 0
1078
+
1079
+
/* CS42L43_SPI_MSTR_INT */
1080
+
#define CS42L43_IRQ_SPI_STALLING_INT_MASK 0x00000004
1081
+
#define CS42L43_IRQ_SPI_STALLING_INT_SHIFT 2
1082
+
#define CS42L43_IRQ_SPI_STS_INT_MASK 0x00000002
1083
+
#define CS42L43_IRQ_SPI_STS_INT_SHIFT 1
1084
+
#define CS42L43_IRQ_SPI_BLOCK_INT_MASK 0x00000001
1085
+
#define CS42L43_IRQ_SPI_BLOCK_INT_SHIFT 0
1086
+
1087
+
/* CS42L43_SW_TO_SPI_BRIDGE_INT */
1088
+
#define CS42L43_SW2SPI_BUF_OVF_UDF_INT_MASK 0x00000001
1089
+
#define CS42L43_SW2SPI_BUF_OVF_UDF_INT_SHIFT 0
1090
+
1091
+
/* CS42L43_CLASS_D_AMP_INT */
1092
+
#define CS42L43_AMP2_CLK_STOP_FAULT_INT_MASK 0x00002000
1093
+
#define CS42L43_AMP2_CLK_STOP_FAULT_INT_SHIFT 13
1094
+
#define CS42L43_AMP1_CLK_STOP_FAULT_INT_MASK 0x00001000
1095
+
#define CS42L43_AMP1_CLK_STOP_FAULT_INT_SHIFT 12
1096
+
#define CS42L43_AMP2_VDDSPK_FAULT_INT_MASK 0x00000800
1097
+
#define CS42L43_AMP2_VDDSPK_FAULT_INT_SHIFT 11
1098
+
#define CS42L43_AMP1_VDDSPK_FAULT_INT_MASK 0x00000400
1099
+
#define CS42L43_AMP1_VDDSPK_FAULT_INT_SHIFT 10
1100
+
#define CS42L43_AMP2_SHUTDOWN_DONE_INT_MASK 0x00000200
1101
+
#define CS42L43_AMP2_SHUTDOWN_DONE_INT_SHIFT 9
1102
+
#define CS42L43_AMP1_SHUTDOWN_DONE_INT_MASK 0x00000100
1103
+
#define CS42L43_AMP1_SHUTDOWN_DONE_INT_SHIFT 8
1104
+
#define CS42L43_AMP2_STARTUP_DONE_INT_MASK 0x00000080
1105
+
#define CS42L43_AMP2_STARTUP_DONE_INT_SHIFT 7
1106
+
#define CS42L43_AMP1_STARTUP_DONE_INT_MASK 0x00000040
1107
+
#define CS42L43_AMP1_STARTUP_DONE_INT_SHIFT 6
1108
+
#define CS42L43_AMP2_THERM_SHDN_INT_MASK 0x00000020
1109
+
#define CS42L43_AMP2_THERM_SHDN_INT_SHIFT 5
1110
+
#define CS42L43_AMP1_THERM_SHDN_INT_MASK 0x00000010
1111
+
#define CS42L43_AMP1_THERM_SHDN_INT_SHIFT 4
1112
+
#define CS42L43_AMP2_THERM_WARN_INT_MASK 0x00000008
1113
+
#define CS42L43_AMP2_THERM_WARN_INT_SHIFT 3
1114
+
#define CS42L43_AMP1_THERM_WARN_INT_MASK 0x00000004
1115
+
#define CS42L43_AMP1_THERM_WARN_INT_SHIFT 2
1116
+
#define CS42L43_AMP2_SCDET_INT_MASK 0x00000002
1117
+
#define CS42L43_AMP2_SCDET_INT_SHIFT 1
1118
+
#define CS42L43_AMP1_SCDET_INT_MASK 0x00000001
1119
+
#define CS42L43_AMP1_SCDET_INT_SHIFT 0
1120
+
1121
+
/* CS42L43_GPIO_INT */
1122
+
#define CS42L43_GPIO3_FALL_INT_MASK 0x00000020
1123
+
#define CS42L43_GPIO3_FALL_INT_SHIFT 5
1124
+
#define CS42L43_GPIO3_RISE_INT_MASK 0x00000010
1125
+
#define CS42L43_GPIO3_RISE_INT_SHIFT 4
1126
+
#define CS42L43_GPIO2_FALL_INT_MASK 0x00000008
1127
+
#define CS42L43_GPIO2_FALL_INT_SHIFT 3
1128
+
#define CS42L43_GPIO2_RISE_INT_MASK 0x00000004
1129
+
#define CS42L43_GPIO2_RISE_INT_SHIFT 2
1130
+
#define CS42L43_GPIO1_FALL_INT_MASK 0x00000002
1131
+
#define CS42L43_GPIO1_FALL_INT_SHIFT 1
1132
+
#define CS42L43_GPIO1_RISE_INT_MASK 0x00000001
1133
+
#define CS42L43_GPIO1_RISE_INT_SHIFT 0
1134
+
1135
+
/* CS42L43_HPOUT_INT */
1136
+
#define CS42L43_HP_ILIMIT_INT_MASK 0x00000002
1137
+
#define CS42L43_HP_ILIMIT_INT_SHIFT 1
1138
+
#define CS42L43_HP_LOADDET_DONE_INT_MASK 0x00000001
1139
+
#define CS42L43_HP_LOADDET_DONE_INT_SHIFT 0
1140
+
1141
+
/* CS42L43_BOOT_CONTROL */
1142
+
#define CS42L43_LOCK_HW_STS_MASK 0x00000002
1143
+
#define CS42L43_LOCK_HW_STS_SHIFT 1
1144
+
1145
+
/* CS42L43_BLOCK_EN */
1146
+
#define CS42L43_MCU_EN_MASK 0x00000001
1147
+
#define CS42L43_MCU_EN_SHIFT 0
1148
+
1149
+
/* CS42L43_SHUTTER_CONTROL */
1150
+
#define CS42L43_STATUS_SPK_SHUTTER_MUTE_MASK 0x00008000
1151
+
#define CS42L43_STATUS_SPK_SHUTTER_MUTE_SHIFT 15
1152
+
#define CS42L43_SPK_SHUTTER_CFG_MASK 0x00000F00
1153
+
#define CS42L43_SPK_SHUTTER_CFG_SHIFT 8
1154
+
#define CS42L43_STATUS_MIC_SHUTTER_MUTE_MASK 0x00000080
1155
+
#define CS42L43_STATUS_MIC_SHUTTER_MUTE_SHIFT 7
1156
+
#define CS42L43_MIC_SHUTTER_CFG_MASK 0x0000000F
1157
+
#define CS42L43_MIC_SHUTTER_CFG_SHIFT 0
1158
+
1159
+
/* CS42L43_MCU_SW_REV */
1160
+
#define CS42L43_BIOS_SUBMINOR_REV_MASK 0xFF000000
1161
+
#define CS42L43_BIOS_SUBMINOR_REV_SHIFT 24
1162
+
#define CS42L43_BIOS_MINOR_REV_MASK 0x00F00000
1163
+
#define CS42L43_BIOS_MINOR_REV_SHIFT 20
1164
+
#define CS42L43_BIOS_MAJOR_REV_MASK 0x000F0000
1165
+
#define CS42L43_BIOS_MAJOR_REV_SHIFT 16
1166
+
#define CS42L43_FW_SUBMINOR_REV_MASK 0x0000FF00
1167
+
#define CS42L43_FW_SUBMINOR_REV_SHIFT 8
1168
+
#define CS42L43_FW_MINOR_REV_MASK 0x000000F0
1169
+
#define CS42L43_FW_MINOR_REV_SHIFT 4
1170
+
#define CS42L43_FW_MAJOR_REV_MASK 0x0000000F
1171
+
#define CS42L43_FW_MAJOR_REV_SHIFT 0
1172
+
1173
+
/* CS42L43_NEED_CONFIGS */
1174
+
#define CS42L43_FW_PATCH_NEED_CFG_MASK 0x80000000
1175
+
#define CS42L43_FW_PATCH_NEED_CFG_SHIFT 31
1176
+
1177
+
/* CS42L43_FW_MISSION_CTRL_MM_CTRL_SELECTION */
1178
+
#define CS42L43_FW_MM_CTRL_MCU_SEL_MASK 0x00000001
1179
+
#define CS42L43_FW_MM_CTRL_MCU_SEL_SHIFT 0
1180
+
1181
+
/* CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_REG */
1182
+
#define CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_DISABLE_VAL 0xF05AA50F
1183
+
1184
+
#endif /* CS42L43_CORE_REGS_H */
+102
include/linux/mfd/cs42l43.h
+102
include/linux/mfd/cs42l43.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* CS42L43 core driver external data
4
+
*
5
+
* Copyright (C) 2022-2023 Cirrus Logic, Inc. and
6
+
* Cirrus Logic International Semiconductor Ltd.
7
+
*/
8
+
9
+
#include <linux/completion.h>
10
+
#include <linux/device.h>
11
+
#include <linux/gpio/consumer.h>
12
+
#include <linux/mutex.h>
13
+
#include <linux/regmap.h>
14
+
#include <linux/regulator/consumer.h>
15
+
#include <linux/soundwire/sdw.h>
16
+
#include <linux/workqueue.h>
17
+
18
+
#ifndef CS42L43_CORE_EXT_H
19
+
#define CS42L43_CORE_EXT_H
20
+
21
+
#define CS42L43_N_SUPPLIES 3
22
+
23
+
enum cs42l43_irq_numbers {
24
+
CS42L43_PLL_LOST_LOCK,
25
+
CS42L43_PLL_READY,
26
+
27
+
CS42L43_HP_STARTUP_DONE,
28
+
CS42L43_HP_SHUTDOWN_DONE,
29
+
CS42L43_HSDET_DONE,
30
+
CS42L43_TIPSENSE_UNPLUG_DB,
31
+
CS42L43_TIPSENSE_PLUG_DB,
32
+
CS42L43_RINGSENSE_UNPLUG_DB,
33
+
CS42L43_RINGSENSE_PLUG_DB,
34
+
CS42L43_TIPSENSE_UNPLUG_PDET,
35
+
CS42L43_TIPSENSE_PLUG_PDET,
36
+
CS42L43_RINGSENSE_UNPLUG_PDET,
37
+
CS42L43_RINGSENSE_PLUG_PDET,
38
+
39
+
CS42L43_HS2_BIAS_SENSE,
40
+
CS42L43_HS1_BIAS_SENSE,
41
+
CS42L43_DC_DETECT1_FALSE,
42
+
CS42L43_DC_DETECT1_TRUE,
43
+
CS42L43_HSBIAS_CLAMPED,
44
+
CS42L43_HS3_4_BIAS_SENSE,
45
+
46
+
CS42L43_AMP2_CLK_STOP_FAULT,
47
+
CS42L43_AMP1_CLK_STOP_FAULT,
48
+
CS42L43_AMP2_VDDSPK_FAULT,
49
+
CS42L43_AMP1_VDDSPK_FAULT,
50
+
CS42L43_AMP2_SHUTDOWN_DONE,
51
+
CS42L43_AMP1_SHUTDOWN_DONE,
52
+
CS42L43_AMP2_STARTUP_DONE,
53
+
CS42L43_AMP1_STARTUP_DONE,
54
+
CS42L43_AMP2_THERM_SHDN,
55
+
CS42L43_AMP1_THERM_SHDN,
56
+
CS42L43_AMP2_THERM_WARN,
57
+
CS42L43_AMP1_THERM_WARN,
58
+
CS42L43_AMP2_SCDET,
59
+
CS42L43_AMP1_SCDET,
60
+
61
+
CS42L43_GPIO3_FALL,
62
+
CS42L43_GPIO3_RISE,
63
+
CS42L43_GPIO2_FALL,
64
+
CS42L43_GPIO2_RISE,
65
+
CS42L43_GPIO1_FALL,
66
+
CS42L43_GPIO1_RISE,
67
+
68
+
CS42L43_HP_ILIMIT,
69
+
CS42L43_HP_LOADDET_DONE,
70
+
};
71
+
72
+
struct cs42l43 {
73
+
struct device *dev;
74
+
struct regmap *regmap;
75
+
struct sdw_slave *sdw;
76
+
77
+
struct regulator *vdd_p;
78
+
struct regulator *vdd_d;
79
+
struct regulator_bulk_data core_supplies[CS42L43_N_SUPPLIES];
80
+
81
+
struct gpio_desc *reset;
82
+
83
+
int irq;
84
+
struct regmap_irq_chip irq_chip;
85
+
struct regmap_irq_chip_data *irq_data;
86
+
87
+
struct work_struct boot_work;
88
+
struct completion device_attach;
89
+
struct completion device_detach;
90
+
struct completion firmware_download;
91
+
int firmware_error;
92
+
93
+
unsigned int sdw_freq;
94
+
/* Lock to gate control of the PLL and its sources. */
95
+
struct mutex pll_lock;
96
+
97
+
bool sdw_pll_active;
98
+
bool attached;
99
+
bool hw_lock;
100
+
};
101
+
102
+
#endif /* CS42L43_CORE_EXT_H */