Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915/display: Disable DMG Clock Gating
Incorrect clock is connected to DMG registers.
Disable DMG Clock gating during display initialization.
WA: 22021451799
Bspec: 69095
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Nemesa Garg <nemesa.garg@intel.com>
Link: https://patch.msgid.link/20260122031818.703590-1-suraj.kandpal@intel.com
+10
-1
+9
-1
drivers/gpu/drm/i915/display/intel_display_wa.c
+9
-1
drivers/gpu/drm/i915/display/intel_display_wa.c
···
32
32
intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, 0);
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}
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35
+
static void xe3plpd_display_wa_apply(struct intel_display *display)
36
+
{
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+
/* Wa_22021451799 */
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+
intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0, DMG_GATING_DIS);
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+
}
40
+
35
41
void intel_display_wa_apply(struct intel_display *display)
36
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{
37
-
if (display->platform.alderlake_p)
43
+
if (DISPLAY_VER(display) == 35)
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+
xe3plpd_display_wa_apply(display);
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+
else if (display->platform.alderlake_p)
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adlp_display_wa_apply(display);
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else if (DISPLAY_VER(display) == 12)
40
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xe_d_display_wa_apply(display);
+1
drivers/gpu/drm/i915/i915_reg.h
+1
drivers/gpu/drm/i915/i915_reg.h
···
763
763
*/
764
764
#define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
765
765
#define DARBF_GATING_DIS REG_BIT(27)
766
+
#define DMG_GATING_DIS REG_BIT(21)
766
767
#define MTL_PIPEDMC_GATING_DIS(pipe) REG_BIT(15 - (pipe))
767
768
#define PWM2_GATING_DIS REG_BIT(14)
768
769
#define PWM1_GATING_DIS REG_BIT(13)