Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

+1

arch/x86/boot/compressed/Makefile

··· 37 37 KBUILD_CFLAGS += $(call cc-option,-fno-stack-protector) 38 38 KBUILD_CFLAGS += $(call cc-disable-warning, address-of-packed-member) 39 39 KBUILD_CFLAGS += $(call cc-disable-warning, gnu) 40 + KBUILD_CFLAGS += -Wno-pointer-sign 40 41 41 42 KBUILD_AFLAGS := $(KBUILD_CFLAGS) -D__ASSEMBLY__ 42 43 GCOV_PROFILE := n

+7 -6

arch/x86/entry/entry_32.S

··· 389 389 * that register for the time this macro runs 390 390 */ 391 391 392 + /* 393 + * The high bits of the CS dword (__csh) are used for 394 + * CS_FROM_ENTRY_STACK and CS_FROM_USER_CR3. Clear them in case 395 + * hardware didn't do this for us. 396 + */ 397 + andl $(0x0000ffff), PT_CS(%esp) 398 + 392 399 /* Are we on the entry stack? Bail out if not! */ 393 400 movl PER_CPU_VAR(cpu_entry_area), %ecx 394 401 addl $CPU_ENTRY_AREA_entry_stack + SIZEOF_entry_stack, %ecx ··· 413 406 414 407 /* Load top of task-stack into %edi */ 415 408 movl TSS_entry2task_stack(%edi), %edi 416 - 417 - /* 418 - * Clear unused upper bits of the dword containing the word-sized CS 419 - * slot in pt_regs in case hardware didn't clear it for us. 420 - */ 421 - andl $(0x0000ffff), PT_CS(%esp) 422 409 423 410 /* Special case - entry from kernel mode via entry stack */ 424 411 #ifdef CONFIG_VM86

+13

arch/x86/entry/entry_64.S

··· 1187 1187 xorl %ebx, %ebx 1188 1188 1189 1189 1: 1190 + /* 1191 + * Always stash CR3 in %r14. This value will be restored, 1192 + * verbatim, at exit. Needed if paranoid_entry interrupted 1193 + * another entry that already switched to the user CR3 value 1194 + * but has not yet returned to userspace. 1195 + * 1196 + * This is also why CS (stashed in the "iret frame" by the 1197 + * hardware at entry) can not be used: this may be a return 1198 + * to kernel code, but with a user CR3 value. 1199 + */ 1190 1200 SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg=%rax save_reg=%r14 1191 1201 1192 1202 ret ··· 1221 1211 testl %ebx, %ebx /* swapgs needed? */ 1222 1212 jnz .Lparanoid_exit_no_swapgs 1223 1213 TRACE_IRQS_IRETQ 1214 + /* Always restore stashed CR3 value (see paranoid_entry) */ 1224 1215 RESTORE_CR3 scratch_reg=%rbx save_reg=%r14 1225 1216 SWAPGS_UNSAFE_STACK 1226 1217 jmp .Lparanoid_exit_restore 1227 1218 .Lparanoid_exit_no_swapgs: 1228 1219 TRACE_IRQS_IRETQ_DEBUG 1220 + /* Always restore stashed CR3 value (see paranoid_entry) */ 1229 1221 RESTORE_CR3 scratch_reg=%rbx save_reg=%r14 1230 1222 .Lparanoid_exit_restore: 1231 1223 jmp restore_regs_and_return_to_kernel ··· 1638 1626 movq $-1, %rsi 1639 1627 call do_nmi 1640 1628 1629 + /* Always restore stashed CR3 value (see paranoid_entry) */ 1641 1630 RESTORE_CR3 scratch_reg=%r15 save_reg=%r14 1642 1631 1643 1632 testl %ebx, %ebx /* swapgs needed? */

+1 -1

arch/x86/include/asm/fpu/internal.h

··· 528 528 static inline void 529 529 switch_fpu_prepare(struct fpu *old_fpu, int cpu) 530 530 { 531 - if (old_fpu->initialized) { 531 + if (static_cpu_has(X86_FEATURE_FPU) && old_fpu->initialized) { 532 532 if (!copy_fpregs_to_fpstate(old_fpu)) 533 533 old_fpu->last_cpu = -1; 534 534 else

+4 -4

arch/x86/include/asm/percpu.h

··· 185 185 typeof(var) pfo_ret__; \ 186 186 switch (sizeof(var)) { \ 187 187 case 1: \ 188 - asm(op "b "__percpu_arg(1)",%0" \ 188 + asm volatile(op "b "__percpu_arg(1)",%0"\ 189 189 : "=q" (pfo_ret__) \ 190 190 : "m" (var)); \ 191 191 break; \ 192 192 case 2: \ 193 - asm(op "w "__percpu_arg(1)",%0" \ 193 + asm volatile(op "w "__percpu_arg(1)",%0"\ 194 194 : "=r" (pfo_ret__) \ 195 195 : "m" (var)); \ 196 196 break; \ 197 197 case 4: \ 198 - asm(op "l "__percpu_arg(1)",%0" \ 198 + asm volatile(op "l "__percpu_arg(1)",%0"\ 199 199 : "=r" (pfo_ret__) \ 200 200 : "m" (var)); \ 201 201 break; \ 202 202 case 8: \ 203 - asm(op "q "__percpu_arg(1)",%0" \ 203 + asm volatile(op "q "__percpu_arg(1)",%0"\ 204 204 : "=r" (pfo_ret__) \ 205 205 : "m" (var)); \ 206 206 break; \

-1

arch/x86/kernel/fpu/signal.c

··· 314 314 * thread's fpu state, reconstruct fxstate from the fsave 315 315 * header. Validate and sanitize the copied state. 316 316 */ 317 - struct fpu *fpu = &tsk->thread.fpu; 318 317 struct user_i387_ia32_struct env; 319 318 int err = 0; 320 319

-2

arch/x86/kernel/pci-swiotlb.c

··· 42 42 int __init pci_swiotlb_detect_4gb(void) 43 43 { 44 44 /* don't initialize swiotlb if iommu=off (no_iommu=1) */ 45 - #ifdef CONFIG_X86_64 46 45 if (!no_iommu && max_possible_pfn > MAX_DMA32_PFN) 47 46 swiotlb = 1; 48 - #endif 49 47 50 48 /* 51 49 * If SME is active then swiotlb will be set to 1 so that bounce

+1 -1

arch/x86/kernel/time.c

··· 25 25 #include <asm/time.h> 26 26 27 27 #ifdef CONFIG_X86_64 28 - __visible volatile unsigned long jiffies __cacheline_aligned = INITIAL_JIFFIES; 28 + __visible volatile unsigned long jiffies __cacheline_aligned_in_smp = INITIAL_JIFFIES; 29 29 #endif 30 30 31 31 unsigned long profile_pc(struct pt_regs *regs)

+3 -3

arch/x86/kernel/tsc.c

··· 58 58 59 59 static DEFINE_PER_CPU_ALIGNED(struct cyc2ns, cyc2ns); 60 60 61 - void cyc2ns_read_begin(struct cyc2ns_data *data) 61 + void __always_inline cyc2ns_read_begin(struct cyc2ns_data *data) 62 62 { 63 63 int seq, idx; 64 64 ··· 75 75 } while (unlikely(seq != this_cpu_read(cyc2ns.seq.sequence))); 76 76 } 77 77 78 - void cyc2ns_read_end(void) 78 + void __always_inline cyc2ns_read_end(void) 79 79 { 80 80 preempt_enable_notrace(); 81 81 } ··· 104 104 * -johnstul@us.ibm.com "math is hard, lets go shopping!" 105 105 */ 106 106 107 - static inline unsigned long long cycles_2_ns(unsigned long long cyc) 107 + static __always_inline unsigned long long cycles_2_ns(unsigned long long cyc) 108 108 { 109 109 struct cyc2ns_data data; 110 110 unsigned long long ns;

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