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phy: qcom-qmp-pcie: fix the regs layout table for sm8450 gen3x1 PHY

The sm8450 gen3x1 PHY references the pciephy_v4_regs_layout while the
PHY itself uses v5 regs. While there are only minor differences between
v4 and v5 regs and none of them concerns registers mentions in
regs_layout, switch the PHY to use pciephy_v5_regs_layout to remove
possible confusion.

Fixes: bbe207a1aba1 ("phy: qcom-qmp-pcie: rename regs layout arrays")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230113212138.421583-1-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Dmitry Baryshkov and committed by
Vinod Koul c08436c1 aa14cff1

+1 -1
+1 -1
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
··· 2164 2164 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2165 2165 .vreg_list = qmp_phy_vreg_l, 2166 2166 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2167 - .regs = pciephy_v4_regs_layout, 2167 + .regs = pciephy_v5_regs_layout, 2168 2168 2169 2169 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2170 2170 .phy_status = PHYSTATUS,