Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
mips: pci-mt7620: add more register init values
These missing register init values are ported from the vendor SDK.
It should have some stability enhancements. Tested on both MT7620
and MT7628.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
authored by
Shiji Yang
and committed by
Thomas Bogendoerfer
c2631cc4
3dbb0827
+45
-12
+45
-12
arch/mips/pci/pci-mt7620.c
+45
-12
arch/mips/pci/pci-mt7620.c
···
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#define RALINK_INT_PCIE0 4
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+
#define RALINK_SYSCFG0 0x10
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#define RALINK_SYSCFG0_XTAL40 BIT(6)
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#define RALINK_CLKCFG1 0x30
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#define RALINK_GPIOMODE 0x60
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···
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#define PCIEPHY0_CFG 0x90
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-
#define RALINK_PCIEPHY_P0_CTL_OFFSET 0x7498
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#define RALINK_PCIEPHY_P0_CTL_OFFSET 0x7000
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#define RALINK_PCIE0_CLK_EN BIT(26)
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#define BUSY 0x80000000
···
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val &= ~clr;
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val |= set;
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pcie_w32(val, reg);
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}
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+
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static inline void
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pcie_phyctrl_set(unsigned offset, u32 b_start, u32 bits, u32 val)
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{
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pcie_m32(GENMASK(b_start + bits - 1, b_start),
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val << b_start,
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RALINK_PCIEPHY_P0_CTL_OFFSET + offset);
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}
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static int wait_pciephy_busy(void)
···
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return 0;
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}
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-
static int mt7628_pci_hw_init(struct platform_device *pdev)
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static void mt7628_pci_hw_init(struct platform_device *pdev)
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{
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-
u32 val = 0;
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-
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/* bring the core out of reset */
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rt_sysc_m32(BIT(16), 0, RALINK_GPIOMODE);
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reset_control_deassert(rstpcie0);
···
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mdelay(100);
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/* voodoo from the SDK driver */
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-
pcie_m32(~0xff, 0x5, RALINK_PCIEPHY_P0_CTL_OFFSET);
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pcie_phyctrl_set(0x400, 8, 1, 0x1);
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pcie_phyctrl_set(0x400, 9, 2, 0x0);
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pcie_phyctrl_set(0x000, 4, 1, 0x1);
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pcie_phyctrl_set(0x000, 5, 1, 0x0);
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pcie_phyctrl_set(0x4ac, 16, 3, 0x3);
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-
pci_config_read(NULL, 0, 0x70c, 4, &val);
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val &= ~(0xff) << 8;
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val |= 0x50 << 8;
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pci_config_write(NULL, 0, 0x70c, 4, val);
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if (rt_sysc_r32(RALINK_SYSCFG0) & RALINK_SYSCFG0_XTAL40) {
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pcie_phyctrl_set(0x4bc, 24, 8, 0x7d);
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pcie_phyctrl_set(0x490, 12, 4, 0x08);
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pcie_phyctrl_set(0x490, 6, 2, 0x01);
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pcie_phyctrl_set(0x4c0, 0, 32, 0x1f400000);
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pcie_phyctrl_set(0x4a4, 0, 16, 0x013d);
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pcie_phyctrl_set(0x4a8, 16, 16, 0x74);
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pcie_phyctrl_set(0x4a8, 0, 16, 0x74);
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} else {
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pcie_phyctrl_set(0x4bc, 24, 8, 0x64);
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pcie_phyctrl_set(0x490, 12, 4, 0x0a);
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pcie_phyctrl_set(0x490, 6, 2, 0x00);
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pcie_phyctrl_set(0x4c0, 0, 32, 0x19000000);
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pcie_phyctrl_set(0x4a4, 0, 16, 0x018d);
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pcie_phyctrl_set(0x4a8, 16, 16, 0x4a);
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pcie_phyctrl_set(0x4a8, 0, 16, 0x4a);
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}
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-
return 0;
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pcie_phyctrl_set(0x498, 0, 8, 0x5);
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pcie_phyctrl_set(0x000, 5, 1, 0x1);
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pcie_phyctrl_set(0x000, 4, 1, 0x0);
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}
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static int mt7620_pci_probe(struct platform_device *pdev)
···
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case MT762X_SOC_MT7628AN:
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case MT762X_SOC_MT7688:
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-
if (mt7628_pci_hw_init(pdev))
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-
return -1;
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mt7628_pci_hw_init(pdev);
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break;
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default:
···
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rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
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if (ralink_soc == MT762X_SOC_MT7620A)
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rt_sysc_m32(LC_CKDRVPD, PDRV_SW_SET, PPLL_DRV);
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else
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pcie_phyctrl_set(0x000, 0, 32, 0x10);
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dev_info(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n");
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return -1;
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}
···
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/* voodoo from the SDK driver */
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pci_config_read(NULL, 0, 4, 4, &val);
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pci_config_write(NULL, 0, 4, 4, val | 0x7);
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+
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pci_config_read(NULL, 0, 0x70c, 4, &val);
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val &= ~(0xff) << 8;
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val |= 0x50 << 8;
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pci_config_write(NULL, 0, 0x70c, 4, val);
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pci_load_of_ranges(&mt7620_controller, pdev->dev.of_node);
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register_pci_controller(&mt7620_controller);