···271271 prop->source_ports = BIT(CS35L56_SDW1_CAPTURE_PORT);272272 prop->sink_ports = BIT(CS35L56_SDW1_PLAYBACK_PORT);273273 prop->paging_support = true;274274- prop->clk_stop_mode1 = false;275274 prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;276275 prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY | SDW_SCP_INT1_IMPL_DEF;277276···316317 return 0;317318}318319319319-static int cs35l56_a1_kick_divider(struct cs35l56_private *cs35l56,320320- struct sdw_slave *peripheral)321321-{322322- unsigned int curr_scale_reg, next_scale_reg;323323- int curr_scale, next_scale, ret;324324-325325- if (!cs35l56->base.init_done)326326- return 0;327327-328328- if (peripheral->bus->params.curr_bank) {329329- curr_scale_reg = SDW_SCP_BUSCLOCK_SCALE_B1;330330- next_scale_reg = SDW_SCP_BUSCLOCK_SCALE_B0;331331- } else {332332- curr_scale_reg = SDW_SCP_BUSCLOCK_SCALE_B0;333333- next_scale_reg = SDW_SCP_BUSCLOCK_SCALE_B1;334334- }335335-336336- /*337337- * Current clock scale value must be different to new value.338338- * Modify current to guarantee this. If next still has the dummy339339- * value we wrote when it was current, the core code has not set340340- * a new scale so restore its original good value341341- */342342- curr_scale = sdw_read_no_pm(peripheral, curr_scale_reg);343343- if (curr_scale < 0) {344344- dev_err(cs35l56->base.dev, "Failed to read current clock scale: %d\n", curr_scale);345345- return curr_scale;346346- }347347-348348- next_scale = sdw_read_no_pm(peripheral, next_scale_reg);349349- if (next_scale < 0) {350350- dev_err(cs35l56->base.dev, "Failed to read next clock scale: %d\n", next_scale);351351- return next_scale;352352- }353353-354354- if (next_scale == CS35L56_SDW_INVALID_BUS_SCALE) {355355- next_scale = cs35l56->old_sdw_clock_scale;356356- ret = sdw_write_no_pm(peripheral, next_scale_reg, next_scale);357357- if (ret < 0) {358358- dev_err(cs35l56->base.dev, "Failed to modify current clock scale: %d\n",359359- ret);360360- return ret;361361- }362362- }363363-364364- cs35l56->old_sdw_clock_scale = curr_scale;365365- ret = sdw_write_no_pm(peripheral, curr_scale_reg, CS35L56_SDW_INVALID_BUS_SCALE);366366- if (ret < 0) {367367- dev_err(cs35l56->base.dev, "Failed to modify current clock scale: %d\n", ret);368368- return ret;369369- }370370-371371- dev_dbg(cs35l56->base.dev, "Next bus scale: %#x\n", next_scale);372372-373373- return 0;374374-}375375-376376-static int cs35l56_sdw_bus_config(struct sdw_slave *peripheral,377377- struct sdw_bus_params *params)378378-{379379- struct cs35l56_private *cs35l56 = dev_get_drvdata(&peripheral->dev);380380- int sclk;381381-382382- sclk = params->curr_dr_freq / 2;383383- dev_dbg(cs35l56->base.dev, "%s: sclk=%u c=%u r=%u\n",384384- __func__, sclk, params->col, params->row);385385-386386- if ((cs35l56->base.type == 0x56) && (cs35l56->base.rev < 0xb0))387387- return cs35l56_a1_kick_divider(cs35l56, peripheral);388388-389389- return 0;390390-}391391-392320static int __maybe_unused cs35l56_sdw_clk_stop(struct sdw_slave *peripheral,393321 enum sdw_clk_stop_mode mode,394322 enum sdw_clk_stop_type type)···331405 .read_prop = cs35l56_sdw_read_prop,332406 .interrupt_callback = cs35l56_sdw_interrupt,333407 .update_status = cs35l56_sdw_update_status,334334- .bus_config = cs35l56_sdw_bus_config,335408#ifdef DEBUG336409 .clk_stop = cs35l56_sdw_clk_stop,337410#endif
+26-96
sound/soc/codecs/cs35l56-shared.c
···2020 * Firmware can change these to non-defaults to satisfy SDCA.2121 * Ensure that they are at known defaults.2222 */2323+ { CS35L56_ASP1_ENABLES1, 0x00000000 },2424+ { CS35L56_ASP1_CONTROL1, 0x00000028 },2525+ { CS35L56_ASP1_CONTROL2, 0x18180200 },2626+ { CS35L56_ASP1_CONTROL3, 0x00000002 },2727+ { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 },2828+ { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 },2929+ { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 },3030+ { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 },3131+ { CS35L56_ASP1TX1_INPUT, 0x00000000 },3232+ { CS35L56_ASP1TX2_INPUT, 0x00000000 },3333+ { CS35L56_ASP1TX3_INPUT, 0x00000000 },3434+ { CS35L56_ASP1TX4_INPUT, 0x00000000 },2335 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 },2436 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 },2537 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 },···5341static const struct reg_default cs35l56_reg_defaults[] = {5442 /* no defaults for OTP_MEM - first read populates cache */55435656- /*5757- * No defaults for ASP1 control or ASP1TX mixer. See5858- * cs35l56_populate_asp1_register_defaults() and5959- * cs35l56_sync_asp1_mixer_widgets_with_firmware().6060- */6161-4444+ { CS35L56_ASP1_ENABLES1, 0x00000000 },4545+ { CS35L56_ASP1_CONTROL1, 0x00000028 },4646+ { CS35L56_ASP1_CONTROL2, 0x18180200 },4747+ { CS35L56_ASP1_CONTROL3, 0x00000002 },4848+ { CS35L56_ASP1_FRAME_CONTROL1, 0x03020100 },4949+ { CS35L56_ASP1_FRAME_CONTROL5, 0x00020100 },5050+ { CS35L56_ASP1_DATA_CONTROL1, 0x00000018 },5151+ { CS35L56_ASP1_DATA_CONTROL5, 0x00000018 },5252+ { CS35L56_ASP1TX1_INPUT, 0x00000000 },5353+ { CS35L56_ASP1TX2_INPUT, 0x00000000 },5454+ { CS35L56_ASP1TX3_INPUT, 0x00000000 },5555+ { CS35L56_ASP1TX4_INPUT, 0x00000000 },6256 { CS35L56_SWIRE_DP3_CH1_INPUT, 0x00000018 },6357 { CS35L56_SWIRE_DP3_CH2_INPUT, 0x00000019 },6458 { CS35L56_SWIRE_DP3_CH3_INPUT, 0x00000029 },···224206 }225207}226208227227-static const struct reg_sequence cs35l56_asp1_defaults[] = {228228- REG_SEQ0(CS35L56_ASP1_ENABLES1, 0x00000000),229229- REG_SEQ0(CS35L56_ASP1_CONTROL1, 0x00000028),230230- REG_SEQ0(CS35L56_ASP1_CONTROL2, 0x18180200),231231- REG_SEQ0(CS35L56_ASP1_CONTROL3, 0x00000002),232232- REG_SEQ0(CS35L56_ASP1_FRAME_CONTROL1, 0x03020100),233233- REG_SEQ0(CS35L56_ASP1_FRAME_CONTROL5, 0x00020100),234234- REG_SEQ0(CS35L56_ASP1_DATA_CONTROL1, 0x00000018),235235- REG_SEQ0(CS35L56_ASP1_DATA_CONTROL5, 0x00000018),236236- REG_SEQ0(CS35L56_ASP1TX1_INPUT, 0x00000000),237237- REG_SEQ0(CS35L56_ASP1TX2_INPUT, 0x00000000),238238- REG_SEQ0(CS35L56_ASP1TX3_INPUT, 0x00000000),239239- REG_SEQ0(CS35L56_ASP1TX4_INPUT, 0x00000000),240240-};241241-242242-/*243243- * The firmware can have control of the ASP so we don't provide regmap244244- * with defaults for these registers, to prevent a regcache_sync() from245245- * overwriting the firmware settings. But if the machine driver hooks up246246- * the ASP it means the driver is taking control of the ASP, so then the247247- * registers are populated with the defaults.248248- */249249-int cs35l56_init_asp1_regs_for_driver_control(struct cs35l56_base *cs35l56_base)250250-{251251- if (!cs35l56_base->fw_owns_asp1)252252- return 0;253253-254254- cs35l56_base->fw_owns_asp1 = false;255255-256256- return regmap_multi_reg_write(cs35l56_base->regmap, cs35l56_asp1_defaults,257257- ARRAY_SIZE(cs35l56_asp1_defaults));258258-}259259-EXPORT_SYMBOL_NS_GPL(cs35l56_init_asp1_regs_for_driver_control, SND_SOC_CS35L56_SHARED);260260-261261-/*262262- * The firmware boot sequence can overwrite the ASP1 config registers so that263263- * they don't match regmap's view of their values. Rewrite the values from the264264- * regmap cache into the hardware registers.265265- */266266-int cs35l56_force_sync_asp1_registers_from_cache(struct cs35l56_base *cs35l56_base)267267-{268268- struct reg_sequence asp1_regs[ARRAY_SIZE(cs35l56_asp1_defaults)];269269- int i, ret;270270-271271- if (cs35l56_base->fw_owns_asp1)272272- return 0;273273-274274- memcpy(asp1_regs, cs35l56_asp1_defaults, sizeof(asp1_regs));275275-276276- /* Read current values from regmap cache into the write sequence */277277- for (i = 0; i < ARRAY_SIZE(asp1_regs); ++i) {278278- ret = regmap_read(cs35l56_base->regmap, asp1_regs[i].reg, &asp1_regs[i].def);279279- if (ret)280280- goto err;281281- }282282-283283- /* Write the values cache-bypassed so that they will be written to silicon */284284- ret = regmap_multi_reg_write_bypassed(cs35l56_base->regmap, asp1_regs,285285- ARRAY_SIZE(asp1_regs));286286- if (ret)287287- goto err;288288-289289- return 0;290290-291291-err:292292- dev_err(cs35l56_base->dev, "Failed to sync ASP1 registers: %d\n", ret);293293-294294- return ret;295295-}296296-EXPORT_SYMBOL_NS_GPL(cs35l56_force_sync_asp1_registers_from_cache, SND_SOC_CS35L56_SHARED);297297-298209int cs35l56_mbox_send(struct cs35l56_base *cs35l56_base, unsigned int command)299210{300211 unsigned int val;···245298int cs35l56_firmware_shutdown(struct cs35l56_base *cs35l56_base)246299{247300 int ret;248248- unsigned int reg;249301 unsigned int val;250302251303 ret = cs35l56_mbox_send(cs35l56_base, CS35L56_MBOX_CMD_SHUTDOWN);252304 if (ret)253305 return ret;254306255255- if (cs35l56_base->rev < CS35L56_REVID_B0)256256- reg = CS35L56_DSP1_PM_CUR_STATE_A1;257257- else258258- reg = CS35L56_DSP1_PM_CUR_STATE;259259-260260- ret = regmap_read_poll_timeout(cs35l56_base->regmap, reg,307307+ ret = regmap_read_poll_timeout(cs35l56_base->regmap, CS35L56_DSP1_PM_CUR_STATE,261308 val, (val == CS35L56_HALO_STATE_SHUTDOWN),262309 CS35L56_HALO_STATE_POLL_US,263310 CS35L56_HALO_STATE_TIMEOUT_US);···264323265324int cs35l56_wait_for_firmware_boot(struct cs35l56_base *cs35l56_base)266325{267267- unsigned int reg;268326 unsigned int val = 0;269327 int read_ret, poll_ret;270270-271271- if (cs35l56_base->rev < CS35L56_REVID_B0)272272- reg = CS35L56_DSP1_HALO_STATE_A1;273273- else274274- reg = CS35L56_DSP1_HALO_STATE;275328276329 /*277330 * The regmap must remain in cache-only until the chip has···276341 CS35L56_HALO_STATE_POLL_US,277342 CS35L56_HALO_STATE_TIMEOUT_US,278343 false,279279- cs35l56_base->regmap, reg, &val);344344+ cs35l56_base->regmap, CS35L56_DSP1_HALO_STATE, &val);280345281346 if (poll_ret) {282347 dev_err(cs35l56_base->dev, "Firmware boot timed out(%d): HALO_STATE=%#x\n",···714779 else715780 cs35l56_wait_control_port_ready();716781717717- /*718718- * The HALO_STATE register is in different locations on Ax and B0719719- * devices so the REVID needs to be determined before waiting for the720720- * firmware to boot.721721- */722782 ret = regmap_read_bypassed(cs35l56_base->regmap, CS35L56_REVID, &revid);723783 if (ret < 0) {724784 dev_err(cs35l56_base->dev, "Get Revision ID failed\n");
+13-192
sound/soc/codecs/cs35l56.c
···6363 return snd_soc_put_volsw(kcontrol, ucontrol);6464}65656666-static const unsigned short cs35l56_asp1_mixer_regs[] = {6767- CS35L56_ASP1TX1_INPUT, CS35L56_ASP1TX2_INPUT,6868- CS35L56_ASP1TX3_INPUT, CS35L56_ASP1TX4_INPUT,6969-};7070-7171-static const char * const cs35l56_asp1_mux_control_names[] = {7272- "ASP1 TX1 Source", "ASP1 TX2 Source", "ASP1 TX3 Source", "ASP1 TX4 Source"7373-};7474-7575-static int cs35l56_sync_asp1_mixer_widgets_with_firmware(struct cs35l56_private *cs35l56)7676-{7777- struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(cs35l56->component);7878- const char *prefix = cs35l56->component->name_prefix;7979- char full_name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];8080- const char *name;8181- struct snd_kcontrol *kcontrol;8282- struct soc_enum *e;8383- unsigned int val[4];8484- int i, item, ret;8585-8686- if (cs35l56->asp1_mixer_widgets_initialized)8787- return 0;8888-8989- /*9090- * Resume so we can read the registers from silicon if the regmap9191- * cache has not yet been populated.9292- */9393- ret = pm_runtime_resume_and_get(cs35l56->base.dev);9494- if (ret < 0)9595- return ret;9696-9797- /* Wait for firmware download and reboot */9898- cs35l56_wait_dsp_ready(cs35l56);9999-100100- ret = regmap_bulk_read(cs35l56->base.regmap, CS35L56_ASP1TX1_INPUT,101101- val, ARRAY_SIZE(val));102102-103103- pm_runtime_mark_last_busy(cs35l56->base.dev);104104- pm_runtime_put_autosuspend(cs35l56->base.dev);105105-106106- if (ret) {107107- dev_err(cs35l56->base.dev, "Failed to read ASP1 mixer regs: %d\n", ret);108108- return ret;109109- }110110-111111- for (i = 0; i < ARRAY_SIZE(cs35l56_asp1_mux_control_names); ++i) {112112- name = cs35l56_asp1_mux_control_names[i];113113-114114- if (prefix) {115115- snprintf(full_name, sizeof(full_name), "%s %s", prefix, name);116116- name = full_name;117117- }118118-119119- kcontrol = snd_soc_card_get_kcontrol_locked(dapm->card, name);120120- if (!kcontrol) {121121- dev_warn(cs35l56->base.dev, "Could not find control %s\n", name);122122- continue;123123- }124124-125125- e = (struct soc_enum *)kcontrol->private_value;126126- item = snd_soc_enum_val_to_item(e, val[i] & CS35L56_ASP_TXn_SRC_MASK);127127- snd_soc_dapm_mux_update_power(dapm, kcontrol, item, e, NULL);128128- }129129-130130- cs35l56->asp1_mixer_widgets_initialized = true;131131-132132- return 0;133133-}134134-135135-static int cs35l56_dspwait_asp1tx_get(struct snd_kcontrol *kcontrol,136136- struct snd_ctl_elem_value *ucontrol)137137-{138138- struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);139139- struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component);140140- struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;141141- int index = e->shift_l;142142- unsigned int addr, val;143143- int ret;144144-145145- ret = cs35l56_sync_asp1_mixer_widgets_with_firmware(cs35l56);146146- if (ret)147147- return ret;148148-149149- addr = cs35l56_asp1_mixer_regs[index];150150- ret = regmap_read(cs35l56->base.regmap, addr, &val);151151- if (ret)152152- return ret;153153-154154- val &= CS35L56_ASP_TXn_SRC_MASK;155155- ucontrol->value.enumerated.item[0] = snd_soc_enum_val_to_item(e, val);156156-157157- return 0;158158-}159159-160160-static int cs35l56_dspwait_asp1tx_put(struct snd_kcontrol *kcontrol,161161- struct snd_ctl_elem_value *ucontrol)162162-{163163- struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);164164- struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kcontrol);165165- struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component);166166- struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;167167- int item = ucontrol->value.enumerated.item[0];168168- int index = e->shift_l;169169- unsigned int addr, val;170170- bool changed;171171- int ret;172172-173173- ret = cs35l56_sync_asp1_mixer_widgets_with_firmware(cs35l56);174174- if (ret)175175- return ret;176176-177177- addr = cs35l56_asp1_mixer_regs[index];178178- val = snd_soc_enum_item_to_val(e, item);179179-180180- ret = regmap_update_bits_check(cs35l56->base.regmap, addr,181181- CS35L56_ASP_TXn_SRC_MASK, val, &changed);182182- if (ret)183183- return ret;184184-185185- if (changed)186186- snd_soc_dapm_mux_update_power(dapm, kcontrol, item, e, NULL);187187-188188- return changed;189189-}190190-19166static DECLARE_TLV_DB_SCALE(vol_tlv, -10000, 25, 0);1926719368static const struct snd_kcontrol_new cs35l56_controls[] = {···81206};8220783208static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_asp1tx1_enum,8484- SND_SOC_NOPM,8585- 0, 0,209209+ CS35L56_ASP1TX1_INPUT,210210+ 0, CS35L56_ASP_TXn_SRC_MASK,86211 cs35l56_tx_input_texts,87212 cs35l56_tx_input_values);8821389214static const struct snd_kcontrol_new asp1_tx1_mux =9090- SOC_DAPM_ENUM_EXT("ASP1TX1 SRC", cs35l56_asp1tx1_enum,9191- cs35l56_dspwait_asp1tx_get, cs35l56_dspwait_asp1tx_put);215215+ SOC_DAPM_ENUM("ASP1TX1 SRC", cs35l56_asp1tx1_enum);9221693217static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_asp1tx2_enum,9494- SND_SOC_NOPM,9595- 1, 0,218218+ CS35L56_ASP1TX2_INPUT,219219+ 0, CS35L56_ASP_TXn_SRC_MASK,96220 cs35l56_tx_input_texts,97221 cs35l56_tx_input_values);9822299223static const struct snd_kcontrol_new asp1_tx2_mux =100100- SOC_DAPM_ENUM_EXT("ASP1TX2 SRC", cs35l56_asp1tx2_enum,101101- cs35l56_dspwait_asp1tx_get, cs35l56_dspwait_asp1tx_put);224224+ SOC_DAPM_ENUM("ASP1TX2 SRC", cs35l56_asp1tx2_enum);102225103226static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_asp1tx3_enum,104104- SND_SOC_NOPM,105105- 2, 0,227227+ CS35L56_ASP1TX3_INPUT,228228+ 0, CS35L56_ASP_TXn_SRC_MASK,106229 cs35l56_tx_input_texts,107230 cs35l56_tx_input_values);108231109232static const struct snd_kcontrol_new asp1_tx3_mux =110110- SOC_DAPM_ENUM_EXT("ASP1TX3 SRC", cs35l56_asp1tx3_enum,111111- cs35l56_dspwait_asp1tx_get, cs35l56_dspwait_asp1tx_put);233233+ SOC_DAPM_ENUM("ASP1TX3 SRC", cs35l56_asp1tx3_enum);112234113235static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_asp1tx4_enum,114114- SND_SOC_NOPM,115115- 3, 0,236236+ CS35L56_ASP1TX4_INPUT,237237+ 0, CS35L56_ASP_TXn_SRC_MASK,116238 cs35l56_tx_input_texts,117239 cs35l56_tx_input_values);118240119241static const struct snd_kcontrol_new asp1_tx4_mux =120120- SOC_DAPM_ENUM_EXT("ASP1TX4 SRC", cs35l56_asp1tx4_enum,121121- cs35l56_dspwait_asp1tx_get, cs35l56_dspwait_asp1tx_put);242242+ SOC_DAPM_ENUM("ASP1TX4 SRC", cs35l56_asp1tx4_enum);122243123244static SOC_VALUE_ENUM_SINGLE_DECL(cs35l56_sdw1tx1_enum,124245 CS35L56_SWIRE_DP3_CH1_INPUT,···152281static const struct snd_kcontrol_new sdw1_tx4_mux =153282 SOC_DAPM_ENUM("SDW1TX4 SRC", cs35l56_sdw1tx4_enum);154283155155-static int cs35l56_asp1_cfg_event(struct snd_soc_dapm_widget *w,156156- struct snd_kcontrol *kcontrol, int event)157157-{158158- struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);159159- struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(component);160160-161161- switch (event) {162162- case SND_SOC_DAPM_PRE_PMU:163163- /* Override register values set by firmware boot */164164- return cs35l56_force_sync_asp1_registers_from_cache(&cs35l56->base);165165- default:166166- return 0;167167- }168168-}169169-170284static int cs35l56_play_event(struct snd_soc_dapm_widget *w,171285 struct snd_kcontrol *kcontrol, int event)172286{···187331static const struct snd_soc_dapm_widget cs35l56_dapm_widgets[] = {188332 SND_SOC_DAPM_REGULATOR_SUPPLY("VDD_B", 0, 0),189333 SND_SOC_DAPM_REGULATOR_SUPPLY("VDD_AMP", 0, 0),190190-191191- SND_SOC_DAPM_SUPPLY("ASP1 CFG", SND_SOC_NOPM, 0, 0, cs35l56_asp1_cfg_event,192192- SND_SOC_DAPM_PRE_PMU),193334194335 SND_SOC_DAPM_SUPPLY("PLAY", SND_SOC_NOPM, 0, 0, cs35l56_play_event,195336 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),···255402 { "AMP", NULL, "VDD_B" },256403 { "AMP", NULL, "VDD_AMP" },257404258258- { "ASP1 Playback", NULL, "ASP1 CFG" },259259- { "ASP1 Capture", NULL, "ASP1 CFG" },260260-261405 { "ASP1 Playback", NULL, "PLAY" },262406 { "SDW1 Playback", NULL, "PLAY" },263407···305455{306456 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(codec_dai->component);307457 unsigned int val;308308- int ret;309458310459 dev_dbg(cs35l56->base.dev, "%s: %#x\n", __func__, fmt);311311-312312- ret = cs35l56_init_asp1_regs_for_driver_control(&cs35l56->base);313313- if (ret)314314- return ret;315460316461 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {317462 case SND_SOC_DAIFMT_CBC_CFC:···381536 unsigned int rx_mask, int slots, int slot_width)382537{383538 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(dai->component);384384- int ret;385385-386386- ret = cs35l56_init_asp1_regs_for_driver_control(&cs35l56->base);387387- if (ret)388388- return ret;389539390540 if ((slots == 0) || (slot_width == 0)) {391541 dev_dbg(cs35l56->base.dev, "tdm config cleared\n");···429589 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(dai->component);430590 unsigned int rate = params_rate(params);431591 u8 asp_width, asp_wl;432432- int ret;433433-434434- ret = cs35l56_init_asp1_regs_for_driver_control(&cs35l56->base);435435- if (ret)436436- return ret;437592438593 asp_wl = params_width(params);439594 if (cs35l56->asp_slot_width)···485650 int clk_id, unsigned int freq, int dir)486651{487652 struct cs35l56_private *cs35l56 = snd_soc_component_get_drvdata(dai->component);488488- int freq_id, ret;489489-490490- ret = cs35l56_init_asp1_regs_for_driver_control(&cs35l56->base);491491- if (ret)492492- return ret;653653+ int freq_id;493654494655 if (freq == 0) {495656 cs35l56->sysclk_set = false;···8651034 debugfs_create_bool("init_done", 0444, debugfs_root, &cs35l56->base.init_done);8661035 debugfs_create_bool("can_hibernate", 0444, debugfs_root, &cs35l56->base.can_hibernate);8671036 debugfs_create_bool("fw_patched", 0444, debugfs_root, &cs35l56->base.fw_patched);868868-869869- /*870870- * The widgets for the ASP1TX mixer can't be initialized871871- * until the firmware has been downloaded and rebooted.872872- */873873- regcache_drop_region(cs35l56->base.regmap, CS35L56_ASP1TX1_INPUT, CS35L56_ASP1TX4_INPUT);874874- cs35l56->asp1_mixer_widgets_initialized = false;87510378761038 queue_work(cs35l56->dsp_wq, &cs35l56->dsp_work);8771039···12551431 mutex_init(&cs35l56->base.irq_lock);12561432 cs35l56->base.cal_index = -1;12571433 cs35l56->speaker_id = -ENOENT;12581258-12591259- /* Assume that the firmware owns ASP1 until we know different */12601260- cs35l56->base.fw_owns_asp1 = true;1261143412621435 dev_set_drvdata(cs35l56->base.dev, cs35l56);12631436