Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'mtd/for-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux
Pull MTD updates from Miquel Raynal:
"MTD device changes:
- switch platform_driver back to remove()
- misc fixes
SPI-NAND changes:
- a load of fixes to Winbond manufacturer driver
- structure constification
Raw NAND changes:
- improve the power management of the GPMI driver
- Davinci driver clean-ups
- fix leak in the Atmel driver
- fix some typos in the core
SPI NOR changes:
- Introduce byte swap support for 8D-8D-8D mode and a user for it:
macronix.
SPI NOR flashes may swap the bytes on a 16-bit boundary when
configured in Octal DTR mode. For such cases the byte order is
propagated through SPI MEM to the SPI controllers so that the
controllers swap the bytes back at runtime. This avoids breaking
the boot sequence because of the endianness problems that appear
when the bootloaders use 1-1-1 and the kernel uses 8D-8D-8D with
byte swap support. Along with the SPI MEM byte swap support we
queue a patch for the SPI MXIC controller that swaps the bytes back
at runtime"
* tag 'mtd/for-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (25 commits)
mtd: spi-nor: core: replace dummy buswidth from addr to data
mtd: spi-nor: winbond: add "w/ and w/o SFDP" comment
mtd: spi-nor: spansion: Use nor->addr_nbytes in octal DTR mode in RD_ANY_REG_OP
mtd: Switch back to struct platform_driver::remove()
mtd: cfi_cmdset_0002: remove redundant assignment to variable ret
mtd: spinand: Constify struct nand_ecc_engine_ops
MAINTAINERS: add mailing list for GPMI NAND driver
mtd: spinand: winbond: Sort the devices
mtd: spinand: winbond: Ignore the last ID characters
mtd: spinand: winbond: Fix 512GW, 01GW, 01JW and 02JW ECC information
mtd: spinand: winbond: Fix 512GW and 02JW OOB layout
mtd: nand: raw: gpmi: improve power management handling
mtd: nand: raw: gpmi: switch to SYSTEM_SLEEP_PM_OPS
mtd: rawnand: davinci: use generic device property helpers
mtd: rawnand: davinci: break the line correctly
mtd: rawnand: davinci: order headers alphabetically
mtd: rawnand: atmel: Fix possible memory leak
mtd: rawnand: Correct multiple typos in comments
mtd: hyperbus: rpc-if: Add missing MODULE_DEVICE_TABLE
mtd: spi-nor: add support for Macronix Octal flash
...
+368
-226
+1
MAINTAINERS
+1
MAINTAINERS
+1
-3
drivers/mtd/chips/cfi_cmdset_0002.c
+1
-3
drivers/mtd/chips/cfi_cmdset_0002.c
···
1779
1779
map_write(map, CMD(0xF0), chip->start);
1780
1780
/* FIXME - should have reset delay before continuing */
1781
1781
1782
-
if (++retry_cnt <= MAX_RETRIES) {
1783
-
ret = 0;
1782
+
if (++retry_cnt <= MAX_RETRIES)
1784
1783
goto retry;
1785
-
}
1786
1784
}
1787
1785
xip_enable(map, chip, adr);
1788
1786
+1
-1
drivers/mtd/devices/bcm47xxsflash.c
+1
-1
drivers/mtd/devices/bcm47xxsflash.c
+1
-1
drivers/mtd/devices/docg3.c
+1
-1
drivers/mtd/devices/docg3.c
+1
-1
drivers/mtd/devices/phram.c
+1
-1
drivers/mtd/devices/phram.c
+1
-1
drivers/mtd/devices/powernv_flash.c
+1
-1
drivers/mtd/devices/powernv_flash.c
+1
-1
drivers/mtd/devices/spear_smi.c
+1
-1
drivers/mtd/devices/spear_smi.c
+1
-1
drivers/mtd/devices/st_spi_fsm.c
+1
-1
drivers/mtd/devices/st_spi_fsm.c
+1
-1
drivers/mtd/hyperbus/hbmc-am654.c
+1
-1
drivers/mtd/hyperbus/hbmc-am654.c
+8
-1
drivers/mtd/hyperbus/rpc-if.c
+8
-1
drivers/mtd/hyperbus/rpc-if.c
···
163
163
pm_runtime_disable(hyperbus->rpc.dev);
164
164
}
165
165
166
+
static const struct platform_device_id rpc_if_hyperflash_id_table[] = {
167
+
{ .name = "rpc-if-hyperflash" },
168
+
{ /* sentinel */ }
169
+
};
170
+
MODULE_DEVICE_TABLE(platform, rpc_if_hyperflash_id_table);
171
+
166
172
static struct platform_driver rpcif_platform_driver = {
167
173
.probe = rpcif_hb_probe,
168
-
.remove_new = rpcif_hb_remove,
174
+
.remove = rpcif_hb_remove,
175
+
.id_table = rpc_if_hyperflash_id_table,
169
176
.driver = {
170
177
.name = "rpc-if-hyperflash",
171
178
},
+1
-1
drivers/mtd/lpddr/lpddr2_nvm.c
+1
-1
drivers/mtd/lpddr/lpddr2_nvm.c
+1
-1
drivers/mtd/maps/lantiq-flash.c
+1
-1
drivers/mtd/maps/lantiq-flash.c
+1
-1
drivers/mtd/maps/physmap-core.c
+1
-1
drivers/mtd/maps/physmap-core.c
+1
-1
drivers/mtd/maps/plat-ram.c
+1
-1
drivers/mtd/maps/plat-ram.c
+1
-1
drivers/mtd/maps/pxa2xx-flash.c
+1
-1
drivers/mtd/maps/pxa2xx-flash.c
+1
-1
drivers/mtd/maps/sa1100-flash.c
+1
-1
drivers/mtd/maps/sa1100-flash.c
+1
-1
drivers/mtd/maps/sun_uflash.c
+1
-1
drivers/mtd/maps/sun_uflash.c
+4
-4
drivers/mtd/nand/ecc-mxic.c
+4
-4
drivers/mtd/nand/ecc-mxic.c
···
723
723
return ret;
724
724
}
725
725
726
-
static struct nand_ecc_engine_ops mxic_ecc_engine_external_ops = {
726
+
static const struct nand_ecc_engine_ops mxic_ecc_engine_external_ops = {
727
727
.init_ctx = mxic_ecc_init_ctx_external,
728
728
.cleanup_ctx = mxic_ecc_cleanup_ctx,
729
729
.prepare_io_req = mxic_ecc_prepare_io_req_external,
730
730
.finish_io_req = mxic_ecc_finish_io_req_external,
731
731
};
732
732
733
-
static struct nand_ecc_engine_ops mxic_ecc_engine_pipelined_ops = {
733
+
static const struct nand_ecc_engine_ops mxic_ecc_engine_pipelined_ops = {
734
734
.init_ctx = mxic_ecc_init_ctx_pipelined,
735
735
.cleanup_ctx = mxic_ecc_cleanup_ctx,
736
736
.prepare_io_req = mxic_ecc_prepare_io_req_pipelined,
737
737
.finish_io_req = mxic_ecc_finish_io_req_pipelined,
738
738
};
739
739
740
-
struct nand_ecc_engine_ops *mxic_ecc_get_pipelined_ops(void)
740
+
const struct nand_ecc_engine_ops *mxic_ecc_get_pipelined_ops(void)
741
741
{
742
742
return &mxic_ecc_engine_pipelined_ops;
743
743
}
···
869
869
.of_match_table = mxic_ecc_of_ids,
870
870
},
871
871
.probe = mxic_ecc_probe,
872
-
.remove_new = mxic_ecc_remove,
872
+
.remove = mxic_ecc_remove,
873
873
};
874
874
module_platform_driver(mxic_ecc_driver);
875
875
+1
-1
drivers/mtd/nand/ecc-sw-bch.c
+1
-1
drivers/mtd/nand/ecc-sw-bch.c
···
384
384
return max_bitflips;
385
385
}
386
386
387
-
static struct nand_ecc_engine_ops nand_ecc_sw_bch_engine_ops = {
387
+
static const struct nand_ecc_engine_ops nand_ecc_sw_bch_engine_ops = {
388
388
.init_ctx = nand_ecc_sw_bch_init_ctx,
389
389
.cleanup_ctx = nand_ecc_sw_bch_cleanup_ctx,
390
390
.prepare_io_req = nand_ecc_sw_bch_prepare_io_req,
+1
-1
drivers/mtd/nand/ecc-sw-hamming.c
+1
-1
drivers/mtd/nand/ecc-sw-hamming.c
···
638
638
return max_bitflips;
639
639
}
640
640
641
-
static struct nand_ecc_engine_ops nand_ecc_sw_hamming_engine_ops = {
641
+
static const struct nand_ecc_engine_ops nand_ecc_sw_hamming_engine_ops = {
642
642
.init_ctx = nand_ecc_sw_hamming_init_ctx,
643
643
.cleanup_ctx = nand_ecc_sw_hamming_cleanup_ctx,
644
644
.prepare_io_req = nand_ecc_sw_hamming_prepare_io_req,
+1
-1
drivers/mtd/nand/onenand/generic.c
+1
-1
drivers/mtd/nand/onenand/generic.c
+1
-1
drivers/mtd/nand/onenand/onenand_omap2.c
+1
-1
drivers/mtd/nand/onenand/onenand_omap2.c
+1
-1
drivers/mtd/nand/onenand/onenand_samsung.c
+1
-1
drivers/mtd/nand/onenand/onenand_samsung.c
+1
-1
drivers/mtd/nand/raw/ams-delta.c
+1
-1
drivers/mtd/nand/raw/ams-delta.c
+1
-1
drivers/mtd/nand/raw/arasan-nand-controller.c
+1
-1
drivers/mtd/nand/raw/arasan-nand-controller.c
+1
-1
drivers/mtd/nand/raw/atmel/nand-controller.c
+1
-1
drivers/mtd/nand/raw/atmel/nand-controller.c
+1
-7
drivers/mtd/nand/raw/atmel/pmecc.c
+1
-7
drivers/mtd/nand/raw/atmel/pmecc.c
···
362
362
size = ALIGN(size, sizeof(s32));
363
363
size += (req->ecc.strength + 1) * sizeof(s32) * 3;
364
364
365
-
user = kzalloc(size, GFP_KERNEL);
365
+
user = devm_kzalloc(pmecc->dev, size, GFP_KERNEL);
366
366
if (!user)
367
367
return ERR_PTR(-ENOMEM);
368
368
···
407
407
return user;
408
408
}
409
409
EXPORT_SYMBOL_GPL(atmel_pmecc_create_user);
410
-
411
-
void atmel_pmecc_destroy_user(struct atmel_pmecc_user *user)
412
-
{
413
-
kfree(user);
414
-
}
415
-
EXPORT_SYMBOL_GPL(atmel_pmecc_destroy_user);
416
410
417
411
static int get_strength(struct atmel_pmecc_user *user)
418
412
{
-2
drivers/mtd/nand/raw/atmel/pmecc.h
-2
drivers/mtd/nand/raw/atmel/pmecc.h
···
55
55
struct atmel_pmecc_user *
56
56
atmel_pmecc_create_user(struct atmel_pmecc *pmecc,
57
57
struct atmel_pmecc_user_req *req);
58
-
void atmel_pmecc_destroy_user(struct atmel_pmecc_user *user);
59
-
60
58
void atmel_pmecc_reset(struct atmel_pmecc *pmecc);
61
59
int atmel_pmecc_enable(struct atmel_pmecc_user *user, int op);
62
60
void atmel_pmecc_disable(struct atmel_pmecc_user *user);
+1
-1
drivers/mtd/nand/raw/au1550nd.c
+1
-1
drivers/mtd/nand/raw/au1550nd.c
+1
-1
drivers/mtd/nand/raw/bcm47xxnflash/main.c
+1
-1
drivers/mtd/nand/raw/bcm47xxnflash/main.c
+1
-1
drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c
+1
-1
drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c
+1
-1
drivers/mtd/nand/raw/brcmnand/bcma_nand.c
+1
-1
drivers/mtd/nand/raw/brcmnand/bcma_nand.c
+1
-1
drivers/mtd/nand/raw/brcmnand/bcmbca_nand.c
+1
-1
drivers/mtd/nand/raw/brcmnand/bcmbca_nand.c
+1
-1
drivers/mtd/nand/raw/brcmnand/brcmnand.c
+1
-1
drivers/mtd/nand/raw/brcmnand/brcmnand.c
+1
-1
drivers/mtd/nand/raw/brcmnand/brcmstb_nand.c
+1
-1
drivers/mtd/nand/raw/brcmnand/brcmstb_nand.c
+1
-1
drivers/mtd/nand/raw/brcmnand/iproc_nand.c
+1
-1
drivers/mtd/nand/raw/brcmnand/iproc_nand.c
+2
-2
drivers/mtd/nand/raw/cadence-nand-controller.c
+2
-2
drivers/mtd/nand/raw/cadence-nand-controller.c
···
1891
1891
1892
1892
int len_in_words = (data_dma_width == 4) ? len >> 2 : len >> 3;
1893
1893
1894
-
/* read alingment data */
1894
+
/* read alignment data */
1895
1895
if (data_dma_width == 4)
1896
1896
ioread32_rep(cdns_ctrl->io.virt, buf, len_in_words);
1897
1897
#ifdef CONFIG_64BIT
···
3055
3055
3056
3056
static struct platform_driver cadence_nand_dt_driver = {
3057
3057
.probe = cadence_nand_dt_probe,
3058
-
.remove_new = cadence_nand_dt_remove,
3058
+
.remove = cadence_nand_dt_remove,
3059
3059
.driver = {
3060
3060
.name = "cadence-nand-controller",
3061
3061
.of_match_table = cadence_nand_dt_ids,
+1
-1
drivers/mtd/nand/raw/cs553x_nand.c
+1
-1
drivers/mtd/nand/raw/cs553x_nand.c
+30
-30
drivers/mtd/nand/raw/davinci_nand.c
+30
-30
drivers/mtd/nand/raw/davinci_nand.c
···
10
10
* Dirk Behme <Dirk.Behme@gmail.com>
11
11
*/
12
12
13
-
#include <linux/kernel.h>
14
-
#include <linux/module.h>
15
-
#include <linux/platform_device.h>
16
13
#include <linux/err.h>
17
14
#include <linux/iopoll.h>
18
-
#include <linux/mtd/rawnand.h>
15
+
#include <linux/kernel.h>
16
+
#include <linux/module.h>
19
17
#include <linux/mtd/partitions.h>
18
+
#include <linux/mtd/rawnand.h>
19
+
#include <linux/platform_device.h>
20
+
#include <linux/property.h>
20
21
#include <linux/slab.h>
21
-
#include <linux/of.h>
22
22
23
23
#define NRCSR_OFFSET 0x00
24
24
#define NANDFCR_OFFSET 0x60
···
487
487
};
488
488
MODULE_DEVICE_TABLE(of, davinci_nand_of_match);
489
489
490
-
static struct davinci_nand_pdata
491
-
*nand_davinci_get_pdata(struct platform_device *pdev)
490
+
static struct davinci_nand_pdata *
491
+
nand_davinci_get_pdata(struct platform_device *pdev)
492
492
{
493
-
if (!dev_get_platdata(&pdev->dev) && pdev->dev.of_node) {
493
+
if (!dev_get_platdata(&pdev->dev)) {
494
494
struct davinci_nand_pdata *pdata;
495
495
const char *mode;
496
496
u32 prop;
···
501
501
pdev->dev.platform_data = pdata;
502
502
if (!pdata)
503
503
return ERR_PTR(-ENOMEM);
504
-
if (!of_property_read_u32(pdev->dev.of_node,
505
-
"ti,davinci-chipselect", &prop))
504
+
if (!device_property_read_u32(&pdev->dev,
505
+
"ti,davinci-chipselect", &prop))
506
506
pdata->core_chipsel = prop;
507
507
else
508
508
return ERR_PTR(-EINVAL);
509
509
510
-
if (!of_property_read_u32(pdev->dev.of_node,
511
-
"ti,davinci-mask-ale", &prop))
510
+
if (!device_property_read_u32(&pdev->dev,
511
+
"ti,davinci-mask-ale", &prop))
512
512
pdata->mask_ale = prop;
513
-
if (!of_property_read_u32(pdev->dev.of_node,
514
-
"ti,davinci-mask-cle", &prop))
513
+
if (!device_property_read_u32(&pdev->dev,
514
+
"ti,davinci-mask-cle", &prop))
515
515
pdata->mask_cle = prop;
516
-
if (!of_property_read_u32(pdev->dev.of_node,
517
-
"ti,davinci-mask-chipsel", &prop))
516
+
if (!device_property_read_u32(&pdev->dev,
517
+
"ti,davinci-mask-chipsel", &prop))
518
518
pdata->mask_chipsel = prop;
519
-
if (!of_property_read_string(pdev->dev.of_node,
520
-
"ti,davinci-ecc-mode", &mode)) {
519
+
if (!device_property_read_string(&pdev->dev,
520
+
"ti,davinci-ecc-mode",
521
+
&mode)) {
521
522
if (!strncmp("none", mode, 4))
522
523
pdata->engine_type = NAND_ECC_ENGINE_TYPE_NONE;
523
524
if (!strncmp("soft", mode, 4))
···
526
525
if (!strncmp("hw", mode, 2))
527
526
pdata->engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
528
527
}
529
-
if (!of_property_read_u32(pdev->dev.of_node,
530
-
"ti,davinci-ecc-bits", &prop))
528
+
if (!device_property_read_u32(&pdev->dev,
529
+
"ti,davinci-ecc-bits", &prop))
531
530
pdata->ecc_bits = prop;
532
531
533
-
if (!of_property_read_u32(pdev->dev.of_node,
534
-
"ti,davinci-nand-buswidth", &prop) && prop == 16)
532
+
if (!device_property_read_u32(&pdev->dev,
533
+
"ti,davinci-nand-buswidth",
534
+
&prop) && prop == 16)
535
535
pdata->options |= NAND_BUSWIDTH_16;
536
536
537
-
if (of_property_read_bool(pdev->dev.of_node,
538
-
"ti,davinci-nand-use-bbt"))
537
+
if (device_property_read_bool(&pdev->dev,
538
+
"ti,davinci-nand-use-bbt"))
539
539
pdata->bbt_options = NAND_BBT_USE_FLASH;
540
540
541
541
/*
···
550
548
* then use "ti,davinci-nand" as the compatible in your
551
549
* device-tree file.
552
550
*/
553
-
if (of_device_is_compatible(pdev->dev.of_node,
554
-
"ti,keystone-nand")) {
551
+
if (device_is_compatible(&pdev->dev, "ti,keystone-nand"))
555
552
pdata->options |= NAND_NO_SUBPAGE_WRITE;
556
-
}
557
553
}
558
554
559
555
return dev_get_platdata(&pdev->dev);
560
556
}
561
557
#else
562
-
static struct davinci_nand_pdata
563
-
*nand_davinci_get_pdata(struct platform_device *pdev)
558
+
static struct davinci_nand_pdata *
559
+
nand_davinci_get_pdata(struct platform_device *pdev)
564
560
{
565
561
return dev_get_platdata(&pdev->dev);
566
562
}
···
901
901
902
902
static struct platform_driver nand_davinci_driver = {
903
903
.probe = nand_davinci_probe,
904
-
.remove_new = nand_davinci_remove,
904
+
.remove = nand_davinci_remove,
905
905
.driver = {
906
906
.name = "davinci_nand",
907
907
.of_match_table = of_match_ptr(davinci_nand_of_match),
+1
-1
drivers/mtd/nand/raw/denali_dt.c
+1
-1
drivers/mtd/nand/raw/denali_dt.c
+1
-1
drivers/mtd/nand/raw/fsl_elbc_nand.c
+1
-1
drivers/mtd/nand/raw/fsl_elbc_nand.c
+1
-1
drivers/mtd/nand/raw/fsl_ifc_nand.c
+1
-1
drivers/mtd/nand/raw/fsl_ifc_nand.c
+1
-1
drivers/mtd/nand/raw/fsl_upm.c
+1
-1
drivers/mtd/nand/raw/fsl_upm.c
+1
-1
drivers/mtd/nand/raw/fsmc_nand.c
+1
-1
drivers/mtd/nand/raw/fsmc_nand.c
···
1221
1221
MODULE_DEVICE_TABLE(of, fsmc_nand_id_table);
1222
1222
1223
1223
static struct platform_driver fsmc_nand_driver = {
1224
-
.remove_new = fsmc_nand_remove,
1224
+
.remove = fsmc_nand_remove,
1225
1225
.driver = {
1226
1226
.name = "fsmc-nand",
1227
1227
.of_match_table = fsmc_nand_id_table,
+1
-1
drivers/mtd/nand/raw/gpio.c
+1
-1
drivers/mtd/nand/raw/gpio.c
+37
-32
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
+37
-32
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
···
15
15
#include <linux/of.h>
16
16
#include <linux/platform_device.h>
17
17
#include <linux/pm_runtime.h>
18
+
#include <linux/pinctrl/consumer.h>
18
19
#include <linux/dma/mxs-dma.h>
19
20
#include "gpmi-nand.h"
20
21
#include "gpmi-regs.h"
···
738
737
if (ret)
739
738
return ret;
740
739
741
-
ret = pm_runtime_get_sync(this->dev);
740
+
ret = pm_runtime_resume_and_get(this->dev);
742
741
if (ret < 0) {
743
-
pm_runtime_put_autosuspend(this->dev);
744
742
return ret;
745
743
}
746
744
···
2761
2761
if (ret)
2762
2762
goto exit_acquire_resources;
2763
2763
2764
-
ret = __gpmi_enable_clk(this, true);
2765
-
if (ret)
2766
-
goto exit_acquire_resources;
2767
-
2764
+
pm_runtime_enable(&pdev->dev);
2768
2765
pm_runtime_set_autosuspend_delay(&pdev->dev, 500);
2769
2766
pm_runtime_use_autosuspend(&pdev->dev);
2770
-
pm_runtime_set_active(&pdev->dev);
2771
-
pm_runtime_enable(&pdev->dev);
2772
-
pm_runtime_get_sync(&pdev->dev);
2773
2767
2774
2768
ret = gpmi_init(this);
2775
2769
if (ret)
···
2773
2779
if (ret)
2774
2780
goto exit_nfc_init;
2775
2781
2776
-
pm_runtime_mark_last_busy(&pdev->dev);
2777
-
pm_runtime_put_autosuspend(&pdev->dev);
2778
-
2779
2782
dev_info(this->dev, "driver registered.\n");
2780
2783
2781
2784
return 0;
2782
2785
2783
2786
exit_nfc_init:
2784
-
pm_runtime_put(&pdev->dev);
2787
+
pm_runtime_dont_use_autosuspend(&pdev->dev);
2785
2788
pm_runtime_disable(&pdev->dev);
2786
2789
release_resources(this);
2787
2790
exit_acquire_resources:
···
2792
2801
struct nand_chip *chip = &this->nand;
2793
2802
int ret;
2794
2803
2795
-
pm_runtime_put_sync(&pdev->dev);
2796
-
pm_runtime_disable(&pdev->dev);
2797
-
2798
2804
ret = mtd_device_unregister(nand_to_mtd(chip));
2799
2805
WARN_ON(ret);
2800
2806
nand_cleanup(chip);
2801
2807
gpmi_free_dma_buffer(this);
2802
2808
release_resources(this);
2809
+
pm_runtime_dont_use_autosuspend(&pdev->dev);
2810
+
pm_runtime_disable(&pdev->dev);
2803
2811
}
2804
2812
2805
-
#ifdef CONFIG_PM_SLEEP
2806
2813
static int gpmi_pm_suspend(struct device *dev)
2807
2814
{
2808
-
struct gpmi_nand_data *this = dev_get_drvdata(dev);
2815
+
int ret;
2809
2816
2810
-
release_dma_channels(this);
2811
-
return 0;
2817
+
pinctrl_pm_select_sleep_state(dev);
2818
+
ret = pm_runtime_force_suspend(dev);
2819
+
2820
+
return ret;
2812
2821
}
2813
2822
2814
2823
static int gpmi_pm_resume(struct device *dev)
···
2816
2825
struct gpmi_nand_data *this = dev_get_drvdata(dev);
2817
2826
int ret;
2818
2827
2819
-
ret = acquire_dma_channels(this);
2820
-
if (ret < 0)
2828
+
ret = pm_runtime_force_resume(dev);
2829
+
if (ret) {
2830
+
dev_err(this->dev, "Error in resume %d\n", ret);
2821
2831
return ret;
2832
+
}
2833
+
2834
+
pinctrl_pm_select_default_state(dev);
2822
2835
2823
2836
/* re-init the GPMI registers */
2824
2837
ret = gpmi_init(this);
···
2844
2849
2845
2850
return 0;
2846
2851
}
2847
-
#endif /* CONFIG_PM_SLEEP */
2848
2852
2849
-
static int __maybe_unused gpmi_runtime_suspend(struct device *dev)
2853
+
#define gpmi_enable_clk(x) __gpmi_enable_clk(x, true)
2854
+
#define gpmi_disable_clk(x) __gpmi_enable_clk(x, false)
2855
+
2856
+
static int gpmi_runtime_suspend(struct device *dev)
2850
2857
{
2851
2858
struct gpmi_nand_data *this = dev_get_drvdata(dev);
2852
2859
2853
-
return __gpmi_enable_clk(this, false);
2860
+
gpmi_disable_clk(this);
2861
+
2862
+
return 0;
2854
2863
}
2855
2864
2856
-
static int __maybe_unused gpmi_runtime_resume(struct device *dev)
2865
+
static int gpmi_runtime_resume(struct device *dev)
2857
2866
{
2858
2867
struct gpmi_nand_data *this = dev_get_drvdata(dev);
2868
+
int ret;
2859
2869
2860
-
return __gpmi_enable_clk(this, true);
2870
+
ret = gpmi_enable_clk(this);
2871
+
if (ret)
2872
+
return ret;
2873
+
2874
+
return 0;
2875
+
2861
2876
}
2862
2877
2863
2878
static const struct dev_pm_ops gpmi_pm_ops = {
2864
-
SET_SYSTEM_SLEEP_PM_OPS(gpmi_pm_suspend, gpmi_pm_resume)
2865
-
SET_RUNTIME_PM_OPS(gpmi_runtime_suspend, gpmi_runtime_resume, NULL)
2879
+
SYSTEM_SLEEP_PM_OPS(gpmi_pm_suspend, gpmi_pm_resume)
2880
+
RUNTIME_PM_OPS(gpmi_runtime_suspend, gpmi_runtime_resume, NULL)
2866
2881
};
2867
2882
2868
2883
static struct platform_driver gpmi_nand_driver = {
2869
2884
.driver = {
2870
2885
.name = "gpmi-nand",
2871
-
.pm = &gpmi_pm_ops,
2886
+
.pm = pm_ptr(&gpmi_pm_ops),
2872
2887
.of_match_table = gpmi_nand_id_table,
2873
2888
},
2874
-
.probe = gpmi_nand_probe,
2875
-
.remove_new = gpmi_nand_remove,
2889
+
.probe = gpmi_nand_probe,
2890
+
.remove = gpmi_nand_remove,
2876
2891
};
2877
2892
module_platform_driver(gpmi_nand_driver);
2878
2893
+1
-1
drivers/mtd/nand/raw/hisi504_nand.c
+1
-1
drivers/mtd/nand/raw/hisi504_nand.c
+1
-1
drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c
+1
-1
drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c
+1
-1
drivers/mtd/nand/raw/intel-nand-controller.c
+1
-1
drivers/mtd/nand/raw/intel-nand-controller.c
+1
-1
drivers/mtd/nand/raw/lpc32xx_mlc.c
+1
-1
drivers/mtd/nand/raw/lpc32xx_mlc.c
···
891
891
892
892
static struct platform_driver lpc32xx_nand_driver = {
893
893
.probe = lpc32xx_nand_probe,
894
-
.remove_new = lpc32xx_nand_remove,
894
+
.remove = lpc32xx_nand_remove,
895
895
.resume = pm_ptr(lpc32xx_nand_resume),
896
896
.suspend = pm_ptr(lpc32xx_nand_suspend),
897
897
.driver = {
+1
-1
drivers/mtd/nand/raw/lpc32xx_slc.c
+1
-1
drivers/mtd/nand/raw/lpc32xx_slc.c
···
1010
1010
1011
1011
static struct platform_driver lpc32xx_nand_driver = {
1012
1012
.probe = lpc32xx_nand_probe,
1013
-
.remove_new = lpc32xx_nand_remove,
1013
+
.remove = lpc32xx_nand_remove,
1014
1014
.resume = pm_ptr(lpc32xx_nand_resume),
1015
1015
.suspend = pm_ptr(lpc32xx_nand_suspend),
1016
1016
.driver = {
+1
-1
drivers/mtd/nand/raw/marvell_nand.c
+1
-1
drivers/mtd/nand/raw/marvell_nand.c
+1
-1
drivers/mtd/nand/raw/meson_nand.c
+1
-1
drivers/mtd/nand/raw/meson_nand.c
+1
-1
drivers/mtd/nand/raw/mpc5121_nfc.c
+1
-1
drivers/mtd/nand/raw/mpc5121_nfc.c
+1
-1
drivers/mtd/nand/raw/mtk_nand.c
+1
-1
drivers/mtd/nand/raw/mtk_nand.c
+1
-1
drivers/mtd/nand/raw/mxc_nand.c
+1
-1
drivers/mtd/nand/raw/mxc_nand.c
+1
-1
drivers/mtd/nand/raw/mxic_nand.c
+1
-1
drivers/mtd/nand/raw/mxic_nand.c
+1
-1
drivers/mtd/nand/raw/nand_macronix.c
+1
-1
drivers/mtd/nand/raw/nand_macronix.c
···
113
113
rand_otp = of_property_read_bool(dn, "mxic,enable-randomizer-otp");
114
114
115
115
mxic = (struct nand_onfi_vendor_macronix *)p->onfi->vendor;
116
-
/* Subpage write is prohibited in randomizer operatoin */
116
+
/* Subpage write is prohibited in randomizer operation */
117
117
if (rand_otp && chip->options & NAND_NO_SUBPAGE_WRITE &&
118
118
mxic->reliability_func & MACRONIX_RANDOMIZER_BIT) {
119
119
if (p->supports_set_get_features) {
+1
-1
drivers/mtd/nand/raw/ndfc.c
+1
-1
drivers/mtd/nand/raw/ndfc.c
+1
-1
drivers/mtd/nand/raw/omap2.c
+1
-1
drivers/mtd/nand/raw/omap2.c
+1
-1
drivers/mtd/nand/raw/omap_elm.c
+1
-1
drivers/mtd/nand/raw/omap_elm.c
+1
-1
drivers/mtd/nand/raw/orion_nand.c
+1
-1
drivers/mtd/nand/raw/orion_nand.c
+1
-1
drivers/mtd/nand/raw/pasemi_nand.c
+1
-1
drivers/mtd/nand/raw/pasemi_nand.c
+2
-2
drivers/mtd/nand/raw/pl35x-nand-controller.c
+2
-2
drivers/mtd/nand/raw/pl35x-nand-controller.c
···
187
187
.free = pl35x_ecc_ooblayout16_free,
188
188
};
189
189
190
-
/* Generic flash bbt decriptors */
190
+
/* Generic flash bbt descriptors */
191
191
static u8 bbt_pattern[] = { 'B', 'b', 't', '0' };
192
192
static u8 mirror_pattern[] = { '1', 't', 'b', 'B' };
193
193
···
1184
1184
1185
1185
static struct platform_driver pl35x_nandc_driver = {
1186
1186
.probe = pl35x_nand_probe,
1187
-
.remove_new = pl35x_nand_remove,
1187
+
.remove = pl35x_nand_remove,
1188
1188
.driver = {
1189
1189
.name = PL35X_NANDC_DRIVER_NAME,
1190
1190
.of_match_table = pl35x_nand_of_match,
+1
-1
drivers/mtd/nand/raw/plat_nand.c
+1
-1
drivers/mtd/nand/raw/plat_nand.c
+2
-2
drivers/mtd/nand/raw/qcom_nandc.c
+2
-2
drivers/mtd/nand/raw/qcom_nandc.c
···
3535
3535
.name = "qcom-nandc",
3536
3536
.of_match_table = qcom_nandc_of_match,
3537
3537
},
3538
-
.probe = qcom_nandc_probe,
3539
-
.remove_new = qcom_nandc_remove,
3538
+
.probe = qcom_nandc_probe,
3539
+
.remove = qcom_nandc_remove,
3540
3540
};
3541
3541
module_platform_driver(qcom_nandc_driver);
3542
3542
+2
-2
drivers/mtd/nand/raw/r852.c
+2
-2
drivers/mtd/nand/raw/r852.c
···
335
335
else
336
336
dev->ctlreg &= ~R852_CTL_WRITE;
337
337
338
-
/* when write is stareted, enable write access */
338
+
/* when write is started, enable write access */
339
339
if (dat == NAND_CMD_ERASE1)
340
340
dev->ctlreg |= R852_CTL_WRITE;
341
341
···
372
372
373
373
nand_status_op(chip, &status);
374
374
375
-
/* Unfortunelly, no way to send detailed error status... */
375
+
/* Unfortunately, no way to send detailed error status... */
376
376
if (dev->dma_error) {
377
377
status |= NAND_STATUS_FAIL;
378
378
dev->dma_error = 0;
+1
-1
drivers/mtd/nand/raw/renesas-nand-controller.c
+1
-1
drivers/mtd/nand/raw/renesas-nand-controller.c
+1
-1
drivers/mtd/nand/raw/rockchip-nand-controller.c
+1
-1
drivers/mtd/nand/raw/rockchip-nand-controller.c
+1
-1
drivers/mtd/nand/raw/s3c2410.c
+1
-1
drivers/mtd/nand/raw/s3c2410.c
···
1213
1213
1214
1214
static struct platform_driver s3c24xx_nand_driver = {
1215
1215
.probe = s3c24xx_nand_probe,
1216
-
.remove_new = s3c24xx_nand_remove,
1216
+
.remove = s3c24xx_nand_remove,
1217
1217
.suspend = s3c24xx_nand_suspend,
1218
1218
.resume = s3c24xx_nand_resume,
1219
1219
.id_table = s3c24xx_driver_ids,
+1
-1
drivers/mtd/nand/raw/sh_flctl.c
+1
-1
drivers/mtd/nand/raw/sh_flctl.c
+1
-1
drivers/mtd/nand/raw/sharpsl.c
+1
-1
drivers/mtd/nand/raw/sharpsl.c
+2
-2
drivers/mtd/nand/raw/sm_common.c
+2
-2
drivers/mtd/nand/raw/sm_common.c
···
52
52
.free = oob_sm_ooblayout_free,
53
53
};
54
54
55
-
/* NOTE: This layout is not compatabable with SmartMedia, */
56
-
/* because the 256 byte devices have page depenent oob layout */
55
+
/* NOTE: This layout is not compatible with SmartMedia, */
56
+
/* because the 256 byte devices have page dependent oob layout */
57
57
/* However it does preserve the bad block markers */
58
58
/* If you use smftl, it will bypass this and work correctly */
59
59
/* If you not, then you break SmartMedia compliance anyway */
+1
-1
drivers/mtd/nand/raw/socrates_nand.c
+1
-1
drivers/mtd/nand/raw/socrates_nand.c
+1
-1
drivers/mtd/nand/raw/stm32_fmc2_nand.c
+1
-1
drivers/mtd/nand/raw/stm32_fmc2_nand.c
···
2147
2147
2148
2148
static struct platform_driver stm32_fmc2_nfc_driver = {
2149
2149
.probe = stm32_fmc2_nfc_probe,
2150
-
.remove_new = stm32_fmc2_nfc_remove,
2150
+
.remove = stm32_fmc2_nfc_remove,
2151
2151
.driver = {
2152
2152
.name = "stm32_fmc2_nfc",
2153
2153
.of_match_table = stm32_fmc2_nfc_match,
+1
-1
drivers/mtd/nand/raw/sunxi_nand.c
+1
-1
drivers/mtd/nand/raw/sunxi_nand.c
+1
-1
drivers/mtd/nand/raw/technologic-nand-controller.c
+1
-1
drivers/mtd/nand/raw/technologic-nand-controller.c
+1
-1
drivers/mtd/nand/raw/tegra_nand.c
+1
-1
drivers/mtd/nand/raw/tegra_nand.c
+1
-1
drivers/mtd/nand/raw/txx9ndfmc.c
+1
-1
drivers/mtd/nand/raw/txx9ndfmc.c
+1
-1
drivers/mtd/nand/raw/vf610_nfc.c
+1
-1
drivers/mtd/nand/raw/vf610_nfc.c
+1
-1
drivers/mtd/nand/raw/xway_nand.c
+1
-1
drivers/mtd/nand/raw/xway_nand.c
+1
-1
drivers/mtd/nand/spi/core.c
+1
-1
drivers/mtd/nand/spi/core.c
···
337
337
return ret;
338
338
}
339
339
340
-
static struct nand_ecc_engine_ops spinand_ondie_ecc_engine_ops = {
340
+
static const struct nand_ecc_engine_ops spinand_ondie_ecc_engine_ops = {
341
341
.init_ctx = spinand_ondie_ecc_init_ctx,
342
342
.cleanup_ctx = spinand_ondie_ecc_cleanup_ctx,
343
343
.prepare_io_req = spinand_ondie_ecc_prepare_io_req,
+63
-50
drivers/mtd/nand/spi/winbond.c
+63
-50
drivers/mtd/nand/spi/winbond.c
···
161
161
}
162
162
163
163
static const struct spinand_info winbond_spinand_table[] = {
164
-
SPINAND_INFO("W25M02GV",
164
+
/* 512M-bit densities */
165
+
SPINAND_INFO("W25N512GW", /* 1.8V */
166
+
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xba, 0x20),
167
+
NAND_MEMORG(1, 2048, 64, 64, 512, 10, 1, 1, 1),
168
+
NAND_ECCREQ(1, 512),
169
+
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
170
+
&write_cache_variants,
171
+
&update_cache_variants),
172
+
0,
173
+
SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)),
174
+
/* 1G-bit densities */
175
+
SPINAND_INFO("W25N01GV", /* 3.3V */
176
+
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x21),
177
+
NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
178
+
NAND_ECCREQ(1, 512),
179
+
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
180
+
&write_cache_variants,
181
+
&update_cache_variants),
182
+
0,
183
+
SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)),
184
+
SPINAND_INFO("W25N01GW", /* 1.8V */
185
+
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xba, 0x21),
186
+
NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
187
+
NAND_ECCREQ(1, 512),
188
+
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
189
+
&write_cache_variants,
190
+
&update_cache_variants),
191
+
0,
192
+
SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)),
193
+
SPINAND_INFO("W25N01JW", /* high-speed 1.8V */
194
+
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xbc, 0x21),
195
+
NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
196
+
NAND_ECCREQ(1, 512),
197
+
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
198
+
&write_cache_variants,
199
+
&update_cache_variants),
200
+
0,
201
+
SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)),
202
+
SPINAND_INFO("W25N01KV", /* 3.3V */
203
+
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xae, 0x21),
204
+
NAND_MEMORG(1, 2048, 96, 64, 1024, 20, 1, 1, 1),
205
+
NAND_ECCREQ(4, 512),
206
+
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
207
+
&write_cache_variants,
208
+
&update_cache_variants),
209
+
0,
210
+
SPINAND_ECCINFO(&w25n01kv_ooblayout, w25n02kv_ecc_get_status)),
211
+
/* 2G-bit densities */
212
+
SPINAND_INFO("W25M02GV", /* 2x1G-bit 3.3V */
165
213
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xab, 0x21),
166
214
NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 2),
167
215
NAND_ECCREQ(1, 512),
···
219
171
0,
220
172
SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL),
221
173
SPINAND_SELECT_TARGET(w25m02gv_select_target)),
222
-
SPINAND_INFO("W25N01GV",
223
-
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x21),
224
-
NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
174
+
SPINAND_INFO("W25N02JW", /* high-speed 1.8V */
175
+
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xbf, 0x22),
176
+
NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 2, 1),
225
177
NAND_ECCREQ(1, 512),
226
178
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
227
179
&write_cache_variants,
228
180
&update_cache_variants),
229
181
0,
230
182
SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)),
231
-
SPINAND_INFO("W25N01KV",
232
-
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xae, 0x21),
233
-
NAND_MEMORG(1, 2048, 96, 64, 1024, 20, 1, 1, 1),
234
-
NAND_ECCREQ(4, 512),
235
-
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
236
-
&write_cache_variants,
237
-
&update_cache_variants),
238
-
0,
239
-
SPINAND_ECCINFO(&w25n01kv_ooblayout, w25n02kv_ecc_get_status)),
240
-
SPINAND_INFO("W25N02KV",
183
+
SPINAND_INFO("W25N02KV", /* 3.3V */
241
184
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x22),
242
185
NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
243
186
NAND_ECCREQ(8, 512),
···
237
198
&update_cache_variants),
238
199
0,
239
200
SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)),
240
-
SPINAND_INFO("W25N01JW",
241
-
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xbc, 0x21),
242
-
NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
243
-
NAND_ECCREQ(4, 512),
244
-
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
245
-
&write_cache_variants,
246
-
&update_cache_variants),
247
-
0,
248
-
SPINAND_ECCINFO(&w25m02gv_ooblayout, w25n02kv_ecc_get_status)),
249
-
SPINAND_INFO("W25N02JWZEIF",
250
-
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xbf, 0x22),
251
-
NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 2, 1),
252
-
NAND_ECCREQ(4, 512),
253
-
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
254
-
&write_cache_variants,
255
-
&update_cache_variants),
256
-
0,
257
-
SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)),
258
-
SPINAND_INFO("W25N512GW",
259
-
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xba, 0x20),
260
-
NAND_MEMORG(1, 2048, 64, 64, 512, 10, 1, 1, 1),
261
-
NAND_ECCREQ(4, 512),
262
-
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
263
-
&write_cache_variants,
264
-
&update_cache_variants),
265
-
0,
266
-
SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)),
267
-
SPINAND_INFO("W25N02KWZEIR",
201
+
SPINAND_INFO("W25N02KW", /* 1.8V */
268
202
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xba, 0x22),
269
203
NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
270
204
NAND_ECCREQ(8, 512),
···
246
234
&update_cache_variants),
247
235
0,
248
236
SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)),
249
-
SPINAND_INFO("W25N01GWZEIG",
250
-
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xba, 0x21),
251
-
NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
252
-
NAND_ECCREQ(4, 512),
237
+
/* 4G-bit densities */
238
+
SPINAND_INFO("W25N04KV", /* 3.3V */
239
+
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x23),
240
+
NAND_MEMORG(1, 2048, 128, 64, 4096, 40, 2, 1, 1),
241
+
NAND_ECCREQ(8, 512),
253
242
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
254
243
&write_cache_variants,
255
244
&update_cache_variants),
256
245
0,
257
-
SPINAND_ECCINFO(&w25m02gv_ooblayout, w25n02kv_ecc_get_status)),
258
-
SPINAND_INFO("W25N04KV",
259
-
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x23),
260
-
NAND_MEMORG(1, 2048, 128, 64, 4096, 40, 2, 1, 1),
246
+
SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)),
247
+
SPINAND_INFO("W25N04KW", /* 1.8V */
248
+
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xba, 0x23),
249
+
NAND_MEMORG(1, 2048, 128, 64, 4096, 40, 1, 1, 1),
261
250
NAND_ECCREQ(8, 512),
262
251
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
263
252
&write_cache_variants,
+1
-1
drivers/mtd/spi-nor/controllers/hisi-sfc.c
+1
-1
drivers/mtd/spi-nor/controllers/hisi-sfc.c
+1
-1
drivers/mtd/spi-nor/controllers/nxp-spifi.c
+1
-1
drivers/mtd/spi-nor/controllers/nxp-spifi.c
+4
-1
drivers/mtd/spi-nor/core.c
+4
-1
drivers/mtd/spi-nor/core.c
···
89
89
op->addr.buswidth = spi_nor_get_protocol_addr_nbits(proto);
90
90
91
91
if (op->dummy.nbytes)
92
-
op->dummy.buswidth = spi_nor_get_protocol_addr_nbits(proto);
92
+
op->dummy.buswidth = spi_nor_get_protocol_data_nbits(proto);
93
93
94
94
if (op->data.nbytes)
95
95
op->data.buswidth = spi_nor_get_protocol_data_nbits(proto);
···
113
113
op->cmd.opcode = (op->cmd.opcode << 8) | ext;
114
114
op->cmd.nbytes = 2;
115
115
}
116
+
117
+
if (proto == SNOR_PROTO_8_8_8_DTR && nor->flags & SNOR_F_SWAP16)
118
+
op->data.swap16 = true;
116
119
}
117
120
118
121
/**
+1
drivers/mtd/spi-nor/core.h
+1
drivers/mtd/spi-nor/core.h
+98
-1
drivers/mtd/spi-nor/macronix.c
+98
-1
drivers/mtd/spi-nor/macronix.c
···
8
8
9
9
#include "core.h"
10
10
11
+
#define MXIC_NOR_OP_RD_CR2 0x71 /* Read configuration register 2 opcode */
12
+
#define MXIC_NOR_OP_WR_CR2 0x72 /* Write configuration register 2 opcode */
13
+
#define MXIC_NOR_ADDR_CR2_MODE 0x00000000 /* CR2 address for setting spi/sopi/dopi mode */
14
+
#define MXIC_NOR_ADDR_CR2_DC 0x00000300 /* CR2 address for setting dummy cycles */
15
+
#define MXIC_NOR_REG_DOPI_EN 0x2 /* Enable Octal DTR */
16
+
#define MXIC_NOR_REG_SPI_EN 0x0 /* Enable SPI */
17
+
18
+
/* Convert dummy cycles to bit pattern */
19
+
#define MXIC_NOR_REG_DC(p) \
20
+
((20 - (p)) >> 1)
21
+
22
+
#define MXIC_NOR_WR_CR2(addr, ndata, buf) \
23
+
SPI_MEM_OP(SPI_MEM_OP_CMD(MXIC_NOR_OP_WR_CR2, 0), \
24
+
SPI_MEM_OP_ADDR(4, addr, 0), \
25
+
SPI_MEM_OP_NO_DUMMY, \
26
+
SPI_MEM_OP_DATA_OUT(ndata, buf, 0))
27
+
11
28
static int
12
29
mx25l25635_post_bfpt_fixups(struct spi_nor *nor,
13
30
const struct sfdp_parameter_header *bfpt_header,
···
199
182
.name = "mx25l3255e",
200
183
.size = SZ_4M,
201
184
.no_sfdp_flags = SECT_4K,
202
-
}
185
+
},
186
+
/*
187
+
* This spares us of adding new flash entries for flashes that can be
188
+
* initialized solely based on the SFDP data, but still need the
189
+
* manufacturer hooks to set parameters that can't be discovered at SFDP
190
+
* parsing time.
191
+
*/
192
+
{ .id = SNOR_ID(0xc2) }
203
193
};
194
+
195
+
static int macronix_nor_octal_dtr_en(struct spi_nor *nor)
196
+
{
197
+
struct spi_mem_op op;
198
+
u8 *buf = nor->bouncebuf, i;
199
+
int ret;
200
+
201
+
/* Use dummy cycles which is parse by SFDP and convert to bit pattern. */
202
+
buf[0] = MXIC_NOR_REG_DC(nor->params->reads[SNOR_CMD_READ_8_8_8_DTR].num_wait_states);
203
+
op = (struct spi_mem_op)MXIC_NOR_WR_CR2(MXIC_NOR_ADDR_CR2_DC, 1, buf);
204
+
ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
205
+
if (ret)
206
+
return ret;
207
+
208
+
/* Set the octal and DTR enable bits. */
209
+
buf[0] = MXIC_NOR_REG_DOPI_EN;
210
+
op = (struct spi_mem_op)MXIC_NOR_WR_CR2(MXIC_NOR_ADDR_CR2_MODE, 1, buf);
211
+
ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
212
+
if (ret)
213
+
return ret;
214
+
215
+
/* Read flash ID to make sure the switch was successful. */
216
+
ret = spi_nor_read_id(nor, 4, 4, buf, SNOR_PROTO_8_8_8_DTR);
217
+
if (ret) {
218
+
dev_dbg(nor->dev, "error %d reading JEDEC ID after enabling 8D-8D-8D mode\n", ret);
219
+
return ret;
220
+
}
221
+
222
+
/* Macronix SPI-NOR flash 8D-8D-8D read ID would get 6 bytes data A-A-B-B-C-C */
223
+
for (i = 0; i < nor->info->id->len; i++)
224
+
if (buf[i * 2] != buf[(i * 2) + 1] || buf[i * 2] != nor->info->id->bytes[i])
225
+
return -EINVAL;
226
+
227
+
return 0;
228
+
}
229
+
230
+
static int macronix_nor_octal_dtr_dis(struct spi_nor *nor)
231
+
{
232
+
struct spi_mem_op op;
233
+
u8 *buf = nor->bouncebuf;
234
+
int ret;
235
+
236
+
/*
237
+
* The register is 1-byte wide, but 1-byte transactions are not
238
+
* allowed in 8D-8D-8D mode. Since there is no register at the
239
+
* next location, just initialize the value to 0 and let the
240
+
* transaction go on.
241
+
*/
242
+
buf[0] = MXIC_NOR_REG_SPI_EN;
243
+
buf[1] = 0x0;
244
+
op = (struct spi_mem_op)MXIC_NOR_WR_CR2(MXIC_NOR_ADDR_CR2_MODE, 2, buf);
245
+
ret = spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_8_8_8_DTR);
246
+
if (ret)
247
+
return ret;
248
+
249
+
/* Read flash ID to make sure the switch was successful. */
250
+
ret = spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1);
251
+
if (ret) {
252
+
dev_dbg(nor->dev, "error %d reading JEDEC ID after disabling 8D-8D-8D mode\n", ret);
253
+
return ret;
254
+
}
255
+
256
+
if (memcmp(buf, nor->info->id->bytes, nor->info->id->len))
257
+
return -EINVAL;
258
+
259
+
return 0;
260
+
}
261
+
262
+
static int macronix_nor_set_octal_dtr(struct spi_nor *nor, bool enable)
263
+
{
264
+
return enable ? macronix_nor_octal_dtr_en(nor) : macronix_nor_octal_dtr_dis(nor);
265
+
}
204
266
205
267
static void macronix_nor_default_init(struct spi_nor *nor)
206
268
{
···
290
194
{
291
195
if (!nor->params->set_4byte_addr_mode)
292
196
nor->params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode_en4b_ex4b;
197
+
nor->params->set_octal_dtr = macronix_nor_set_octal_dtr;
293
198
294
199
return 0;
295
200
}
+4
drivers/mtd/spi-nor/sfdp.c
+4
drivers/mtd/spi-nor/sfdp.c
+1
drivers/mtd/spi-nor/sfdp.h
+1
drivers/mtd/spi-nor/sfdp.h
···
130
130
#define BFPT_DWORD18_CMD_EXT_INV (0x1UL << 29) /* Invert */
131
131
#define BFPT_DWORD18_CMD_EXT_RES (0x2UL << 29) /* Reserved */
132
132
#define BFPT_DWORD18_CMD_EXT_16B (0x3UL << 29) /* 16-bit opcode */
133
+
#define BFPT_DWORD18_BYTE_ORDER_SWAPPED BIT(31) /* Byte order swapped in 8D-8D-8D mode */
133
134
134
135
struct sfdp_parameter_header {
135
136
u8 id_lsb;
+1
drivers/mtd/spi-nor/spansion.c
+1
drivers/mtd/spi-nor/spansion.c
+1
drivers/mtd/spi-nor/winbond.c
+1
drivers/mtd/spi-nor/winbond.c
+3
drivers/spi/spi-mem.c
+3
drivers/spi/spi-mem.c
+1
-1
drivers/spi/spi-mtk-snfi.c
+1
-1
drivers/spi/spi-mtk-snfi.c
···
776
776
return snf->ecc_stats.failed ? -EBADMSG : snf->ecc_stats.bitflips;
777
777
}
778
778
779
-
static struct nand_ecc_engine_ops mtk_snfi_ecc_engine_ops = {
779
+
static const struct nand_ecc_engine_ops mtk_snfi_ecc_engine_ops = {
780
780
.init_ctx = mtk_snand_ecc_init_ctx,
781
781
.cleanup_ctx = mtk_snand_ecc_cleanup_ctx,
782
782
.prepare_io_req = mtk_snand_ecc_prepare_io_req,
+18
-9
drivers/spi/spi-mxic.c
+18
-9
drivers/spi/spi-mxic.c
···
294
294
mxic->regs + HC_CFG);
295
295
}
296
296
297
-
static u32 mxic_spi_prep_hc_cfg(struct spi_device *spi, u32 flags)
297
+
static u32 mxic_spi_prep_hc_cfg(struct spi_device *spi, u32 flags,
298
+
bool swap16)
298
299
{
299
300
int nio = 1;
300
301
···
305
304
nio = 4;
306
305
else if (spi->mode & (SPI_TX_DUAL | SPI_RX_DUAL))
307
306
nio = 2;
307
+
308
+
if (swap16)
309
+
flags &= ~HC_CFG_DATA_PASS;
310
+
else
311
+
flags |= HC_CFG_DATA_PASS;
308
312
309
313
return flags | HC_CFG_NIO(nio) |
310
314
HC_CFG_TYPE(spi_get_chipselect(spi, 0), HC_CFG_TYPE_SPI_NOR) |
···
403
397
if (WARN_ON(offs + desc->info.offset + len > U32_MAX))
404
398
return -EINVAL;
405
399
406
-
writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0), mxic->regs + HC_CFG);
400
+
writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0, desc->info.op_tmpl.data.swap16),
401
+
mxic->regs + HC_CFG);
407
402
408
403
writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl, len),
409
404
mxic->regs + LRD_CFG);
···
448
441
if (WARN_ON(offs + desc->info.offset + len > U32_MAX))
449
442
return -EINVAL;
450
443
451
-
writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0), mxic->regs + HC_CFG);
444
+
writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0, desc->info.op_tmpl.data.swap16),
445
+
mxic->regs + HC_CFG);
452
446
453
447
writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl, len),
454
448
mxic->regs + LWR_CFG);
···
526
518
if (ret)
527
519
return ret;
528
520
529
-
writel(mxic_spi_prep_hc_cfg(mem->spi, HC_CFG_MAN_CS_EN),
521
+
writel(mxic_spi_prep_hc_cfg(mem->spi, HC_CFG_MAN_CS_EN, op->data.swap16),
530
522
mxic->regs + HC_CFG);
531
523
532
524
writel(HC_EN_BIT, mxic->regs + HC_EN);
···
581
573
static const struct spi_controller_mem_caps mxic_spi_mem_caps = {
582
574
.dtr = true,
583
575
.ecc = true,
576
+
.swap16 = true,
584
577
};
585
578
586
579
static void mxic_spi_set_cs(struct spi_device *spi, bool lvl)
···
649
640
/* ECC wrapper */
650
641
static int mxic_spi_mem_ecc_init_ctx(struct nand_device *nand)
651
642
{
652
-
struct nand_ecc_engine_ops *ops = mxic_ecc_get_pipelined_ops();
643
+
const struct nand_ecc_engine_ops *ops = mxic_ecc_get_pipelined_ops();
653
644
struct mxic_spi *mxic = nand->ecc.engine->priv;
654
645
655
646
mxic->ecc.use_pipelined_conf = true;
···
659
650
660
651
static void mxic_spi_mem_ecc_cleanup_ctx(struct nand_device *nand)
661
652
{
662
-
struct nand_ecc_engine_ops *ops = mxic_ecc_get_pipelined_ops();
653
+
const struct nand_ecc_engine_ops *ops = mxic_ecc_get_pipelined_ops();
663
654
struct mxic_spi *mxic = nand->ecc.engine->priv;
664
655
665
656
mxic->ecc.use_pipelined_conf = false;
···
670
661
static int mxic_spi_mem_ecc_prepare_io_req(struct nand_device *nand,
671
662
struct nand_page_io_req *req)
672
663
{
673
-
struct nand_ecc_engine_ops *ops = mxic_ecc_get_pipelined_ops();
664
+
const struct nand_ecc_engine_ops *ops = mxic_ecc_get_pipelined_ops();
674
665
675
666
return ops->prepare_io_req(nand, req);
676
667
}
···
678
669
static int mxic_spi_mem_ecc_finish_io_req(struct nand_device *nand,
679
670
struct nand_page_io_req *req)
680
671
{
681
-
struct nand_ecc_engine_ops *ops = mxic_ecc_get_pipelined_ops();
672
+
const struct nand_ecc_engine_ops *ops = mxic_ecc_get_pipelined_ops();
682
673
683
674
return ops->finish_io_req(nand, req);
684
675
}
685
676
686
-
static struct nand_ecc_engine_ops mxic_spi_mem_ecc_engine_pipelined_ops = {
677
+
static const struct nand_ecc_engine_ops mxic_spi_mem_ecc_engine_pipelined_ops = {
687
678
.init_ctx = mxic_spi_mem_ecc_init_ctx,
688
679
.cleanup_ctx = mxic_spi_mem_ecc_cleanup_ctx,
689
680
.prepare_io_req = mxic_spi_mem_ecc_prepare_io_req,
+2
-2
include/linux/mtd/nand-ecc-mxic.h
+2
-2
include/linux/mtd/nand-ecc-mxic.h
···
16
16
17
17
#if IS_ENABLED(CONFIG_MTD_NAND_ECC_MXIC) && IS_REACHABLE(CONFIG_MTD_NAND_CORE)
18
18
19
-
struct nand_ecc_engine_ops *mxic_ecc_get_pipelined_ops(void);
19
+
const struct nand_ecc_engine_ops *mxic_ecc_get_pipelined_ops(void);
20
20
struct nand_ecc_engine *mxic_ecc_get_pipelined_engine(struct platform_device *spi_pdev);
21
21
void mxic_ecc_put_pipelined_engine(struct nand_ecc_engine *eng);
22
22
int mxic_ecc_process_data_pipelined(struct nand_ecc_engine *eng,
···
24
24
25
25
#else /* !CONFIG_MTD_NAND_ECC_MXIC */
26
26
27
-
static inline struct nand_ecc_engine_ops *mxic_ecc_get_pipelined_ops(void)
27
+
static inline const struct nand_ecc_engine_ops *mxic_ecc_get_pipelined_ops(void)
28
28
{
29
29
return NULL;
30
30
}
+1
-1
include/linux/mtd/nand.h
+1
-1
include/linux/mtd/nand.h
+7
-1
include/linux/spi/spi-mem.h
+7
-1
include/linux/spi/spi-mem.h
···
90
90
* @data.buswidth: number of IO lanes used to send/receive the data
91
91
* @data.dtr: whether the data should be sent in DTR mode or not
92
92
* @data.ecc: whether error correction is required or not
93
+
* @data.swap16: whether the byte order of 16-bit words is swapped when read
94
+
* or written in Octal DTR mode compared to STR mode.
93
95
* @data.dir: direction of the transfer
94
96
* @data.nbytes: number of data bytes to send/receive. Can be zero if the
95
97
* operation does not involve transferring data
···
126
124
u8 buswidth;
127
125
u8 dtr : 1;
128
126
u8 ecc : 1;
129
-
u8 __pad : 6;
127
+
u8 swap16 : 1;
128
+
u8 __pad : 5;
130
129
enum spi_mem_data_dir dir;
131
130
unsigned int nbytes;
132
131
union {
···
300
297
* struct spi_controller_mem_caps - SPI memory controller capabilities
301
298
* @dtr: Supports DTR operations
302
299
* @ecc: Supports operations with error correction
300
+
* @swap16: Supports swapping bytes on a 16 bit boundary when configured in
301
+
* Octal DTR
303
302
*/
304
303
struct spi_controller_mem_caps {
305
304
bool dtr;
306
305
bool ecc;
306
+
bool swap16;
307
307
};
308
308
309
309
#define spi_mem_controller_is_capable(ctlr, cap) \