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watchdog: it87_wdt: Keep WDTCTRL bit 3 unmodified for IT8784/IT8786

WDTCTRL bit 3 sets the mode choice for the clock input of IT8784/IT8786.
Some motherboards require this bit to be set to 1 (= PCICLK mode),
otherwise the watchdog functionality gets broken. The BIOS of those
motherboards sets WDTCTRL bit 3 already to 1.

Instead of setting all bits of WDTCTRL to 0 by writing 0x00 to it, keep
bit 3 of it unchanged for IT8784/IT8786 chips. In this way, bit 3 keeps
the status as set by the BIOS of the motherboard.

Watchdog tests have been successful with this patch with the following
systems:
IT8784: Thomas-Krenn LES plus v2 (YANLING YL-KBRL2 V2)
IT8786: Thomas-Krenn LES plus v3 (YANLING YL-CLU L2)
IT8786: Thomas-Krenn LES network 6L v2 (YANLING YL-CLU6L)

Link: https://lore.kernel.org/all/140b264d-341f-465b-8715-dacfe84b3f71@roeck-us.net/

Signed-off-by: Werner Fischer <devlists@wefi.net>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20231213094525.11849-4-devlists@wefi.net
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>

authored by

Werner Fischer and committed by
Wim Van Sebroeck
d1297184 ab6dea00

+13 -1
+13 -1
drivers/watchdog/it87_wdt.c
··· 258 258 static int __init it87_wdt_init(void) 259 259 { 260 260 u8 chip_rev; 261 + u8 ctrl; 261 262 int rc; 262 263 263 264 rc = superio_enter(); ··· 317 316 318 317 superio_select(GPIO); 319 318 superio_outb(WDT_TOV1, WDTCFG); 320 - superio_outb(0x00, WDTCTRL); 319 + 320 + switch (chip_type) { 321 + case IT8784_ID: 322 + case IT8786_ID: 323 + ctrl = superio_inb(WDTCTRL); 324 + ctrl &= 0x08; 325 + superio_outb(ctrl, WDTCTRL); 326 + break; 327 + default: 328 + superio_outb(0x00, WDTCTRL); 329 + } 330 + 321 331 superio_exit(); 322 332 323 333 if (timeout < 1 || timeout > max_units * 60) {