Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
soc: qcom: geni-se: Add support to load QUP SE Firmware via Linux subsystem
In Qualcomm SoCs, firmware loading for Serial Engines (SE) within the QUP
hardware has traditionally been managed by TrustZone (TZ). This restriction
poses a significant challenge for developers, as it limits their ability to
enable various protocols on any of the SEs from the Linux side, reducing
flexibility.
Load the firmware to QUP SE based on the 'firmware-name' property specified
in devicetree at bootup time.
Co-developed-by: Mukesh Kumar Savaliya <mukesh.savaliya@oss.qualcomm.com>
Signed-off-by: Mukesh Kumar Savaliya <mukesh.savaliya@oss.qualcomm.com>
Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250911043256.3523057-4-viken.dadhaniya@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
authored by
Viken Dadhaniya
and committed by
Bjorn Andersson
d4bf0659
b44a593f
+475
-3
+471
-3
drivers/soc/qcom/qcom-geni-se.c
+471
-3
drivers/soc/qcom/qcom-geni-se.c
···
8
8
#define __DISABLE_TRACE_MMIO__
9
9
10
10
#include <linux/acpi.h>
11
+
#include <linux/bitfield.h>
11
12
#include <linux/clk.h>
13
+
#include <linux/firmware.h>
12
14
#include <linux/slab.h>
13
15
#include <linux/dma-mapping.h>
14
16
#include <linux/io.h>
···
115
113
static const char * const icc_path_names[] = {"qup-core", "qup-config",
116
114
"qup-memory"};
117
115
116
+
static const char * const protocol_name[] = { "None", "SPI", "UART", "I2C", "I3C", "SPI SLAVE" };
117
+
118
+
/**
119
+
* struct se_fw_hdr - Serial Engine firmware configuration header
120
+
*
121
+
* This structure defines the SE firmware header, which together with the
122
+
* firmware payload is stored in individual ELF segments.
123
+
*
124
+
* @magic: Set to 'SEFW'.
125
+
* @version: Structure version number.
126
+
* @core_version: QUPV3 hardware version.
127
+
* @serial_protocol: Encoded in GENI_FW_REVISION.
128
+
* @fw_version: Firmware version, from GENI_FW_REVISION.
129
+
* @cfg_version: Configuration version, from GENI_INIT_CFG_REVISION.
130
+
* @fw_size_in_items: Number of 32-bit words in GENI_FW_RAM.
131
+
* @fw_offset: Byte offset to GENI_FW_RAM array.
132
+
* @cfg_size_in_items: Number of GENI_FW_CFG index/value pairs.
133
+
* @cfg_idx_offset: Byte offset to GENI_FW_CFG index array.
134
+
* @cfg_val_offset: Byte offset to GENI_FW_CFG values array.
135
+
*/
136
+
struct se_fw_hdr {
137
+
__le32 magic;
138
+
__le32 version;
139
+
__le32 core_version;
140
+
__le16 serial_protocol;
141
+
__le16 fw_version;
142
+
__le16 cfg_version;
143
+
__le16 fw_size_in_items;
144
+
__le16 fw_offset;
145
+
__le16 cfg_size_in_items;
146
+
__le16 cfg_idx_offset;
147
+
__le16 cfg_val_offset;
148
+
};
149
+
150
+
/*Magic numbers*/
151
+
#define SE_MAGIC_NUM 0x57464553
152
+
153
+
#define MAX_GENI_CFG_RAMn_CNT 455
154
+
155
+
#define MI_PBT_NON_PAGED_SEGMENT 0x0
156
+
#define MI_PBT_HASH_SEGMENT 0x2
157
+
#define MI_PBT_NOTUSED_SEGMENT 0x3
158
+
#define MI_PBT_SHARED_SEGMENT 0x4
159
+
160
+
#define MI_PBT_FLAG_PAGE_MODE BIT(20)
161
+
#define MI_PBT_FLAG_SEGMENT_TYPE GENMASK(26, 24)
162
+
#define MI_PBT_FLAG_ACCESS_TYPE GENMASK(23, 21)
163
+
164
+
#define MI_PBT_PAGE_MODE_VALUE(x) FIELD_GET(MI_PBT_FLAG_PAGE_MODE, x)
165
+
166
+
#define MI_PBT_SEGMENT_TYPE_VALUE(x) FIELD_GET(MI_PBT_FLAG_SEGMENT_TYPE, x)
167
+
168
+
#define MI_PBT_ACCESS_TYPE_VALUE(x) FIELD_GET(MI_PBT_FLAG_ACCESS_TYPE, x)
169
+
170
+
#define M_COMMON_GENI_M_IRQ_EN (GENMASK(6, 1) | \
171
+
M_IO_DATA_DEASSERT_EN | \
172
+
M_IO_DATA_ASSERT_EN | M_RX_FIFO_RD_ERR_EN | \
173
+
M_RX_FIFO_WR_ERR_EN | M_TX_FIFO_RD_ERR_EN | \
174
+
M_TX_FIFO_WR_ERR_EN)
175
+
118
176
/* Common QUPV3 registers */
119
177
#define QUPV3_HW_VER_REG 0x4
178
+
#define QUPV3_SE_AHB_M_CFG 0x118
179
+
#define QUPV3_COMMON_CFG 0x120
180
+
#define QUPV3_COMMON_CGC_CTRL 0x21c
181
+
182
+
/* QUPV3_COMMON_CFG fields */
183
+
#define FAST_SWITCH_TO_HIGH_DISABLE BIT(0)
184
+
185
+
/* QUPV3_SE_AHB_M_CFG fields */
186
+
#define AHB_M_CLK_CGC_ON BIT(0)
187
+
188
+
/* QUPV3_COMMON_CGC_CTRL fields */
189
+
#define COMMON_CSR_SLV_CLK_CGC_ON BIT(0)
120
190
121
191
/* Common SE registers */
122
192
#define SE_GENI_INIT_CFG_REVISION 0x0
···
196
122
#define SE_GENI_CGC_CTRL 0x28
197
123
#define SE_GENI_CLK_CTRL_RO 0x60
198
124
#define SE_GENI_FW_S_REVISION_RO 0x6c
125
+
#define SE_GENI_CFG_REG0 0x100
199
126
#define SE_GENI_BYTE_GRAN 0x254
200
127
#define SE_GENI_TX_PACKING_CFG0 0x260
201
128
#define SE_GENI_TX_PACKING_CFG1 0x264
202
129
#define SE_GENI_RX_PACKING_CFG0 0x284
203
130
#define SE_GENI_RX_PACKING_CFG1 0x288
131
+
#define SE_GENI_S_IRQ_ENABLE 0x644
204
132
#define SE_DMA_TX_PTR_L 0xc30
205
133
#define SE_DMA_TX_PTR_H 0xc34
206
134
#define SE_DMA_TX_ATTR 0xc38
···
224
148
#define SE_GSI_EVENT_EN 0xe18
225
149
#define SE_IRQ_EN 0xe1c
226
150
#define SE_DMA_GENERAL_CFG 0xe30
151
+
#define SE_GENI_FW_REVISION 0x1000
152
+
#define SE_GENI_S_FW_REVISION 0x1004
153
+
#define SE_GENI_CFG_RAMN 0x1010
154
+
#define SE_GENI_CLK_CTRL 0x2000
155
+
#define SE_DMA_IF_EN 0x2004
156
+
#define SE_FIFO_IF_DISABLE 0x2008
157
+
158
+
/* GENI_FW_REVISION_RO fields */
159
+
#define FW_REV_VERSION_MSK GENMASK(7, 0)
227
160
228
161
/* GENI_OUTPUT_CTRL fields */
229
162
#define DEFAULT_IO_OUTPUT_CTRL_MSK GENMASK(6, 0)
···
270
185
#define RX_DMA_ZERO_PADDING_EN BIT(5)
271
186
#define RX_DMA_IRQ_DELAY_MSK GENMASK(8, 6)
272
187
#define RX_DMA_IRQ_DELAY_SHFT 6
188
+
189
+
/* GENI_CLK_CTRL fields */
190
+
#define SER_CLK_SEL BIT(0)
191
+
192
+
/* GENI_DMA_IF_EN fields */
193
+
#define DMA_IF_EN BIT(0)
194
+
195
+
#define geni_setbits32(_addr, _v) writel(readl(_addr) | (_v), _addr)
196
+
#define geni_clrbits32(_addr, _v) writel(readl(_addr) & ~(_v), _addr)
273
197
274
198
/**
275
199
* geni_se_get_qup_hw_version() - Read the QUP wrapper Hardware version
···
752
658
}
753
659
EXPORT_SYMBOL_GPL(geni_se_clk_freq_match);
754
660
755
-
#define GENI_SE_DMA_DONE_EN BIT(0)
756
-
#define GENI_SE_DMA_EOT_EN BIT(1)
757
-
#define GENI_SE_DMA_AHB_ERR_EN BIT(2)
661
+
#define GENI_SE_DMA_DONE_EN BIT(0)
662
+
#define GENI_SE_DMA_EOT_EN BIT(1)
663
+
#define GENI_SE_DMA_AHB_ERR_EN BIT(2)
664
+
#define GENI_SE_DMA_RESET_DONE_EN BIT(3)
665
+
#define GENI_SE_DMA_FLUSH_DONE BIT(4)
666
+
758
667
#define GENI_SE_DMA_EOT_BUF BIT(0)
759
668
760
669
/**
···
987
890
return 0;
988
891
}
989
892
EXPORT_SYMBOL_GPL(geni_icc_disable);
893
+
894
+
/**
895
+
* geni_find_protocol_fw() - Locate and validate SE firmware for a protocol.
896
+
* @dev: Pointer to the device structure.
897
+
* @fw: Pointer to the firmware image.
898
+
* @protocol: Expected serial engine protocol type.
899
+
*
900
+
* Identifies the appropriate firmware image or configuration required for a
901
+
* specific communication protocol instance running on a Qualcomm GENI
902
+
* controller.
903
+
*
904
+
* Return: pointer to a valid 'struct se_fw_hdr' if found, or NULL otherwise.
905
+
*/
906
+
static struct se_fw_hdr *geni_find_protocol_fw(struct device *dev, const struct firmware *fw,
907
+
enum geni_se_protocol_type protocol)
908
+
{
909
+
const struct elf32_hdr *ehdr;
910
+
const struct elf32_phdr *phdrs;
911
+
const struct elf32_phdr *phdr;
912
+
struct se_fw_hdr *sefw;
913
+
u32 fw_end, cfg_idx_end, cfg_val_end;
914
+
u16 fw_size;
915
+
int i;
916
+
917
+
if (!fw || fw->size < sizeof(struct elf32_hdr))
918
+
return NULL;
919
+
920
+
ehdr = (const struct elf32_hdr *)fw->data;
921
+
phdrs = (const struct elf32_phdr *)(fw->data + ehdr->e_phoff);
922
+
923
+
/*
924
+
* The firmware is expected to have at least two program headers (segments).
925
+
* One for metadata and the other for the actual protocol-specific firmware.
926
+
*/
927
+
if (ehdr->e_phnum < 2) {
928
+
dev_err(dev, "Invalid firmware: less than 2 program headers\n");
929
+
return NULL;
930
+
}
931
+
932
+
for (i = 0; i < ehdr->e_phnum; i++) {
933
+
phdr = &phdrs[i];
934
+
935
+
if (fw->size < phdr->p_offset + phdr->p_filesz) {
936
+
dev_err(dev, "Firmware size (%zu) < expected offset (%u) + size (%u)\n",
937
+
fw->size, phdr->p_offset, phdr->p_filesz);
938
+
return NULL;
939
+
}
940
+
941
+
if (phdr->p_type != PT_LOAD || !phdr->p_memsz)
942
+
continue;
943
+
944
+
if (MI_PBT_PAGE_MODE_VALUE(phdr->p_flags) != MI_PBT_NON_PAGED_SEGMENT ||
945
+
MI_PBT_SEGMENT_TYPE_VALUE(phdr->p_flags) == MI_PBT_HASH_SEGMENT ||
946
+
MI_PBT_ACCESS_TYPE_VALUE(phdr->p_flags) == MI_PBT_NOTUSED_SEGMENT ||
947
+
MI_PBT_ACCESS_TYPE_VALUE(phdr->p_flags) == MI_PBT_SHARED_SEGMENT)
948
+
continue;
949
+
950
+
if (phdr->p_filesz < sizeof(struct se_fw_hdr))
951
+
continue;
952
+
953
+
sefw = (struct se_fw_hdr *)(fw->data + phdr->p_offset);
954
+
fw_size = le16_to_cpu(sefw->fw_size_in_items);
955
+
fw_end = le16_to_cpu(sefw->fw_offset) + fw_size * sizeof(u32);
956
+
cfg_idx_end = le16_to_cpu(sefw->cfg_idx_offset) +
957
+
le16_to_cpu(sefw->cfg_size_in_items) * sizeof(u8);
958
+
cfg_val_end = le16_to_cpu(sefw->cfg_val_offset) +
959
+
le16_to_cpu(sefw->cfg_size_in_items) * sizeof(u32);
960
+
961
+
if (le32_to_cpu(sefw->magic) != SE_MAGIC_NUM || le32_to_cpu(sefw->version) != 1)
962
+
continue;
963
+
964
+
if (le32_to_cpu(sefw->serial_protocol) != protocol)
965
+
continue;
966
+
967
+
if (fw_size % 2 != 0) {
968
+
fw_size++;
969
+
sefw->fw_size_in_items = cpu_to_le16(fw_size);
970
+
}
971
+
972
+
if (fw_size >= MAX_GENI_CFG_RAMn_CNT) {
973
+
dev_err(dev,
974
+
"Firmware size (%u) exceeds max allowed RAMn count (%u)\n",
975
+
fw_size, MAX_GENI_CFG_RAMn_CNT);
976
+
continue;
977
+
}
978
+
979
+
if (fw_end > phdr->p_filesz || cfg_idx_end > phdr->p_filesz ||
980
+
cfg_val_end > phdr->p_filesz) {
981
+
dev_err(dev, "Truncated or corrupt SE FW segment found at index %d\n", i);
982
+
continue;
983
+
}
984
+
985
+
return sefw;
986
+
}
987
+
988
+
dev_err(dev, "Failed to get %s protocol firmware\n", protocol_name[protocol]);
989
+
return NULL;
990
+
}
991
+
992
+
/**
993
+
* geni_configure_xfer_mode() - Set the transfer mode.
994
+
* @se: Pointer to the concerned serial engine.
995
+
* @mode: SE data transfer mode.
996
+
*
997
+
* Set the transfer mode to either FIFO or DMA according to the mode specified
998
+
* by the protocol driver.
999
+
*
1000
+
* Return: 0 if successful, otherwise return an error value.
1001
+
*/
1002
+
static int geni_configure_xfer_mode(struct geni_se *se, enum geni_se_xfer_mode mode)
1003
+
{
1004
+
/* Configure SE FIFO, DMA or GSI mode. */
1005
+
switch (mode) {
1006
+
case GENI_GPI_DMA:
1007
+
geni_setbits32(se->base + SE_GENI_DMA_MODE_EN, GENI_DMA_MODE_EN);
1008
+
writel(0x0, se->base + SE_IRQ_EN);
1009
+
writel(DMA_RX_EVENT_EN | DMA_TX_EVENT_EN | GENI_M_EVENT_EN | GENI_S_EVENT_EN,
1010
+
se->base + SE_GSI_EVENT_EN);
1011
+
break;
1012
+
1013
+
case GENI_SE_FIFO:
1014
+
geni_clrbits32(se->base + SE_GENI_DMA_MODE_EN, GENI_DMA_MODE_EN);
1015
+
writel(DMA_RX_IRQ_EN | DMA_TX_IRQ_EN | GENI_M_IRQ_EN | GENI_S_IRQ_EN,
1016
+
se->base + SE_IRQ_EN);
1017
+
writel(0x0, se->base + SE_GSI_EVENT_EN);
1018
+
break;
1019
+
1020
+
case GENI_SE_DMA:
1021
+
geni_setbits32(se->base + SE_GENI_DMA_MODE_EN, GENI_DMA_MODE_EN);
1022
+
writel(DMA_RX_IRQ_EN | DMA_TX_IRQ_EN | GENI_M_IRQ_EN | GENI_S_IRQ_EN,
1023
+
se->base + SE_IRQ_EN);
1024
+
writel(0x0, se->base + SE_GSI_EVENT_EN);
1025
+
break;
1026
+
1027
+
default:
1028
+
dev_err(se->dev, "Invalid geni-se transfer mode: %d\n", mode);
1029
+
return -EINVAL;
1030
+
}
1031
+
return 0;
1032
+
}
1033
+
1034
+
/**
1035
+
* geni_enable_interrupts() - Enable interrupts.
1036
+
* @se: Pointer to the concerned serial engine.
1037
+
*
1038
+
* Enable the required interrupts during the firmware load process.
1039
+
*/
1040
+
static void geni_enable_interrupts(struct geni_se *se)
1041
+
{
1042
+
u32 val;
1043
+
1044
+
/* Enable required interrupts. */
1045
+
writel(M_COMMON_GENI_M_IRQ_EN, se->base + SE_GENI_M_IRQ_EN);
1046
+
1047
+
val = S_CMD_OVERRUN_EN | S_ILLEGAL_CMD_EN | S_CMD_CANCEL_EN | S_CMD_ABORT_EN |
1048
+
S_GP_IRQ_0_EN | S_GP_IRQ_1_EN | S_GP_IRQ_2_EN | S_GP_IRQ_3_EN |
1049
+
S_RX_FIFO_WR_ERR_EN | S_RX_FIFO_RD_ERR_EN;
1050
+
writel(val, se->base + SE_GENI_S_IRQ_ENABLE);
1051
+
1052
+
/* DMA mode configuration. */
1053
+
val = GENI_SE_DMA_RESET_DONE_EN | GENI_SE_DMA_AHB_ERR_EN | GENI_SE_DMA_DONE_EN;
1054
+
writel(val, se->base + SE_DMA_TX_IRQ_EN_SET);
1055
+
val = GENI_SE_DMA_FLUSH_DONE | GENI_SE_DMA_RESET_DONE_EN | GENI_SE_DMA_AHB_ERR_EN |
1056
+
GENI_SE_DMA_DONE_EN;
1057
+
writel(val, se->base + SE_DMA_RX_IRQ_EN_SET);
1058
+
}
1059
+
1060
+
/**
1061
+
* geni_write_fw_revision() - Write the firmware revision.
1062
+
* @se: Pointer to the concerned serial engine.
1063
+
* @serial_protocol: serial protocol type.
1064
+
* @fw_version: QUP firmware version.
1065
+
*
1066
+
* Write the firmware revision and protocol into the respective register.
1067
+
*/
1068
+
static void geni_write_fw_revision(struct geni_se *se, u16 serial_protocol, u16 fw_version)
1069
+
{
1070
+
u32 reg;
1071
+
1072
+
reg = FIELD_PREP(FW_REV_PROTOCOL_MSK, serial_protocol);
1073
+
reg |= FIELD_PREP(FW_REV_VERSION_MSK, fw_version);
1074
+
1075
+
writel(reg, se->base + SE_GENI_FW_REVISION);
1076
+
writel(reg, se->base + SE_GENI_S_FW_REVISION);
1077
+
}
1078
+
1079
+
/**
1080
+
* geni_load_se_fw() - Load Serial Engine specific firmware.
1081
+
* @se: Pointer to the concerned serial engine.
1082
+
* @fw: Pointer to the firmware structure.
1083
+
* @mode: SE data transfer mode.
1084
+
* @protocol: Protocol type to be used with the SE (e.g., UART, SPI, I2C).
1085
+
*
1086
+
* Load the protocol firmware into the IRAM of the Serial Engine.
1087
+
*
1088
+
* Return: 0 if successful, otherwise return an error value.
1089
+
*/
1090
+
static int geni_load_se_fw(struct geni_se *se, const struct firmware *fw,
1091
+
enum geni_se_xfer_mode mode, enum geni_se_protocol_type protocol)
1092
+
{
1093
+
const u32 *fw_data, *cfg_val_arr;
1094
+
const u8 *cfg_idx_arr;
1095
+
u32 i, reg_value;
1096
+
int ret;
1097
+
struct se_fw_hdr *hdr;
1098
+
1099
+
hdr = geni_find_protocol_fw(se->dev, fw, protocol);
1100
+
if (!hdr)
1101
+
return -EINVAL;
1102
+
1103
+
fw_data = (const u32 *)((u8 *)hdr + le16_to_cpu(hdr->fw_offset));
1104
+
cfg_idx_arr = (const u8 *)hdr + le16_to_cpu(hdr->cfg_idx_offset);
1105
+
cfg_val_arr = (const u32 *)((u8 *)hdr + le16_to_cpu(hdr->cfg_val_offset));
1106
+
1107
+
ret = geni_icc_set_bw(se);
1108
+
if (ret)
1109
+
return ret;
1110
+
1111
+
ret = geni_icc_enable(se);
1112
+
if (ret)
1113
+
return ret;
1114
+
1115
+
ret = geni_se_resources_on(se);
1116
+
if (ret)
1117
+
goto out_icc_disable;
1118
+
1119
+
/*
1120
+
* Disable high-priority interrupts until all currently executing
1121
+
* low-priority interrupts have been fully handled.
1122
+
*/
1123
+
geni_setbits32(se->wrapper->base + QUPV3_COMMON_CFG, FAST_SWITCH_TO_HIGH_DISABLE);
1124
+
1125
+
/* Set AHB_M_CLK_CGC_ON to indicate hardware controls se-wrapper cgc clock. */
1126
+
geni_setbits32(se->wrapper->base + QUPV3_SE_AHB_M_CFG, AHB_M_CLK_CGC_ON);
1127
+
1128
+
/* Let hardware to control common cgc. */
1129
+
geni_setbits32(se->wrapper->base + QUPV3_COMMON_CGC_CTRL, COMMON_CSR_SLV_CLK_CGC_ON);
1130
+
1131
+
/*
1132
+
* Setting individual bits in GENI_OUTPUT_CTRL activates corresponding output lines,
1133
+
* allowing the hardware to drive data as configured.
1134
+
*/
1135
+
writel(0x0, se->base + GENI_OUTPUT_CTRL);
1136
+
1137
+
/* Set SCLK and HCLK to program RAM */
1138
+
geni_setbits32(se->base + SE_GENI_CGC_CTRL, PROG_RAM_SCLK_OFF | PROG_RAM_HCLK_OFF);
1139
+
writel(0x0, se->base + SE_GENI_CLK_CTRL);
1140
+
geni_clrbits32(se->base + SE_GENI_CGC_CTRL, PROG_RAM_SCLK_OFF | PROG_RAM_HCLK_OFF);
1141
+
1142
+
/* Enable required clocks for DMA CSR, TX and RX. */
1143
+
reg_value = AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CLK_CGC_ON |
1144
+
DMA_TX_CLK_CGC_ON | DMA_RX_CLK_CGC_ON;
1145
+
geni_setbits32(se->base + SE_DMA_GENERAL_CFG, reg_value);
1146
+
1147
+
/* Let hardware control CGC by default. */
1148
+
writel(DEFAULT_CGC_EN, se->base + SE_GENI_CGC_CTRL);
1149
+
1150
+
/* Set version of the configuration register part of firmware. */
1151
+
writel(le16_to_cpu(hdr->cfg_version), se->base + SE_GENI_INIT_CFG_REVISION);
1152
+
writel(le16_to_cpu(hdr->cfg_version), se->base + SE_GENI_S_INIT_CFG_REVISION);
1153
+
1154
+
/* Configure GENI primitive table. */
1155
+
for (i = 0; i < le16_to_cpu(hdr->cfg_size_in_items); i++)
1156
+
writel(cfg_val_arr[i],
1157
+
se->base + SE_GENI_CFG_REG0 + (cfg_idx_arr[i] * sizeof(u32)));
1158
+
1159
+
/* Configure condition for assertion of RX_RFR_WATERMARK condition. */
1160
+
reg_value = geni_se_get_rx_fifo_depth(se);
1161
+
writel(reg_value - 2, se->base + SE_GENI_RX_RFR_WATERMARK_REG);
1162
+
1163
+
/* Let hardware control CGC */
1164
+
geni_setbits32(se->base + GENI_OUTPUT_CTRL, DEFAULT_IO_OUTPUT_CTRL_MSK);
1165
+
1166
+
ret = geni_configure_xfer_mode(se, mode);
1167
+
if (ret)
1168
+
goto out_resources_off;
1169
+
1170
+
geni_enable_interrupts(se);
1171
+
1172
+
geni_write_fw_revision(se, le16_to_cpu(hdr->serial_protocol), le16_to_cpu(hdr->fw_version));
1173
+
1174
+
/* Program RAM address space. */
1175
+
memcpy_toio(se->base + SE_GENI_CFG_RAMN, fw_data,
1176
+
le16_to_cpu(hdr->fw_size_in_items) * sizeof(u32));
1177
+
1178
+
/* Put default values on GENI's output pads. */
1179
+
writel_relaxed(0x1, se->base + GENI_FORCE_DEFAULT_REG);
1180
+
1181
+
/* Toggle SCLK/HCLK from high to low to finalize RAM programming and apply config. */
1182
+
geni_setbits32(se->base + SE_GENI_CGC_CTRL, PROG_RAM_SCLK_OFF | PROG_RAM_HCLK_OFF);
1183
+
geni_setbits32(se->base + SE_GENI_CLK_CTRL, SER_CLK_SEL);
1184
+
geni_clrbits32(se->base + SE_GENI_CGC_CTRL, PROG_RAM_SCLK_OFF | PROG_RAM_HCLK_OFF);
1185
+
1186
+
/* Serial engine DMA interface is enabled. */
1187
+
geni_setbits32(se->base + SE_DMA_IF_EN, DMA_IF_EN);
1188
+
1189
+
/* Enable or disable FIFO interface of the serial engine. */
1190
+
if (mode == GENI_SE_FIFO)
1191
+
geni_clrbits32(se->base + SE_FIFO_IF_DISABLE, FIFO_IF_DISABLE);
1192
+
else
1193
+
geni_setbits32(se->base + SE_FIFO_IF_DISABLE, FIFO_IF_DISABLE);
1194
+
1195
+
out_resources_off:
1196
+
geni_se_resources_off(se);
1197
+
1198
+
out_icc_disable:
1199
+
geni_icc_disable(se);
1200
+
return ret;
1201
+
}
1202
+
1203
+
/**
1204
+
* geni_load_se_firmware() - Load firmware for SE based on protocol
1205
+
* @se: Pointer to the concerned serial engine.
1206
+
* @protocol: Protocol type to be used with the SE (e.g., UART, SPI, I2C).
1207
+
*
1208
+
* Retrieves the firmware name from device properties and sets the transfer mode
1209
+
* (FIFO or GSI DMA) based on device tree configuration. Enforces FIFO mode for
1210
+
* UART protocol due to lack of GSI DMA support. Requests the firmware and loads
1211
+
* it into the SE.
1212
+
*
1213
+
* Return: 0 on success, negative error code on failure.
1214
+
*/
1215
+
int geni_load_se_firmware(struct geni_se *se, enum geni_se_protocol_type protocol)
1216
+
{
1217
+
const char *fw_name;
1218
+
const struct firmware *fw;
1219
+
enum geni_se_xfer_mode mode = GENI_SE_FIFO;
1220
+
int ret;
1221
+
1222
+
if (protocol >= ARRAY_SIZE(protocol_name)) {
1223
+
dev_err(se->dev, "Invalid geni-se protocol: %d", protocol);
1224
+
return -EINVAL;
1225
+
}
1226
+
1227
+
ret = device_property_read_string(se->wrapper->dev, "firmware-name", &fw_name);
1228
+
if (ret) {
1229
+
dev_err(se->dev, "Failed to read firmware-name property: %d\n", ret);
1230
+
return -EINVAL;
1231
+
}
1232
+
1233
+
if (of_property_read_bool(se->dev->of_node, "qcom,enable-gsi-dma"))
1234
+
mode = GENI_GPI_DMA;
1235
+
1236
+
/* GSI mode is not supported by the UART driver; therefore, setting FIFO mode */
1237
+
if (protocol == GENI_SE_UART)
1238
+
mode = GENI_SE_FIFO;
1239
+
1240
+
ret = request_firmware(&fw, fw_name, se->dev);
1241
+
if (ret) {
1242
+
if (ret == -ENOENT)
1243
+
return -EPROBE_DEFER;
1244
+
1245
+
dev_err(se->dev, "Failed to request firmware '%s' for protocol %d: ret: %d\n",
1246
+
fw_name, protocol, ret);
1247
+
return ret;
1248
+
}
1249
+
1250
+
ret = geni_load_se_fw(se, fw, mode, protocol);
1251
+
release_firmware(fw);
1252
+
1253
+
if (ret) {
1254
+
dev_err(se->dev, "Failed to load SE firmware for protocol %d: ret: %d\n",
1255
+
protocol, ret);
1256
+
return ret;
1257
+
}
1258
+
1259
+
dev_dbg(se->dev, "Firmware load for %s protocol is successful for xfer mode: %d\n",
1260
+
protocol_name[protocol], mode);
1261
+
return 0;
1262
+
}
1263
+
EXPORT_SYMBOL_GPL(geni_load_se_firmware);
990
1264
991
1265
static int geni_se_probe(struct platform_device *pdev)
992
1266
{
+4
include/linux/soc/qcom/geni-se.h
+4
include/linux/soc/qcom/geni-se.h
···
1
1
/* SPDX-License-Identifier: GPL-2.0 */
2
2
/*
3
3
* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
4
+
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4
5
*/
5
6
6
7
#ifndef _LINUX_QCOM_GENI_SE
···
37
36
GENI_SE_I2C,
38
37
GENI_SE_I3C,
39
38
GENI_SE_SPI_SLAVE,
39
+
GENI_SE_INVALID_PROTO = 255,
40
40
};
41
41
42
42
struct geni_wrapper;
···
533
531
int geni_icc_enable(struct geni_se *se);
534
532
535
533
int geni_icc_disable(struct geni_se *se);
534
+
535
+
int geni_load_se_firmware(struct geni_se *se, enum geni_se_protocol_type protocol);
536
536
#endif
537
537
#endif