Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
- some small fixes for msm and exynos
- a regression revert affecting nouveau users with old userspace
- intel pageflip deadlock and gpu hang fixes, hsw modesetting hangs
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (22 commits)
Revert "drm: mark context support as a legacy subsystem"
drm/i915: Don't enable the cursor on a disable pipe
drm/i915: do not update cursor in crtc mode set
drm/exynos: fix return value check in lowlevel_buffer_allocate()
drm/exynos: Fix address space warnings in exynos_drm_fbdev.c
drm/exynos: Fix address space warning in exynos_drm_buf.c
drm/exynos: Remove redundant OF dependency
drm/msm: drop unnecessary set_need_resched()
drm/i915: kill set_need_resched
drm/msm: fix potential NULL pointer dereference
drm/i915/dvo: set crtc timings again for panel fixed modes
drm/i915/sdvo: Robustify the dtd<->drm_mode conversions
drm/msm: workaround for missing irq
drm/msm: return -EBUSY if bo still active
drm/msm: fix return value check in ERR_PTR()
drm/msm: fix cmdstream size check
drm/msm: hangcheck harder
drm/msm: handle read vs write fences
drm/i915/sdvo: Fully translate sync flags in the dtd->mode conversion
drm/i915: Use proper print format for debug prints
...
+274
-195
+8
-65
drivers/gpu/drm/drm_context.c
+8
-65
drivers/gpu/drm/drm_context.c
···
42
42
43
43
#include <drm/drmP.h>
44
44
45
+
/******************************************************************/
46
+
/** \name Context bitmap support */
47
+
/*@{*/
48
+
45
49
/**
46
50
* Free a handle from the context bitmap.
47
51
*
···
56
52
* in drm_device::ctx_idr, while holding the drm_device::struct_mutex
57
53
* lock.
58
54
*/
59
-
static void drm_ctxbitmap_free(struct drm_device * dev, int ctx_handle)
55
+
void drm_ctxbitmap_free(struct drm_device * dev, int ctx_handle)
60
56
{
61
-
if (drm_core_check_feature(dev, DRIVER_MODESET))
62
-
return;
63
-
64
57
mutex_lock(&dev->struct_mutex);
65
58
idr_remove(&dev->ctx_idr, ctx_handle);
66
59
mutex_unlock(&dev->struct_mutex);
67
-
}
68
-
69
-
/******************************************************************/
70
-
/** \name Context bitmap support */
71
-
/*@{*/
72
-
73
-
void drm_legacy_ctxbitmap_release(struct drm_device *dev,
74
-
struct drm_file *file_priv)
75
-
{
76
-
if (drm_core_check_feature(dev, DRIVER_MODESET))
77
-
return;
78
-
79
-
mutex_lock(&dev->ctxlist_mutex);
80
-
if (!list_empty(&dev->ctxlist)) {
81
-
struct drm_ctx_list *pos, *n;
82
-
83
-
list_for_each_entry_safe(pos, n, &dev->ctxlist, head) {
84
-
if (pos->tag == file_priv &&
85
-
pos->handle != DRM_KERNEL_CONTEXT) {
86
-
if (dev->driver->context_dtor)
87
-
dev->driver->context_dtor(dev,
88
-
pos->handle);
89
-
90
-
drm_ctxbitmap_free(dev, pos->handle);
91
-
92
-
list_del(&pos->head);
93
-
kfree(pos);
94
-
--dev->ctx_count;
95
-
}
96
-
}
97
-
}
98
-
mutex_unlock(&dev->ctxlist_mutex);
99
60
}
100
61
101
62
/**
···
90
121
*
91
122
* Initialise the drm_device::ctx_idr
92
123
*/
93
-
void drm_legacy_ctxbitmap_init(struct drm_device * dev)
124
+
int drm_ctxbitmap_init(struct drm_device * dev)
94
125
{
95
-
if (drm_core_check_feature(dev, DRIVER_MODESET))
96
-
return;
97
-
98
126
idr_init(&dev->ctx_idr);
127
+
return 0;
99
128
}
100
129
101
130
/**
···
104
137
* Free all idr members using drm_ctx_sarea_free helper function
105
138
* while holding the drm_device::struct_mutex lock.
106
139
*/
107
-
void drm_legacy_ctxbitmap_cleanup(struct drm_device * dev)
140
+
void drm_ctxbitmap_cleanup(struct drm_device * dev)
108
141
{
109
142
mutex_lock(&dev->struct_mutex);
110
143
idr_destroy(&dev->ctx_idr);
···
135
168
struct drm_ctx_priv_map *request = data;
136
169
struct drm_local_map *map;
137
170
struct drm_map_list *_entry;
138
-
139
-
if (drm_core_check_feature(dev, DRIVER_MODESET))
140
-
return -EINVAL;
141
171
142
172
mutex_lock(&dev->struct_mutex);
143
173
···
179
215
struct drm_ctx_priv_map *request = data;
180
216
struct drm_local_map *map = NULL;
181
217
struct drm_map_list *r_list = NULL;
182
-
183
-
if (drm_core_check_feature(dev, DRIVER_MODESET))
184
-
return -EINVAL;
185
218
186
219
mutex_lock(&dev->struct_mutex);
187
220
list_for_each_entry(r_list, &dev->maplist, head) {
···
280
319
struct drm_ctx ctx;
281
320
int i;
282
321
283
-
if (drm_core_check_feature(dev, DRIVER_MODESET))
284
-
return -EINVAL;
285
-
286
322
if (res->count >= DRM_RESERVED_CONTEXTS) {
287
323
memset(&ctx, 0, sizeof(ctx));
288
324
for (i = 0; i < DRM_RESERVED_CONTEXTS; i++) {
···
309
351
{
310
352
struct drm_ctx_list *ctx_entry;
311
353
struct drm_ctx *ctx = data;
312
-
313
-
if (drm_core_check_feature(dev, DRIVER_MODESET))
314
-
return -EINVAL;
315
354
316
355
ctx->handle = drm_ctxbitmap_next(dev);
317
356
if (ctx->handle == DRM_KERNEL_CONTEXT) {
···
353
398
{
354
399
struct drm_ctx *ctx = data;
355
400
356
-
if (drm_core_check_feature(dev, DRIVER_MODESET))
357
-
return -EINVAL;
358
-
359
401
/* This is 0, because we don't handle any context flags */
360
402
ctx->flags = 0;
361
403
···
375
423
{
376
424
struct drm_ctx *ctx = data;
377
425
378
-
if (drm_core_check_feature(dev, DRIVER_MODESET))
379
-
return -EINVAL;
380
-
381
426
DRM_DEBUG("%d\n", ctx->handle);
382
427
return drm_context_switch(dev, dev->last_context, ctx->handle);
383
428
}
···
394
445
struct drm_file *file_priv)
395
446
{
396
447
struct drm_ctx *ctx = data;
397
-
398
-
if (drm_core_check_feature(dev, DRIVER_MODESET))
399
-
return -EINVAL;
400
448
401
449
DRM_DEBUG("%d\n", ctx->handle);
402
450
drm_context_switch_complete(dev, file_priv, ctx->handle);
···
416
470
struct drm_file *file_priv)
417
471
{
418
472
struct drm_ctx *ctx = data;
419
-
420
-
if (drm_core_check_feature(dev, DRIVER_MODESET))
421
-
return -EINVAL;
422
473
423
474
DRM_DEBUG("%d\n", ctx->handle);
424
475
if (ctx->handle != DRM_KERNEL_CONTEXT) {
+20
-1
drivers/gpu/drm/drm_fops.c
+20
-1
drivers/gpu/drm/drm_fops.c
···
439
439
if (dev->driver->driver_features & DRIVER_GEM)
440
440
drm_gem_release(dev, file_priv);
441
441
442
-
drm_legacy_ctxbitmap_release(dev, file_priv);
442
+
mutex_lock(&dev->ctxlist_mutex);
443
+
if (!list_empty(&dev->ctxlist)) {
444
+
struct drm_ctx_list *pos, *n;
445
+
446
+
list_for_each_entry_safe(pos, n, &dev->ctxlist, head) {
447
+
if (pos->tag == file_priv &&
448
+
pos->handle != DRM_KERNEL_CONTEXT) {
449
+
if (dev->driver->context_dtor)
450
+
dev->driver->context_dtor(dev,
451
+
pos->handle);
452
+
453
+
drm_ctxbitmap_free(dev, pos->handle);
454
+
455
+
list_del(&pos->head);
456
+
kfree(pos);
457
+
--dev->ctx_count;
458
+
}
459
+
}
460
+
}
461
+
mutex_unlock(&dev->ctxlist_mutex);
443
462
444
463
mutex_lock(&dev->struct_mutex);
445
464
+8
-2
drivers/gpu/drm/drm_stub.c
+8
-2
drivers/gpu/drm/drm_stub.c
···
292
292
goto error_out_unreg;
293
293
}
294
294
295
-
drm_legacy_ctxbitmap_init(dev);
295
+
296
+
297
+
retcode = drm_ctxbitmap_init(dev);
298
+
if (retcode) {
299
+
DRM_ERROR("Cannot allocate memory for context bitmap.\n");
300
+
goto error_out_unreg;
301
+
}
296
302
297
303
if (driver->driver_features & DRIVER_GEM) {
298
304
retcode = drm_gem_init(dev);
···
452
446
drm_rmmap(dev, r_list->map);
453
447
drm_ht_remove(&dev->map_hash);
454
448
455
-
drm_legacy_ctxbitmap_cleanup(dev);
449
+
drm_ctxbitmap_cleanup(dev);
456
450
457
451
if (drm_core_check_feature(dev, DRIVER_MODESET))
458
452
drm_put_minor(&dev->control);
+1
-1
drivers/gpu/drm/exynos/Kconfig
+1
-1
drivers/gpu/drm/exynos/Kconfig
+4
-3
drivers/gpu/drm/exynos/exynos_drm_buf.c
+4
-3
drivers/gpu/drm/exynos/exynos_drm_buf.c
···
63
63
return -ENOMEM;
64
64
}
65
65
66
-
buf->kvaddr = dma_alloc_attrs(dev->dev, buf->size,
66
+
buf->kvaddr = (void __iomem *)dma_alloc_attrs(dev->dev,
67
+
buf->size,
67
68
&buf->dma_addr, GFP_KERNEL,
68
69
&buf->dma_attrs);
69
70
if (!buf->kvaddr) {
···
91
90
}
92
91
93
92
buf->sgt = drm_prime_pages_to_sg(buf->pages, nr_pages);
94
-
if (!buf->sgt) {
93
+
if (IS_ERR(buf->sgt)) {
95
94
DRM_ERROR("failed to get sg table.\n");
96
-
ret = -ENOMEM;
95
+
ret = PTR_ERR(buf->sgt);
97
96
goto err_free_attrs;
98
97
}
99
98
+3
-2
drivers/gpu/drm/exynos/exynos_drm_fbdev.c
+3
-2
drivers/gpu/drm/exynos/exynos_drm_fbdev.c
···
99
99
if (is_drm_iommu_supported(dev)) {
100
100
unsigned int nr_pages = buffer->size >> PAGE_SHIFT;
101
101
102
-
buffer->kvaddr = vmap(buffer->pages, nr_pages, VM_MAP,
102
+
buffer->kvaddr = (void __iomem *) vmap(buffer->pages,
103
+
nr_pages, VM_MAP,
103
104
pgprot_writecombine(PAGE_KERNEL));
104
105
} else {
105
106
phys_addr_t dma_addr = buffer->dma_addr;
106
107
if (dma_addr)
107
-
buffer->kvaddr = phys_to_virt(dma_addr);
108
+
buffer->kvaddr = (void __iomem *)phys_to_virt(dma_addr);
108
109
else
109
110
buffer->kvaddr = (void __iomem *)NULL;
110
111
}
+4
-7
drivers/gpu/drm/i915/i915_gem.c
+4
-7
drivers/gpu/drm/i915/i915_gem.c
···
1392
1392
if (i915_terminally_wedged(&dev_priv->gpu_error))
1393
1393
return VM_FAULT_SIGBUS;
1394
1394
case -EAGAIN:
1395
-
/* Give the error handler a chance to run and move the
1396
-
* objects off the GPU active list. Next time we service the
1397
-
* fault, we should be able to transition the page into the
1398
-
* GTT without touching the GPU (and so avoid further
1399
-
* EIO/EGAIN). If the GPU is wedged, then there is no issue
1400
-
* with coherency, just lost writes.
1395
+
/*
1396
+
* EAGAIN means the gpu is hung and we'll wait for the error
1397
+
* handler to reset everything when re-faulting in
1398
+
* i915_mutex_lock_interruptible.
1401
1399
*/
1402
-
set_need_resched();
1403
1400
case 0:
1404
1401
case -ERESTARTSYS:
1405
1402
case -EINTR:
+54
-14
drivers/gpu/drm/i915/i915_irq.c
+54
-14
drivers/gpu/drm/i915/i915_irq.c
···
1469
1469
return ret;
1470
1470
}
1471
1471
1472
+
static void i915_error_wake_up(struct drm_i915_private *dev_priv,
1473
+
bool reset_completed)
1474
+
{
1475
+
struct intel_ring_buffer *ring;
1476
+
int i;
1477
+
1478
+
/*
1479
+
* Notify all waiters for GPU completion events that reset state has
1480
+
* been changed, and that they need to restart their wait after
1481
+
* checking for potential errors (and bail out to drop locks if there is
1482
+
* a gpu reset pending so that i915_error_work_func can acquire them).
1483
+
*/
1484
+
1485
+
/* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
1486
+
for_each_ring(ring, dev_priv, i)
1487
+
wake_up_all(&ring->irq_queue);
1488
+
1489
+
/* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
1490
+
wake_up_all(&dev_priv->pending_flip_queue);
1491
+
1492
+
/*
1493
+
* Signal tasks blocked in i915_gem_wait_for_error that the pending
1494
+
* reset state is cleared.
1495
+
*/
1496
+
if (reset_completed)
1497
+
wake_up_all(&dev_priv->gpu_error.reset_queue);
1498
+
}
1499
+
1472
1500
/**
1473
1501
* i915_error_work_func - do process context error handling work
1474
1502
* @work: work struct
···
1511
1483
drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
1512
1484
gpu_error);
1513
1485
struct drm_device *dev = dev_priv->dev;
1514
-
struct intel_ring_buffer *ring;
1515
1486
char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
1516
1487
char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
1517
1488
char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
1518
-
int i, ret;
1489
+
int ret;
1519
1490
1520
1491
kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
1521
1492
···
1533
1506
kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
1534
1507
reset_event);
1535
1508
1509
+
/*
1510
+
* All state reset _must_ be completed before we update the
1511
+
* reset counter, for otherwise waiters might miss the reset
1512
+
* pending state and not properly drop locks, resulting in
1513
+
* deadlocks with the reset work.
1514
+
*/
1536
1515
ret = i915_reset(dev);
1516
+
1517
+
intel_display_handle_reset(dev);
1537
1518
1538
1519
if (ret == 0) {
1539
1520
/*
···
1563
1528
atomic_set(&error->reset_counter, I915_WEDGED);
1564
1529
}
1565
1530
1566
-
for_each_ring(ring, dev_priv, i)
1567
-
wake_up_all(&ring->irq_queue);
1568
-
1569
-
intel_display_handle_reset(dev);
1570
-
1571
-
wake_up_all(&dev_priv->gpu_error.reset_queue);
1531
+
/*
1532
+
* Note: The wake_up also serves as a memory barrier so that
1533
+
* waiters see the update value of the reset counter atomic_t.
1534
+
*/
1535
+
i915_error_wake_up(dev_priv, true);
1572
1536
}
1573
1537
}
1574
1538
···
1676
1642
void i915_handle_error(struct drm_device *dev, bool wedged)
1677
1643
{
1678
1644
struct drm_i915_private *dev_priv = dev->dev_private;
1679
-
struct intel_ring_buffer *ring;
1680
-
int i;
1681
1645
1682
1646
i915_capture_error_state(dev);
1683
1647
i915_report_and_clear_eir(dev);
···
1685
1653
&dev_priv->gpu_error.reset_counter);
1686
1654
1687
1655
/*
1688
-
* Wakeup waiting processes so that the reset work item
1689
-
* doesn't deadlock trying to grab various locks.
1656
+
* Wakeup waiting processes so that the reset work function
1657
+
* i915_error_work_func doesn't deadlock trying to grab various
1658
+
* locks. By bumping the reset counter first, the woken
1659
+
* processes will see a reset in progress and back off,
1660
+
* releasing their locks and then wait for the reset completion.
1661
+
* We must do this for _all_ gpu waiters that might hold locks
1662
+
* that the reset work needs to acquire.
1663
+
*
1664
+
* Note: The wake_up serves as the required memory barrier to
1665
+
* ensure that the waiters see the updated value of the reset
1666
+
* counter atomic_t.
1690
1667
*/
1691
-
for_each_ring(ring, dev_priv, i)
1692
-
wake_up_all(&ring->irq_queue);
1668
+
i915_error_wake_up(dev_priv, false);
1693
1669
}
1694
1670
1695
1671
/*
+1
-1
drivers/gpu/drm/i915/intel_ddi.c
+1
-1
drivers/gpu/drm/i915/intel_ddi.c
···
778
778
/* Can only use the always-on power well for eDP when
779
779
* not using the panel fitter, and when not using motion
780
780
* blur mitigation (which we don't support). */
781
-
if (intel_crtc->config.pch_pfit.size)
781
+
if (intel_crtc->config.pch_pfit.enabled)
782
782
temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
783
783
else
784
784
temp |= TRANS_DDI_EDP_INPUT_A_ON;
+20
-22
drivers/gpu/drm/i915/intel_display.c
+20
-22
drivers/gpu/drm/i915/intel_display.c
···
2249
2249
I915_WRITE(PIPESRC(intel_crtc->pipe),
2250
2250
((crtc->mode.hdisplay - 1) << 16) |
2251
2251
(crtc->mode.vdisplay - 1));
2252
-
if (!intel_crtc->config.pch_pfit.size &&
2252
+
if (!intel_crtc->config.pch_pfit.enabled &&
2253
2253
(intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2254
2254
intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2255
2255
I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
···
3203
3203
struct drm_i915_private *dev_priv = dev->dev_private;
3204
3204
int pipe = crtc->pipe;
3205
3205
3206
-
if (crtc->config.pch_pfit.size) {
3206
+
if (crtc->config.pch_pfit.enabled) {
3207
3207
/* Force use of hard-coded filter coefficients
3208
3208
* as some pre-programmed values are broken,
3209
3209
* e.g. x201.
···
3428
3428
3429
3429
/* To avoid upsetting the power well on haswell only disable the pfit if
3430
3430
* it's in use. The hw state code will make sure we get this right. */
3431
-
if (crtc->config.pch_pfit.size) {
3431
+
if (crtc->config.pch_pfit.enabled) {
3432
3432
I915_WRITE(PF_CTL(pipe), 0);
3433
3433
I915_WRITE(PF_WIN_POS(pipe), 0);
3434
3434
I915_WRITE(PF_WIN_SZ(pipe), 0);
···
4877
4877
return -EINVAL;
4878
4878
}
4879
4879
4880
-
/* Ensure that the cursor is valid for the new mode before changing... */
4881
-
intel_crtc_update_cursor(crtc, true);
4882
-
4883
4880
if (is_lvds && dev_priv->lvds_downclock_avail) {
4884
4881
/*
4885
4882
* Ensure we match the reduced clock's P to the target clock.
···
5765
5768
intel_crtc->config.dpll.p2 = clock.p2;
5766
5769
}
5767
5770
5768
-
/* Ensure that the cursor is valid for the new mode before changing... */
5769
-
intel_crtc_update_cursor(crtc, true);
5770
-
5771
5771
/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5772
5772
if (intel_crtc->config.has_pch_encoder) {
5773
5773
fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
···
5853
5859
tmp = I915_READ(PF_CTL(crtc->pipe));
5854
5860
5855
5861
if (tmp & PF_ENABLE) {
5862
+
pipe_config->pch_pfit.enabled = true;
5856
5863
pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5857
5864
pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5858
5865
···
6231
6236
if (!crtc->base.enabled)
6232
6237
continue;
6233
6238
6234
-
if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
6239
+
if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled ||
6235
6240
crtc->config.cpu_transcoder != TRANSCODER_EDP)
6236
6241
enable = true;
6237
6242
}
···
6253
6258
6254
6259
if (!intel_ddi_pll_mode_set(crtc))
6255
6260
return -EINVAL;
6256
-
6257
-
/* Ensure that the cursor is valid for the new mode before changing... */
6258
-
intel_crtc_update_cursor(crtc, true);
6259
6261
6260
6262
if (intel_crtc->config.has_dp_encoder)
6261
6263
intel_dp_set_m_n(intel_crtc);
···
6486
6494
6487
6495
/* Set ELD valid state */
6488
6496
tmp = I915_READ(aud_cntrl_st2);
6489
-
DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6497
+
DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
6490
6498
tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6491
6499
I915_WRITE(aud_cntrl_st2, tmp);
6492
6500
tmp = I915_READ(aud_cntrl_st2);
6493
-
DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6501
+
DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
6494
6502
6495
6503
/* Enable HDMI mode */
6496
6504
tmp = I915_READ(aud_config);
6497
-
DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6505
+
DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
6498
6506
/* clear N_programing_enable and N_value_index */
6499
6507
tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6500
6508
I915_WRITE(aud_config, tmp);
···
6929
6937
intel_crtc->cursor_width = width;
6930
6938
intel_crtc->cursor_height = height;
6931
6939
6932
-
intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6940
+
if (intel_crtc->active)
6941
+
intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6933
6942
6934
6943
return 0;
6935
6944
fail_unpin:
···
6949
6956
intel_crtc->cursor_x = x;
6950
6957
intel_crtc->cursor_y = y;
6951
6958
6952
-
intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6959
+
if (intel_crtc->active)
6960
+
intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6953
6961
6954
6962
return 0;
6955
6963
}
···
8199
8205
pipe_config->gmch_pfit.control,
8200
8206
pipe_config->gmch_pfit.pgm_ratios,
8201
8207
pipe_config->gmch_pfit.lvds_border_bits);
8202
-
DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
8208
+
DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8203
8209
pipe_config->pch_pfit.pos,
8204
-
pipe_config->pch_pfit.size);
8210
+
pipe_config->pch_pfit.size,
8211
+
pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
8205
8212
DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8206
8213
}
8207
8214
···
8598
8603
if (INTEL_INFO(dev)->gen < 4)
8599
8604
PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8600
8605
PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8601
-
PIPE_CONF_CHECK_I(pch_pfit.pos);
8602
-
PIPE_CONF_CHECK_I(pch_pfit.size);
8606
+
PIPE_CONF_CHECK_I(pch_pfit.enabled);
8607
+
if (current_config->pch_pfit.enabled) {
8608
+
PIPE_CONF_CHECK_I(pch_pfit.pos);
8609
+
PIPE_CONF_CHECK_I(pch_pfit.size);
8610
+
}
8603
8611
8604
8612
PIPE_CONF_CHECK_I(ips_enabled);
8605
8613
+1
drivers/gpu/drm/i915/intel_drv.h
+1
drivers/gpu/drm/i915/intel_drv.h
+2
drivers/gpu/drm/i915/intel_dvo.c
+2
drivers/gpu/drm/i915/intel_dvo.c
+1
drivers/gpu/drm/i915/intel_panel.c
+1
drivers/gpu/drm/i915/intel_panel.c
+3
-3
drivers/gpu/drm/i915/intel_pm.c
+3
-3
drivers/gpu/drm/i915/intel_pm.c
···
2096
2096
struct drm_crtc *crtc)
2097
2097
{
2098
2098
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2099
-
uint32_t pixel_rate, pfit_size;
2099
+
uint32_t pixel_rate;
2100
2100
2101
2101
pixel_rate = intel_crtc->config.adjusted_mode.clock;
2102
2102
2103
2103
/* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2104
2104
* adjust the pixel_rate here. */
2105
2105
2106
-
pfit_size = intel_crtc->config.pch_pfit.size;
2107
-
if (pfit_size) {
2106
+
if (intel_crtc->config.pch_pfit.enabled) {
2108
2107
uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
2108
+
uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
2109
2109
2110
2110
pipe_w = intel_crtc->config.requested_mode.hdisplay;
2111
2111
pipe_h = intel_crtc->config.requested_mode.vdisplay;
+35
-26
drivers/gpu/drm/i915/intel_sdvo.c
+35
-26
drivers/gpu/drm/i915/intel_sdvo.c
···
788
788
uint16_t h_sync_offset, v_sync_offset;
789
789
int mode_clock;
790
790
791
+
memset(dtd, 0, sizeof(*dtd));
792
+
791
793
width = mode->hdisplay;
792
794
height = mode->vdisplay;
793
795
···
832
830
if (mode->flags & DRM_MODE_FLAG_PVSYNC)
833
831
dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
834
832
835
-
dtd->part2.sdvo_flags = 0;
836
833
dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
837
-
dtd->part2.reserved = 0;
838
834
}
839
835
840
-
static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
836
+
static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode,
841
837
const struct intel_sdvo_dtd *dtd)
842
838
{
843
-
mode->hdisplay = dtd->part1.h_active;
844
-
mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
845
-
mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
846
-
mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
847
-
mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
848
-
mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
849
-
mode->htotal = mode->hdisplay + dtd->part1.h_blank;
850
-
mode->htotal += (dtd->part1.h_high & 0xf) << 8;
839
+
struct drm_display_mode mode = {};
851
840
852
-
mode->vdisplay = dtd->part1.v_active;
853
-
mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
854
-
mode->vsync_start = mode->vdisplay;
855
-
mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
856
-
mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
857
-
mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
858
-
mode->vsync_end = mode->vsync_start +
841
+
mode.hdisplay = dtd->part1.h_active;
842
+
mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
843
+
mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off;
844
+
mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
845
+
mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width;
846
+
mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
847
+
mode.htotal = mode.hdisplay + dtd->part1.h_blank;
848
+
mode.htotal += (dtd->part1.h_high & 0xf) << 8;
849
+
850
+
mode.vdisplay = dtd->part1.v_active;
851
+
mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
852
+
mode.vsync_start = mode.vdisplay;
853
+
mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
854
+
mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
855
+
mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0;
856
+
mode.vsync_end = mode.vsync_start +
859
857
(dtd->part2.v_sync_off_width & 0xf);
860
-
mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
861
-
mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
862
-
mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
858
+
mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
859
+
mode.vtotal = mode.vdisplay + dtd->part1.v_blank;
860
+
mode.vtotal += (dtd->part1.v_high & 0xf) << 8;
863
861
864
-
mode->clock = dtd->part1.clock * 10;
862
+
mode.clock = dtd->part1.clock * 10;
865
863
866
-
mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
867
864
if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
868
-
mode->flags |= DRM_MODE_FLAG_INTERLACE;
865
+
mode.flags |= DRM_MODE_FLAG_INTERLACE;
869
866
if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
870
-
mode->flags |= DRM_MODE_FLAG_PHSYNC;
867
+
mode.flags |= DRM_MODE_FLAG_PHSYNC;
868
+
else
869
+
mode.flags |= DRM_MODE_FLAG_NHSYNC;
871
870
if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
872
-
mode->flags |= DRM_MODE_FLAG_PVSYNC;
871
+
mode.flags |= DRM_MODE_FLAG_PVSYNC;
872
+
else
873
+
mode.flags |= DRM_MODE_FLAG_NVSYNC;
874
+
875
+
drm_mode_set_crtcinfo(&mode, 0);
876
+
877
+
drm_mode_copy(pmode, &mode);
873
878
}
874
879
875
880
static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
+9
-1
drivers/gpu/drm/msm/adreno/adreno_gpu.c
+9
-1
drivers/gpu/drm/msm/adreno/adreno_gpu.c
···
124
124
125
125
/* reset completed fence seqno, just discard anything pending: */
126
126
adreno_gpu->memptrs->fence = gpu->submitted_fence;
127
+
adreno_gpu->memptrs->rptr = 0;
128
+
adreno_gpu->memptrs->wptr = 0;
127
129
128
130
gpu->funcs->pm_resume(gpu);
129
131
ret = gpu->funcs->hw_init(gpu);
···
231
229
return;
232
230
} while(time_before(jiffies, t));
233
231
234
-
DRM_ERROR("timeout waiting for %s to drain ringbuffer!\n", gpu->name);
232
+
DRM_ERROR("%s: timeout waiting to drain ringbuffer!\n", gpu->name);
235
233
236
234
/* TODO maybe we need to reset GPU here to recover from hang? */
237
235
}
···
258
256
{
259
257
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
260
258
uint32_t freedwords;
259
+
unsigned long t = jiffies + ADRENO_IDLE_TIMEOUT;
261
260
do {
262
261
uint32_t size = gpu->rb->size / 4;
263
262
uint32_t wptr = get_wptr(gpu->rb);
264
263
uint32_t rptr = adreno_gpu->memptrs->rptr;
265
264
freedwords = (rptr + (size - 1) - wptr) % size;
265
+
266
+
if (time_after(jiffies, t)) {
267
+
DRM_ERROR("%s: timeout waiting for ringbuffer space\n", gpu->name);
268
+
break;
269
+
}
266
270
} while(freedwords < ndwords);
267
271
}
268
272
+32
-16
drivers/gpu/drm/msm/msm_drv.c
+32
-16
drivers/gpu/drm/msm/msm_drv.c
···
499
499
struct timespec *timeout)
500
500
{
501
501
struct msm_drm_private *priv = dev->dev_private;
502
-
unsigned long timeout_jiffies = timespec_to_jiffies(timeout);
503
-
unsigned long start_jiffies = jiffies;
504
-
unsigned long remaining_jiffies;
505
502
int ret;
506
503
507
-
if (time_after(start_jiffies, timeout_jiffies))
508
-
remaining_jiffies = 0;
509
-
else
510
-
remaining_jiffies = timeout_jiffies - start_jiffies;
504
+
if (!priv->gpu)
505
+
return 0;
511
506
512
-
ret = wait_event_interruptible_timeout(priv->fence_event,
513
-
priv->completed_fence >= fence,
514
-
remaining_jiffies);
515
-
if (ret == 0) {
516
-
DBG("timeout waiting for fence: %u (completed: %u)",
517
-
fence, priv->completed_fence);
518
-
ret = -ETIMEDOUT;
519
-
} else if (ret != -ERESTARTSYS) {
520
-
ret = 0;
507
+
if (fence > priv->gpu->submitted_fence) {
508
+
DRM_ERROR("waiting on invalid fence: %u (of %u)\n",
509
+
fence, priv->gpu->submitted_fence);
510
+
return -EINVAL;
511
+
}
512
+
513
+
if (!timeout) {
514
+
/* no-wait: */
515
+
ret = fence_completed(dev, fence) ? 0 : -EBUSY;
516
+
} else {
517
+
unsigned long timeout_jiffies = timespec_to_jiffies(timeout);
518
+
unsigned long start_jiffies = jiffies;
519
+
unsigned long remaining_jiffies;
520
+
521
+
if (time_after(start_jiffies, timeout_jiffies))
522
+
remaining_jiffies = 0;
523
+
else
524
+
remaining_jiffies = timeout_jiffies - start_jiffies;
525
+
526
+
ret = wait_event_interruptible_timeout(priv->fence_event,
527
+
fence_completed(dev, fence),
528
+
remaining_jiffies);
529
+
530
+
if (ret == 0) {
531
+
DBG("timeout waiting for fence: %u (completed: %u)",
532
+
fence, priv->completed_fence);
533
+
ret = -ETIMEDOUT;
534
+
} else if (ret != -ERESTARTSYS) {
535
+
ret = 0;
536
+
}
521
537
}
522
538
523
539
return ret;
+7
-1
drivers/gpu/drm/msm/msm_drv.h
+7
-1
drivers/gpu/drm/msm/msm_drv.h
···
153
153
int msm_gem_queue_inactive_work(struct drm_gem_object *obj,
154
154
struct work_struct *work);
155
155
void msm_gem_move_to_active(struct drm_gem_object *obj,
156
-
struct msm_gpu *gpu, uint32_t fence);
156
+
struct msm_gpu *gpu, bool write, uint32_t fence);
157
157
void msm_gem_move_to_inactive(struct drm_gem_object *obj);
158
158
int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op,
159
159
struct timespec *timeout);
···
190
190
191
191
#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
192
192
#define VERB(fmt, ...) if (0) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
193
+
194
+
static inline bool fence_completed(struct drm_device *dev, uint32_t fence)
195
+
{
196
+
struct msm_drm_private *priv = dev->dev_private;
197
+
return priv->completed_fence >= fence;
198
+
}
193
199
194
200
static inline int align_pitch(int width, int bpp)
195
201
{
+24
-10
drivers/gpu/drm/msm/msm_gem.c
+24
-10
drivers/gpu/drm/msm/msm_gem.c
···
40
40
}
41
41
42
42
msm_obj->sgt = drm_prime_pages_to_sg(p, npages);
43
-
if (!msm_obj->sgt) {
43
+
if (IS_ERR(msm_obj->sgt)) {
44
44
dev_err(dev->dev, "failed to allocate sgt\n");
45
-
return ERR_PTR(-ENOMEM);
45
+
return ERR_CAST(msm_obj->sgt);
46
46
}
47
47
48
48
msm_obj->pages = p;
···
159
159
out:
160
160
switch (ret) {
161
161
case -EAGAIN:
162
-
set_need_resched();
163
162
case 0:
164
163
case -ERESTARTSYS:
165
164
case -EINTR:
···
392
393
}
393
394
394
395
void msm_gem_move_to_active(struct drm_gem_object *obj,
395
-
struct msm_gpu *gpu, uint32_t fence)
396
+
struct msm_gpu *gpu, bool write, uint32_t fence)
396
397
{
397
398
struct msm_gem_object *msm_obj = to_msm_bo(obj);
398
399
msm_obj->gpu = gpu;
399
-
msm_obj->fence = fence;
400
+
if (write)
401
+
msm_obj->write_fence = fence;
402
+
else
403
+
msm_obj->read_fence = fence;
400
404
list_del_init(&msm_obj->mm_list);
401
405
list_add_tail(&msm_obj->mm_list, &gpu->active_list);
402
406
}
···
413
411
WARN_ON(!mutex_is_locked(&dev->struct_mutex));
414
412
415
413
msm_obj->gpu = NULL;
416
-
msm_obj->fence = 0;
414
+
msm_obj->read_fence = 0;
415
+
msm_obj->write_fence = 0;
417
416
list_del_init(&msm_obj->mm_list);
418
417
list_add_tail(&msm_obj->mm_list, &priv->inactive_list);
419
418
···
436
433
struct msm_gem_object *msm_obj = to_msm_bo(obj);
437
434
int ret = 0;
438
435
439
-
if (is_active(msm_obj) && !(op & MSM_PREP_NOSYNC))
440
-
ret = msm_wait_fence_interruptable(dev, msm_obj->fence, timeout);
436
+
if (is_active(msm_obj)) {
437
+
uint32_t fence = 0;
438
+
439
+
if (op & MSM_PREP_READ)
440
+
fence = msm_obj->write_fence;
441
+
if (op & MSM_PREP_WRITE)
442
+
fence = max(fence, msm_obj->read_fence);
443
+
if (op & MSM_PREP_NOSYNC)
444
+
timeout = NULL;
445
+
446
+
ret = msm_wait_fence_interruptable(dev, fence, timeout);
447
+
}
441
448
442
449
/* TODO cache maintenance */
443
450
···
468
455
uint64_t off = drm_vma_node_start(&obj->vma_node);
469
456
470
457
WARN_ON(!mutex_is_locked(&dev->struct_mutex));
471
-
seq_printf(m, "%08x: %c(%d) %2d (%2d) %08llx %p %d\n",
458
+
seq_printf(m, "%08x: %c(r=%u,w=%u) %2d (%2d) %08llx %p %d\n",
472
459
msm_obj->flags, is_active(msm_obj) ? 'A' : 'I',
473
-
msm_obj->fence, obj->name, obj->refcount.refcount.counter,
460
+
msm_obj->read_fence, msm_obj->write_fence,
461
+
obj->name, obj->refcount.refcount.counter,
474
462
off, msm_obj->vaddr, obj->size);
475
463
}
476
464
+1
-1
drivers/gpu/drm/msm/msm_gem.h
+1
-1
drivers/gpu/drm/msm/msm_gem.h
···
36
36
*/
37
37
struct list_head mm_list;
38
38
struct msm_gpu *gpu; /* non-null if active */
39
-
uint32_t fence;
39
+
uint32_t read_fence, write_fence;
40
40
41
41
/* Transiently in the process of submit ioctl, objects associated
42
42
* with the submit are on submit->bo_list.. this only lasts for
+13
-11
drivers/gpu/drm/msm/msm_gem_submit.c
+13
-11
drivers/gpu/drm/msm/msm_gem_submit.c
···
78
78
}
79
79
80
80
if (submit_bo.flags & BO_INVALID_FLAGS) {
81
-
DBG("invalid flags: %x", submit_bo.flags);
81
+
DRM_ERROR("invalid flags: %x\n", submit_bo.flags);
82
82
ret = -EINVAL;
83
83
goto out_unlock;
84
84
}
···
92
92
*/
93
93
obj = idr_find(&file->object_idr, submit_bo.handle);
94
94
if (!obj) {
95
-
DBG("invalid handle %u at index %u", submit_bo.handle, i);
95
+
DRM_ERROR("invalid handle %u at index %u\n", submit_bo.handle, i);
96
96
ret = -EINVAL;
97
97
goto out_unlock;
98
98
}
···
100
100
msm_obj = to_msm_bo(obj);
101
101
102
102
if (!list_empty(&msm_obj->submit_entry)) {
103
-
DBG("handle %u at index %u already on submit list",
103
+
DRM_ERROR("handle %u at index %u already on submit list\n",
104
104
submit_bo.handle, i);
105
105
ret = -EINVAL;
106
106
goto out_unlock;
···
216
216
struct msm_gem_object **obj, uint32_t *iova, bool *valid)
217
217
{
218
218
if (idx >= submit->nr_bos) {
219
-
DBG("invalid buffer index: %u (out of %u)", idx, submit->nr_bos);
220
-
return EINVAL;
219
+
DRM_ERROR("invalid buffer index: %u (out of %u)\n",
220
+
idx, submit->nr_bos);
221
+
return -EINVAL;
221
222
}
222
223
223
224
if (obj)
···
240
239
int ret;
241
240
242
241
if (offset % 4) {
243
-
DBG("non-aligned cmdstream buffer: %u", offset);
242
+
DRM_ERROR("non-aligned cmdstream buffer: %u\n", offset);
244
243
return -EINVAL;
245
244
}
246
245
···
267
266
return -EFAULT;
268
267
269
268
if (submit_reloc.submit_offset % 4) {
270
-
DBG("non-aligned reloc offset: %u",
269
+
DRM_ERROR("non-aligned reloc offset: %u\n",
271
270
submit_reloc.submit_offset);
272
271
return -EINVAL;
273
272
}
···
277
276
278
277
if ((off >= (obj->base.size / 4)) ||
279
278
(off < last_offset)) {
280
-
DBG("invalid offset %u at reloc %u", off, i);
279
+
DRM_ERROR("invalid offset %u at reloc %u\n", off, i);
281
280
return -EINVAL;
282
281
}
283
282
···
375
374
goto out;
376
375
377
376
if (submit_cmd.size % 4) {
378
-
DBG("non-aligned cmdstream buffer size: %u",
377
+
DRM_ERROR("non-aligned cmdstream buffer size: %u\n",
379
378
submit_cmd.size);
380
379
ret = -EINVAL;
381
380
goto out;
382
381
}
383
382
384
-
if (submit_cmd.size >= msm_obj->base.size) {
385
-
DBG("invalid cmdstream size: %u", submit_cmd.size);
383
+
if ((submit_cmd.size + submit_cmd.submit_offset) >=
384
+
msm_obj->base.size) {
385
+
DRM_ERROR("invalid cmdstream size: %u\n", submit_cmd.size);
386
386
ret = -EINVAL;
387
387
goto out;
388
388
}
+20
-4
drivers/gpu/drm/msm/msm_gpu.c
+20
-4
drivers/gpu/drm/msm/msm_gpu.c
···
29
29
static void bs_init(struct msm_gpu *gpu, struct platform_device *pdev)
30
30
{
31
31
struct drm_device *dev = gpu->dev;
32
-
struct kgsl_device_platform_data *pdata = pdev->dev.platform_data;
32
+
struct kgsl_device_platform_data *pdata;
33
33
34
34
if (!pdev) {
35
35
dev_err(dev->dev, "could not find dtv pdata\n");
36
36
return;
37
37
}
38
38
39
+
pdata = pdev->dev.platform_data;
39
40
if (pdata->bus_scale_table) {
40
41
gpu->bsc = msm_bus_scale_register_client(pdata->bus_scale_table);
41
42
DBG("bus scale client: %08x", gpu->bsc);
···
231
230
static void hangcheck_handler(unsigned long data)
232
231
{
233
232
struct msm_gpu *gpu = (struct msm_gpu *)data;
233
+
struct drm_device *dev = gpu->dev;
234
+
struct msm_drm_private *priv = dev->dev_private;
234
235
uint32_t fence = gpu->funcs->last_fence(gpu);
235
236
236
237
if (fence != gpu->hangcheck_fence) {
···
240
237
gpu->hangcheck_fence = fence;
241
238
} else if (fence < gpu->submitted_fence) {
242
239
/* no progress and not done.. hung! */
243
-
struct msm_drm_private *priv = gpu->dev->dev_private;
244
240
gpu->hangcheck_fence = fence;
241
+
dev_err(dev->dev, "%s: hangcheck detected gpu lockup!\n",
242
+
gpu->name);
243
+
dev_err(dev->dev, "%s: completed fence: %u\n",
244
+
gpu->name, fence);
245
+
dev_err(dev->dev, "%s: submitted fence: %u\n",
246
+
gpu->name, gpu->submitted_fence);
245
247
queue_work(priv->wq, &gpu->recover_work);
246
248
}
247
249
248
250
/* if still more pending work, reset the hangcheck timer: */
249
251
if (gpu->submitted_fence > gpu->hangcheck_fence)
250
252
hangcheck_timer_reset(gpu);
253
+
254
+
/* workaround for missing irq: */
255
+
queue_work(priv->wq, &gpu->retire_work);
251
256
}
252
257
253
258
/*
···
276
265
obj = list_first_entry(&gpu->active_list,
277
266
struct msm_gem_object, mm_list);
278
267
279
-
if (obj->fence <= fence) {
268
+
if ((obj->read_fence <= fence) &&
269
+
(obj->write_fence <= fence)) {
280
270
/* move to inactive: */
281
271
msm_gem_move_to_inactive(&obj->base);
282
272
msm_gem_put_iova(&obj->base, gpu->id);
···
333
321
submit->gpu->id, &iova);
334
322
}
335
323
336
-
msm_gem_move_to_active(&msm_obj->base, gpu, submit->fence);
324
+
if (submit->bos[i].flags & MSM_SUBMIT_BO_READ)
325
+
msm_gem_move_to_active(&msm_obj->base, gpu, false, submit->fence);
326
+
327
+
if (submit->bos[i].flags & MSM_SUBMIT_BO_WRITE)
328
+
msm_gem_move_to_active(&msm_obj->base, gpu, true, submit->fence);
337
329
}
338
330
hangcheck_timer_reset(gpu);
339
331
mutex_unlock(&dev->struct_mutex);
+3
-4
include/drm/drmP.h
+3
-4
include/drm/drmP.h
···
1322
1322
extern int drm_rmctx(struct drm_device *dev, void *data,
1323
1323
struct drm_file *file_priv);
1324
1324
1325
-
extern void drm_legacy_ctxbitmap_init(struct drm_device *dev);
1326
-
extern void drm_legacy_ctxbitmap_cleanup(struct drm_device *dev);
1327
-
extern void drm_legacy_ctxbitmap_release(struct drm_device *dev,
1328
-
struct drm_file *file_priv);
1325
+
extern int drm_ctxbitmap_init(struct drm_device *dev);
1326
+
extern void drm_ctxbitmap_cleanup(struct drm_device *dev);
1327
+
extern void drm_ctxbitmap_free(struct drm_device *dev, int ctx_handle);
1329
1328
1330
1329
extern int drm_setsareactx(struct drm_device *dev, void *data,
1331
1330
struct drm_file *file_priv);