Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
platform: mellanox: mlx-platform: Add support for new Nvidia DGX system based on class VMOD0010
This system is based on Nvidia QM9700 64x400G QTM-2 switch, with the
following key changes:
Key changes:
1. New system SKU: HI73.
2. Power Supply: PSU AC replaiced with PDB board (added pdb/pwr
attributes).
3. CPLD: Update register map with new PDB related signals.
Signed-off-by: Oleksandr Shamray <oleksandrs@nvidia.com>
Reviewed-by: Vadim Pasternak <vadimp@nvidia.com>
Link: https://patch.msgid.link/20260128075939.2704019-2-oleksandrs@nvidia.com
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
authored by
Oleksandr Shamray
and committed by
Ilpo Järvinen
dbf76f86
c46f7cb3
+456
+456
drivers/platform/mellanox/mlx-platform.c
+456
drivers/platform/mellanox/mlx-platform.c
···
6
6
* Copyright (C) 2016-2018 Vadim Pasternak <vadimp@mellanox.com>
7
7
*/
8
8
9
+
#include <linux/array_size.h>
10
+
#include <linux/bits.h>
9
11
#include <linux/device.h>
10
12
#include <linux/dmi.h>
11
13
#include <linux/i2c.h>
···
729
727
},
730
728
};
731
729
730
+
/* Platform hotplug dgx data */
731
+
static struct mlxreg_core_data mlxplat_mlxcpld_dgx_pdb_items_data[] = {
732
+
{
733
+
.label = "pdb1",
734
+
.reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
735
+
.mask = BIT(0),
736
+
.hpdev.nr = MLXPLAT_CPLD_NR_NONE,
737
+
},
738
+
};
739
+
732
740
static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_items_data[] = {
733
741
{
734
742
.label = "pwr1",
···
785
773
.mask = BIT(1),
786
774
.hpdev.brdinfo = &mlxplat_mlxcpld_pwr_ng800[1],
787
775
.hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
776
+
},
777
+
};
778
+
779
+
static struct mlxreg_core_data mlxplat_mlxcpld_dgx_pwr_items_data[] = {
780
+
{
781
+
.label = "pwr1",
782
+
.reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
783
+
.mask = BIT(0),
784
+
.hpdev.nr = MLXPLAT_CPLD_NR_NONE,
788
785
},
789
786
};
790
787
···
1420
1399
}
1421
1400
};
1422
1401
1402
+
static struct mlxreg_core_item mlxplat_mlxcpld_ext_dgx_items[] = {
1403
+
{
1404
+
.data = mlxplat_mlxcpld_dgx_pdb_items_data,
1405
+
.aggr_mask = MLXPLAT_CPLD_AGGR_PSU_MASK_DEF,
1406
+
.reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
1407
+
.mask = MLXPLAT_CPLD_PSU_MASK,
1408
+
.count = ARRAY_SIZE(mlxplat_mlxcpld_dgx_pdb_items_data),
1409
+
.inversed = 1,
1410
+
.health = false,
1411
+
},
1412
+
{
1413
+
.data = mlxplat_mlxcpld_dgx_pwr_items_data,
1414
+
.aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF,
1415
+
.reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
1416
+
.mask = MLXPLAT_CPLD_PWR_MASK,
1417
+
.count = ARRAY_SIZE(mlxplat_mlxcpld_dgx_pwr_items_data),
1418
+
.inversed = 0,
1419
+
.health = false,
1420
+
},
1421
+
{
1422
+
.data = mlxplat_mlxcpld_default_ng_fan_items_data,
1423
+
.aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
1424
+
.reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
1425
+
.mask = MLXPLAT_CPLD_FAN_NG_MASK,
1426
+
.count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data),
1427
+
.inversed = 1,
1428
+
.health = false,
1429
+
},
1430
+
{
1431
+
.data = mlxplat_mlxcpld_default_asic_items_data,
1432
+
.aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
1433
+
.reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
1434
+
.mask = MLXPLAT_CPLD_ASIC_MASK,
1435
+
.count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data),
1436
+
.inversed = 0,
1437
+
.health = true,
1438
+
},
1439
+
};
1440
+
1423
1441
static struct mlxreg_core_item mlxplat_mlxcpld_ng800_items[] = {
1424
1442
{
1425
1443
.data = mlxplat_mlxcpld_default_ng_psu_items_data,
···
1504
1444
struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = {
1505
1445
.items = mlxplat_mlxcpld_ext_items,
1506
1446
.count = ARRAY_SIZE(mlxplat_mlxcpld_ext_items),
1447
+
.cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
1448
+
.mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX,
1449
+
.cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
1450
+
.mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2,
1451
+
};
1452
+
1453
+
static
1454
+
struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_dgx_ext_data = {
1455
+
.items = mlxplat_mlxcpld_ext_dgx_items,
1456
+
.count = ARRAY_SIZE(mlxplat_mlxcpld_ext_dgx_items),
1507
1457
.cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
1508
1458
.mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX,
1509
1459
.cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
···
4695
4625
.counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_regs_io_data),
4696
4626
};
4697
4627
4628
+
/* Platform register access for next generation systems families data */
4629
+
static struct mlxreg_core_data mlxplat_mlxcpld_dgx_ng_regs_io_data[] = {
4630
+
{
4631
+
.label = "cpld1_version",
4632
+
.reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET,
4633
+
.bit = GENMASK(7, 0),
4634
+
.mode = 0444,
4635
+
},
4636
+
{
4637
+
.label = "cpld2_version",
4638
+
.reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET,
4639
+
.bit = GENMASK(7, 0),
4640
+
.mode = 0444,
4641
+
},
4642
+
{
4643
+
.label = "cpld3_version",
4644
+
.reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET,
4645
+
.bit = GENMASK(7, 0),
4646
+
.mode = 0444,
4647
+
},
4648
+
{
4649
+
.label = "cpld4_version",
4650
+
.reg = MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET,
4651
+
.bit = GENMASK(7, 0),
4652
+
.mode = 0444,
4653
+
},
4654
+
{
4655
+
.label = "cpld1_pn",
4656
+
.reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET,
4657
+
.bit = GENMASK(15, 0),
4658
+
.mode = 0444,
4659
+
.regnum = 2,
4660
+
},
4661
+
{
4662
+
.label = "cpld2_pn",
4663
+
.reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET,
4664
+
.bit = GENMASK(15, 0),
4665
+
.mode = 0444,
4666
+
.regnum = 2,
4667
+
},
4668
+
{
4669
+
.label = "cpld3_pn",
4670
+
.reg = MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET,
4671
+
.bit = GENMASK(15, 0),
4672
+
.mode = 0444,
4673
+
.regnum = 2,
4674
+
},
4675
+
{
4676
+
.label = "cpld4_pn",
4677
+
.reg = MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET,
4678
+
.bit = GENMASK(15, 0),
4679
+
.mode = 0444,
4680
+
.regnum = 2,
4681
+
},
4682
+
{
4683
+
.label = "cpld1_version_min",
4684
+
.reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET,
4685
+
.bit = GENMASK(7, 0),
4686
+
.mode = 0444,
4687
+
},
4688
+
{
4689
+
.label = "cpld2_version_min",
4690
+
.reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET,
4691
+
.bit = GENMASK(7, 0),
4692
+
.mode = 0444,
4693
+
},
4694
+
{
4695
+
.label = "cpld3_version_min",
4696
+
.reg = MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET,
4697
+
.bit = GENMASK(7, 0),
4698
+
.mode = 0444,
4699
+
},
4700
+
{
4701
+
.label = "cpld4_version_min",
4702
+
.reg = MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET,
4703
+
.bit = GENMASK(7, 0),
4704
+
.mode = 0444,
4705
+
},
4706
+
{
4707
+
.label = "asic_reset",
4708
+
.reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET,
4709
+
.mask = GENMASK(7, 0) & ~BIT(3),
4710
+
.mode = 0200,
4711
+
},
4712
+
{
4713
+
.label = "reset_long_pb",
4714
+
.reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
4715
+
.mask = GENMASK(7, 0) & ~BIT(0),
4716
+
.mode = 0444,
4717
+
},
4718
+
{
4719
+
.label = "reset_short_pb",
4720
+
.reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
4721
+
.mask = GENMASK(7, 0) & ~BIT(1),
4722
+
.mode = 0444,
4723
+
},
4724
+
{
4725
+
.label = "reset_aux_pwr_or_ref",
4726
+
.reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
4727
+
.mask = GENMASK(7, 0) & ~BIT(2),
4728
+
.mode = 0444,
4729
+
},
4730
+
{
4731
+
.label = "reset_swb_dc_dc_pwr_fail",
4732
+
.reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
4733
+
.mask = GENMASK(7, 0) & ~BIT(3),
4734
+
.mode = 0444,
4735
+
},
4736
+
{
4737
+
.label = "reset_from_asic",
4738
+
.reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
4739
+
.mask = GENMASK(7, 0) & ~BIT(5),
4740
+
.mode = 0444,
4741
+
},
4742
+
{
4743
+
.label = "reset_swb_wd",
4744
+
.reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
4745
+
.mask = GENMASK(7, 0) & ~BIT(6),
4746
+
.mode = 0444,
4747
+
},
4748
+
{
4749
+
.label = "reset_asic_thermal",
4750
+
.reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
4751
+
.mask = GENMASK(7, 0) & ~BIT(7),
4752
+
.mode = 0444,
4753
+
},
4754
+
{
4755
+
.label = "reset_sw_reset",
4756
+
.reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
4757
+
.mask = GENMASK(7, 0) & ~BIT(0),
4758
+
.mode = 0444,
4759
+
},
4760
+
{
4761
+
.label = "reset_comex_pwr_fail",
4762
+
.reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
4763
+
.mask = GENMASK(7, 0) & ~BIT(3),
4764
+
.mode = 0444,
4765
+
},
4766
+
{
4767
+
.label = "reset_platform",
4768
+
.reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
4769
+
.mask = GENMASK(7, 0) & ~BIT(4),
4770
+
.mode = 0444,
4771
+
},
4772
+
{
4773
+
.label = "reset_soc",
4774
+
.reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
4775
+
.mask = GENMASK(7, 0) & ~BIT(5),
4776
+
.mode = 0444,
4777
+
},
4778
+
{
4779
+
.label = "reset_comex_wd",
4780
+
.reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET,
4781
+
.mask = GENMASK(7, 0) & ~BIT(6),
4782
+
.mode = 0444,
4783
+
},
4784
+
{
4785
+
.label = "reset_system",
4786
+
.reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
4787
+
.mask = GENMASK(7, 0) & ~BIT(1),
4788
+
.mode = 0444,
4789
+
},
4790
+
{
4791
+
.label = "reset_sw_pwr_off",
4792
+
.reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
4793
+
.mask = GENMASK(7, 0) & ~BIT(2),
4794
+
.mode = 0444,
4795
+
},
4796
+
{
4797
+
.label = "reset_comex_thermal",
4798
+
.reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
4799
+
.mask = GENMASK(7, 0) & ~BIT(3),
4800
+
.mode = 0444,
4801
+
},
4802
+
{
4803
+
.label = "reset_reload_bios",
4804
+
.reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
4805
+
.mask = GENMASK(7, 0) & ~BIT(5),
4806
+
.mode = 0444,
4807
+
},
4808
+
{
4809
+
.label = "reset_pdb_pwr_fail",
4810
+
.reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET,
4811
+
.mask = GENMASK(7, 0) & ~BIT(6),
4812
+
.mode = 0444,
4813
+
},
4814
+
{
4815
+
.label = "pdb_reset_stby",
4816
+
.reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
4817
+
.mask = GENMASK(7, 0) & ~BIT(0),
4818
+
.mode = 0200,
4819
+
},
4820
+
{
4821
+
.label = "pwr_cycle",
4822
+
.reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
4823
+
.mask = GENMASK(7, 0) & ~BIT(2),
4824
+
.mode = 0200,
4825
+
},
4826
+
{
4827
+
.label = "pwr_down",
4828
+
.reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
4829
+
.mask = GENMASK(7, 0) & ~BIT(3),
4830
+
.mode = 0200,
4831
+
},
4832
+
{
4833
+
.label = "deep_pwr_cycle",
4834
+
.reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
4835
+
.mask = GENMASK(7, 0) & ~BIT(5),
4836
+
.mode = 0200,
4837
+
},
4838
+
{
4839
+
.label = "latch_reset",
4840
+
.reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
4841
+
.mask = GENMASK(7, 0) & ~BIT(6),
4842
+
.mode = 0200,
4843
+
},
4844
+
{
4845
+
.label = "jtag_cap",
4846
+
.reg = MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET,
4847
+
.mask = MLXPLAT_CPLD_FU_CAP_MASK,
4848
+
.bit = 1,
4849
+
.mode = 0444,
4850
+
},
4851
+
{
4852
+
.label = "jtag_enable",
4853
+
.reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET,
4854
+
.mask = GENMASK(7, 0) & ~BIT(4),
4855
+
.mode = 0644,
4856
+
},
4857
+
{
4858
+
.label = "dbg1",
4859
+
.reg = MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET,
4860
+
.bit = GENMASK(7, 0),
4861
+
.mode = 0644,
4862
+
},
4863
+
{
4864
+
.label = "dbg2",
4865
+
.reg = MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET,
4866
+
.bit = GENMASK(7, 0),
4867
+
.mode = 0644,
4868
+
},
4869
+
{
4870
+
.label = "dbg3",
4871
+
.reg = MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET,
4872
+
.bit = GENMASK(7, 0),
4873
+
.mode = 0644,
4874
+
},
4875
+
{
4876
+
.label = "dbg4",
4877
+
.reg = MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET,
4878
+
.bit = GENMASK(7, 0),
4879
+
.mode = 0644,
4880
+
},
4881
+
{
4882
+
.label = "asic_health",
4883
+
.reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET,
4884
+
.mask = MLXPLAT_CPLD_ASIC_MASK,
4885
+
.bit = 1,
4886
+
.mode = 0444,
4887
+
},
4888
+
{
4889
+
.label = "fan_dir",
4890
+
.reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION,
4891
+
.bit = GENMASK(7, 0),
4892
+
.mode = 0444,
4893
+
},
4894
+
{
4895
+
.label = "bios_safe_mode",
4896
+
.reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
4897
+
.mask = GENMASK(7, 0) & ~BIT(4),
4898
+
.mode = 0444,
4899
+
},
4900
+
{
4901
+
.label = "bios_active_image",
4902
+
.reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
4903
+
.mask = GENMASK(7, 0) & ~BIT(5),
4904
+
.mode = 0444,
4905
+
},
4906
+
{
4907
+
.label = "bios_auth_fail",
4908
+
.reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
4909
+
.mask = GENMASK(7, 0) & ~BIT(6),
4910
+
.mode = 0444,
4911
+
},
4912
+
{
4913
+
.label = "bios_upgrade_fail",
4914
+
.reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET,
4915
+
.mask = GENMASK(7, 0) & ~BIT(7),
4916
+
.mode = 0444,
4917
+
},
4918
+
{
4919
+
.label = "voltreg_update_status",
4920
+
.reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET,
4921
+
.mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK,
4922
+
.bit = 5,
4923
+
.mode = 0444,
4924
+
},
4925
+
{
4926
+
.label = "pwr_converter_prog_en",
4927
+
.reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,
4928
+
.mask = GENMASK(7, 0) & ~BIT(0),
4929
+
.mode = 0644,
4930
+
.secured = 1,
4931
+
},
4932
+
{
4933
+
.label = "vpd_wp",
4934
+
.reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,
4935
+
.mask = GENMASK(7, 0) & ~BIT(3),
4936
+
.mode = 0644,
4937
+
},
4938
+
{
4939
+
.label = "pcie_asic_reset_dis",
4940
+
.reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,
4941
+
.mask = GENMASK(7, 0) & ~BIT(4),
4942
+
.mode = 0644,
4943
+
},
4944
+
{
4945
+
.label = "shutdown_unlock",
4946
+
.reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET,
4947
+
.mask = GENMASK(7, 0) & ~BIT(5),
4948
+
.mode = 0644,
4949
+
},
4950
+
{
4951
+
.label = "config1",
4952
+
.reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET,
4953
+
.bit = GENMASK(7, 0),
4954
+
.mode = 0444,
4955
+
},
4956
+
{
4957
+
.label = "config2",
4958
+
.reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET,
4959
+
.bit = GENMASK(7, 0),
4960
+
.mode = 0444,
4961
+
},
4962
+
{
4963
+
.label = "config3",
4964
+
.reg = MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET,
4965
+
.bit = GENMASK(7, 0),
4966
+
.mode = 0444,
4967
+
},
4968
+
{
4969
+
.label = "ufm_version",
4970
+
.reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET,
4971
+
.bit = GENMASK(7, 0),
4972
+
.mode = 0444,
4973
+
},
4974
+
};
4975
+
4976
+
static struct mlxreg_core_platform_data mlxplat_dgx_ng_regs_io_data = {
4977
+
.data = mlxplat_mlxcpld_dgx_ng_regs_io_data,
4978
+
.counter = ARRAY_SIZE(mlxplat_mlxcpld_dgx_ng_regs_io_data),
4979
+
};
4980
+
4698
4981
/* Platform register access for modular systems families data */
4699
4982
static struct mlxreg_core_data mlxplat_mlxcpld_modular_regs_io_data[] = {
4700
4983
{
···
7662
7239
return mlxplat_register_platform_device();
7663
7240
}
7664
7241
7242
+
static int __init mlxplat_dmi_ng400_dgx_matched(const struct dmi_system_id *dmi)
7243
+
{
7244
+
int i;
7245
+
7246
+
mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM;
7247
+
mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data);
7248
+
mlxplat_mux_data = mlxplat_default_mux_data;
7249
+
for (i = 0; i < mlxplat_mux_num; i++) {
7250
+
mlxplat_mux_data[i].values = mlxplat_msn21xx_channels;
7251
+
mlxplat_mux_data[i].n_values =
7252
+
ARRAY_SIZE(mlxplat_msn21xx_channels);
7253
+
}
7254
+
mlxplat_hotplug = &mlxplat_mlxcpld_dgx_ext_data;
7255
+
mlxplat_hotplug->deferred_nr =
7256
+
mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1];
7257
+
mlxplat_led = &mlxplat_default_ng_led_data;
7258
+
mlxplat_regs_io = &mlxplat_dgx_ng_regs_io_data;
7259
+
mlxplat_fan = &mlxplat_default_fan_data;
7260
+
for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++)
7261
+
mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i];
7262
+
mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data;
7263
+
mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400;
7264
+
7265
+
return mlxplat_register_platform_device();
7266
+
}
7267
+
7665
7268
static int __init mlxplat_dmi_modular_matched(const struct dmi_system_id *dmi)
7666
7269
{
7667
7270
int i;
···
7905
7456
.matches = {
7906
7457
DMI_MATCH(DMI_BOARD_NAME, "VMOD0010"),
7907
7458
DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI142"),
7459
+
},
7460
+
},
7461
+
{
7462
+
.callback = mlxplat_dmi_ng400_dgx_matched,
7463
+
.matches = {
7464
+
DMI_MATCH(DMI_BOARD_NAME, "VMOD0010"),
7465
+
DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI173"),
7908
7466
},
7909
7467
},
7910
7468
{