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ARM: dts: r9a06g032: Describe MII converter

Add the MII converter node which describes the MII converter that is
present on the RZ/N1 SoC.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Link: https://lore.kernel.org/r/20220624144001.95518-13-clement.leger@bootlin.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

authored by

Clément Léger and committed by
Geert Uytterhoeven dc0f6731 d1273f54

+39
+39
arch/arm/boot/dts/r9a06g032.dtsi
··· 304 304 data-width = <8>; 305 305 }; 306 306 307 + eth_miic: eth-miic@44030000 { 308 + compatible = "renesas,r9a06g032-miic", "renesas,rzn1-miic"; 309 + #address-cells = <1>; 310 + #size-cells = <0>; 311 + reg = <0x44030000 0x10000>; 312 + clocks = <&sysctrl R9A06G032_CLK_MII_REF>, 313 + <&sysctrl R9A06G032_CLK_RGMII_REF>, 314 + <&sysctrl R9A06G032_CLK_RMII_REF>, 315 + <&sysctrl R9A06G032_HCLK_SWITCH_RG>; 316 + clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk"; 317 + power-domains = <&sysctrl>; 318 + status = "disabled"; 319 + 320 + mii_conv1: mii-conv@1 { 321 + reg = <1>; 322 + status = "disabled"; 323 + }; 324 + 325 + mii_conv2: mii-conv@2 { 326 + reg = <2>; 327 + status = "disabled"; 328 + }; 329 + 330 + mii_conv3: mii-conv@3 { 331 + reg = <3>; 332 + status = "disabled"; 333 + }; 334 + 335 + mii_conv4: mii-conv@4 { 336 + reg = <4>; 337 + status = "disabled"; 338 + }; 339 + 340 + mii_conv5: mii-conv@5 { 341 + reg = <5>; 342 + status = "disabled"; 343 + }; 344 + }; 345 + 307 346 gic: interrupt-controller@44101000 { 308 347 compatible = "arm,gic-400", "arm,cortex-a7-gic"; 309 348 interrupt-controller;