Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2026-03-07' of https://gitlab.freedesktop.org/drm/kernel
Pull drm fixes from Dave Airlie:
"Weekly fixes pull.
There is one mm fix in here for a HMM livelock triggered by the xe
driver tests. Otherwise it's a pretty wide range of fixes across the
board, ttm UAF regression fix, amdgpu fixes, nouveau doesn't crash my
laptop anymore fix, and a fair bit of misc.
Seems about right for rc3.
mm:
- mm: Fix a hmm_range_fault() livelock / starvation problem
pagemap:
- Revert "drm/pagemap: Disable device-to-device migration"
ttm:
- fix function return breaking reclaim
- fix build failure on PREEMPT_RT
- fix bo->resource UAF
dma-buf:
- include ioctl.h in uapi header
sched:
- fix kernel doc warning
amdgpu:
- LUT fixes
- VCN5 fix
- Dispclk fix
- SMU 13.x fix
- Fix race in VM acquire
- PSP 15.x fix
- UserQ fix
amdxdna:
- fix invalid payload for failed command
- fix NULL ptr dereference
- fix major fw version check
- avoid inconsistent fw state on error
i915/display:
- Fix for Lenovo T14 G7 display not refreshing
xe:
- Do not preempt fence signaling CS instructions
- Some leak and finalization fixes
- Workaround fix
nouveau:
- avoid runtime suspend oops when using dp aux
panthor:
- fix gem_sync argument ordering
solomon:
- fix incorrect display output
renesas:
- fix DSI divider programming
ethosu:
- fix job submit error clean-up refcount
- fix NPU_OP_ELEMENTWISE validation
- handle possible underflows in IFM size calcs"
* tag 'drm-fixes-2026-03-07' of https://gitlab.freedesktop.org/drm/kernel: (38 commits)
accel: ethosu: Handle possible underflow in IFM size calculations
accel: ethosu: Fix NPU_OP_ELEMENTWISE validation with scalar
accel: ethosu: Fix job submit error clean-up refcount underflows
accel/amdxdna: Split mailbox channel create function
drm/panthor: Correct the order of arguments passed to gem_sync
Revert "drm/syncobj: Fix handle <-> fd ioctls with dirty stack"
drm/ttm: Fix bo resource use-after-free
nouveau/dpcd: return EBUSY for aux xfer if the device is asleep
accel/amdxdna: Fix major version check on NPU1 platform
drm/amdgpu/userq: refcount userqueues to avoid any race conditions
drm/amdgpu/userq: Consolidate wait ioctl exit path
drm/amdgpu/psp: Use Indirect access address for GFX to PSP mailbox
drm/amdgpu: Fix use-after-free race in VM acquire
drm/amd/pm: remove invalid gpu_metrics.energy_accumulator on smu v13.0.x
drm/xe: Fix memory leak in xe_vm_madvise_ioctl
drm/xe/reg_sr: Fix leak on xa_store failure
drm/xe/xe2_hpg: Correct implementation of Wa_16025250150
drm/xe/gsc: Fix GSC proxy cleanup on early initialization failure
Revert "drm/pagemap: Disable device-to-device migration"
drm/i915/psr: Fix for Panel Replay X granularity DPCD register handling
...
+516
-291
+8
-15
drivers/accel/amdxdna/aie2_ctx.c
+8
-15
drivers/accel/amdxdna/aie2_ctx.c
···
186
186
cmd_abo = job->cmd_bo;
187
187
188
188
if (unlikely(job->job_timeout)) {
189
-
amdxdna_cmd_set_state(cmd_abo, ERT_CMD_STATE_TIMEOUT);
189
+
amdxdna_cmd_set_error(cmd_abo, job, 0, ERT_CMD_STATE_TIMEOUT);
190
190
ret = -EINVAL;
191
191
goto out;
192
192
}
193
193
194
194
if (unlikely(!data) || unlikely(size != sizeof(u32))) {
195
-
amdxdna_cmd_set_state(cmd_abo, ERT_CMD_STATE_ABORT);
195
+
amdxdna_cmd_set_error(cmd_abo, job, 0, ERT_CMD_STATE_ABORT);
196
196
ret = -EINVAL;
197
197
goto out;
198
198
}
···
202
202
if (status == AIE2_STATUS_SUCCESS)
203
203
amdxdna_cmd_set_state(cmd_abo, ERT_CMD_STATE_COMPLETED);
204
204
else
205
-
amdxdna_cmd_set_state(cmd_abo, ERT_CMD_STATE_ERROR);
205
+
amdxdna_cmd_set_error(cmd_abo, job, 0, ERT_CMD_STATE_ERROR);
206
206
207
207
out:
208
208
aie2_sched_notify(job);
···
244
244
cmd_abo = job->cmd_bo;
245
245
246
246
if (unlikely(job->job_timeout)) {
247
-
amdxdna_cmd_set_state(cmd_abo, ERT_CMD_STATE_TIMEOUT);
247
+
amdxdna_cmd_set_error(cmd_abo, job, 0, ERT_CMD_STATE_TIMEOUT);
248
248
ret = -EINVAL;
249
249
goto out;
250
250
}
251
251
252
252
if (unlikely(!data) || unlikely(size != sizeof(u32) * 3)) {
253
-
amdxdna_cmd_set_state(cmd_abo, ERT_CMD_STATE_ABORT);
253
+
amdxdna_cmd_set_error(cmd_abo, job, 0, ERT_CMD_STATE_ABORT);
254
254
ret = -EINVAL;
255
255
goto out;
256
256
}
···
270
270
fail_cmd_idx, fail_cmd_status);
271
271
272
272
if (fail_cmd_status == AIE2_STATUS_SUCCESS) {
273
-
amdxdna_cmd_set_state(cmd_abo, ERT_CMD_STATE_ABORT);
273
+
amdxdna_cmd_set_error(cmd_abo, job, fail_cmd_idx, ERT_CMD_STATE_ABORT);
274
274
ret = -EINVAL;
275
-
goto out;
275
+
} else {
276
+
amdxdna_cmd_set_error(cmd_abo, job, fail_cmd_idx, ERT_CMD_STATE_ERROR);
276
277
}
277
-
amdxdna_cmd_set_state(cmd_abo, ERT_CMD_STATE_ERROR);
278
278
279
-
if (amdxdna_cmd_get_op(cmd_abo) == ERT_CMD_CHAIN) {
280
-
struct amdxdna_cmd_chain *cc = amdxdna_cmd_get_payload(cmd_abo, NULL);
281
-
282
-
cc->error_index = fail_cmd_idx;
283
-
if (cc->error_index >= cc->command_count)
284
-
cc->error_index = 0;
285
-
}
286
279
out:
287
280
aie2_sched_notify(job);
288
281
return ret;
+28
-8
drivers/accel/amdxdna/aie2_message.c
+28
-8
drivers/accel/amdxdna/aie2_message.c
···
40
40
return -ENODEV;
41
41
42
42
ret = xdna_send_msg_wait(xdna, ndev->mgmt_chann, msg);
43
-
if (ret == -ETIME) {
44
-
xdna_mailbox_stop_channel(ndev->mgmt_chann);
45
-
xdna_mailbox_destroy_channel(ndev->mgmt_chann);
46
-
ndev->mgmt_chann = NULL;
47
-
}
43
+
if (ret == -ETIME)
44
+
aie2_destroy_mgmt_chann(ndev);
48
45
49
46
if (!ret && *hdl->status != AIE2_STATUS_SUCCESS) {
50
47
XDNA_ERR(xdna, "command opcode 0x%x failed, status 0x%x",
···
293
296
}
294
297
295
298
intr_reg = i2x.mb_head_ptr_reg + 4;
296
-
hwctx->priv->mbox_chann = xdna_mailbox_create_channel(ndev->mbox, &x2i, &i2x,
297
-
intr_reg, ret);
299
+
hwctx->priv->mbox_chann = xdna_mailbox_alloc_channel(ndev->mbox);
298
300
if (!hwctx->priv->mbox_chann) {
299
301
XDNA_ERR(xdna, "Not able to create channel");
300
302
ret = -EINVAL;
301
303
goto del_ctx_req;
304
+
}
305
+
306
+
ret = xdna_mailbox_start_channel(hwctx->priv->mbox_chann, &x2i, &i2x,
307
+
intr_reg, ret);
308
+
if (ret) {
309
+
XDNA_ERR(xdna, "Not able to create channel");
310
+
ret = -EINVAL;
311
+
goto free_channel;
302
312
}
303
313
ndev->hwctx_num++;
304
314
···
314
310
315
311
return 0;
316
312
313
+
free_channel:
314
+
xdna_mailbox_free_channel(hwctx->priv->mbox_chann);
317
315
del_ctx_req:
318
316
aie2_destroy_context_req(ndev, hwctx->fw_ctx_id);
319
317
return ret;
···
331
325
332
326
xdna_mailbox_stop_channel(hwctx->priv->mbox_chann);
333
327
ret = aie2_destroy_context_req(ndev, hwctx->fw_ctx_id);
334
-
xdna_mailbox_destroy_channel(hwctx->priv->mbox_chann);
328
+
xdna_mailbox_free_channel(hwctx->priv->mbox_chann);
335
329
XDNA_DBG(xdna, "Destroyed fw ctx %d", hwctx->fw_ctx_id);
336
330
hwctx->priv->mbox_chann = NULL;
337
331
hwctx->fw_ctx_id = -1;
···
918
912
ndev->exec_msg_ops = &npu_exec_message_ops;
919
913
else
920
914
ndev->exec_msg_ops = &legacy_exec_message_ops;
915
+
}
916
+
917
+
void aie2_destroy_mgmt_chann(struct amdxdna_dev_hdl *ndev)
918
+
{
919
+
struct amdxdna_dev *xdna = ndev->xdna;
920
+
921
+
drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock));
922
+
923
+
if (!ndev->mgmt_chann)
924
+
return;
925
+
926
+
xdna_mailbox_stop_channel(ndev->mgmt_chann);
927
+
xdna_mailbox_free_channel(ndev->mgmt_chann);
928
+
ndev->mgmt_chann = NULL;
921
929
}
922
930
923
931
static inline struct amdxdna_gem_obj *
+37
-29
drivers/accel/amdxdna/aie2_pci.c
+37
-29
drivers/accel/amdxdna/aie2_pci.c
···
330
330
331
331
aie2_runtime_cfg(ndev, AIE2_RT_CFG_CLK_GATING, NULL);
332
332
aie2_mgmt_fw_fini(ndev);
333
-
xdna_mailbox_stop_channel(ndev->mgmt_chann);
334
-
xdna_mailbox_destroy_channel(ndev->mgmt_chann);
335
-
ndev->mgmt_chann = NULL;
333
+
aie2_destroy_mgmt_chann(ndev);
336
334
drmm_kfree(&xdna->ddev, ndev->mbox);
337
335
ndev->mbox = NULL;
338
336
aie2_psp_stop(ndev->psp_hdl);
···
361
363
}
362
364
pci_set_master(pdev);
363
365
366
+
mbox_res.ringbuf_base = ndev->sram_base;
367
+
mbox_res.ringbuf_size = pci_resource_len(pdev, xdna->dev_info->sram_bar);
368
+
mbox_res.mbox_base = ndev->mbox_base;
369
+
mbox_res.mbox_size = MBOX_SIZE(ndev);
370
+
mbox_res.name = "xdna_mailbox";
371
+
ndev->mbox = xdnam_mailbox_create(&xdna->ddev, &mbox_res);
372
+
if (!ndev->mbox) {
373
+
XDNA_ERR(xdna, "failed to create mailbox device");
374
+
ret = -ENODEV;
375
+
goto disable_dev;
376
+
}
377
+
378
+
ndev->mgmt_chann = xdna_mailbox_alloc_channel(ndev->mbox);
379
+
if (!ndev->mgmt_chann) {
380
+
XDNA_ERR(xdna, "failed to alloc channel");
381
+
ret = -ENODEV;
382
+
goto disable_dev;
383
+
}
384
+
364
385
ret = aie2_smu_init(ndev);
365
386
if (ret) {
366
387
XDNA_ERR(xdna, "failed to init smu, ret %d", ret);
367
-
goto disable_dev;
388
+
goto free_channel;
368
389
}
369
390
370
391
ret = aie2_psp_start(ndev->psp_hdl);
···
398
381
goto stop_psp;
399
382
}
400
383
401
-
mbox_res.ringbuf_base = ndev->sram_base;
402
-
mbox_res.ringbuf_size = pci_resource_len(pdev, xdna->dev_info->sram_bar);
403
-
mbox_res.mbox_base = ndev->mbox_base;
404
-
mbox_res.mbox_size = MBOX_SIZE(ndev);
405
-
mbox_res.name = "xdna_mailbox";
406
-
ndev->mbox = xdnam_mailbox_create(&xdna->ddev, &mbox_res);
407
-
if (!ndev->mbox) {
408
-
XDNA_ERR(xdna, "failed to create mailbox device");
409
-
ret = -ENODEV;
410
-
goto stop_psp;
411
-
}
412
-
413
384
mgmt_mb_irq = pci_irq_vector(pdev, ndev->mgmt_chan_idx);
414
385
if (mgmt_mb_irq < 0) {
415
386
ret = mgmt_mb_irq;
···
406
401
}
407
402
408
403
xdna_mailbox_intr_reg = ndev->mgmt_i2x.mb_head_ptr_reg + 4;
409
-
ndev->mgmt_chann = xdna_mailbox_create_channel(ndev->mbox,
410
-
&ndev->mgmt_x2i,
411
-
&ndev->mgmt_i2x,
412
-
xdna_mailbox_intr_reg,
413
-
mgmt_mb_irq);
414
-
if (!ndev->mgmt_chann) {
415
-
XDNA_ERR(xdna, "failed to create management mailbox channel");
404
+
ret = xdna_mailbox_start_channel(ndev->mgmt_chann,
405
+
&ndev->mgmt_x2i,
406
+
&ndev->mgmt_i2x,
407
+
xdna_mailbox_intr_reg,
408
+
mgmt_mb_irq);
409
+
if (ret) {
410
+
XDNA_ERR(xdna, "failed to start management mailbox channel");
416
411
ret = -EINVAL;
417
412
goto stop_psp;
418
413
}
···
420
415
ret = aie2_mgmt_fw_init(ndev);
421
416
if (ret) {
422
417
XDNA_ERR(xdna, "initial mgmt firmware failed, ret %d", ret);
423
-
goto destroy_mgmt_chann;
418
+
goto stop_fw;
424
419
}
425
420
426
421
ret = aie2_pm_init(ndev);
427
422
if (ret) {
428
423
XDNA_ERR(xdna, "failed to init pm, ret %d", ret);
429
-
goto destroy_mgmt_chann;
424
+
goto stop_fw;
430
425
}
431
426
432
427
ret = aie2_mgmt_fw_query(ndev);
433
428
if (ret) {
434
429
XDNA_ERR(xdna, "failed to query fw, ret %d", ret);
435
-
goto destroy_mgmt_chann;
430
+
goto stop_fw;
436
431
}
437
432
438
433
ret = aie2_error_async_events_alloc(ndev);
439
434
if (ret) {
440
435
XDNA_ERR(xdna, "Allocate async events failed, ret %d", ret);
441
-
goto destroy_mgmt_chann;
436
+
goto stop_fw;
442
437
}
443
438
444
439
ndev->dev_status = AIE2_DEV_START;
445
440
446
441
return 0;
447
442
448
-
destroy_mgmt_chann:
443
+
stop_fw:
444
+
aie2_suspend_fw(ndev);
449
445
xdna_mailbox_stop_channel(ndev->mgmt_chann);
450
-
xdna_mailbox_destroy_channel(ndev->mgmt_chann);
451
446
stop_psp:
452
447
aie2_psp_stop(ndev->psp_hdl);
453
448
fini_smu:
454
449
aie2_smu_fini(ndev);
450
+
free_channel:
451
+
xdna_mailbox_free_channel(ndev->mgmt_chann);
452
+
ndev->mgmt_chann = NULL;
455
453
disable_dev:
456
454
pci_disable_device(pdev);
457
455
+1
drivers/accel/amdxdna/aie2_pci.h
+1
drivers/accel/amdxdna/aie2_pci.h
···
303
303
304
304
/* aie2_message.c */
305
305
void aie2_msg_init(struct amdxdna_dev_hdl *ndev);
306
+
void aie2_destroy_mgmt_chann(struct amdxdna_dev_hdl *ndev);
306
307
int aie2_suspend_fw(struct amdxdna_dev_hdl *ndev);
307
308
int aie2_resume_fw(struct amdxdna_dev_hdl *ndev);
308
309
int aie2_set_runtime_cfg(struct amdxdna_dev_hdl *ndev, u32 type, u64 value);
+27
drivers/accel/amdxdna/amdxdna_ctx.c
+27
drivers/accel/amdxdna/amdxdna_ctx.c
···
135
135
return INVALID_CU_IDX;
136
136
}
137
137
138
+
int amdxdna_cmd_set_error(struct amdxdna_gem_obj *abo,
139
+
struct amdxdna_sched_job *job, u32 cmd_idx,
140
+
enum ert_cmd_state error_state)
141
+
{
142
+
struct amdxdna_client *client = job->hwctx->client;
143
+
struct amdxdna_cmd *cmd = abo->mem.kva;
144
+
struct amdxdna_cmd_chain *cc = NULL;
145
+
146
+
cmd->header &= ~AMDXDNA_CMD_STATE;
147
+
cmd->header |= FIELD_PREP(AMDXDNA_CMD_STATE, error_state);
148
+
149
+
if (amdxdna_cmd_get_op(abo) == ERT_CMD_CHAIN) {
150
+
cc = amdxdna_cmd_get_payload(abo, NULL);
151
+
cc->error_index = (cmd_idx < cc->command_count) ? cmd_idx : 0;
152
+
abo = amdxdna_gem_get_obj(client, cc->data[0], AMDXDNA_BO_CMD);
153
+
if (!abo)
154
+
return -EINVAL;
155
+
cmd = abo->mem.kva;
156
+
}
157
+
158
+
memset(cmd->data, 0xff, abo->mem.size - sizeof(*cmd));
159
+
if (cc)
160
+
amdxdna_gem_put_obj(abo);
161
+
162
+
return 0;
163
+
}
164
+
138
165
/*
139
166
* This should be called in close() and remove(). DO NOT call in other syscalls.
140
167
* This guarantee that when hwctx and resources will be released, if user
+3
drivers/accel/amdxdna/amdxdna_ctx.h
+3
drivers/accel/amdxdna/amdxdna_ctx.h
···
167
167
168
168
void *amdxdna_cmd_get_payload(struct amdxdna_gem_obj *abo, u32 *size);
169
169
u32 amdxdna_cmd_get_cu_idx(struct amdxdna_gem_obj *abo);
170
+
int amdxdna_cmd_set_error(struct amdxdna_gem_obj *abo,
171
+
struct amdxdna_sched_job *job, u32 cmd_idx,
172
+
enum ert_cmd_state error_state);
170
173
171
174
void amdxdna_sched_job_cleanup(struct amdxdna_sched_job *job);
172
175
void amdxdna_hwctx_remove_all(struct amdxdna_client *client);
+49
-50
drivers/accel/amdxdna/amdxdna_mailbox.c
+49
-50
drivers/accel/amdxdna/amdxdna_mailbox.c
···
460
460
return ret;
461
461
}
462
462
463
-
struct mailbox_channel *
464
-
xdna_mailbox_create_channel(struct mailbox *mb,
465
-
const struct xdna_mailbox_chann_res *x2i,
466
-
const struct xdna_mailbox_chann_res *i2x,
467
-
u32 iohub_int_addr,
468
-
int mb_irq)
463
+
struct mailbox_channel *xdna_mailbox_alloc_channel(struct mailbox *mb)
469
464
{
470
465
struct mailbox_channel *mb_chann;
471
-
int ret;
472
-
473
-
if (!is_power_of_2(x2i->rb_size) || !is_power_of_2(i2x->rb_size)) {
474
-
pr_err("Ring buf size must be power of 2");
475
-
return NULL;
476
-
}
477
466
478
467
mb_chann = kzalloc_obj(*mb_chann);
479
468
if (!mb_chann)
480
469
return NULL;
481
470
471
+
INIT_WORK(&mb_chann->rx_work, mailbox_rx_worker);
472
+
mb_chann->work_q = create_singlethread_workqueue(MAILBOX_NAME);
473
+
if (!mb_chann->work_q) {
474
+
MB_ERR(mb_chann, "Create workqueue failed");
475
+
goto free_chann;
476
+
}
482
477
mb_chann->mb = mb;
478
+
479
+
return mb_chann;
480
+
481
+
free_chann:
482
+
kfree(mb_chann);
483
+
return NULL;
484
+
}
485
+
486
+
void xdna_mailbox_free_channel(struct mailbox_channel *mb_chann)
487
+
{
488
+
destroy_workqueue(mb_chann->work_q);
489
+
kfree(mb_chann);
490
+
}
491
+
492
+
int
493
+
xdna_mailbox_start_channel(struct mailbox_channel *mb_chann,
494
+
const struct xdna_mailbox_chann_res *x2i,
495
+
const struct xdna_mailbox_chann_res *i2x,
496
+
u32 iohub_int_addr,
497
+
int mb_irq)
498
+
{
499
+
int ret;
500
+
501
+
if (!is_power_of_2(x2i->rb_size) || !is_power_of_2(i2x->rb_size)) {
502
+
pr_err("Ring buf size must be power of 2");
503
+
return -EINVAL;
504
+
}
505
+
483
506
mb_chann->msix_irq = mb_irq;
484
507
mb_chann->iohub_int_addr = iohub_int_addr;
485
508
memcpy(&mb_chann->res[CHAN_RES_X2I], x2i, sizeof(*x2i));
···
512
489
mb_chann->x2i_tail = mailbox_get_tailptr(mb_chann, CHAN_RES_X2I);
513
490
mb_chann->i2x_head = mailbox_get_headptr(mb_chann, CHAN_RES_I2X);
514
491
515
-
INIT_WORK(&mb_chann->rx_work, mailbox_rx_worker);
516
-
mb_chann->work_q = create_singlethread_workqueue(MAILBOX_NAME);
517
-
if (!mb_chann->work_q) {
518
-
MB_ERR(mb_chann, "Create workqueue failed");
519
-
goto free_and_out;
520
-
}
521
-
522
492
/* Everything look good. Time to enable irq handler */
523
493
ret = request_irq(mb_irq, mailbox_irq_handler, 0, MAILBOX_NAME, mb_chann);
524
494
if (ret) {
525
495
MB_ERR(mb_chann, "Failed to request irq %d ret %d", mb_irq, ret);
526
-
goto destroy_wq;
496
+
return ret;
527
497
}
528
498
529
499
mb_chann->bad_state = false;
530
500
mailbox_reg_write(mb_chann, mb_chann->iohub_int_addr, 0);
531
501
532
-
MB_DBG(mb_chann, "Mailbox channel created (irq: %d)", mb_chann->msix_irq);
533
-
return mb_chann;
534
-
535
-
destroy_wq:
536
-
destroy_workqueue(mb_chann->work_q);
537
-
free_and_out:
538
-
kfree(mb_chann);
539
-
return NULL;
540
-
}
541
-
542
-
int xdna_mailbox_destroy_channel(struct mailbox_channel *mb_chann)
543
-
{
544
-
struct mailbox_msg *mb_msg;
545
-
unsigned long msg_id;
546
-
547
-
MB_DBG(mb_chann, "IRQ disabled and RX work cancelled");
548
-
free_irq(mb_chann->msix_irq, mb_chann);
549
-
destroy_workqueue(mb_chann->work_q);
550
-
/* We can clean up and release resources */
551
-
552
-
xa_for_each(&mb_chann->chan_xa, msg_id, mb_msg)
553
-
mailbox_release_msg(mb_chann, mb_msg);
554
-
555
-
xa_destroy(&mb_chann->chan_xa);
556
-
557
-
MB_DBG(mb_chann, "Mailbox channel destroyed, irq: %d", mb_chann->msix_irq);
558
-
kfree(mb_chann);
502
+
MB_DBG(mb_chann, "Mailbox channel started (irq: %d)", mb_chann->msix_irq);
559
503
return 0;
560
504
}
561
505
562
506
void xdna_mailbox_stop_channel(struct mailbox_channel *mb_chann)
563
507
{
508
+
struct mailbox_msg *mb_msg;
509
+
unsigned long msg_id;
510
+
564
511
/* Disable an irq and wait. This might sleep. */
565
-
disable_irq(mb_chann->msix_irq);
512
+
free_irq(mb_chann->msix_irq, mb_chann);
566
513
567
514
/* Cancel RX work and wait for it to finish */
568
-
cancel_work_sync(&mb_chann->rx_work);
569
-
MB_DBG(mb_chann, "IRQ disabled and RX work cancelled");
515
+
drain_workqueue(mb_chann->work_q);
516
+
517
+
/* We can clean up and release resources */
518
+
xa_for_each(&mb_chann->chan_xa, msg_id, mb_msg)
519
+
mailbox_release_msg(mb_chann, mb_msg);
520
+
xa_destroy(&mb_chann->chan_xa);
521
+
522
+
MB_DBG(mb_chann, "Mailbox channel stopped, irq: %d", mb_chann->msix_irq);
570
523
}
571
524
572
525
struct mailbox *xdnam_mailbox_create(struct drm_device *ddev,
+17
-14
drivers/accel/amdxdna/amdxdna_mailbox.h
+17
-14
drivers/accel/amdxdna/amdxdna_mailbox.h
···
74
74
const struct xdna_mailbox_res *res);
75
75
76
76
/*
77
-
* xdna_mailbox_create_channel() -- Create a mailbox channel instance
77
+
* xdna_mailbox_alloc_channel() -- alloc a mailbox channel
78
78
*
79
-
* @mailbox: the handle return from xdna_mailbox_create()
79
+
* @mb: mailbox handle
80
+
*/
81
+
struct mailbox_channel *xdna_mailbox_alloc_channel(struct mailbox *mb);
82
+
83
+
/*
84
+
* xdna_mailbox_start_channel() -- start a mailbox channel instance
85
+
*
86
+
* @mb_chann: the handle return from xdna_mailbox_alloc_channel()
80
87
* @x2i: host to firmware mailbox resources
81
88
* @i2x: firmware to host mailbox resources
82
89
* @xdna_mailbox_intr_reg: register addr of MSI-X interrupt
···
91
84
*
92
85
* Return: If success, return a handle of mailbox channel. Otherwise, return NULL.
93
86
*/
94
-
struct mailbox_channel *
95
-
xdna_mailbox_create_channel(struct mailbox *mailbox,
96
-
const struct xdna_mailbox_chann_res *x2i,
97
-
const struct xdna_mailbox_chann_res *i2x,
98
-
u32 xdna_mailbox_intr_reg,
99
-
int mb_irq);
87
+
int
88
+
xdna_mailbox_start_channel(struct mailbox_channel *mb_chann,
89
+
const struct xdna_mailbox_chann_res *x2i,
90
+
const struct xdna_mailbox_chann_res *i2x,
91
+
u32 xdna_mailbox_intr_reg,
92
+
int mb_irq);
100
93
101
94
/*
102
-
* xdna_mailbox_destroy_channel() -- destroy mailbox channel
95
+
* xdna_mailbox_free_channel() -- free mailbox channel
103
96
*
104
97
* @mailbox_chann: the handle return from xdna_mailbox_create_channel()
105
-
*
106
-
* Return: if success, return 0. otherwise return error code
107
98
*/
108
-
int xdna_mailbox_destroy_channel(struct mailbox_channel *mailbox_chann);
99
+
void xdna_mailbox_free_channel(struct mailbox_channel *mailbox_chann);
109
100
110
101
/*
111
102
* xdna_mailbox_stop_channel() -- stop mailbox channel
112
103
*
113
104
* @mailbox_chann: the handle return from xdna_mailbox_create_channel()
114
-
*
115
-
* Return: if success, return 0. otherwise return error code
116
105
*/
117
106
void xdna_mailbox_stop_channel(struct mailbox_channel *mailbox_chann);
118
107
+1
-1
drivers/accel/amdxdna/npu1_regs.c
+1
-1
drivers/accel/amdxdna/npu1_regs.c
+9
-3
drivers/accel/ethosu/ethosu_gem.c
+9
-3
drivers/accel/ethosu/ethosu_gem.c
···
245
245
((st->ifm.stride_kernel >> 1) & 0x1) + 1;
246
246
u32 stride_x = ((st->ifm.stride_kernel >> 5) & 0x2) +
247
247
(st->ifm.stride_kernel & 0x1) + 1;
248
-
u32 ifm_height = st->ofm.height[2] * stride_y +
248
+
s32 ifm_height = st->ofm.height[2] * stride_y +
249
249
st->ifm.height[2] - (st->ifm.pad_top + st->ifm.pad_bottom);
250
-
u32 ifm_width = st->ofm.width * stride_x +
250
+
s32 ifm_width = st->ofm.width * stride_x +
251
251
st->ifm.width - (st->ifm.pad_left + st->ifm.pad_right);
252
+
253
+
if (ifm_height < 0 || ifm_width < 0)
254
+
return -EINVAL;
252
255
253
256
len = feat_matrix_length(info, &st->ifm, ifm_width,
254
257
ifm_height, st->ifm.depth);
···
420
417
return ret;
421
418
break;
422
419
case NPU_OP_ELEMENTWISE:
423
-
use_ifm2 = !((st.ifm2.broadcast == 8) || (param == 5) ||
420
+
use_scale = ethosu_is_u65(edev) ?
421
+
(st.ifm2.broadcast & 0x80) :
422
+
(st.ifm2.broadcast == 8);
423
+
use_ifm2 = !(use_scale || (param == 5) ||
424
424
(param == 6) || (param == 7) || (param == 0x24));
425
425
use_ifm = st.ifm.broadcast != 8;
426
426
ret = calc_sizes_elemwise(ddev, info, cmd, &st, use_ifm, use_ifm2);
+19
-9
drivers/accel/ethosu/ethosu_job.c
+19
-9
drivers/accel/ethosu/ethosu_job.c
···
143
143
return ret;
144
144
}
145
145
146
-
static void ethosu_job_cleanup(struct kref *ref)
146
+
static void ethosu_job_err_cleanup(struct ethosu_job *job)
147
147
{
148
-
struct ethosu_job *job = container_of(ref, struct ethosu_job,
149
-
refcount);
150
148
unsigned int i;
151
-
152
-
pm_runtime_put_autosuspend(job->dev->base.dev);
153
-
154
-
dma_fence_put(job->done_fence);
155
-
dma_fence_put(job->inference_done_fence);
156
149
157
150
for (i = 0; i < job->region_cnt; i++)
158
151
drm_gem_object_put(job->region_bo[i]);
···
153
160
drm_gem_object_put(job->cmd_bo);
154
161
155
162
kfree(job);
163
+
}
164
+
165
+
static void ethosu_job_cleanup(struct kref *ref)
166
+
{
167
+
struct ethosu_job *job = container_of(ref, struct ethosu_job,
168
+
refcount);
169
+
170
+
pm_runtime_put_autosuspend(job->dev->base.dev);
171
+
172
+
dma_fence_put(job->done_fence);
173
+
dma_fence_put(job->inference_done_fence);
174
+
175
+
ethosu_job_err_cleanup(job);
156
176
}
157
177
158
178
static void ethosu_job_put(struct ethosu_job *job)
···
460
454
}
461
455
}
462
456
ret = ethosu_job_push(ejob);
457
+
if (!ret) {
458
+
ethosu_job_put(ejob);
459
+
return 0;
460
+
}
463
461
464
462
out_cleanup_job:
465
463
if (ret)
466
464
drm_sched_job_cleanup(&ejob->base);
467
465
out_put_job:
468
-
ethosu_job_put(ejob);
466
+
ethosu_job_err_cleanup(ejob);
469
467
470
468
return ret;
471
469
}
+5
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+5
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
···
1439
1439
*process_info = info;
1440
1440
}
1441
1441
1442
-
vm->process_info = *process_info;
1442
+
if (cmpxchg(&vm->process_info, NULL, *process_info) != NULL) {
1443
+
ret = -EINVAL;
1444
+
goto already_acquired;
1445
+
}
1443
1446
1444
1447
/* Validate page directory and attach eviction fence */
1445
1448
ret = amdgpu_bo_reserve(vm->root.bo, true);
···
1482
1479
amdgpu_bo_unreserve(vm->root.bo);
1483
1480
reserve_pd_fail:
1484
1481
vm->process_info = NULL;
1482
+
already_acquired:
1485
1483
if (info) {
1486
1484
dma_fence_put(&info->eviction_fence->base);
1487
1485
*process_info = NULL;
+81
-35
drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
+81
-35
drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
···
446
446
return ret;
447
447
}
448
448
449
-
static void amdgpu_userq_cleanup(struct amdgpu_usermode_queue *queue,
450
-
int queue_id)
449
+
static void amdgpu_userq_cleanup(struct amdgpu_usermode_queue *queue)
451
450
{
452
451
struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr;
453
452
struct amdgpu_device *adev = uq_mgr->adev;
···
460
461
uq_funcs->mqd_destroy(queue);
461
462
amdgpu_userq_fence_driver_free(queue);
462
463
/* Use interrupt-safe locking since IRQ handlers may access these XArrays */
463
-
xa_erase_irq(&uq_mgr->userq_xa, (unsigned long)queue_id);
464
464
xa_erase_irq(&adev->userq_doorbell_xa, queue->doorbell_index);
465
465
queue->userq_mgr = NULL;
466
466
list_del(&queue->userq_va_list);
467
467
kfree(queue);
468
468
469
469
up_read(&adev->reset_domain->sem);
470
-
}
471
-
472
-
static struct amdgpu_usermode_queue *
473
-
amdgpu_userq_find(struct amdgpu_userq_mgr *uq_mgr, int qid)
474
-
{
475
-
return xa_load(&uq_mgr->userq_xa, qid);
476
470
}
477
471
478
472
void
···
617
625
}
618
626
619
627
static int
620
-
amdgpu_userq_destroy(struct drm_file *filp, int queue_id)
628
+
amdgpu_userq_destroy(struct amdgpu_userq_mgr *uq_mgr, struct amdgpu_usermode_queue *queue)
621
629
{
622
-
struct amdgpu_fpriv *fpriv = filp->driver_priv;
623
-
struct amdgpu_userq_mgr *uq_mgr = &fpriv->userq_mgr;
624
630
struct amdgpu_device *adev = uq_mgr->adev;
625
-
struct amdgpu_usermode_queue *queue;
626
631
int r = 0;
627
632
628
633
cancel_delayed_work_sync(&uq_mgr->resume_work);
629
634
mutex_lock(&uq_mgr->userq_mutex);
630
-
queue = amdgpu_userq_find(uq_mgr, queue_id);
631
-
if (!queue) {
632
-
drm_dbg_driver(adev_to_drm(uq_mgr->adev), "Invalid queue id to destroy\n");
633
-
mutex_unlock(&uq_mgr->userq_mutex);
634
-
return -EINVAL;
635
-
}
636
635
amdgpu_userq_wait_for_last_fence(queue);
637
636
/* Cancel any pending hang detection work and cleanup */
638
637
if (queue->hang_detect_fence) {
···
655
672
drm_warn(adev_to_drm(uq_mgr->adev), "trying to destroy a HW mapping userq\n");
656
673
queue->state = AMDGPU_USERQ_STATE_HUNG;
657
674
}
658
-
amdgpu_userq_cleanup(queue, queue_id);
675
+
amdgpu_userq_cleanup(queue);
659
676
mutex_unlock(&uq_mgr->userq_mutex);
660
677
661
678
pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
662
679
663
680
return r;
681
+
}
682
+
683
+
static void amdgpu_userq_kref_destroy(struct kref *kref)
684
+
{
685
+
int r;
686
+
struct amdgpu_usermode_queue *queue =
687
+
container_of(kref, struct amdgpu_usermode_queue, refcount);
688
+
struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr;
689
+
690
+
r = amdgpu_userq_destroy(uq_mgr, queue);
691
+
if (r)
692
+
drm_file_err(uq_mgr->file, "Failed to destroy usermode queue %d\n", r);
693
+
}
694
+
695
+
struct amdgpu_usermode_queue *amdgpu_userq_get(struct amdgpu_userq_mgr *uq_mgr, u32 qid)
696
+
{
697
+
struct amdgpu_usermode_queue *queue;
698
+
699
+
xa_lock(&uq_mgr->userq_xa);
700
+
queue = xa_load(&uq_mgr->userq_xa, qid);
701
+
if (queue)
702
+
kref_get(&queue->refcount);
703
+
xa_unlock(&uq_mgr->userq_xa);
704
+
705
+
return queue;
706
+
}
707
+
708
+
void amdgpu_userq_put(struct amdgpu_usermode_queue *queue)
709
+
{
710
+
if (queue)
711
+
kref_put(&queue->refcount, amdgpu_userq_kref_destroy);
664
712
}
665
713
666
714
static int amdgpu_userq_priority_permit(struct drm_file *filp,
···
848
834
goto unlock;
849
835
}
850
836
837
+
/* drop this refcount during queue destroy */
838
+
kref_init(&queue->refcount);
839
+
851
840
/* Wait for mode-1 reset to complete */
852
841
down_read(&adev->reset_domain->sem);
853
842
r = xa_err(xa_store_irq(&adev->userq_doorbell_xa, index, queue, GFP_KERNEL));
···
1002
985
struct drm_file *filp)
1003
986
{
1004
987
union drm_amdgpu_userq *args = data;
1005
-
int r;
988
+
struct amdgpu_fpriv *fpriv = filp->driver_priv;
989
+
struct amdgpu_usermode_queue *queue;
990
+
int r = 0;
1006
991
1007
992
if (!amdgpu_userq_enabled(dev))
1008
993
return -ENOTSUPP;
···
1019
1000
drm_file_err(filp, "Failed to create usermode queue\n");
1020
1001
break;
1021
1002
1022
-
case AMDGPU_USERQ_OP_FREE:
1023
-
r = amdgpu_userq_destroy(filp, args->in.queue_id);
1024
-
if (r)
1025
-
drm_file_err(filp, "Failed to destroy usermode queue\n");
1003
+
case AMDGPU_USERQ_OP_FREE: {
1004
+
xa_lock(&fpriv->userq_mgr.userq_xa);
1005
+
queue = __xa_erase(&fpriv->userq_mgr.userq_xa, args->in.queue_id);
1006
+
xa_unlock(&fpriv->userq_mgr.userq_xa);
1007
+
if (!queue)
1008
+
return -ENOENT;
1009
+
1010
+
amdgpu_userq_put(queue);
1026
1011
break;
1012
+
}
1027
1013
1028
1014
default:
1029
1015
drm_dbg_driver(dev, "Invalid user queue op specified: %d\n", args->in.op);
···
1047
1023
1048
1024
/* Resume all the queues for this process */
1049
1025
xa_for_each(&uq_mgr->userq_xa, queue_id, queue) {
1026
+
queue = amdgpu_userq_get(uq_mgr, queue_id);
1027
+
if (!queue)
1028
+
continue;
1029
+
1050
1030
if (!amdgpu_userq_buffer_vas_mapped(queue)) {
1051
1031
drm_file_err(uq_mgr->file,
1052
1032
"trying restore queue without va mapping\n");
1053
1033
queue->state = AMDGPU_USERQ_STATE_INVALID_VA;
1034
+
amdgpu_userq_put(queue);
1054
1035
continue;
1055
1036
}
1056
1037
1057
1038
r = amdgpu_userq_restore_helper(queue);
1058
1039
if (r)
1059
1040
ret = r;
1041
+
1042
+
amdgpu_userq_put(queue);
1060
1043
}
1061
1044
1062
1045
if (ret)
···
1297
1266
amdgpu_userq_detect_and_reset_queues(uq_mgr);
1298
1267
/* Try to unmap all the queues in this process ctx */
1299
1268
xa_for_each(&uq_mgr->userq_xa, queue_id, queue) {
1269
+
queue = amdgpu_userq_get(uq_mgr, queue_id);
1270
+
if (!queue)
1271
+
continue;
1300
1272
r = amdgpu_userq_preempt_helper(queue);
1301
1273
if (r)
1302
1274
ret = r;
1275
+
amdgpu_userq_put(queue);
1303
1276
}
1304
1277
1305
1278
if (ret)
···
1336
1301
int ret;
1337
1302
1338
1303
xa_for_each(&uq_mgr->userq_xa, queue_id, queue) {
1304
+
queue = amdgpu_userq_get(uq_mgr, queue_id);
1305
+
if (!queue)
1306
+
continue;
1307
+
1339
1308
struct dma_fence *f = queue->last_fence;
1340
1309
1341
-
if (!f || dma_fence_is_signaled(f))
1310
+
if (!f || dma_fence_is_signaled(f)) {
1311
+
amdgpu_userq_put(queue);
1342
1312
continue;
1313
+
}
1343
1314
ret = dma_fence_wait_timeout(f, true, msecs_to_jiffies(100));
1344
1315
if (ret <= 0) {
1345
1316
drm_file_err(uq_mgr->file, "Timed out waiting for fence=%llu:%llu\n",
1346
1317
f->context, f->seqno);
1318
+
amdgpu_userq_put(queue);
1347
1319
return -ETIMEDOUT;
1348
1320
}
1321
+
amdgpu_userq_put(queue);
1349
1322
}
1350
1323
1351
1324
return 0;
···
1404
1361
void amdgpu_userq_mgr_fini(struct amdgpu_userq_mgr *userq_mgr)
1405
1362
{
1406
1363
struct amdgpu_usermode_queue *queue;
1407
-
unsigned long queue_id;
1364
+
unsigned long queue_id = 0;
1408
1365
1409
-
cancel_delayed_work_sync(&userq_mgr->resume_work);
1366
+
for (;;) {
1367
+
xa_lock(&userq_mgr->userq_xa);
1368
+
queue = xa_find(&userq_mgr->userq_xa, &queue_id, ULONG_MAX,
1369
+
XA_PRESENT);
1370
+
if (queue)
1371
+
__xa_erase(&userq_mgr->userq_xa, queue_id);
1372
+
xa_unlock(&userq_mgr->userq_xa);
1410
1373
1411
-
mutex_lock(&userq_mgr->userq_mutex);
1412
-
amdgpu_userq_detect_and_reset_queues(userq_mgr);
1413
-
xa_for_each(&userq_mgr->userq_xa, queue_id, queue) {
1414
-
amdgpu_userq_wait_for_last_fence(queue);
1415
-
amdgpu_userq_unmap_helper(queue);
1416
-
amdgpu_userq_cleanup(queue, queue_id);
1374
+
if (!queue)
1375
+
break;
1376
+
1377
+
amdgpu_userq_put(queue);
1417
1378
}
1418
1379
1419
1380
xa_destroy(&userq_mgr->userq_xa);
1420
-
mutex_unlock(&userq_mgr->userq_mutex);
1421
1381
mutex_destroy(&userq_mgr->userq_mutex);
1422
1382
}
1423
1383
+4
drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h
+4
drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h
···
74
74
struct dentry *debugfs_queue;
75
75
struct delayed_work hang_detect_work;
76
76
struct dma_fence *hang_detect_fence;
77
+
struct kref refcount;
77
78
78
79
struct list_head userq_va_list;
79
80
};
···
112
111
uint32_t doorbell_offset;
113
112
struct amdgpu_userq_obj *db_obj;
114
113
};
114
+
115
+
struct amdgpu_usermode_queue *amdgpu_userq_get(struct amdgpu_userq_mgr *uq_mgr, u32 qid);
116
+
void amdgpu_userq_put(struct amdgpu_usermode_queue *queue);
115
117
116
118
int amdgpu_userq_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
117
119
+15
-27
drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c
+15
-27
drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c
···
466
466
struct drm_amdgpu_userq_signal *args = data;
467
467
struct drm_gem_object **gobj_write = NULL;
468
468
struct drm_gem_object **gobj_read = NULL;
469
-
struct amdgpu_usermode_queue *queue;
469
+
struct amdgpu_usermode_queue *queue = NULL;
470
470
struct amdgpu_userq_fence *userq_fence;
471
471
struct drm_syncobj **syncobj = NULL;
472
472
u32 *bo_handles_write, num_write_bo_handles;
···
553
553
}
554
554
555
555
/* Retrieve the user queue */
556
-
queue = xa_load(&userq_mgr->userq_xa, args->queue_id);
556
+
queue = amdgpu_userq_get(userq_mgr, args->queue_id);
557
557
if (!queue) {
558
558
r = -ENOENT;
559
559
goto put_gobj_write;
···
648
648
free_syncobj_handles:
649
649
kfree(syncobj_handles);
650
650
651
+
if (queue)
652
+
amdgpu_userq_put(queue);
653
+
651
654
return r;
652
655
}
653
656
···
663
660
struct drm_amdgpu_userq_wait *wait_info = data;
664
661
struct amdgpu_fpriv *fpriv = filp->driver_priv;
665
662
struct amdgpu_userq_mgr *userq_mgr = &fpriv->userq_mgr;
666
-
struct amdgpu_usermode_queue *waitq;
663
+
struct amdgpu_usermode_queue *waitq = NULL;
667
664
struct drm_gem_object **gobj_write;
668
665
struct drm_gem_object **gobj_read;
669
666
struct dma_fence **fences = NULL;
···
929
926
*/
930
927
num_fences = dma_fence_dedup_array(fences, num_fences);
931
928
932
-
waitq = xa_load(&userq_mgr->userq_xa, wait_info->waitq_id);
929
+
waitq = amdgpu_userq_get(userq_mgr, wait_info->waitq_id);
933
930
if (!waitq) {
934
931
r = -EINVAL;
935
932
goto free_fences;
···
986
983
r = -EFAULT;
987
984
goto free_fences;
988
985
}
989
-
990
-
kfree(fences);
991
-
kfree(fence_info);
992
986
}
993
987
994
-
drm_exec_fini(&exec);
995
-
for (i = 0; i < num_read_bo_handles; i++)
996
-
drm_gem_object_put(gobj_read[i]);
997
-
kfree(gobj_read);
998
-
999
-
for (i = 0; i < num_write_bo_handles; i++)
1000
-
drm_gem_object_put(gobj_write[i]);
1001
-
kfree(gobj_write);
1002
-
1003
-
kfree(timeline_points);
1004
-
kfree(timeline_handles);
1005
-
kfree(syncobj_handles);
1006
-
kfree(bo_handles_write);
1007
-
kfree(bo_handles_read);
1008
-
1009
-
return 0;
1010
-
1011
988
free_fences:
1012
-
while (num_fences-- > 0)
1013
-
dma_fence_put(fences[num_fences]);
1014
-
kfree(fences);
989
+
if (fences) {
990
+
while (num_fences-- > 0)
991
+
dma_fence_put(fences[num_fences]);
992
+
kfree(fences);
993
+
}
1015
994
free_fence_info:
1016
995
kfree(fence_info);
1017
996
exec_fini:
···
1016
1031
kfree(bo_handles_write);
1017
1032
free_bo_handles_read:
1018
1033
kfree(bo_handles_read);
1034
+
1035
+
if (waitq)
1036
+
amdgpu_userq_put(waitq);
1019
1037
1020
1038
return r;
1021
1039
}
+10
-10
drivers/gpu/drm/amd/amdgpu/psp_v15_0.c
+10
-10
drivers/gpu/drm/amd/amdgpu/psp_v15_0.c
···
69
69
0x80000000, 0x80000000, false);
70
70
} else {
71
71
/* Write the ring destroy command*/
72
-
WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64,
72
+
WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64,
73
73
GFX_CTRL_CMD_ID_DESTROY_RINGS);
74
74
/* there might be handshake issue with hardware which needs delay */
75
75
mdelay(20);
76
76
/* Wait for response flag (bit 31) */
77
-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
77
+
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64),
78
78
0x80000000, 0x80000000, false);
79
79
}
80
80
···
116
116
117
117
} else {
118
118
/* Wait for sOS ready for ring creation */
119
-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
119
+
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64),
120
120
0x80000000, 0x80000000, false);
121
121
if (ret) {
122
122
DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
···
125
125
126
126
/* Write low address of the ring to C2PMSG_69 */
127
127
psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
128
-
WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_69, psp_ring_reg);
128
+
WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_69, psp_ring_reg);
129
129
/* Write high address of the ring to C2PMSG_70 */
130
130
psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
131
-
WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_70, psp_ring_reg);
131
+
WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_70, psp_ring_reg);
132
132
/* Write size of ring to C2PMSG_71 */
133
133
psp_ring_reg = ring->ring_size;
134
-
WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_71, psp_ring_reg);
134
+
WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_71, psp_ring_reg);
135
135
/* Write the ring initialization command to C2PMSG_64 */
136
136
psp_ring_reg = ring_type;
137
137
psp_ring_reg = psp_ring_reg << 16;
138
-
WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64, psp_ring_reg);
138
+
WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64, psp_ring_reg);
139
139
140
140
/* there might be handshake issue with hardware which needs delay */
141
141
mdelay(20);
142
142
143
143
/* Wait for response flag (bit 31) in C2PMSG_64 */
144
-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
144
+
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64),
145
145
0x80000000, 0x8000FFFF, false);
146
146
}
147
147
···
174
174
if (amdgpu_sriov_vf(adev))
175
175
data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102);
176
176
else
177
-
data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67);
177
+
data = RREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_67);
178
178
179
179
return data;
180
180
}
···
188
188
WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101,
189
189
GFX_CTRL_CMD_ID_CONSUME_CMD);
190
190
} else
191
-
WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67, value);
191
+
WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_67, value);
192
192
}
193
193
194
194
static const struct psp_funcs psp_v15_0_0_funcs = {
+3
-1
drivers/gpu/drm/amd/amdgpu/soc21.c
+3
-1
drivers/gpu/drm/amd/amdgpu/soc21.c
···
858
858
AMD_CG_SUPPORT_IH_CG |
859
859
AMD_CG_SUPPORT_BIF_MGCG |
860
860
AMD_CG_SUPPORT_BIF_LS;
861
-
adev->pg_flags = AMD_PG_SUPPORT_VCN |
861
+
adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG |
862
+
AMD_PG_SUPPORT_VCN |
863
+
AMD_PG_SUPPORT_JPEG_DPG |
862
864
AMD_PG_SUPPORT_JPEG |
863
865
AMD_PG_SUPPORT_GFX_PG;
864
866
adev->external_rev_id = adev->rev_id + 0x1;
+4
-2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+4
-2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
···
1706
1706
struct dc_transfer_func *tf = &dc_plane_state->in_shaper_func;
1707
1707
struct drm_atomic_state *state = plane_state->state;
1708
1708
const struct amdgpu_device *adev = drm_to_adev(colorop->dev);
1709
+
bool has_3dlut = adev->dm.dc->caps.color.dpp.hw_3d_lut || adev->dm.dc->caps.color.mpc.preblend;
1709
1710
const struct drm_device *dev = colorop->dev;
1710
1711
const struct drm_color_lut32 *lut3d;
1711
1712
uint32_t lut3d_size;
···
1723
1722
}
1724
1723
1725
1724
if (colorop_state && !colorop_state->bypass && colorop->type == DRM_COLOROP_3D_LUT) {
1726
-
if (!adev->dm.dc->caps.color.dpp.hw_3d_lut) {
1725
+
if (!has_3dlut) {
1727
1726
drm_dbg(dev, "3D LUT is not supported by hardware\n");
1728
1727
return -EINVAL;
1729
1728
}
···
1876
1875
struct drm_colorop *colorop = plane_state->color_pipeline;
1877
1876
struct drm_device *dev = plane_state->plane->dev;
1878
1877
struct amdgpu_device *adev = drm_to_adev(dev);
1878
+
bool has_3dlut = adev->dm.dc->caps.color.dpp.hw_3d_lut || adev->dm.dc->caps.color.mpc.preblend;
1879
1879
int ret;
1880
1880
1881
1881
/* 1D Curve - DEGAM TF */
···
1909
1907
if (ret)
1910
1908
return ret;
1911
1909
1912
-
if (adev->dm.dc->caps.color.dpp.hw_3d_lut) {
1910
+
if (has_3dlut) {
1913
1911
/* 1D Curve & LUT - SHAPER TF & LUT */
1914
1912
colorop = colorop->next;
1915
1913
if (!colorop) {
+2
-1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c
+2
-1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c
···
60
60
struct drm_colorop *ops[MAX_COLOR_PIPELINE_OPS];
61
61
struct drm_device *dev = plane->dev;
62
62
struct amdgpu_device *adev = drm_to_adev(dev);
63
+
bool has_3dlut = adev->dm.dc->caps.color.dpp.hw_3d_lut || adev->dm.dc->caps.color.mpc.preblend;
63
64
int ret;
64
65
int i = 0;
65
66
···
113
112
114
113
i++;
115
114
116
-
if (adev->dm.dc->caps.color.dpp.hw_3d_lut) {
115
+
if (has_3dlut) {
117
116
/* 1D curve - SHAPER TF */
118
117
ops[i] = kzalloc_obj(*ops[0]);
119
118
if (!ops[i]) {
+8
-8
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
+8
-8
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
···
765
765
dm->adev->mode_info.crtcs[crtc_index] = acrtc;
766
766
767
767
/* Don't enable DRM CRTC degamma property for
768
-
* 1. Degamma is replaced by color pipeline.
769
-
* 2. DCE since it doesn't support programmable degamma anywhere.
770
-
* 3. DCN401 since pre-blending degamma LUT doesn't apply to cursor.
768
+
* 1. DCE since it doesn't support programmable degamma anywhere.
769
+
* 2. DCN401 since pre-blending degamma LUT doesn't apply to cursor.
770
+
* Note: DEGAMMA properties are created even if the primary plane has the
771
+
* COLOR_PIPELINE property. User space can use either the DEGAMMA properties
772
+
* or the COLOR_PIPELINE property. An atomic commit which attempts to enable
773
+
* both is rejected.
771
774
*/
772
-
if (plane->color_pipeline_property)
773
-
has_degamma = false;
774
-
else
775
-
has_degamma = dm->adev->dm.dc->caps.color.dpp.dcn_arch &&
776
-
dm->adev->dm.dc->ctx->dce_version != DCN_VERSION_4_01;
775
+
has_degamma = dm->adev->dm.dc->caps.color.dpp.dcn_arch &&
776
+
dm->adev->dm.dc->ctx->dce_version != DCN_VERSION_4_01;
777
777
778
778
drm_crtc_enable_color_mgmt(&acrtc->base, has_degamma ? MAX_COLOR_LUT_ENTRIES : 0,
779
779
true, MAX_COLOR_LUT_ENTRIES);
+8
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
+8
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
···
1256
1256
if (ret)
1257
1257
return ret;
1258
1258
1259
+
/* Reject commits that attempt to use both COLOR_PIPELINE and CRTC DEGAMMA_LUT */
1260
+
if (new_plane_state->color_pipeline && new_crtc_state->degamma_lut) {
1261
+
drm_dbg_atomic(plane->dev,
1262
+
"[PLANE:%d:%s] COLOR_PIPELINE and CRTC DEGAMMA_LUT cannot be enabled simultaneously\n",
1263
+
plane->base.id, plane->name);
1264
+
return -EINVAL;
1265
+
}
1266
+
1259
1267
ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, new_plane_state, &scaling_info);
1260
1268
if (ret)
1261
1269
return ret;
+5
-1
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+5
-1
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
···
72
72
* audio corruption. Read current DISPCLK from DENTIST and request the same
73
73
* freq to ensure that the timing is valid and unchanged.
74
74
*/
75
-
clocks->dispclk_khz = dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr);
75
+
if (dc->clk_mgr->funcs->get_dispclk_from_dentist) {
76
+
clocks->dispclk_khz = dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr);
77
+
} else {
78
+
clocks->dispclk_khz = dc->clk_mgr->boot_snapshot.dispclk * 1000;
79
+
}
76
80
}
77
81
clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;
78
82
clocks->fclk_p_state_change_support = true;
+18
drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_0_offset.h
+18
drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_0_offset.h
···
82
82
#define regMPASP_SMN_IH_SW_INT_CTRL 0x0142
83
83
#define regMPASP_SMN_IH_SW_INT_CTRL_BASE_IDX 0
84
84
85
+
// addressBlock: mp_SmuMpASPPub_PcruDec
86
+
// base address: 0x3800000
87
+
#define regMPASP_PCRU1_MPASP_C2PMSG_64 0x4280
88
+
#define regMPASP_PCRU1_MPASP_C2PMSG_64_BASE_IDX 3
89
+
#define regMPASP_PCRU1_MPASP_C2PMSG_65 0x4281
90
+
#define regMPASP_PCRU1_MPASP_C2PMSG_65_BASE_IDX 3
91
+
#define regMPASP_PCRU1_MPASP_C2PMSG_66 0x4282
92
+
#define regMPASP_PCRU1_MPASP_C2PMSG_66_BASE_IDX 3
93
+
#define regMPASP_PCRU1_MPASP_C2PMSG_67 0x4283
94
+
#define regMPASP_PCRU1_MPASP_C2PMSG_67_BASE_IDX 3
95
+
#define regMPASP_PCRU1_MPASP_C2PMSG_68 0x4284
96
+
#define regMPASP_PCRU1_MPASP_C2PMSG_68_BASE_IDX 3
97
+
#define regMPASP_PCRU1_MPASP_C2PMSG_69 0x4285
98
+
#define regMPASP_PCRU1_MPASP_C2PMSG_69_BASE_IDX 3
99
+
#define regMPASP_PCRU1_MPASP_C2PMSG_70 0x4286
100
+
#define regMPASP_PCRU1_MPASP_C2PMSG_70_BASE_IDX 3
101
+
#define regMPASP_PCRU1_MPASP_C2PMSG_71 0x4287
102
+
#define regMPASP_PCRU1_MPASP_C2PMSG_71_BASE_IDX 3
85
103
86
104
// addressBlock: mp_SmuMp1_SmnDec
87
105
// base address: 0x0
+7
-1
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+7
-1
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
···
2034
2034
smu, SMU_DRIVER_TABLE_GPU_METRICS);
2035
2035
SmuMetricsExternal_t metrics_ext;
2036
2036
SmuMetrics_t *metrics = &metrics_ext.SmuMetrics;
2037
+
uint32_t mp1_ver = amdgpu_ip_version(smu->adev, MP1_HWIP, 0);
2037
2038
int ret = 0;
2038
2039
2039
2040
ret = smu_cmn_get_metrics_table(smu,
···
2059
2058
metrics->Vcn1ActivityPercentage);
2060
2059
2061
2060
gpu_metrics->average_socket_power = metrics->AverageSocketPower;
2062
-
gpu_metrics->energy_accumulator = metrics->EnergyAccumulator;
2061
+
2062
+
if ((mp1_ver == IP_VERSION(13, 0, 0) && smu->smc_fw_version <= 0x004e1e00) ||
2063
+
(mp1_ver == IP_VERSION(13, 0, 10) && smu->smc_fw_version <= 0x00500800))
2064
+
gpu_metrics->energy_accumulator = metrics->EnergyAccumulator;
2065
+
else
2066
+
gpu_metrics->energy_accumulator = UINT_MAX;
2063
2067
2064
2068
if (metrics->AverageGfxActivity <= SMU_13_0_0_BUSY_THRESHOLD)
2065
2069
gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs;
+2
-1
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+2
-1
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
···
2065
2065
metrics->Vcn1ActivityPercentage);
2066
2066
2067
2067
gpu_metrics->average_socket_power = metrics->AverageSocketPower;
2068
-
gpu_metrics->energy_accumulator = metrics->EnergyAccumulator;
2068
+
gpu_metrics->energy_accumulator = smu->smc_fw_version <= 0x00521400 ?
2069
+
metrics->EnergyAccumulator : UINT_MAX;
2069
2070
2070
2071
if (metrics->AverageGfxActivity <= SMU_13_0_7_BUSY_THRESHOLD)
2071
2072
gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs;
+2
-12
drivers/gpu/drm/drm_pagemap.c
+2
-12
drivers/gpu/drm/drm_pagemap.c
···
480
480
.start = start,
481
481
.end = end,
482
482
.pgmap_owner = pagemap->owner,
483
-
/*
484
-
* FIXME: MIGRATE_VMA_SELECT_DEVICE_PRIVATE intermittently
485
-
* causes 'xe_exec_system_allocator --r *race*no*' to trigger aa
486
-
* engine reset and a hard hang due to getting stuck on a folio
487
-
* lock. This should work and needs to be root-caused. The only
488
-
* downside of not selecting MIGRATE_VMA_SELECT_DEVICE_PRIVATE
489
-
* is that device-to-device migrations won’t work; instead,
490
-
* memory will bounce through system memory. This path should be
491
-
* rare and only occur when the madvise attributes of memory are
492
-
* changed or atomics are being used.
493
-
*/
494
-
.flags = MIGRATE_VMA_SELECT_SYSTEM | MIGRATE_VMA_SELECT_DEVICE_COHERENT,
483
+
.flags = MIGRATE_VMA_SELECT_SYSTEM | MIGRATE_VMA_SELECT_DEVICE_COHERENT |
484
+
MIGRATE_VMA_SELECT_DEVICE_PRIVATE,
495
485
};
496
486
unsigned long i, npages = npages_in_range(start, end);
497
487
unsigned long own_pages = 0, migrated_pages = 0;
+8
-3
drivers/gpu/drm/i915/display/intel_psr.c
+8
-3
drivers/gpu/drm/i915/display/intel_psr.c
···
1307
1307
u16 sink_y_granularity = crtc_state->has_panel_replay ?
1308
1308
connector->dp.panel_replay_caps.su_y_granularity :
1309
1309
connector->dp.psr_caps.su_y_granularity;
1310
-
u16 sink_w_granularity = crtc_state->has_panel_replay ?
1311
-
connector->dp.panel_replay_caps.su_w_granularity :
1312
-
connector->dp.psr_caps.su_w_granularity;
1310
+
u16 sink_w_granularity;
1311
+
1312
+
if (crtc_state->has_panel_replay)
1313
+
sink_w_granularity = connector->dp.panel_replay_caps.su_w_granularity ==
1314
+
DP_PANEL_REPLAY_FULL_LINE_GRANULARITY ?
1315
+
crtc_hdisplay : connector->dp.panel_replay_caps.su_w_granularity;
1316
+
else
1317
+
sink_w_granularity = connector->dp.psr_caps.su_w_granularity;
1313
1318
1314
1319
/* PSR2 HW only send full lines so we only need to validate the width */
1315
1320
if (crtc_hdisplay % sink_w_granularity)
+3
drivers/gpu/drm/nouveau/nouveau_connector.c
+3
drivers/gpu/drm/nouveau/nouveau_connector.c
+5
-4
drivers/gpu/drm/panthor/panthor_sched.c
+5
-4
drivers/gpu/drm/panthor/panthor_sched.c
···
893
893
894
894
out_sync:
895
895
/* Make sure the CPU caches are invalidated before the seqno is read.
896
-
* drm_gem_shmem_sync() is a NOP if map_wc=true, so no need to check
896
+
* panthor_gem_sync() is a NOP if map_wc=true, so no need to check
897
897
* it here.
898
898
*/
899
-
panthor_gem_sync(&bo->base.base, queue->syncwait.offset,
899
+
panthor_gem_sync(&bo->base.base,
900
+
DRM_PANTHOR_BO_SYNC_CPU_CACHE_FLUSH_AND_INVALIDATE,
901
+
queue->syncwait.offset,
900
902
queue->syncwait.sync64 ?
901
903
sizeof(struct panthor_syncobj_64b) :
902
-
sizeof(struct panthor_syncobj_32b),
903
-
DRM_PANTHOR_BO_SYNC_CPU_CACHE_FLUSH_AND_INVALIDATE);
904
+
sizeof(struct panthor_syncobj_32b));
904
905
905
906
return queue->syncwait.kmap + queue->syncwait.offset;
906
907
+15
-1
drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
+15
-1
drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
···
1122
1122
struct mipi_dsi_device *device)
1123
1123
{
1124
1124
struct rzg2l_mipi_dsi *dsi = host_to_rzg2l_mipi_dsi(host);
1125
+
int bpp;
1125
1126
int ret;
1126
1127
1127
1128
if (device->lanes > dsi->num_data_lanes) {
···
1132
1131
return -EINVAL;
1133
1132
}
1134
1133
1135
-
switch (mipi_dsi_pixel_format_to_bpp(device->format)) {
1134
+
bpp = mipi_dsi_pixel_format_to_bpp(device->format);
1135
+
switch (bpp) {
1136
1136
case 24:
1137
1137
break;
1138
1138
case 18:
···
1163
1161
}
1164
1162
1165
1163
drm_bridge_add(&dsi->bridge);
1164
+
1165
+
/*
1166
+
* Report the required division ratio setting for the MIPI clock dividers.
1167
+
*
1168
+
* vclk * bpp = hsclk * 8 * num_lanes
1169
+
*
1170
+
* vclk * DSI_AB_divider = hsclk * 16
1171
+
*
1172
+
* which simplifies to...
1173
+
* DSI_AB_divider = bpp * 2 / num_lanes
1174
+
*/
1175
+
rzg2l_cpg_dsi_div_set_divider(bpp * 2 / dsi->lanes, PLL5_TARGET_DSI);
1166
1176
1167
1177
return 0;
1168
1178
}
+1
drivers/gpu/drm/scheduler/sched_main.c
+1
drivers/gpu/drm/scheduler/sched_main.c
+2
-4
drivers/gpu/drm/solomon/ssd130x.c
+2
-4
drivers/gpu/drm/solomon/ssd130x.c
···
737
737
unsigned int height = drm_rect_height(rect);
738
738
unsigned int line_length = DIV_ROUND_UP(width, 8);
739
739
unsigned int page_height = SSD130X_PAGE_HEIGHT;
740
+
u8 page_start = ssd130x->page_offset + y / page_height;
740
741
unsigned int pages = DIV_ROUND_UP(height, page_height);
741
742
struct drm_device *drm = &ssd130x->drm;
742
743
u32 array_idx = 0;
···
775
774
*/
776
775
777
776
if (!ssd130x->page_address_mode) {
778
-
u8 page_start;
779
-
780
777
/* Set address range for horizontal addressing mode */
781
778
ret = ssd130x_set_col_range(ssd130x, ssd130x->col_offset + x, width);
782
779
if (ret < 0)
783
780
return ret;
784
781
785
-
page_start = ssd130x->page_offset + y / page_height;
786
782
ret = ssd130x_set_page_range(ssd130x, page_start, pages);
787
783
if (ret < 0)
788
784
return ret;
···
811
813
*/
812
814
if (ssd130x->page_address_mode) {
813
815
ret = ssd130x_set_page_pos(ssd130x,
814
-
ssd130x->page_offset + i,
816
+
page_start + i,
815
817
ssd130x->col_offset + x);
816
818
if (ret < 0)
817
819
return ret;
+2
-2
drivers/gpu/drm/ttm/tests/ttm_bo_test.c
+2
-2
drivers/gpu/drm/ttm/tests/ttm_bo_test.c
···
222
222
KUNIT_FAIL(test, "Couldn't create ttm bo reserve task\n");
223
223
224
224
/* Take a lock so the threaded reserve has to wait */
225
-
mutex_lock(&bo->base.resv->lock.base);
225
+
dma_resv_lock(bo->base.resv, NULL);
226
226
227
227
wake_up_process(task);
228
228
msleep(20);
229
229
err = kthread_stop(task);
230
230
231
-
mutex_unlock(&bo->base.resv->lock.base);
231
+
dma_resv_unlock(bo->base.resv);
232
232
233
233
KUNIT_ASSERT_EQ(test, err, -ERESTARTSYS);
234
234
}
+5
-6
drivers/gpu/drm/ttm/ttm_bo.c
+5
-6
drivers/gpu/drm/ttm/ttm_bo.c
···
1107
1107
static s64
1108
1108
ttm_bo_swapout_cb(struct ttm_lru_walk *walk, struct ttm_buffer_object *bo)
1109
1109
{
1110
-
struct ttm_resource *res = bo->resource;
1111
-
struct ttm_place place = { .mem_type = res->mem_type };
1110
+
struct ttm_place place = { .mem_type = bo->resource->mem_type };
1112
1111
struct ttm_bo_swapout_walk *swapout_walk =
1113
1112
container_of(walk, typeof(*swapout_walk), walk);
1114
1113
struct ttm_operation_ctx *ctx = walk->arg.ctx;
···
1147
1148
/*
1148
1149
* Move to system cached
1149
1150
*/
1150
-
if (res->mem_type != TTM_PL_SYSTEM) {
1151
+
if (bo->resource->mem_type != TTM_PL_SYSTEM) {
1151
1152
struct ttm_resource *evict_mem;
1152
1153
struct ttm_place hop;
1153
1154
···
1179
1180
1180
1181
if (ttm_tt_is_populated(tt)) {
1181
1182
spin_lock(&bdev->lru_lock);
1182
-
ttm_resource_del_bulk_move(res, bo);
1183
+
ttm_resource_del_bulk_move(bo->resource, bo);
1183
1184
spin_unlock(&bdev->lru_lock);
1184
1185
1185
1186
ret = ttm_tt_swapout(bdev, tt, swapout_walk->gfp_flags);
1186
1187
1187
1188
spin_lock(&bdev->lru_lock);
1188
1189
if (ret)
1189
-
ttm_resource_add_bulk_move(res, bo);
1190
-
ttm_resource_move_to_lru_tail(res);
1190
+
ttm_resource_add_bulk_move(bo->resource, bo);
1191
+
ttm_resource_move_to_lru_tail(bo->resource);
1191
1192
spin_unlock(&bdev->lru_lock);
1192
1193
}
1193
1194
+1
-1
drivers/gpu/drm/ttm/ttm_pool_internal.h
+1
-1
drivers/gpu/drm/ttm/ttm_pool_internal.h
+1
drivers/gpu/drm/xe/xe_configfs.c
+1
drivers/gpu/drm/xe/xe_configfs.c
+11
-12
drivers/gpu/drm/xe/xe_exec_queue.c
+11
-12
drivers/gpu/drm/xe/xe_exec_queue.c
···
266
266
return q;
267
267
}
268
268
269
+
static void __xe_exec_queue_fini(struct xe_exec_queue *q)
270
+
{
271
+
int i;
272
+
273
+
q->ops->fini(q);
274
+
275
+
for (i = 0; i < q->width; ++i)
276
+
xe_lrc_put(q->lrc[i]);
277
+
}
278
+
269
279
static int __xe_exec_queue_init(struct xe_exec_queue *q, u32 exec_queue_flags)
270
280
{
271
281
int i, err;
···
330
320
return 0;
331
321
332
322
err_lrc:
333
-
for (i = i - 1; i >= 0; --i)
334
-
xe_lrc_put(q->lrc[i]);
323
+
__xe_exec_queue_fini(q);
335
324
return err;
336
-
}
337
-
338
-
static void __xe_exec_queue_fini(struct xe_exec_queue *q)
339
-
{
340
-
int i;
341
-
342
-
q->ops->fini(q);
343
-
344
-
for (i = 0; i < q->width; ++i)
345
-
xe_lrc_put(q->lrc[i]);
346
325
}
347
326
348
327
struct xe_exec_queue *xe_exec_queue_create(struct xe_device *xe, struct xe_vm *vm,
+35
-8
drivers/gpu/drm/xe/xe_gsc_proxy.c
+35
-8
drivers/gpu/drm/xe/xe_gsc_proxy.c
···
435
435
return 0;
436
436
}
437
437
438
-
static void xe_gsc_proxy_remove(void *arg)
438
+
static void xe_gsc_proxy_stop(struct xe_gsc *gsc)
439
439
{
440
-
struct xe_gsc *gsc = arg;
441
440
struct xe_gt *gt = gsc_to_gt(gsc);
442
441
struct xe_device *xe = gt_to_xe(gt);
443
-
444
-
if (!gsc->proxy.component_added)
445
-
return;
446
442
447
443
/* disable HECI2 IRQs */
448
444
scoped_guard(xe_pm_runtime, xe) {
···
451
455
}
452
456
453
457
xe_gsc_wait_for_worker_completion(gsc);
458
+
gsc->proxy.started = false;
459
+
}
460
+
461
+
static void xe_gsc_proxy_remove(void *arg)
462
+
{
463
+
struct xe_gsc *gsc = arg;
464
+
struct xe_gt *gt = gsc_to_gt(gsc);
465
+
struct xe_device *xe = gt_to_xe(gt);
466
+
467
+
if (!gsc->proxy.component_added)
468
+
return;
469
+
470
+
/*
471
+
* GSC proxy start is an async process that can be ongoing during
472
+
* Xe module load/unload. Using devm managed action to register
473
+
* xe_gsc_proxy_stop could cause issues if Xe module unload has
474
+
* already started when the action is registered, potentially leading
475
+
* to the cleanup being called at the wrong time. Therefore, instead
476
+
* of registering a separate devm action to undo what is done in
477
+
* proxy start, we call it from here, but only if the start has
478
+
* completed successfully (tracked with the 'started' flag).
479
+
*/
480
+
if (gsc->proxy.started)
481
+
xe_gsc_proxy_stop(gsc);
454
482
455
483
component_del(xe->drm.dev, &xe_gsc_proxy_component_ops);
456
484
gsc->proxy.component_added = false;
···
530
510
*/
531
511
int xe_gsc_proxy_start(struct xe_gsc *gsc)
532
512
{
513
+
struct xe_gt *gt = gsc_to_gt(gsc);
533
514
int err;
534
515
535
516
/* enable the proxy interrupt in the GSC shim layer */
···
542
521
*/
543
522
err = xe_gsc_proxy_request_handler(gsc);
544
523
if (err)
545
-
return err;
524
+
goto err_irq_disable;
546
525
547
526
if (!xe_gsc_proxy_init_done(gsc)) {
548
-
xe_gt_err(gsc_to_gt(gsc), "GSC FW reports proxy init not completed\n");
549
-
return -EIO;
527
+
xe_gt_err(gt, "GSC FW reports proxy init not completed\n");
528
+
err = -EIO;
529
+
goto err_irq_disable;
550
530
}
551
531
532
+
gsc->proxy.started = true;
552
533
return 0;
534
+
535
+
err_irq_disable:
536
+
gsc_proxy_irq_toggle(gsc, false);
537
+
return err;
553
538
}
+2
drivers/gpu/drm/xe/xe_gsc_types.h
+2
drivers/gpu/drm/xe/xe_gsc_types.h
···
58
58
struct mutex mutex;
59
59
/** @proxy.component_added: whether the component has been added */
60
60
bool component_added;
61
+
/** @proxy.started: whether the proxy has been started */
62
+
bool started;
61
63
/** @proxy.bo: object to store message to and from the GSC */
62
64
struct xe_bo *bo;
63
65
/** @proxy.to_gsc: map of the memory used to send messages to the GSC */
+2
-1
drivers/gpu/drm/xe/xe_lrc.h
+2
-1
drivers/gpu/drm/xe/xe_lrc.h
+3
-1
drivers/gpu/drm/xe/xe_reg_sr.c
+3
-1
drivers/gpu/drm/xe/xe_reg_sr.c
···
98
98
*pentry = *e;
99
99
ret = xa_err(xa_store(&sr->xa, idx, pentry, GFP_KERNEL));
100
100
if (ret)
101
-
goto fail;
101
+
goto fail_free;
102
102
103
103
return 0;
104
104
105
+
fail_free:
106
+
kfree(pentry);
105
107
fail:
106
108
xe_gt_err(gt,
107
109
"discarding save-restore reg %04lx (clear: %08x, set: %08x, masked: %s, mcr: %s): ret=%d\n",
+9
drivers/gpu/drm/xe/xe_ring_ops.c
+9
drivers/gpu/drm/xe/xe_ring_ops.c
···
280
280
281
281
i = emit_bb_start(batch_addr, ppgtt_flag, dw, i);
282
282
283
+
/* Don't preempt fence signaling */
284
+
dw[i++] = MI_ARB_ON_OFF | MI_ARB_DISABLE;
285
+
283
286
if (job->user_fence.used) {
284
287
i = emit_flush_dw(dw, i);
285
288
i = emit_store_imm_ppgtt_posted(job->user_fence.addr,
···
348
345
349
346
i = emit_bb_start(batch_addr, ppgtt_flag, dw, i);
350
347
348
+
/* Don't preempt fence signaling */
349
+
dw[i++] = MI_ARB_ON_OFF | MI_ARB_DISABLE;
350
+
351
351
if (job->user_fence.used) {
352
352
i = emit_flush_dw(dw, i);
353
353
i = emit_store_imm_ppgtt_posted(job->user_fence.addr,
···
402
396
seqno, dw, i);
403
397
404
398
i = emit_bb_start(batch_addr, ppgtt_flag, dw, i);
399
+
400
+
/* Don't preempt fence signaling */
401
+
dw[i++] = MI_ARB_ON_OFF | MI_ARB_DISABLE;
405
402
406
403
i = emit_render_cache_flush(job, dw, i);
407
404
+2
-1
drivers/gpu/drm/xe/xe_vm_madvise.c
+2
-1
drivers/gpu/drm/xe/xe_vm_madvise.c
···
453
453
madvise_range.num_vmas,
454
454
args->atomic.val)) {
455
455
err = -EINVAL;
456
-
goto madv_fini;
456
+
goto free_vmas;
457
457
}
458
458
}
459
459
···
490
490
err_fini:
491
491
if (madvise_range.has_bo_vmas)
492
492
drm_exec_fini(&exec);
493
+
free_vmas:
493
494
kfree(madvise_range.vmas);
494
495
madvise_range.vmas = NULL;
495
496
madv_fini:
+7
-6
drivers/gpu/drm/xe/xe_wa.c
+7
-6
drivers/gpu/drm/xe/xe_wa.c
···
241
241
242
242
{ XE_RTP_NAME("16025250150"),
243
243
XE_RTP_RULES(GRAPHICS_VERSION(2001)),
244
-
XE_RTP_ACTIONS(SET(LSN_VC_REG2,
245
-
LSN_LNI_WGT(1) |
246
-
LSN_LNE_WGT(1) |
247
-
LSN_DIM_X_WGT(1) |
248
-
LSN_DIM_Y_WGT(1) |
249
-
LSN_DIM_Z_WGT(1)))
244
+
XE_RTP_ACTIONS(FIELD_SET(LSN_VC_REG2,
245
+
LSN_LNI_WGT_MASK | LSN_LNE_WGT_MASK |
246
+
LSN_DIM_X_WGT_MASK | LSN_DIM_Y_WGT_MASK |
247
+
LSN_DIM_Z_WGT_MASK,
248
+
LSN_LNI_WGT(1) | LSN_LNE_WGT(1) |
249
+
LSN_DIM_X_WGT(1) | LSN_DIM_Y_WGT(1) |
250
+
LSN_DIM_Z_WGT(1)))
250
251
},
251
252
252
253
/* Xe2_HPM */
+2
include/drm/display/drm_dp.h
+2
include/drm/display/drm_dp.h
···
571
571
# define DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP (1 << 7)
572
572
573
573
#define DP_PANEL_REPLAY_CAP_X_GRANULARITY 0xb2
574
+
# define DP_PANEL_REPLAY_FULL_LINE_GRANULARITY 0xffff
575
+
574
576
#define DP_PANEL_REPLAY_CAP_Y_GRANULARITY 0xb4
575
577
576
578
/* Link Configuration */
+9
-1
include/linux/migrate.h
+9
-1
include/linux/migrate.h
···
65
65
66
66
int migrate_huge_page_move_mapping(struct address_space *mapping,
67
67
struct folio *dst, struct folio *src);
68
-
void migration_entry_wait_on_locked(softleaf_t entry, spinlock_t *ptl)
68
+
void softleaf_entry_wait_on_locked(softleaf_t entry, spinlock_t *ptl)
69
69
__releases(ptl);
70
70
void folio_migrate_flags(struct folio *newfolio, struct folio *folio);
71
71
int folio_migrate_mapping(struct address_space *mapping,
···
95
95
static inline int set_movable_ops(const struct movable_operations *ops, enum pagetype type)
96
96
{
97
97
return -ENOSYS;
98
+
}
99
+
100
+
static inline void softleaf_entry_wait_on_locked(softleaf_t entry, spinlock_t *ptl)
101
+
__releases(ptl)
102
+
{
103
+
WARN_ON_ONCE(1);
104
+
105
+
spin_unlock(ptl);
98
106
}
99
107
100
108
#endif /* CONFIG_MIGRATION */
+1
include/uapi/linux/dma-buf.h
+1
include/uapi/linux/dma-buf.h
+10
-5
mm/filemap.c
+10
-5
mm/filemap.c
···
1379
1379
1380
1380
#ifdef CONFIG_MIGRATION
1381
1381
/**
1382
-
* migration_entry_wait_on_locked - Wait for a migration entry to be removed
1383
-
* @entry: migration swap entry.
1382
+
* softleaf_entry_wait_on_locked - Wait for a migration entry or
1383
+
* device_private entry to be removed.
1384
+
* @entry: migration or device_private swap entry.
1384
1385
* @ptl: already locked ptl. This function will drop the lock.
1385
1386
*
1386
-
* Wait for a migration entry referencing the given page to be removed. This is
1387
+
* Wait for a migration entry referencing the given page, or device_private
1388
+
* entry referencing a dvice_private page to be unlocked. This is
1387
1389
* equivalent to folio_put_wait_locked(folio, TASK_UNINTERRUPTIBLE) except
1388
1390
* this can be called without taking a reference on the page. Instead this
1389
-
* should be called while holding the ptl for the migration entry referencing
1391
+
* should be called while holding the ptl for @entry referencing
1390
1392
* the page.
1391
1393
*
1392
1394
* Returns after unlocking the ptl.
···
1396
1394
* This follows the same logic as folio_wait_bit_common() so see the comments
1397
1395
* there.
1398
1396
*/
1399
-
void migration_entry_wait_on_locked(softleaf_t entry, spinlock_t *ptl)
1397
+
void softleaf_entry_wait_on_locked(softleaf_t entry, spinlock_t *ptl)
1400
1398
__releases(ptl)
1401
1399
{
1402
1400
struct wait_page_queue wait_page;
···
1430
1428
* If a migration entry exists for the page the migration path must hold
1431
1429
* a valid reference to the page, and it must take the ptl to remove the
1432
1430
* migration entry. So the page is valid until the ptl is dropped.
1431
+
* Similarly any path attempting to drop the last reference to a
1432
+
* device-private page needs to grab the ptl to remove the device-private
1433
+
* entry.
1433
1434
*/
1434
1435
spin_unlock(ptl);
1435
1436
+2
-1
mm/memory.c
+2
-1
mm/memory.c
···
4763
4763
unlock_page(vmf->page);
4764
4764
put_page(vmf->page);
4765
4765
} else {
4766
-
pte_unmap_unlock(vmf->pte, vmf->ptl);
4766
+
pte_unmap(vmf->pte);
4767
+
softleaf_entry_wait_on_locked(entry, vmf->ptl);
4767
4768
}
4768
4769
} else if (softleaf_is_hwpoison(entry)) {
4769
4770
ret = VM_FAULT_HWPOISON;
+4
-4
mm/migrate.c
+4
-4
mm/migrate.c
···
500
500
if (!softleaf_is_migration(entry))
501
501
goto out;
502
502
503
-
migration_entry_wait_on_locked(entry, ptl);
503
+
softleaf_entry_wait_on_locked(entry, ptl);
504
504
return;
505
505
out:
506
506
spin_unlock(ptl);
···
532
532
* If migration entry existed, safe to release vma lock
533
533
* here because the pgtable page won't be freed without the
534
534
* pgtable lock released. See comment right above pgtable
535
-
* lock release in migration_entry_wait_on_locked().
535
+
* lock release in softleaf_entry_wait_on_locked().
536
536
*/
537
537
hugetlb_vma_unlock_read(vma);
538
-
migration_entry_wait_on_locked(entry, ptl);
538
+
softleaf_entry_wait_on_locked(entry, ptl);
539
539
return;
540
540
}
541
541
···
553
553
ptl = pmd_lock(mm, pmd);
554
554
if (!pmd_is_migration_entry(*pmd))
555
555
goto unlock;
556
-
migration_entry_wait_on_locked(softleaf_from_pmd(*pmd), ptl);
556
+
softleaf_entry_wait_on_locked(softleaf_from_pmd(*pmd), ptl);
557
557
return;
558
558
unlock:
559
559
spin_unlock(ptl);