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interconnect: qcom: sm6350: enable QoS configuration

Enable QoS configuration for master ports with predefined values for
priority and urgency forwarding.

While this does require some "clocks" to be specified in devicetree to
work correctly, thanks to ".qos_requires_clocks = true," this is
backwards compatible with old DT as QoS programming will be skipped for
aggre1_noc and aggre2_noc when clocks are not provided.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20251114-sm6350-icc-qos-v2-4-6af348cb9c69@fairphone.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>

authored by

Luca Weiss and committed by
Georgi Djakov ee718481 ccd789e5

+288
+288
drivers/interconnect/qcom/sm6350.c
··· 150 150 .link_nodes = { &srvc_aggre1_noc }, 151 151 }; 152 152 153 + static struct qcom_icc_qosbox qhm_qup_0_qos = { 154 + .num_ports = 1, 155 + .port_offsets = { 0xa000 }, 156 + .prio = 2, 157 + .urg_fwd = 0, 158 + }; 159 + 153 160 static struct qcom_icc_node qhm_qup_0 = { 154 161 .name = "qhm_qup_0", 155 162 .channels = 1, 156 163 .buswidth = 4, 164 + .qosbox = &qhm_qup_0_qos, 157 165 .num_links = 1, 158 166 .link_nodes = { &qns_a1noc_snoc }, 167 + }; 168 + 169 + static struct qcom_icc_qosbox xm_emmc_qos = { 170 + .num_ports = 1, 171 + .port_offsets = { 0x7000 }, 172 + .prio = 2, 173 + .urg_fwd = 0, 159 174 }; 160 175 161 176 static struct qcom_icc_node xm_emmc = { 162 177 .name = "xm_emmc", 163 178 .channels = 1, 164 179 .buswidth = 8, 180 + .qosbox = &xm_emmc_qos, 165 181 .num_links = 1, 166 182 .link_nodes = { &qns_a1noc_snoc }, 183 + }; 184 + 185 + static struct qcom_icc_qosbox xm_ufs_mem_qos = { 186 + .num_ports = 1, 187 + .port_offsets = { 0x8000 }, 188 + .prio = 4, 189 + .urg_fwd = 0, 167 190 }; 168 191 169 192 static struct qcom_icc_node xm_ufs_mem = { 170 193 .name = "xm_ufs_mem", 171 194 .channels = 1, 172 195 .buswidth = 8, 196 + .qosbox = &xm_ufs_mem_qos, 173 197 .num_links = 1, 174 198 .link_nodes = { &qns_a1noc_snoc }, 175 199 }; ··· 206 182 .link_nodes = { &srvc_aggre2_noc }, 207 183 }; 208 184 185 + static struct qcom_icc_qosbox qhm_qdss_bam_qos = { 186 + .num_ports = 1, 187 + .port_offsets = { 0xb000 }, 188 + .prio = 2, 189 + .urg_fwd = 0, 190 + }; 191 + 209 192 static struct qcom_icc_node qhm_qdss_bam = { 210 193 .name = "qhm_qdss_bam", 211 194 .channels = 1, 212 195 .buswidth = 4, 196 + .qosbox = &qhm_qdss_bam_qos, 213 197 .num_links = 1, 214 198 .link_nodes = { &qns_a2noc_snoc }, 215 199 }; 216 200 201 + static struct qcom_icc_qosbox qhm_qup_1_qos = { 202 + .num_ports = 1, 203 + .port_offsets = { 0x9000 }, 204 + .prio = 2, 205 + .urg_fwd = 0, 206 + }; 217 207 static struct qcom_icc_node qhm_qup_1 = { 218 208 .name = "qhm_qup_1", 219 209 .channels = 1, 220 210 .buswidth = 4, 211 + .qosbox = &qhm_qup_1_qos, 221 212 .num_links = 1, 222 213 .link_nodes = { &qns_a2noc_snoc }, 214 + }; 215 + 216 + static struct qcom_icc_qosbox qxm_crypto_qos = { 217 + .num_ports = 1, 218 + .port_offsets = { 0x6000 }, 219 + .prio = 2, 220 + .urg_fwd = 0, 223 221 }; 224 222 225 223 static struct qcom_icc_node qxm_crypto = { 226 224 .name = "qxm_crypto", 227 225 .channels = 1, 228 226 .buswidth = 8, 227 + .qosbox = &qxm_crypto_qos, 229 228 .num_links = 1, 230 229 .link_nodes = { &qns_a2noc_snoc }, 230 + }; 231 + 232 + static struct qcom_icc_qosbox qxm_ipa_qos = { 233 + .num_ports = 1, 234 + .port_offsets = { 0x7000 }, 235 + .prio = 2, 236 + .urg_fwd = 0, 231 237 }; 232 238 233 239 static struct qcom_icc_node qxm_ipa = { 234 240 .name = "qxm_ipa", 235 241 .channels = 1, 236 242 .buswidth = 8, 243 + .qosbox = &qxm_ipa_qos, 237 244 .num_links = 1, 238 245 .link_nodes = { &qns_a2noc_snoc }, 246 + }; 247 + 248 + static struct qcom_icc_qosbox xm_qdss_etr_qos = { 249 + .num_ports = 1, 250 + .port_offsets = { 0xc000 }, 251 + .prio = 2, 252 + .urg_fwd = 0, 239 253 }; 240 254 241 255 static struct qcom_icc_node xm_qdss_etr = { 242 256 .name = "xm_qdss_etr", 243 257 .channels = 1, 244 258 .buswidth = 8, 259 + .qosbox = &xm_qdss_etr_qos, 245 260 .num_links = 1, 246 261 .link_nodes = { &qns_a2noc_snoc }, 262 + }; 263 + 264 + static struct qcom_icc_qosbox xm_sdc2_qos = { 265 + .num_ports = 1, 266 + .port_offsets = { 0x18000 }, 267 + .prio = 2, 268 + .urg_fwd = 0, 247 269 }; 248 270 249 271 static struct qcom_icc_node xm_sdc2 = { 250 272 .name = "xm_sdc2", 251 273 .channels = 1, 252 274 .buswidth = 8, 275 + .qosbox = &xm_sdc2_qos, 253 276 .num_links = 1, 254 277 .link_nodes = { &qns_a2noc_snoc }, 278 + }; 279 + 280 + static struct qcom_icc_qosbox xm_usb3_0_qos = { 281 + .num_ports = 1, 282 + .port_offsets = { 0xd000 }, 283 + .prio = 2, 284 + .urg_fwd = 0, 255 285 }; 256 286 257 287 static struct qcom_icc_node xm_usb3_0 = { 258 288 .name = "xm_usb3_0", 259 289 .channels = 1, 260 290 .buswidth = 8, 291 + .qosbox = &xm_usb3_0_qos, 261 292 .num_links = 1, 262 293 .link_nodes = { &qns_a2noc_snoc }, 263 294 }; ··· 357 278 .link_nodes = { &qup1_core_slave }, 358 279 }; 359 280 281 + static struct qcom_icc_qosbox qnm_npu_qos = { 282 + .num_ports = 2, 283 + .port_offsets = { 0xf000, 0x11000 }, 284 + .prio = 0, 285 + .urg_fwd = 1, 286 + }; 287 + 360 288 static struct qcom_icc_node qnm_npu = { 361 289 .name = "qnm_npu", 362 290 .channels = 2, 363 291 .buswidth = 32, 292 + .qosbox = &qnm_npu_qos, 364 293 .num_links = 1, 365 294 .link_nodes = { &qns_cdsp_gemnoc }, 295 + }; 296 + 297 + static struct qcom_icc_qosbox qxm_npu_dsp_qos = { 298 + .num_ports = 1, 299 + .port_offsets = { 0x13000 }, 300 + .prio = 0, 301 + .urg_fwd = 1, 366 302 }; 367 303 368 304 static struct qcom_icc_node qxm_npu_dsp = { 369 305 .name = "qxm_npu_dsp", 370 306 .channels = 1, 371 307 .buswidth = 8, 308 + .qosbox = &qxm_npu_dsp_qos, 372 309 .num_links = 1, 373 310 .link_nodes = { &qns_cdsp_gemnoc }, 374 311 }; ··· 496 401 &qhs_gemnoc }, 497 402 }; 498 403 404 + static struct qcom_icc_qosbox acm_apps_qos = { 405 + .num_ports = 2, 406 + .port_offsets = { 0x2f100, 0x2f000 }, 407 + .prio = 0, 408 + .urg_fwd = 0, 409 + }; 410 + 499 411 static struct qcom_icc_node acm_apps = { 500 412 .name = "acm_apps", 501 413 .channels = 1, 502 414 .buswidth = 16, 415 + .qosbox = &acm_apps_qos, 503 416 .num_links = 2, 504 417 .link_nodes = { &qns_llcc, 505 418 &qns_gem_noc_snoc }, 419 + }; 420 + 421 + static struct qcom_icc_qosbox acm_sys_tcu_qos = { 422 + .num_ports = 1, 423 + .port_offsets = { 0x35000 }, 424 + .prio = 6, 425 + .urg_fwd = 0, 506 426 }; 507 427 508 428 static struct qcom_icc_node acm_sys_tcu = { 509 429 .name = "acm_sys_tcu", 510 430 .channels = 1, 511 431 .buswidth = 8, 432 + .qosbox = &acm_sys_tcu_qos, 512 433 .num_links = 2, 513 434 .link_nodes = { &qns_llcc, 514 435 &qns_gem_noc_snoc }, ··· 540 429 &qhs_mdsp_ms_mpu_cfg }, 541 430 }; 542 431 432 + static struct qcom_icc_qosbox qnm_cmpnoc_qos = { 433 + .num_ports = 1, 434 + .port_offsets = { 0x2e000 }, 435 + .prio = 0, 436 + .urg_fwd = 1, 437 + }; 438 + 543 439 static struct qcom_icc_node qnm_cmpnoc = { 544 440 .name = "qnm_cmpnoc", 545 441 .channels = 1, 546 442 .buswidth = 32, 443 + .qosbox = &qnm_cmpnoc_qos, 547 444 .num_links = 2, 548 445 .link_nodes = { &qns_llcc, 549 446 &qns_gem_noc_snoc }, 447 + }; 448 + 449 + static struct qcom_icc_qosbox qnm_mnoc_hf_qos = { 450 + .num_ports = 1, 451 + .port_offsets = { 0x30000 }, 452 + .prio = 0, 453 + .urg_fwd = 1, 550 454 }; 551 455 552 456 static struct qcom_icc_node qnm_mnoc_hf = { 553 457 .name = "qnm_mnoc_hf", 554 458 .channels = 1, 555 459 .buswidth = 32, 460 + .qosbox = &qnm_mnoc_hf_qos, 556 461 .num_links = 2, 557 462 .link_nodes = { &qns_llcc, 558 463 &qns_gem_noc_snoc }, 464 + }; 465 + 466 + static struct qcom_icc_qosbox qnm_mnoc_sf_qos = { 467 + .num_ports = 1, 468 + .port_offsets = { 0x34000 }, 469 + .prio = 0, 470 + .urg_fwd = 1, 559 471 }; 560 472 561 473 static struct qcom_icc_node qnm_mnoc_sf = { 562 474 .name = "qnm_mnoc_sf", 563 475 .channels = 1, 564 476 .buswidth = 32, 477 + .qosbox = &qnm_mnoc_sf_qos, 565 478 .num_links = 2, 566 479 .link_nodes = { &qns_llcc, 567 480 &qns_gem_noc_snoc }, 481 + }; 482 + 483 + static struct qcom_icc_qosbox qnm_snoc_gc_qos = { 484 + .num_ports = 1, 485 + .port_offsets = { 0x32000 }, 486 + .prio = 0, 487 + .urg_fwd = 1, 568 488 }; 569 489 570 490 static struct qcom_icc_node qnm_snoc_gc = { 571 491 .name = "qnm_snoc_gc", 572 492 .channels = 1, 573 493 .buswidth = 8, 494 + .qosbox = &qnm_snoc_gc_qos, 574 495 .num_links = 1, 575 496 .link_nodes = { &qns_llcc }, 497 + }; 498 + 499 + static struct qcom_icc_qosbox qnm_snoc_sf_qos = { 500 + .num_ports = 1, 501 + .port_offsets = { 0x31000 }, 502 + .prio = 0, 503 + .urg_fwd = 1, 576 504 }; 577 505 578 506 static struct qcom_icc_node qnm_snoc_sf = { 579 507 .name = "qnm_snoc_sf", 580 508 .channels = 1, 581 509 .buswidth = 16, 510 + .qosbox = &qnm_snoc_sf_qos, 582 511 .num_links = 1, 583 512 .link_nodes = { &qns_llcc }, 513 + }; 514 + 515 + static struct qcom_icc_qosbox qxm_gpu_qos = { 516 + .num_ports = 2, 517 + .port_offsets = { 0x33000, 0x33080 }, 518 + .prio = 0, 519 + .urg_fwd = 0, 584 520 }; 585 521 586 522 static struct qcom_icc_node qxm_gpu = { 587 523 .name = "qxm_gpu", 588 524 .channels = 2, 589 525 .buswidth = 32, 526 + .qosbox = &qxm_gpu_qos, 590 527 .num_links = 2, 591 528 .link_nodes = { &qns_llcc, 592 529 &qns_gem_noc_snoc }, ··· 656 497 .link_nodes = { &srvc_mnoc }, 657 498 }; 658 499 500 + static struct qcom_icc_qosbox qnm_video0_qos = { 501 + .num_ports = 1, 502 + .port_offsets = { 0xf000 }, 503 + .prio = 2, 504 + .urg_fwd = 1, 505 + }; 506 + 659 507 static struct qcom_icc_node qnm_video0 = { 660 508 .name = "qnm_video0", 661 509 .channels = 1, 662 510 .buswidth = 32, 511 + .qosbox = &qnm_video0_qos, 663 512 .num_links = 1, 664 513 .link_nodes = { &qns_mem_noc_sf }, 514 + }; 515 + 516 + static struct qcom_icc_qosbox qnm_video_cvp_qos = { 517 + .num_ports = 1, 518 + .port_offsets = { 0xe000 }, 519 + .prio = 5, 520 + .urg_fwd = 1, 665 521 }; 666 522 667 523 static struct qcom_icc_node qnm_video_cvp = { 668 524 .name = "qnm_video_cvp", 669 525 .channels = 1, 670 526 .buswidth = 8, 527 + .qosbox = &qnm_video_cvp_qos, 671 528 .num_links = 1, 672 529 .link_nodes = { &qns_mem_noc_sf }, 530 + }; 531 + 532 + static struct qcom_icc_qosbox qxm_camnoc_hf_qos = { 533 + .num_ports = 2, 534 + .port_offsets = { 0xa000, 0xb000 }, 535 + .prio = 3, 536 + .urg_fwd = 1, 673 537 }; 674 538 675 539 static struct qcom_icc_node qxm_camnoc_hf = { 676 540 .name = "qxm_camnoc_hf", 677 541 .channels = 2, 678 542 .buswidth = 32, 543 + .qosbox = &qxm_camnoc_hf_qos, 679 544 .num_links = 1, 680 545 .link_nodes = { &qns_mem_noc_hf }, 546 + }; 547 + 548 + static struct qcom_icc_qosbox qxm_camnoc_icp_qos = { 549 + .num_ports = 1, 550 + .port_offsets = { 0xd000 }, 551 + .prio = 5, 552 + .urg_fwd = 0, 681 553 }; 682 554 683 555 static struct qcom_icc_node qxm_camnoc_icp = { 684 556 .name = "qxm_camnoc_icp", 685 557 .channels = 1, 686 558 .buswidth = 8, 559 + .qosbox = &qxm_camnoc_icp_qos, 687 560 .num_links = 1, 688 561 .link_nodes = { &qns_mem_noc_sf }, 562 + }; 563 + 564 + static struct qcom_icc_qosbox qxm_camnoc_sf_qos = { 565 + .num_ports = 1, 566 + .port_offsets = { 0x9000 }, 567 + .prio = 3, 568 + .urg_fwd = 1, 689 569 }; 690 570 691 571 static struct qcom_icc_node qxm_camnoc_sf = { 692 572 .name = "qxm_camnoc_sf", 693 573 .channels = 1, 694 574 .buswidth = 32, 575 + .qosbox = &qxm_camnoc_sf_qos, 695 576 .num_links = 1, 696 577 .link_nodes = { &qns_mem_noc_sf }, 578 + }; 579 + 580 + static struct qcom_icc_qosbox qxm_mdp0_qos = { 581 + .num_ports = 1, 582 + .port_offsets = { 0xc000 }, 583 + .prio = 3, 584 + .urg_fwd = 1, 697 585 }; 698 586 699 587 static struct qcom_icc_node qxm_mdp0 = { 700 588 .name = "qxm_mdp0", 701 589 .channels = 1, 702 590 .buswidth = 32, 591 + .qosbox = &qxm_mdp0_qos, 703 592 .num_links = 1, 704 593 .link_nodes = { &qns_mem_noc_hf }, 705 594 }; ··· 823 616 &xs_qdss_stm }, 824 617 }; 825 618 619 + static struct qcom_icc_qosbox qxm_pimem_qos = { 620 + .num_ports = 1, 621 + .port_offsets = { 0xd000 }, 622 + .prio = 2, 623 + .urg_fwd = 0, 624 + }; 625 + 826 626 static struct qcom_icc_node qxm_pimem = { 827 627 .name = "qxm_pimem", 828 628 .channels = 1, 829 629 .buswidth = 8, 630 + .qosbox = &qxm_pimem_qos, 830 631 .num_links = 2, 831 632 .link_nodes = { &qns_gemnoc_gc, 832 633 &qxs_imem }, 634 + }; 635 + 636 + static struct qcom_icc_qosbox xm_gic_qos = { 637 + .num_ports = 1, 638 + .port_offsets = { 0xb000 }, 639 + .prio = 3, 640 + .urg_fwd = 0, 833 641 }; 834 642 835 643 static struct qcom_icc_node xm_gic = { 836 644 .name = "xm_gic", 837 645 .channels = 1, 838 646 .buswidth = 8, 647 + .qosbox = &xm_gic_qos, 839 648 .num_links = 1, 840 649 .link_nodes = { &qns_gemnoc_gc }, 841 650 }; ··· 1611 1388 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, 1612 1389 }; 1613 1390 1391 + static const struct regmap_config sm6350_aggre1_noc_regmap_config = { 1392 + .reg_bits = 32, 1393 + .reg_stride = 4, 1394 + .val_bits = 32, 1395 + .max_register = 0x15080, 1396 + .fast_io = true, 1397 + }; 1398 + 1614 1399 static const struct qcom_icc_desc sm6350_aggre1_noc = { 1400 + .config = &sm6350_aggre1_noc_regmap_config, 1615 1401 .nodes = aggre1_noc_nodes, 1616 1402 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 1617 1403 .bcms = aggre1_noc_bcms, 1618 1404 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 1405 + .qos_requires_clocks = true, 1619 1406 }; 1620 1407 1621 1408 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { ··· 1646 1413 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, 1647 1414 }; 1648 1415 1416 + static const struct regmap_config sm6350_aggre2_noc_regmap_config = { 1417 + .reg_bits = 32, 1418 + .reg_stride = 4, 1419 + .val_bits = 32, 1420 + .max_register = 0x1f880, 1421 + .fast_io = true, 1422 + }; 1423 + 1649 1424 static const struct qcom_icc_desc sm6350_aggre2_noc = { 1425 + .config = &sm6350_aggre2_noc_regmap_config, 1650 1426 .nodes = aggre2_noc_nodes, 1651 1427 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 1652 1428 .bcms = aggre2_noc_bcms, 1653 1429 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 1430 + .qos_requires_clocks = true, 1654 1431 }; 1655 1432 1656 1433 static struct qcom_icc_bcm * const clk_virt_bcms[] = { ··· 1702 1459 [SLAVE_CDSP_GEM_NOC] = &qns_cdsp_gemnoc, 1703 1460 }; 1704 1461 1462 + static const struct regmap_config sm6350_compute_noc_regmap_config = { 1463 + .reg_bits = 32, 1464 + .reg_stride = 4, 1465 + .val_bits = 32, 1466 + .max_register = 0x1f880, 1467 + .fast_io = true, 1468 + }; 1469 + 1705 1470 static const struct qcom_icc_desc sm6350_compute_noc = { 1471 + .config = &sm6350_compute_noc_regmap_config, 1706 1472 .nodes = compute_noc_nodes, 1707 1473 .num_nodes = ARRAY_SIZE(compute_noc_nodes), 1708 1474 .bcms = compute_noc_bcms, ··· 1784 1532 [SLAVE_LLCC_CFG] = &qhs_llcc, 1785 1533 }; 1786 1534 1535 + static const struct regmap_config sm6350_dc_noc_regmap_config = { 1536 + .reg_bits = 32, 1537 + .reg_stride = 4, 1538 + .val_bits = 32, 1539 + .max_register = 0x3200, 1540 + .fast_io = true, 1541 + }; 1542 + 1787 1543 static const struct qcom_icc_desc sm6350_dc_noc = { 1544 + .config = &sm6350_dc_noc_regmap_config, 1788 1545 .nodes = dc_noc_nodes, 1789 1546 .num_nodes = ARRAY_SIZE(dc_noc_nodes), 1790 1547 }; ··· 1822 1561 [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc, 1823 1562 }; 1824 1563 1564 + static const struct regmap_config sm6350_gem_noc_regmap_config = { 1565 + .reg_bits = 32, 1566 + .reg_stride = 4, 1567 + .val_bits = 32, 1568 + .max_register = 0x3e200, 1569 + .fast_io = true, 1570 + }; 1571 + 1825 1572 static const struct qcom_icc_desc sm6350_gem_noc = { 1573 + .config = &sm6350_gem_noc_regmap_config, 1826 1574 .nodes = gem_noc_nodes, 1827 1575 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 1828 1576 .bcms = gem_noc_bcms, ··· 1858 1588 [SLAVE_SERVICE_MNOC] = &srvc_mnoc, 1859 1589 }; 1860 1590 1591 + static const struct regmap_config sm6350_mmss_noc_regmap_config = { 1592 + .reg_bits = 32, 1593 + .reg_stride = 4, 1594 + .val_bits = 32, 1595 + .max_register = 0x1c100, 1596 + .fast_io = true, 1597 + }; 1598 + 1861 1599 static const struct qcom_icc_desc sm6350_mmss_noc = { 1600 + .config = &sm6350_mmss_noc_regmap_config, 1862 1601 .nodes = mmss_noc_nodes, 1863 1602 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 1864 1603 .bcms = mmss_noc_bcms, ··· 1922 1643 [SLAVE_TCU] = &xs_sys_tcu_cfg, 1923 1644 }; 1924 1645 1646 + static const struct regmap_config sm6350_system_noc_regmap_config = { 1647 + .reg_bits = 32, 1648 + .reg_stride = 4, 1649 + .val_bits = 32, 1650 + .max_register = 0x17080, 1651 + .fast_io = true, 1652 + }; 1653 + 1925 1654 static const struct qcom_icc_desc sm6350_system_noc = { 1655 + .config = &sm6350_system_noc_regmap_config, 1926 1656 .nodes = system_noc_nodes, 1927 1657 .num_nodes = ARRAY_SIZE(system_noc_nodes), 1928 1658 .bcms = system_noc_bcms,