Merge tag 'v6.4-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt

+20 -4

Documentation/devicetree/bindings/arm/rockchip.yaml

··· 185 185 - const: firefly,rk3566-roc-pc 186 186 - const: rockchip,rk3566 187 187 188 - - description: FriendlyElec NanoPi R2S 188 + - description: FriendlyElec NanoPi R2 series boards 189 189 items: 190 - - const: friendlyarm,nanopi-r2s 190 + - enum: 191 + - friendlyarm,nanopi-r2c 192 + - friendlyarm,nanopi-r2s 191 193 - const: rockchip,rk3328 192 194 193 195 - description: FriendlyElec NanoPi4 series boards ··· 202 200 - friendlyarm,nanopi-r4s 203 201 - friendlyarm,nanopi-r4s-enterprise 204 202 - const: rockchip,rk3399 203 + 204 + - description: FriendlyElec NanoPi R5 series boards 205 + items: 206 + - enum: 207 + - friendlyarm,nanopi-r5c 208 + - friendlyarm,nanopi-r5s 209 + - const: rockchip,rk3568 205 210 206 211 - description: GeekBuying GeekBox 207 212 items: ··· 542 533 - khadas,edge-v 543 534 - const: rockchip,rk3399 544 535 536 + - description: Khadas Edge2 series boards 537 + items: 538 + - const: khadas,edge2 539 + - const: rockchip,rk3588s 540 + 545 541 - description: Kobol Helios64 546 542 items: 547 543 - const: kobol,helios64 ··· 831 817 - const: tronsmart,orion-r68-meta 832 818 - const: rockchip,rk3368 833 819 834 - - description: Xunlong Orange Pi R1 Plus 820 + - description: Xunlong Orange Pi R1 Plus / LTS 835 821 items: 836 - - const: xunlong,orangepi-r1-plus 822 + - enum: 823 + - xunlong,orangepi-r1-plus 824 + - xunlong,orangepi-r1-plus-lts 837 825 - const: rockchip,rk3328 838 826 839 827 - description: Zkmagic A95X Z2

+1

Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml

··· 29 29 - rockchip,rk3368-wdt 30 30 - rockchip,rk3399-wdt 31 31 - rockchip,rk3568-wdt 32 + - rockchip,rk3588-wdt 32 33 - rockchip,rv1108-wdt 33 34 - const: snps,dw-wdt 34 35

+5

arch/arm64/boot/dts/rockchip/Makefile

··· 14 14 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go3.dtb 15 15 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb 16 16 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb 17 + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb 17 18 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb 18 19 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb 20 + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb 19 21 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb 20 22 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb 21 23 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb ··· 86 84 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb 87 85 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb 88 86 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lubancat-2.dtb 87 + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb 88 + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb 89 89 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb 90 90 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb 91 91 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb 92 92 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb 93 93 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb 94 94 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb 95 + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb 95 96 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb

+10 -2

arch/arm64/boot/dts/rockchip/px30.dtsi

··· 474 474 #address-cells = <1>; 475 475 #size-cells = <0>; 476 476 477 - port@0 { 477 + lvds_in: port@0 { 478 478 reg = <0>; 479 479 #address-cells = <1>; 480 480 #size-cells = <0>; ··· 488 488 reg = <1>; 489 489 remote-endpoint = <&vopl_out_lvds>; 490 490 }; 491 + }; 492 + 493 + lvds_out: port@1 { 494 + reg = <1>; 491 495 }; 492 496 }; 493 497 }; ··· 1138 1134 #address-cells = <1>; 1139 1135 #size-cells = <0>; 1140 1136 1141 - port@0 { 1137 + dsi_in: port@0 { 1142 1138 reg = <0>; 1143 1139 #address-cells = <1>; 1144 1140 #size-cells = <0>; ··· 1152 1148 reg = <1>; 1153 1149 remote-endpoint = <&vopl_out_dsi>; 1154 1150 }; 1151 + }; 1152 + 1153 + dsi_out: port@1 { 1154 + reg = <1>; 1155 1155 }; 1156 1156 }; 1157 1157 };

+4 -1

arch/arm64/boot/dts/rockchip/rk3326-odroid-go3.dts

··· 142 142 }; 143 143 144 144 &internal_display { 145 - status = "disabled"; 145 + compatible = "elida,kd50t048a", "sitronix,st7701"; 146 + reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; 147 + IOVCC-supply = <&vcc_lcd>; 148 + VCC-supply = <&vcc_lcd>; 146 149 }; 147 150 148 151 &rk817_charger {

+40

arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts

··· 1 + // SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2 + /* 3 + * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. 4 + * (http://www.friendlyarm.com) 5 + * 6 + * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com> 7 + */ 8 + 9 + /dts-v1/; 10 + #include "rk3328-nanopi-r2s.dts" 11 + 12 + / { 13 + model = "FriendlyElec NanoPi R2C"; 14 + compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328"; 15 + }; 16 + 17 + &gmac2io { 18 + phy-handle = <&yt8521s>; 19 + tx_delay = <0x22>; 20 + rx_delay = <0x12>; 21 + 22 + mdio { 23 + /delete-node/ ethernet-phy@1; 24 + 25 + yt8521s: ethernet-phy@3 { 26 + compatible = "ethernet-phy-ieee802.3-c22"; 27 + reg = <3>; 28 + 29 + motorcomm,clk-out-frequency-hz = <125000000>; 30 + motorcomm,keep-pll-enabled; 31 + motorcomm,auto-sleep-disabled; 32 + 33 + pinctrl-0 = <&eth_phy_reset_pin>; 34 + pinctrl-names = "default"; 35 + reset-assert-us = <10000>; 36 + reset-deassert-us = <50000>; 37 + reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; 38 + }; 39 + }; 40 + };

+40

arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts

··· 1 + // SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2 + /* 3 + * Copyright (c) 2016 Xunlong Software. Co., Ltd. 4 + * (http://www.orangepi.org) 5 + * 6 + * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com> 7 + */ 8 + 9 + /dts-v1/; 10 + #include "rk3328-orangepi-r1-plus.dts" 11 + 12 + / { 13 + model = "Xunlong Orange Pi R1 Plus LTS"; 14 + compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328"; 15 + }; 16 + 17 + &gmac2io { 18 + phy-handle = <&yt8531c>; 19 + tx_delay = <0x19>; 20 + rx_delay = <0x05>; 21 + 22 + mdio { 23 + /delete-node/ ethernet-phy@1; 24 + 25 + yt8531c: ethernet-phy@0 { 26 + compatible = "ethernet-phy-ieee802.3-c22"; 27 + reg = <0>; 28 + 29 + motorcomm,clk-out-frequency-hz = <125000000>; 30 + motorcomm,keep-pll-enabled; 31 + motorcomm,auto-sleep-disabled; 32 + 33 + pinctrl-0 = <&eth_phy_reset_pin>; 34 + pinctrl-names = "default"; 35 + reset-assert-us = <15000>; 36 + reset-deassert-us = <50000>; 37 + reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; 38 + }; 39 + }; 40 + };

+114

arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts

··· 29 29 stdout-path = "serial2:115200n8"; 30 30 }; 31 31 32 + backlight: backlight { 33 + compatible = "pwm-backlight"; 34 + pwms = <&pwm0 0 50000 0>; 35 + }; 36 + 32 37 gpio-keys { 33 38 compatible = "gpio-keys"; 34 39 pinctrl-names = "default"; ··· 107 102 /* WL_REG_ON on module */ 108 103 reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; 109 104 }; 105 + 106 + /* MIPI DSI panel 1.8v supply */ 107 + vcc1v8_lcd: vcc1v8-lcd { 108 + compatible = "regulator-fixed"; 109 + enable-active-high; 110 + regulator-name = "vcc1v8_lcd"; 111 + regulator-min-microvolt = <1800000>; 112 + regulator-max-microvolt = <1800000>; 113 + vin-supply = <&vcc3v3_sys>; 114 + gpio = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; 115 + pinctrl-names = "default"; 116 + }; 117 + 118 + /* MIPI DSI panel 2.8v supply */ 119 + vcc2v8_lcd: vcc2v8-lcd { 120 + compatible = "regulator-fixed"; 121 + enable-active-high; 122 + regulator-name = "vcc2v8_lcd"; 123 + regulator-min-microvolt = <2800000>; 124 + regulator-max-microvolt = <2800000>; 125 + vin-supply = <&vcc3v3_sys>; 126 + gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; 127 + pinctrl-names = "default"; 128 + }; 110 129 }; 111 130 112 131 &cpu_alert0 { ··· 165 136 }; 166 137 167 138 &emmc_phy { 139 + status = "okay"; 140 + }; 141 + 142 + &gpu { 143 + mali-supply = <&vdd_gpu>; 168 144 status = "okay"; 169 145 }; 170 146 ··· 367 333 }; 368 334 }; 369 335 336 + &i2c3 { 337 + i2c-scl-rising-time-ns = <450>; 338 + i2c-scl-falling-time-ns = <15>; 339 + status = "okay"; 340 + 341 + touchscreen@14 { 342 + compatible = "goodix,gt1158"; 343 + reg = <0x14>; 344 + interrupt-parent = <&gpio3>; 345 + interrupts = <RK_PB5 IRQ_TYPE_EDGE_RISING>; 346 + irq-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>; 347 + reset-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>; 348 + AVDD28-supply = <&vcc3v0_touch>; 349 + VDDIO-supply = <&vcc3v0_touch>; 350 + touchscreen-size-x = <720>; 351 + touchscreen-size-y = <1440>; 352 + }; 353 + }; 354 + 370 355 &cluster0_opp { 371 356 opp04 { 372 357 status = "disabled"; ··· 413 360 sdmmc-supply = <&vccio_sd>; 414 361 gpio1830-supply = <&vcc_3v0>; 415 362 status = "okay"; 363 + }; 364 + 365 + &mipi_dsi { 366 + status = "okay"; 367 + clock-master; 368 + 369 + ports { 370 + mipi_out: port@1 { 371 + #address-cells = <0>; 372 + #size-cells = <0>; 373 + reg = <1>; 374 + 375 + mipi_out_panel: endpoint { 376 + remote-endpoint = <&mipi_in_panel>; 377 + }; 378 + }; 379 + }; 380 + 381 + panel@0 { 382 + compatible = "hannstar,hsd060bhw4"; 383 + reg = <0>; 384 + backlight = <&backlight>; 385 + reset-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_LOW>; 386 + vcc-supply = <&vcc2v8_lcd>; 387 + iovcc-supply = <&vcc1v8_lcd>; 388 + pinctrl-names = "default"; 389 + 390 + port { 391 + mipi_in_panel: endpoint { 392 + remote-endpoint = <&mipi_out_panel>; 393 + }; 394 + }; 395 + }; 416 396 }; 417 397 418 398 &pmu_io_domains { ··· 515 429 status = "okay"; 516 430 }; 517 431 432 + &pwm0 { 433 + status = "okay"; 434 + }; 435 + 518 436 &sdmmc { 519 437 bus-width = <4>; 520 438 cap-sd-highspeed; ··· 567 477 }; 568 478 569 479 &uart2 { 480 + status = "okay"; 481 + }; 482 + 483 + &vopb { 484 + status = "okay"; 485 + assigned-clocks = <&cru DCLK_VOP0_DIV>, <&cru DCLK_VOP0>, 486 + <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 487 + assigned-clock-rates = <0>, <0>, <400000000>, <100000000>; 488 + assigned-clock-parents = <&cru PLL_GPLL>, <&cru DCLK_VOP0_DIV>; 489 + }; 490 + 491 + &vopb_mmu { 492 + status = "okay"; 493 + }; 494 + 495 + &vopl { 496 + status = "okay"; 497 + assigned-clocks = <&cru DCLK_VOP1_DIV>, <&cru DCLK_VOP1>, 498 + <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 499 + assigned-clock-rates = <0>, <0>, <400000000>, <100000000>; 500 + assigned-clock-parents = <&cru PLL_GPLL>, <&cru DCLK_VOP1_DIV>; 501 + }; 502 + 503 + &vopl_mmu { 570 504 status = "okay"; 571 505 };

+17 -3

arch/arm64/boot/dts/rockchip/rk3399.dtsi

··· 1954 1954 }; 1955 1955 }; 1956 1956 1957 - mipi_dsi: mipi@ff960000 { 1957 + mipi_dsi: dsi@ff960000 { 1958 1958 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 1959 1959 reg = <0x0 0xff960000 0x0 0x8000>; 1960 1960 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; ··· 1982 1982 reg = <0>; 1983 1983 remote-endpoint = <&vopb_out_mipi>; 1984 1984 }; 1985 + 1985 1986 mipi_in_vopl: endpoint@1 { 1986 1987 reg = <1>; 1987 1988 remote-endpoint = <&vopl_out_mipi>; 1988 1989 }; 1989 1990 }; 1991 + 1992 + mipi_out: port@1 { 1993 + reg = <1>; 1994 + }; 1990 1995 }; 1991 1996 }; 1992 1997 1993 - mipi_dsi1: mipi@ff968000 { 1998 + mipi_dsi1: dsi@ff968000 { 1994 1999 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 1995 2000 reg = <0x0 0xff968000 0x0 0x8000>; 1996 2001 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>; ··· 2030 2025 remote-endpoint = <&vopl_out_mipi1>; 2031 2026 }; 2032 2027 }; 2028 + 2029 + mipi1_out: port@1 { 2030 + reg = <1>; 2031 + }; 2033 2032 }; 2034 2033 }; 2035 2034 2036 - edp: edp@ff970000 { 2035 + edp: dp@ff970000 { 2037 2036 compatible = "rockchip,rk3399-edp"; 2038 2037 reg = <0x0 0xff970000 0x0 0x8000>; 2039 2038 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; ··· 2054 2045 ports { 2055 2046 #address-cells = <1>; 2056 2047 #size-cells = <0>; 2048 + 2057 2049 edp_in: port@0 { 2058 2050 reg = <0>; 2059 2051 #address-cells = <1>; ··· 2069 2059 reg = <1>; 2070 2060 remote-endpoint = <&vopl_out_edp>; 2071 2061 }; 2062 + }; 2063 + 2064 + edp_out: port@1 { 2065 + reg = <1>; 2072 2066 }; 2073 2067 }; 2074 2068 };

+1 -1

arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts

··· 495 495 }; 496 496 497 497 &usb2phy0_otg { 498 - vbus-supply = <&vcc5v0_usb2_otg>; 498 + phy-supply = <&vcc5v0_usb2_otg>; 499 499 status = "okay"; 500 500 }; 501 501

+8

arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts

··· 254 254 status = "okay"; 255 255 }; 256 256 257 + &usb2phy0_otg { 258 + status = "okay"; 259 + }; 260 + 261 + &usb_host0_xhci { 262 + status = "okay"; 263 + }; 264 + 257 265 &vop { 258 266 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; 259 267 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;

+112

arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts

··· 1 + // SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2 + /* 3 + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. 4 + * (http://www.friendlyelec.com) 5 + * 6 + * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com> 7 + */ 8 + 9 + /dts-v1/; 10 + #include "rk3568-nanopi-r5s.dtsi" 11 + 12 + / { 13 + model = "FriendlyElec NanoPi R5C"; 14 + compatible = "friendlyarm,nanopi-r5c", "rockchip,rk3568"; 15 + 16 + gpio-keys { 17 + compatible = "gpio-keys"; 18 + pinctrl-names = "default"; 19 + pinctrl-0 = <&reset_button_pin>; 20 + 21 + button-reset { 22 + debounce-interval = <50>; 23 + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; 24 + label = "reset"; 25 + linux,code = <KEY_RESTART>; 26 + }; 27 + }; 28 + 29 + gpio-leds { 30 + compatible = "gpio-leds"; 31 + pinctrl-names = "default"; 32 + pinctrl-0 = <&lan_led_pin>, <&power_led_pin>, <&wan_led_pin>, <&wlan_led_pin>; 33 + 34 + led-lan { 35 + color = <LED_COLOR_ID_GREEN>; 36 + function = LED_FUNCTION_LAN; 37 + gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; 38 + }; 39 + 40 + power_led: led-power { 41 + color = <LED_COLOR_ID_RED>; 42 + function = LED_FUNCTION_POWER; 43 + linux,default-trigger = "heartbeat"; 44 + gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; 45 + }; 46 + 47 + led-wan { 48 + color = <LED_COLOR_ID_GREEN>; 49 + function = LED_FUNCTION_WAN; 50 + gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; 51 + }; 52 + 53 + led-wlan { 54 + color = <LED_COLOR_ID_GREEN>; 55 + function = LED_FUNCTION_WLAN; 56 + gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; 57 + }; 58 + }; 59 + }; 60 + 61 + &pcie2x1 { 62 + pinctrl-names = "default"; 63 + pinctrl-0 = <&pcie20_reset_pin>; 64 + reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; 65 + status = "okay"; 66 + }; 67 + 68 + &pcie3x1 { 69 + num-lanes = <1>; 70 + reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; 71 + vpcie3v3-supply = <&vcc3v3_pcie>; 72 + status = "okay"; 73 + }; 74 + 75 + &pcie3x2 { 76 + num-lanes = <1>; 77 + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; 78 + vpcie3v3-supply = <&vcc3v3_pcie>; 79 + status = "okay"; 80 + }; 81 + 82 + &pinctrl { 83 + gpio-leds { 84 + lan_led_pin: lan-led-pin { 85 + rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; 86 + }; 87 + 88 + power_led_pin: power-led-pin { 89 + rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; 90 + }; 91 + 92 + wan_led_pin: wan-led-pin { 93 + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; 94 + }; 95 + 96 + wlan_led_pin: wlan-led-pin { 97 + rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 98 + }; 99 + }; 100 + 101 + pcie { 102 + pcie20_reset_pin: pcie20-reset-pin { 103 + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; 104 + }; 105 + }; 106 + 107 + rockchip-key { 108 + reset_button_pin: reset-button-pin { 109 + rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; 110 + }; 111 + }; 112 + };

+137

arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts

··· 1 + // SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2 + /* 3 + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. 4 + * (http://www.friendlyelec.com) 5 + * 6 + * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com> 7 + */ 8 + 9 + /dts-v1/; 10 + #include "rk3568-nanopi-r5s.dtsi" 11 + 12 + / { 13 + model = "FriendlyElec NanoPi R5S"; 14 + compatible = "friendlyarm,nanopi-r5s", "rockchip,rk3568"; 15 + 16 + aliases { 17 + ethernet0 = &gmac0; 18 + }; 19 + 20 + gpio-leds { 21 + compatible = "gpio-leds"; 22 + pinctrl-names = "default"; 23 + pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, <&power_led_pin>, <&wan_led_pin>; 24 + 25 + led-lan1 { 26 + color = <LED_COLOR_ID_GREEN>; 27 + function = LED_FUNCTION_LAN; 28 + function-enumerator = <1>; 29 + gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; 30 + }; 31 + 32 + led-lan2 { 33 + color = <LED_COLOR_ID_GREEN>; 34 + function = LED_FUNCTION_LAN; 35 + function-enumerator = <2>; 36 + gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>; 37 + }; 38 + 39 + power_led: led-power { 40 + color = <LED_COLOR_ID_RED>; 41 + function = LED_FUNCTION_POWER; 42 + linux,default-trigger = "heartbeat"; 43 + gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; 44 + }; 45 + 46 + led-wan { 47 + color = <LED_COLOR_ID_GREEN>; 48 + function = LED_FUNCTION_WAN; 49 + gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; 50 + }; 51 + }; 52 + }; 53 + 54 + &gmac0 { 55 + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; 56 + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; 57 + assigned-clock-rates = <0>, <125000000>; 58 + clock_in_out = "output"; 59 + phy-handle = <&rgmii_phy0>; 60 + phy-mode = "rgmii"; 61 + pinctrl-names = "default"; 62 + pinctrl-0 = <&gmac0_miim 63 + &gmac0_tx_bus2 64 + &gmac0_rx_bus2 65 + &gmac0_rgmii_clk 66 + &gmac0_rgmii_bus>; 67 + snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>; 68 + snps,reset-active-low; 69 + /* Reset time is 15ms, 50ms for rtl8211f */ 70 + snps,reset-delays-us = <0 15000 50000>; 71 + tx_delay = <0x3c>; 72 + rx_delay = <0x2f>; 73 + status = "okay"; 74 + }; 75 + 76 + &mdio0 { 77 + rgmii_phy0: ethernet-phy@1 { 78 + compatible = "ethernet-phy-ieee802.3-c22"; 79 + reg = <1>; 80 + pinctrl-0 = <&eth_phy0_reset_pin>; 81 + pinctrl-names = "default"; 82 + }; 83 + }; 84 + 85 + &pcie2x1 { 86 + num-lanes = <1>; 87 + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; 88 + status = "okay"; 89 + }; 90 + 91 + &pcie30phy { 92 + data-lanes = <1 2>; 93 + status = "okay"; 94 + }; 95 + 96 + &pcie3x1 { 97 + num-lanes = <1>; 98 + reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; 99 + vpcie3v3-supply = <&vcc3v3_pcie>; 100 + status = "okay"; 101 + }; 102 + 103 + &pcie3x2 { 104 + num-lanes = <1>; 105 + num-ib-windows = <8>; 106 + num-ob-windows = <8>; 107 + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; 108 + vpcie3v3-supply = <&vcc3v3_pcie>; 109 + status = "okay"; 110 + }; 111 + 112 + &pinctrl { 113 + gmac0 { 114 + eth_phy0_reset_pin: eth-phy0-reset-pin { 115 + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; 116 + }; 117 + }; 118 + 119 + gpio-leds { 120 + lan1_led_pin: lan1-led-pin { 121 + rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; 122 + }; 123 + 124 + lan2_led_pin: lan2-led-pin { 125 + rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; 126 + }; 127 + 128 + power_led_pin: power-led-pin { 129 + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 130 + }; 131 + 132 + wan_led_pin: wan-led-pin { 133 + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; 134 + }; 135 + }; 136 + }; 137 +

+590

arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi

··· 1 + // SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2 + /* 3 + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. 4 + * (http://www.friendlyelec.com) 5 + * 6 + * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com> 7 + */ 8 + 9 + /dts-v1/; 10 + #include <dt-bindings/gpio/gpio.h> 11 + #include <dt-bindings/input/input.h> 12 + #include <dt-bindings/leds/common.h> 13 + #include <dt-bindings/pinctrl/rockchip.h> 14 + #include <dt-bindings/soc/rockchip,vop2.h> 15 + #include "rk3568.dtsi" 16 + 17 + / { 18 + aliases { 19 + mmc0 = &sdmmc0; 20 + mmc1 = &sdhci; 21 + }; 22 + 23 + chosen: chosen { 24 + stdout-path = "serial2:1500000n8"; 25 + }; 26 + 27 + hdmi-con { 28 + compatible = "hdmi-connector"; 29 + type = "a"; 30 + 31 + port { 32 + hdmi_con_in: endpoint { 33 + remote-endpoint = <&hdmi_out_con>; 34 + }; 35 + }; 36 + }; 37 + 38 + vdd_usbc: vdd-usbc-regulator { 39 + compatible = "regulator-fixed"; 40 + regulator-name = "vdd_usbc"; 41 + regulator-always-on; 42 + regulator-boot-on; 43 + regulator-min-microvolt = <5000000>; 44 + regulator-max-microvolt = <5000000>; 45 + }; 46 + 47 + vcc3v3_sys: vcc3v3-sys-regulator { 48 + compatible = "regulator-fixed"; 49 + regulator-name = "vcc3v3_sys"; 50 + regulator-always-on; 51 + regulator-boot-on; 52 + regulator-min-microvolt = <3300000>; 53 + regulator-max-microvolt = <3300000>; 54 + vin-supply = <&vdd_usbc>; 55 + }; 56 + 57 + vcc5v0_sys: vcc5v0-sys-regulator { 58 + compatible = "regulator-fixed"; 59 + regulator-name = "vcc5v0_sys"; 60 + regulator-always-on; 61 + regulator-boot-on; 62 + regulator-min-microvolt = <5000000>; 63 + regulator-max-microvolt = <5000000>; 64 + vin-supply = <&vdd_usbc>; 65 + }; 66 + 67 + vcc3v3_pcie: vcc3v3-pcie-regulator { 68 + compatible = "regulator-fixed"; 69 + regulator-name = "vcc3v3_pcie"; 70 + regulator-min-microvolt = <3300000>; 71 + regulator-max-microvolt = <3300000>; 72 + enable-active-high; 73 + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; 74 + startup-delay-us = <200000>; 75 + vin-supply = <&vcc5v0_sys>; 76 + }; 77 + 78 + vcc5v0_usb: vcc5v0-usb-regulator { 79 + compatible = "regulator-fixed"; 80 + regulator-name = "vcc5v0_usb"; 81 + regulator-always-on; 82 + regulator-boot-on; 83 + regulator-min-microvolt = <5000000>; 84 + regulator-max-microvolt = <5000000>; 85 + vin-supply = <&vdd_usbc>; 86 + }; 87 + 88 + vcc5v0_usb_host: vcc5v0-usb-host-regulator { 89 + compatible = "regulator-fixed"; 90 + enable-active-high; 91 + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; 92 + pinctrl-names = "default"; 93 + pinctrl-0 = <&vcc5v0_usb_host_en>; 94 + regulator-name = "vcc5v0_usb_host"; 95 + regulator-always-on; 96 + regulator-boot-on; 97 + regulator-min-microvolt = <5000000>; 98 + regulator-max-microvolt = <5000000>; 99 + vin-supply = <&vcc5v0_usb>; 100 + }; 101 + 102 + vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { 103 + compatible = "regulator-fixed"; 104 + enable-active-high; 105 + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; 106 + pinctrl-names = "default"; 107 + pinctrl-0 = <&vcc5v0_usb_otg_en>; 108 + regulator-name = "vcc5v0_usb_otg"; 109 + regulator-min-microvolt = <5000000>; 110 + regulator-max-microvolt = <5000000>; 111 + vin-supply = <&vcc5v0_usb>; 112 + }; 113 + 114 + pcie30_avdd0v9: pcie30-avdd0v9-regulator { 115 + compatible = "regulator-fixed"; 116 + regulator-name = "pcie30_avdd0v9"; 117 + regulator-always-on; 118 + regulator-boot-on; 119 + regulator-min-microvolt = <900000>; 120 + regulator-max-microvolt = <900000>; 121 + vin-supply = <&vcc3v3_sys>; 122 + }; 123 + 124 + pcie30_avdd1v8: pcie30-avdd1v8-regulator { 125 + compatible = "regulator-fixed"; 126 + regulator-name = "pcie30_avdd1v8"; 127 + regulator-always-on; 128 + regulator-boot-on; 129 + regulator-min-microvolt = <1800000>; 130 + regulator-max-microvolt = <1800000>; 131 + vin-supply = <&vcc3v3_sys>; 132 + }; 133 + }; 134 + 135 + &combphy0 { 136 + status = "okay"; 137 + }; 138 + 139 + &combphy1 { 140 + status = "okay"; 141 + }; 142 + 143 + &combphy2 { 144 + status = "okay"; 145 + }; 146 + 147 + &cpu0 { 148 + cpu-supply = <&vdd_cpu>; 149 + }; 150 + 151 + &cpu1 { 152 + cpu-supply = <&vdd_cpu>; 153 + }; 154 + 155 + &cpu2 { 156 + cpu-supply = <&vdd_cpu>; 157 + }; 158 + 159 + &cpu3 { 160 + cpu-supply = <&vdd_cpu>; 161 + }; 162 + 163 + &gpu { 164 + mali-supply = <&vdd_gpu>; 165 + status = "okay"; 166 + }; 167 + 168 + &hdmi { 169 + avdd-0v9-supply = <&vdda0v9_image>; 170 + avdd-1v8-supply = <&vcca1v8_image>; 171 + status = "okay"; 172 + }; 173 + 174 + &hdmi_in { 175 + hdmi_in_vp0: endpoint { 176 + remote-endpoint = <&vp0_out_hdmi>; 177 + }; 178 + }; 179 + 180 + &hdmi_out { 181 + hdmi_out_con: endpoint { 182 + remote-endpoint = <&hdmi_con_in>; 183 + }; 184 + }; 185 + 186 + &hdmi_sound { 187 + status = "okay"; 188 + }; 189 + 190 + &i2c0 { 191 + status = "okay"; 192 + 193 + vdd_cpu: regulator@1c { 194 + compatible = "tcs,tcs4525"; 195 + reg = <0x1c>; 196 + fcs,suspend-voltage-selector = <1>; 197 + regulator-name = "vdd_cpu"; 198 + regulator-always-on; 199 + regulator-boot-on; 200 + regulator-min-microvolt = <800000>; 201 + regulator-max-microvolt = <1150000>; 202 + regulator-ramp-delay = <2300>; 203 + vin-supply = <&vcc5v0_sys>; 204 + 205 + regulator-state-mem { 206 + regulator-off-in-suspend; 207 + }; 208 + }; 209 + 210 + rk809: pmic@20 { 211 + compatible = "rockchip,rk809"; 212 + reg = <0x20>; 213 + interrupt-parent = <&gpio0>; 214 + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; 215 + #clock-cells = <1>; 216 + pinctrl-names = "default"; 217 + pinctrl-0 = <&pmic_int>; 218 + rockchip,system-power-controller; 219 + vcc1-supply = <&vcc3v3_sys>; 220 + vcc2-supply = <&vcc3v3_sys>; 221 + vcc3-supply = <&vcc3v3_sys>; 222 + vcc4-supply = <&vcc3v3_sys>; 223 + vcc5-supply = <&vcc3v3_sys>; 224 + vcc6-supply = <&vcc3v3_sys>; 225 + vcc7-supply = <&vcc3v3_sys>; 226 + vcc8-supply = <&vcc3v3_sys>; 227 + vcc9-supply = <&vcc3v3_sys>; 228 + wakeup-source; 229 + 230 + regulators { 231 + vdd_logic: DCDC_REG1 { 232 + regulator-name = "vdd_logic"; 233 + regulator-always-on; 234 + regulator-boot-on; 235 + regulator-init-microvolt = <900000>; 236 + regulator-initial-mode = <0x2>; 237 + regulator-min-microvolt = <500000>; 238 + regulator-max-microvolt = <1350000>; 239 + regulator-ramp-delay = <6001>; 240 + 241 + regulator-state-mem { 242 + regulator-off-in-suspend; 243 + }; 244 + }; 245 + 246 + vdd_gpu: DCDC_REG2 { 247 + regulator-name = "vdd_gpu"; 248 + regulator-always-on; 249 + regulator-init-microvolt = <900000>; 250 + regulator-initial-mode = <0x2>; 251 + regulator-min-microvolt = <500000>; 252 + regulator-max-microvolt = <1350000>; 253 + regulator-ramp-delay = <6001>; 254 + 255 + regulator-state-mem { 256 + regulator-off-in-suspend; 257 + }; 258 + }; 259 + 260 + vcc_ddr: DCDC_REG3 { 261 + regulator-name = "vcc_ddr"; 262 + regulator-always-on; 263 + regulator-boot-on; 264 + regulator-initial-mode = <0x2>; 265 + 266 + regulator-state-mem { 267 + regulator-on-in-suspend; 268 + }; 269 + }; 270 + 271 + vdd_npu: DCDC_REG4 { 272 + regulator-name = "vdd_npu"; 273 + regulator-init-microvolt = <900000>; 274 + regulator-initial-mode = <0x2>; 275 + regulator-min-microvolt = <500000>; 276 + regulator-max-microvolt = <1350000>; 277 + regulator-ramp-delay = <6001>; 278 + 279 + regulator-state-mem { 280 + regulator-off-in-suspend; 281 + }; 282 + }; 283 + 284 + vcc_1v8: DCDC_REG5 { 285 + regulator-name = "vcc_1v8"; 286 + regulator-always-on; 287 + regulator-boot-on; 288 + regulator-min-microvolt = <1800000>; 289 + regulator-max-microvolt = <1800000>; 290 + 291 + regulator-state-mem { 292 + regulator-off-in-suspend; 293 + }; 294 + }; 295 + 296 + vdda0v9_image: LDO_REG1 { 297 + regulator-name = "vdda0v9_image"; 298 + regulator-min-microvolt = <950000>; 299 + regulator-max-microvolt = <950000>; 300 + 301 + regulator-state-mem { 302 + regulator-off-in-suspend; 303 + }; 304 + }; 305 + 306 + vdda_0v9: LDO_REG2 { 307 + regulator-name = "vdda_0v9"; 308 + regulator-always-on; 309 + regulator-boot-on; 310 + regulator-min-microvolt = <900000>; 311 + regulator-max-microvolt = <900000>; 312 + 313 + regulator-state-mem { 314 + regulator-off-in-suspend; 315 + }; 316 + }; 317 + 318 + vdda0v9_pmu: LDO_REG3 { 319 + regulator-name = "vdda0v9_pmu"; 320 + regulator-always-on; 321 + regulator-boot-on; 322 + regulator-min-microvolt = <900000>; 323 + regulator-max-microvolt = <900000>; 324 + 325 + regulator-state-mem { 326 + regulator-on-in-suspend; 327 + regulator-suspend-microvolt = <900000>; 328 + }; 329 + }; 330 + 331 + vccio_acodec: LDO_REG4 { 332 + regulator-name = "vccio_acodec"; 333 + regulator-min-microvolt = <3300000>; 334 + regulator-max-microvolt = <3300000>; 335 + 336 + regulator-state-mem { 337 + regulator-off-in-suspend; 338 + }; 339 + }; 340 + 341 + vccio_sd: LDO_REG5 { 342 + regulator-name = "vccio_sd"; 343 + regulator-min-microvolt = <1800000>; 344 + regulator-max-microvolt = <3300000>; 345 + 346 + regulator-state-mem { 347 + regulator-off-in-suspend; 348 + }; 349 + }; 350 + 351 + vcc3v3_pmu: LDO_REG6 { 352 + regulator-name = "vcc3v3_pmu"; 353 + regulator-always-on; 354 + regulator-boot-on; 355 + regulator-min-microvolt = <3300000>; 356 + regulator-max-microvolt = <3300000>; 357 + 358 + regulator-state-mem { 359 + regulator-on-in-suspend; 360 + regulator-suspend-microvolt = <3300000>; 361 + }; 362 + }; 363 + 364 + vcca_1v8: LDO_REG7 { 365 + regulator-name = "vcca_1v8"; 366 + regulator-always-on; 367 + regulator-boot-on; 368 + regulator-min-microvolt = <1800000>; 369 + regulator-max-microvolt = <1800000>; 370 + 371 + regulator-state-mem { 372 + regulator-off-in-suspend; 373 + }; 374 + }; 375 + 376 + vcca1v8_pmu: LDO_REG8 { 377 + regulator-name = "vcca1v8_pmu"; 378 + regulator-always-on; 379 + regulator-boot-on; 380 + regulator-min-microvolt = <1800000>; 381 + regulator-max-microvolt = <1800000>; 382 + 383 + regulator-state-mem { 384 + regulator-on-in-suspend; 385 + regulator-suspend-microvolt = <1800000>; 386 + }; 387 + }; 388 + 389 + vcca1v8_image: LDO_REG9 { 390 + regulator-name = "vcca1v8_image"; 391 + regulator-min-microvolt = <1800000>; 392 + regulator-max-microvolt = <1800000>; 393 + 394 + regulator-state-mem { 395 + regulator-off-in-suspend; 396 + }; 397 + }; 398 + 399 + vcc_3v3: SWITCH_REG1 { 400 + regulator-name = "vcc_3v3"; 401 + regulator-always-on; 402 + regulator-boot-on; 403 + 404 + regulator-state-mem { 405 + regulator-off-in-suspend; 406 + }; 407 + }; 408 + 409 + vcc3v3_sd: SWITCH_REG2 { 410 + regulator-name = "vcc3v3_sd"; 411 + regulator-always-on; 412 + regulator-boot-on; 413 + 414 + regulator-state-mem { 415 + regulator-off-in-suspend; 416 + }; 417 + }; 418 + }; 419 + 420 + }; 421 + }; 422 + 423 + &i2c5 { 424 + status = "okay"; 425 + 426 + hym8563: rtc@51 { 427 + compatible = "haoyu,hym8563"; 428 + reg = <0x51>; 429 + interrupt-parent = <&gpio0>; 430 + interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>; 431 + #clock-cells = <0>; 432 + clock-output-names = "rtcic_32kout"; 433 + pinctrl-names = "default"; 434 + pinctrl-0 = <&hym8563_int>; 435 + wakeup-source; 436 + }; 437 + }; 438 + 439 + &i2s0_8ch { 440 + status = "okay"; 441 + }; 442 + 443 + &pcie30phy { 444 + data-lanes = <1 2>; 445 + status = "okay"; 446 + }; 447 + 448 + &pinctrl { 449 + hym8563 { 450 + hym8563_int: hym8563-int { 451 + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; 452 + }; 453 + }; 454 + 455 + pmic { 456 + pmic_int: pmic-int { 457 + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; 458 + }; 459 + }; 460 + 461 + usb { 462 + vcc5v0_usb_host_en: vcc5v0-usb-host-en { 463 + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 464 + }; 465 + 466 + vcc5v0_usb_otg_en: vcc5v0-usb-otg-en { 467 + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 468 + }; 469 + }; 470 + }; 471 + 472 + &pmu_io_domains { 473 + pmuio1-supply = <&vcc3v3_pmu>; 474 + pmuio2-supply = <&vcc3v3_pmu>; 475 + vccio1-supply = <&vccio_acodec>; 476 + vccio3-supply = <&vccio_sd>; 477 + vccio4-supply = <&vcc_1v8>; 478 + vccio5-supply = <&vcc_3v3>; 479 + vccio6-supply = <&vcc_1v8>; 480 + vccio7-supply = <&vcc_3v3>; 481 + status = "okay"; 482 + }; 483 + 484 + &saradc { 485 + vref-supply = <&vcca_1v8>; 486 + status = "okay"; 487 + }; 488 + 489 + &sdhci { 490 + bus-width = <8>; 491 + max-frequency = <200000000>; 492 + non-removable; 493 + pinctrl-names = "default"; 494 + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; 495 + status = "okay"; 496 + }; 497 + 498 + &sdmmc0 { 499 + max-frequency = <150000000>; 500 + no-sdio; 501 + no-mmc; 502 + bus-width = <4>; 503 + cap-mmc-highspeed; 504 + cap-sd-highspeed; 505 + disable-wp; 506 + vmmc-supply = <&vcc3v3_sd>; 507 + vqmmc-supply = <&vccio_sd>; 508 + pinctrl-names = "default"; 509 + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; 510 + status = "okay"; 511 + }; 512 + 513 + &tsadc { 514 + rockchip,hw-tshut-mode = <1>; 515 + rockchip,hw-tshut-polarity = <0>; 516 + status = "okay"; 517 + }; 518 + 519 + &uart2 { 520 + status = "okay"; 521 + }; 522 + 523 + &usb_host0_ehci { 524 + status = "okay"; 525 + }; 526 + 527 + &usb_host0_ohci { 528 + status = "okay"; 529 + }; 530 + 531 + &usb_host0_xhci { 532 + extcon = <&usb2phy0>; 533 + dr_mode = "host"; 534 + status = "okay"; 535 + }; 536 + 537 + &usb_host1_ehci { 538 + status = "okay"; 539 + }; 540 + 541 + &usb_host1_ohci { 542 + status = "okay"; 543 + }; 544 + 545 + &usb_host1_xhci { 546 + status = "okay"; 547 + }; 548 + 549 + &usb2phy0 { 550 + status = "okay"; 551 + }; 552 + 553 + &usb2phy0_host { 554 + phy-supply = <&vcc5v0_usb_host>; 555 + status = "okay"; 556 + }; 557 + 558 + &usb2phy0_otg { 559 + status = "okay"; 560 + }; 561 + 562 + &usb2phy1 { 563 + status = "okay"; 564 + }; 565 + 566 + &usb2phy1_host { 567 + phy-supply = <&vcc5v0_usb_otg>; 568 + status = "okay"; 569 + }; 570 + 571 + &usb2phy1_otg { 572 + status = "okay"; 573 + }; 574 + 575 + &vop { 576 + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; 577 + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; 578 + status = "okay"; 579 + }; 580 + 581 + &vop_mmu { 582 + status = "okay"; 583 + }; 584 + 585 + &vp0 { 586 + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { 587 + reg = <ROCKCHIP_VOP2_EP_HDMI0>; 588 + remote-endpoint = <&hdmi_in_vp0>; 589 + }; 590 + };

+4 -4

arch/arm64/boot/dts/rockchip/rk356x.dtsi

··· 744 744 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; 745 745 reg = <0x00 0xfe060000 0x00 0x10000>; 746 746 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 747 - clock-names = "pclk", "hclk"; 748 - clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>; 747 + clock-names = "pclk"; 748 + clocks = <&cru PCLK_DSITX_0>; 749 749 phy-names = "dphy"; 750 750 phys = <&dsi_dphy0>; 751 751 power-domains = <&power RK3568_PD_VO>; ··· 772 772 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; 773 773 reg = <0x0 0xfe070000 0x0 0x10000>; 774 774 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 775 - clock-names = "pclk", "hclk"; 776 - clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>; 775 + clock-names = "pclk"; 776 + clocks = <&cru PCLK_DSITX_1>; 777 777 phy-names = "dphy"; 778 778 phys = <&dsi_dphy1>; 779 779 power-domains = <&power RK3568_PD_VO>;

+97

arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts

··· 2 2 3 3 /dts-v1/; 4 4 5 + #include <dt-bindings/gpio/gpio.h> 5 6 #include "rk3588.dtsi" 6 7 7 8 / { ··· 18 17 stdout-path = "serial2:1500000n8"; 19 18 }; 20 19 20 + fan: pwm-fan { 21 + compatible = "pwm-fan"; 22 + cooling-levels = <0 95 145 195 255>; 23 + fan-supply = <&vcc5v0_sys>; 24 + pwms = <&pwm1 0 50000 0>; 25 + #cooling-cells = <2>; 26 + }; 27 + 28 + sound { 29 + compatible = "audio-graph-card"; 30 + label = "Analog"; 31 + 32 + widgets = "Microphone", "Mic Jack", 33 + "Headphone", "Headphones"; 34 + 35 + routing = "MIC2", "Mic Jack", 36 + "Headphones", "HPOL", 37 + "Headphones", "HPOR"; 38 + 39 + dais = <&i2s0_8ch_p0>; 40 + hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; 41 + pinctrl-names = "default"; 42 + pinctrl-0 = <&hp_detect>; 43 + }; 44 + 21 45 vcc5v0_sys: vcc5v0-sys-regulator { 22 46 compatible = "regulator-fixed"; 23 47 regulator-name = "vcc5v0_sys"; ··· 51 25 regulator-min-microvolt = <5000000>; 52 26 regulator-max-microvolt = <5000000>; 53 27 }; 28 + }; 29 + 30 + &i2c6 { 31 + status = "okay"; 32 + 33 + hym8563: rtc@51 { 34 + compatible = "haoyu,hym8563"; 35 + reg = <0x51>; 36 + #clock-cells = <0>; 37 + clock-frequency = <32768>; 38 + clock-output-names = "hym8563"; 39 + pinctrl-names = "default"; 40 + pinctrl-0 = <&hym8563_int>; 41 + interrupt-parent = <&gpio0>; 42 + interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; 43 + wakeup-source; 44 + }; 45 + }; 46 + 47 + &i2c7 { 48 + status = "okay"; 49 + 50 + es8316: es8316@11 { 51 + compatible = "everest,es8316"; 52 + reg = <0x11>; 53 + clocks = <&cru I2S0_8CH_MCLKOUT>; 54 + clock-names = "mclk"; 55 + #sound-dai-cells = <0>; 56 + 57 + port { 58 + es8316_p0_0: endpoint { 59 + remote-endpoint = <&i2s0_8ch_p0_0>; 60 + }; 61 + }; 62 + }; 63 + }; 64 + 65 + &i2s0_8ch { 66 + pinctrl-names = "default"; 67 + pinctrl-0 = <&i2s0_lrck 68 + &i2s0_mclk 69 + &i2s0_sclk 70 + &i2s0_sdi0 71 + &i2s0_sdo0>; 72 + status = "okay"; 73 + 74 + i2s0_8ch_p0: port { 75 + i2s0_8ch_p0_0: endpoint { 76 + dai-format = "i2s"; 77 + mclk-fs = <256>; 78 + remote-endpoint = <&es8316_p0_0>; 79 + }; 80 + }; 81 + }; 82 + 83 + &pinctrl { 84 + hym8563 { 85 + hym8563_int: hym8563-int { 86 + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; 87 + }; 88 + }; 89 + 90 + sound { 91 + hp_detect: hp-detect { 92 + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; 93 + }; 94 + }; 95 + }; 96 + 97 + &pwm1 { 98 + status = "okay"; 54 99 }; 55 100 56 101 &sdhci {

+68

arch/arm64/boot/dts/rockchip/rk3588.dtsi

··· 7 7 #include "rk3588-pinctrl.dtsi" 8 8 9 9 / { 10 + i2s8_8ch: i2s@fddc8000 { 11 + compatible = "rockchip,rk3588-i2s-tdm"; 12 + reg = <0x0 0xfddc8000 0x0 0x1000>; 13 + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>; 14 + clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>; 15 + clock-names = "mclk_tx", "mclk_rx", "hclk"; 16 + assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>; 17 + assigned-clock-parents = <&cru PLL_AUPLL>; 18 + dmas = <&dmac2 22>; 19 + dma-names = "tx"; 20 + power-domains = <&power RK3588_PD_VO0>; 21 + resets = <&cru SRST_M_I2S8_8CH_TX>; 22 + reset-names = "tx-m"; 23 + #sound-dai-cells = <0>; 24 + status = "disabled"; 25 + }; 26 + 27 + i2s6_8ch: i2s@fddf4000 { 28 + compatible = "rockchip,rk3588-i2s-tdm"; 29 + reg = <0x0 0xfddf4000 0x0 0x1000>; 30 + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>; 31 + clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>; 32 + clock-names = "mclk_tx", "mclk_rx", "hclk"; 33 + assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>; 34 + assigned-clock-parents = <&cru PLL_AUPLL>; 35 + dmas = <&dmac2 4>; 36 + dma-names = "tx"; 37 + power-domains = <&power RK3588_PD_VO1>; 38 + resets = <&cru SRST_M_I2S6_8CH_TX>; 39 + reset-names = "tx-m"; 40 + #sound-dai-cells = <0>; 41 + status = "disabled"; 42 + }; 43 + 44 + i2s7_8ch: i2s@fddf8000 { 45 + compatible = "rockchip,rk3588-i2s-tdm"; 46 + reg = <0x0 0xfddf8000 0x0 0x1000>; 47 + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>; 48 + clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>; 49 + clock-names = "mclk_tx", "mclk_rx", "hclk"; 50 + assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>; 51 + assigned-clock-parents = <&cru PLL_AUPLL>; 52 + dmas = <&dmac2 21>; 53 + dma-names = "rx"; 54 + power-domains = <&power RK3588_PD_VO1>; 55 + resets = <&cru SRST_M_I2S7_8CH_RX>; 56 + reset-names = "rx-m"; 57 + #sound-dai-cells = <0>; 58 + status = "disabled"; 59 + }; 60 + 61 + i2s10_8ch: i2s@fde00000 { 62 + compatible = "rockchip,rk3588-i2s-tdm"; 63 + reg = <0x0 0xfde00000 0x0 0x1000>; 64 + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>; 65 + clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>; 66 + clock-names = "mclk_tx", "mclk_rx", "hclk"; 67 + assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>; 68 + assigned-clock-parents = <&cru PLL_AUPLL>; 69 + dmas = <&dmac2 24>; 70 + dma-names = "rx"; 71 + power-domains = <&power RK3588_PD_VO1>; 72 + resets = <&cru SRST_M_I2S10_8CH_RX>; 73 + reset-names = "rx-m"; 74 + #sound-dai-cells = <0>; 75 + status = "disabled"; 76 + }; 77 + 10 78 gmac0: ethernet@fe1b0000 { 11 79 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; 12 80 reg = <0x0 0xfe1b0000 0x0 0x10000>;

+37

arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts

··· 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 + 3 + /dts-v1/; 4 + 5 + #include <dt-bindings/gpio/gpio.h> 6 + #include <dt-bindings/pinctrl/rockchip.h> 7 + #include "rk3588s.dtsi" 8 + 9 + / { 10 + model = "Khadas Edge2"; 11 + compatible = "khadas,edge2", "rockchip,rk3588s"; 12 + 13 + aliases { 14 + mmc0 = &sdhci; 15 + serial2 = &uart2; 16 + }; 17 + 18 + chosen { 19 + stdout-path = "serial2:1500000n8"; 20 + }; 21 + }; 22 + 23 + &sdhci { 24 + bus-width = <8>; 25 + no-sdio; 26 + no-sd; 27 + non-removable; 28 + max-frequency = <200000000>; 29 + mmc-hs400-1_8v; 30 + mmc-hs400-enhanced-strobe; 31 + status = "okay"; 32 + }; 33 + 34 + &uart2 { 35 + pinctrl-0 = <&uart2m0_xfer>; 36 + status = "okay"; 37 + };

+198 -5

arch/arm64/boot/dts/rockchip/rk3588s.dtsi

··· 60 60 enable-method = "psci"; 61 61 capacity-dmips-mhz = <530>; 62 62 clocks = <&scmi_clk SCMI_CLK_CPUL>; 63 + assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>; 64 + assigned-clock-rates = <816000000>; 63 65 cpu-idle-states = <&CPU_SLEEP>; 64 66 i-cache-size = <32768>; 65 67 i-cache-line-size = <64>; ··· 138 136 enable-method = "psci"; 139 137 capacity-dmips-mhz = <1024>; 140 138 clocks = <&scmi_clk SCMI_CLK_CPUB01>; 139 + assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>; 140 + assigned-clock-rates = <816000000>; 141 141 cpu-idle-states = <&CPU_SLEEP>; 142 142 i-cache-size = <65536>; 143 143 i-cache-line-size = <64>; ··· 178 174 enable-method = "psci"; 179 175 capacity-dmips-mhz = <1024>; 180 176 clocks = <&scmi_clk SCMI_CLK_CPUB23>; 177 + assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>; 178 + assigned-clock-rates = <816000000>; 181 179 cpu-idle-states = <&CPU_SLEEP>; 182 180 i-cache-size = <65536>; 183 181 i-cache-line-size = <64>; ··· 310 304 311 305 scmi_clk: protocol@14 { 312 306 reg = <0x14>; 313 - assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>, 314 - <&scmi_clk SCMI_CLK_CPUB23>; 315 - assigned-clock-rates = <1200000000>, 316 - <1200000000>; 317 307 #clock-cells = <1>; 318 308 }; 319 309 ··· 416 414 <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, 417 415 <&cru CLK_GPU>; 418 416 assigned-clock-rates = 419 - <100000000>, <786432000>, 417 + <1100000000>, <786432000>, 420 418 <850000000>, <1188000000>, 421 419 <702000000>, 422 420 <400000000>, <500000000>, ··· 812 810 }; 813 811 }; 814 812 813 + i2s4_8ch: i2s@fddc0000 { 814 + compatible = "rockchip,rk3588-i2s-tdm"; 815 + reg = <0x0 0xfddc0000 0x0 0x1000>; 816 + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>; 817 + clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; 818 + clock-names = "mclk_tx", "mclk_rx", "hclk"; 819 + assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>; 820 + assigned-clock-parents = <&cru PLL_AUPLL>; 821 + dmas = <&dmac2 0>; 822 + dma-names = "tx"; 823 + power-domains = <&power RK3588_PD_VO0>; 824 + resets = <&cru SRST_M_I2S4_8CH_TX>; 825 + reset-names = "tx-m"; 826 + #sound-dai-cells = <0>; 827 + status = "disabled"; 828 + }; 829 + 830 + i2s5_8ch: i2s@fddf0000 { 831 + compatible = "rockchip,rk3588-i2s-tdm"; 832 + reg = <0x0 0xfddf0000 0x0 0x1000>; 833 + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>; 834 + clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; 835 + clock-names = "mclk_tx", "mclk_rx", "hclk"; 836 + assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>; 837 + assigned-clock-parents = <&cru PLL_AUPLL>; 838 + dmas = <&dmac2 2>; 839 + dma-names = "tx"; 840 + power-domains = <&power RK3588_PD_VO1>; 841 + resets = <&cru SRST_M_I2S5_8CH_TX>; 842 + reset-names = "tx-m"; 843 + #sound-dai-cells = <0>; 844 + status = "disabled"; 845 + }; 846 + 847 + i2s9_8ch: i2s@fddfc000 { 848 + compatible = "rockchip,rk3588-i2s-tdm"; 849 + reg = <0x0 0xfddfc000 0x0 0x1000>; 850 + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>; 851 + clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; 852 + clock-names = "mclk_tx", "mclk_rx", "hclk"; 853 + assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>; 854 + assigned-clock-parents = <&cru PLL_AUPLL>; 855 + dmas = <&dmac2 23>; 856 + dma-names = "rx"; 857 + power-domains = <&power RK3588_PD_VO1>; 858 + resets = <&cru SRST_M_I2S9_8CH_RX>; 859 + reset-names = "rx-m"; 860 + #sound-dai-cells = <0>; 861 + status = "disabled"; 862 + }; 863 + 815 864 qos_gpu_m0: qos@fdf35000 { 816 865 compatible = "rockchip,rk3588-qos", "syscon"; 817 866 reg = <0x0 0xfdf35000 0x0 0x20>; ··· 1152 1099 }; 1153 1100 }; 1154 1101 1102 + sdmmc: mmc@fe2c0000 { 1103 + compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; 1104 + reg = <0x0 0xfe2c0000 0x0 0x4000>; 1105 + interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; 1106 + clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>, 1107 + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 1108 + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1109 + fifo-depth = <0x100>; 1110 + max-frequency = <200000000>; 1111 + pinctrl-names = "default"; 1112 + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 1113 + power-domains = <&power RK3588_PD_SDMMC>; 1114 + status = "disabled"; 1115 + }; 1116 + 1155 1117 sdhci: mmc@fe2e0000 { 1156 1118 compatible = "rockchip,rk3588-dwcmshc"; 1157 1119 reg = <0x0 0xfe2e0000 0x0 0x10000>; ··· 1182 1114 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, 1183 1115 <&cru SRST_T_EMMC>; 1184 1116 reset-names = "core", "bus", "axi", "block", "timer"; 1117 + status = "disabled"; 1118 + }; 1119 + 1120 + i2s0_8ch: i2s@fe470000 { 1121 + compatible = "rockchip,rk3588-i2s-tdm"; 1122 + reg = <0x0 0xfe470000 0x0 0x1000>; 1123 + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>; 1124 + clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 1125 + clock-names = "mclk_tx", "mclk_rx", "hclk"; 1126 + assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; 1127 + assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>; 1128 + dmas = <&dmac0 0>, <&dmac0 1>; 1129 + dma-names = "tx", "rx"; 1130 + power-domains = <&power RK3588_PD_AUDIO>; 1131 + resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 1132 + reset-names = "tx-m", "rx-m"; 1133 + rockchip,trcm-sync-tx-only; 1134 + pinctrl-names = "default"; 1135 + pinctrl-0 = <&i2s0_lrck 1136 + &i2s0_sclk 1137 + &i2s0_sdi0 1138 + &i2s0_sdi1 1139 + &i2s0_sdi2 1140 + &i2s0_sdi3 1141 + &i2s0_sdo0 1142 + &i2s0_sdo1 1143 + &i2s0_sdo2 1144 + &i2s0_sdo3>; 1145 + #sound-dai-cells = <0>; 1146 + status = "disabled"; 1147 + }; 1148 + 1149 + i2s1_8ch: i2s@fe480000 { 1150 + compatible = "rockchip,rk3588-i2s-tdm"; 1151 + reg = <0x0 0xfe480000 0x0 0x1000>; 1152 + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>; 1153 + clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; 1154 + clock-names = "mclk_tx", "mclk_rx", "hclk"; 1155 + dmas = <&dmac0 2>, <&dmac0 3>; 1156 + dma-names = "tx", "rx"; 1157 + resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; 1158 + reset-names = "tx-m", "rx-m"; 1159 + rockchip,trcm-sync-tx-only; 1160 + pinctrl-names = "default"; 1161 + pinctrl-0 = <&i2s1m0_lrck 1162 + &i2s1m0_sclk 1163 + &i2s1m0_sdi0 1164 + &i2s1m0_sdi1 1165 + &i2s1m0_sdi2 1166 + &i2s1m0_sdi3 1167 + &i2s1m0_sdo0 1168 + &i2s1m0_sdo1 1169 + &i2s1m0_sdo2 1170 + &i2s1m0_sdo3>; 1171 + #sound-dai-cells = <0>; 1172 + status = "disabled"; 1173 + }; 1174 + 1175 + i2s2_2ch: i2s@fe490000 { 1176 + compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 1177 + reg = <0x0 0xfe490000 0x0 0x1000>; 1178 + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>; 1179 + clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; 1180 + clock-names = "i2s_clk", "i2s_hclk"; 1181 + assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; 1182 + assigned-clock-parents = <&cru PLL_AUPLL>; 1183 + dmas = <&dmac1 0>, <&dmac1 1>; 1184 + dma-names = "tx", "rx"; 1185 + power-domains = <&power RK3588_PD_AUDIO>; 1186 + rockchip,trcm-sync-tx-only; 1187 + pinctrl-names = "default"; 1188 + pinctrl-0 = <&i2s2m1_lrck 1189 + &i2s2m1_sclk 1190 + &i2s2m1_sdi 1191 + &i2s2m1_sdo>; 1192 + #sound-dai-cells = <0>; 1193 + status = "disabled"; 1194 + }; 1195 + 1196 + i2s3_2ch: i2s@fe4a0000 { 1197 + compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 1198 + reg = <0x0 0xfe4a0000 0x0 0x1000>; 1199 + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>; 1200 + clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; 1201 + clock-names = "i2s_clk", "i2s_hclk"; 1202 + assigned-clocks = <&cru CLK_I2S3_2CH_SRC>; 1203 + assigned-clock-parents = <&cru PLL_AUPLL>; 1204 + dmas = <&dmac1 2>, <&dmac1 3>; 1205 + dma-names = "tx", "rx"; 1206 + power-domains = <&power RK3588_PD_AUDIO>; 1207 + rockchip,trcm-sync-tx-only; 1208 + pinctrl-names = "default"; 1209 + pinctrl-0 = <&i2s3_lrck 1210 + &i2s3_sclk 1211 + &i2s3_sdi 1212 + &i2s3_sdo>; 1213 + #sound-dai-cells = <0>; 1185 1214 status = "disabled"; 1186 1215 }; 1187 1216 ··· 1389 1224 #address-cells = <1>; 1390 1225 #size-cells = <0>; 1391 1226 status = "disabled"; 1227 + }; 1228 + 1229 + wdt: watchdog@feaf0000 { 1230 + compatible = "rockchip,rk3588-wdt", "snps,dw-wdt"; 1231 + reg = <0x0 0xfeaf0000 0x0 0x100>; 1232 + clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; 1233 + clock-names = "tclk", "pclk"; 1234 + interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>; 1392 1235 }; 1393 1236 1394 1237 spi0: spi@feb00000 { ··· 1727 1554 pinctrl-0 = <&pwm15m0_pins>; 1728 1555 pinctrl-names = "default"; 1729 1556 #pwm-cells = <3>; 1557 + status = "disabled"; 1558 + }; 1559 + 1560 + tsadc: tsadc@fec00000 { 1561 + compatible = "rockchip,rk3588-tsadc"; 1562 + reg = <0x0 0xfec00000 0x0 0x400>; 1563 + interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>; 1564 + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 1565 + clock-names = "tsadc", "apb_pclk"; 1566 + assigned-clocks = <&cru CLK_TSADC>; 1567 + assigned-clock-rates = <2000000>; 1568 + resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; 1569 + reset-names = "tsadc-apb", "tsadc"; 1570 + rockchip,hw-tshut-temp = <120000>; 1571 + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 1572 + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 1573 + pinctrl-0 = <&tsadc_gpio_func>; 1574 + pinctrl-1 = <&tsadc_shut>; 1575 + pinctrl-names = "gpio", "otpout"; 1576 + #thermal-sensor-cells = <1>; 1730 1577 status = "disabled"; 1731 1578 }; 1732 1579

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