Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amd/pm: add inst to dpm_set_powergating_by_smu
Add an instance parameter to amdgpu_dpm_set_powergating_by_smu() function,
and use the instance to call set_powergating_by_smu().
v2: remove duplicated functions.
remove for-loop in amdgpu_dpm_set_powergating_by_smu(), and temporarily
move it to amdgpu_dpm_enable_vcn(), in order to keep the exact same logic
as before, until further separation in next patch.
v3: drop SI logic in amdgpu_dpm_enable_vcn().
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Boyuan Zhang
and committed by
Alex Deucher
ff69bba0
697cb5cc
+59
-43
+7
-7
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+7
-7
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
···
140
140
* 2. power off the acp tiles
141
141
* 3. check and enter ulv state
142
142
*/
143
-
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);
143
+
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true, 0);
144
144
return 0;
145
145
}
146
146
···
157
157
* 2. turn on acp clock
158
158
* 3. power on acp tiles
159
159
*/
160
-
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false);
160
+
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false, 0);
161
161
return 0;
162
162
}
163
163
···
236
236
ip_block->version->major, ip_block->version->minor);
237
237
/* -ENODEV means board uses AZ rather than ACP */
238
238
if (r == -ENODEV) {
239
-
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);
239
+
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true, 0);
240
240
return 0;
241
241
} else if (r) {
242
242
return r;
···
508
508
509
509
/* return early if no ACP */
510
510
if (!adev->acp.acp_genpd) {
511
-
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false);
511
+
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false, 0);
512
512
return 0;
513
513
}
514
514
···
565
565
566
566
/* power up on suspend */
567
567
if (!adev->acp.acp_cell)
568
-
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false);
568
+
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false, 0);
569
569
return 0;
570
570
}
571
571
···
575
575
576
576
/* power down again on resume */
577
577
if (!adev->acp.acp_cell)
578
-
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);
578
+
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true, 0);
579
579
return 0;
580
580
}
581
581
···
596
596
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
597
597
bool enable = (state == AMD_PG_STATE_GATE);
598
598
599
-
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, enable);
599
+
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, enable, 0);
600
600
601
601
return 0;
602
602
}
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
···
3478
3478
WARN_ON_ONCE(adev->gfx.gfx_off_state);
3479
3479
WARN_ON_ONCE(adev->gfx.gfx_off_req_count);
3480
3480
3481
-
if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true))
3481
+
if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true, 0))
3482
3482
adev->gfx.gfx_off_state = true;
3483
3483
}
3484
3484
+2
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+2
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
···
806
806
/* If going to s2idle, no need to wait */
807
807
if (adev->in_s0ix) {
808
808
if (!amdgpu_dpm_set_powergating_by_smu(adev,
809
-
AMD_IP_BLOCK_TYPE_GFX, true))
809
+
AMD_IP_BLOCK_TYPE_GFX, true, 0))
810
810
adev->gfx.gfx_off_state = true;
811
811
} else {
812
812
schedule_delayed_work(&adev->gfx.gfx_off_delay_work,
···
818
818
cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
819
819
820
820
if (adev->gfx.gfx_off_state &&
821
-
!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false)) {
821
+
!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false, 0)) {
822
822
adev->gfx.gfx_off_state = false;
823
823
824
824
if (adev->gfx.funcs->init_spm_golden) {
+1
-1
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+1
-1
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
···
5319
5319
(adev->asic_type == CHIP_POLARIS12) ||
5320
5320
(adev->asic_type == CHIP_VEGAM))
5321
5321
/* Send msg to SMU via Powerplay */
5322
-
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, enable);
5322
+
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, enable, 0);
5323
5323
5324
5324
WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0);
5325
5325
}
+1
-1
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+1
-1
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+2
-2
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+2
-2
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
···
1956
1956
struct amdgpu_device *adev = ip_block->adev;
1957
1957
1958
1958
if (adev->flags & AMD_IS_APU)
1959
-
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false);
1959
+
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false, 0);
1960
1960
1961
1961
if (!amdgpu_sriov_vf(adev))
1962
1962
sdma_v4_0_init_golden_registers(adev);
···
1983
1983
sdma_v4_0_enable(adev, false);
1984
1984
1985
1985
if (adev->flags & AMD_IS_APU)
1986
-
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true);
1986
+
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true, 0);
1987
1987
1988
1988
return 0;
1989
1989
}
+3
-3
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+3
-3
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
···
303
303
idle_work_unexecuted = cancel_delayed_work_sync(&adev->vcn.idle_work);
304
304
if (idle_work_unexecuted) {
305
305
if (adev->pm.dpm_enabled)
306
-
amdgpu_dpm_enable_uvd(adev, false);
306
+
amdgpu_dpm_enable_vcn(adev, false);
307
307
}
308
308
309
309
r = vcn_v1_0_hw_fini(ip_block);
···
1856
1856
if (fences == 0) {
1857
1857
amdgpu_gfx_off_ctrl(adev, true);
1858
1858
if (adev->pm.dpm_enabled)
1859
-
amdgpu_dpm_enable_uvd(adev, false);
1859
+
amdgpu_dpm_enable_vcn(adev, false);
1860
1860
else
1861
1861
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
1862
1862
AMD_PG_STATE_GATE);
···
1886
1886
if (set_clocks) {
1887
1887
amdgpu_gfx_off_ctrl(adev, false);
1888
1888
if (adev->pm.dpm_enabled)
1889
-
amdgpu_dpm_enable_uvd(adev, true);
1889
+
amdgpu_dpm_enable_vcn(adev, true);
1890
1890
else
1891
1891
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
1892
1892
AMD_PG_STATE_UNGATE);
+2
-2
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+2
-2
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
···
978
978
int i, j, r;
979
979
980
980
if (adev->pm.dpm_enabled)
981
-
amdgpu_dpm_enable_uvd(adev, true);
981
+
amdgpu_dpm_enable_vcn(adev, true);
982
982
983
983
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
984
984
return vcn_v2_0_start_dpg_mode(adev, adev->vcn.indirect_sram);
···
1235
1235
1236
1236
power_off:
1237
1237
if (adev->pm.dpm_enabled)
1238
-
amdgpu_dpm_enable_uvd(adev, false);
1238
+
amdgpu_dpm_enable_vcn(adev, false);
1239
1239
1240
1240
return 0;
1241
1241
}
+2
-2
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+2
-2
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
···
1013
1013
int i, j, k, r;
1014
1014
1015
1015
if (adev->pm.dpm_enabled)
1016
-
amdgpu_dpm_enable_uvd(adev, true);
1016
+
amdgpu_dpm_enable_vcn(adev, true);
1017
1017
1018
1018
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1019
1019
if (adev->vcn.harvest_config & (1 << i))
···
1486
1486
}
1487
1487
1488
1488
if (adev->pm.dpm_enabled)
1489
-
amdgpu_dpm_enable_uvd(adev, false);
1489
+
amdgpu_dpm_enable_vcn(adev, false);
1490
1490
1491
1491
return 0;
1492
1492
}
+2
-2
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+2
-2
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
···
1142
1142
int i, j, k, r;
1143
1143
1144
1144
if (adev->pm.dpm_enabled)
1145
-
amdgpu_dpm_enable_uvd(adev, true);
1145
+
amdgpu_dpm_enable_vcn(adev, true);
1146
1146
1147
1147
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1148
1148
if (adev->vcn.harvest_config & (1 << i))
···
1633
1633
}
1634
1634
1635
1635
if (adev->pm.dpm_enabled)
1636
-
amdgpu_dpm_enable_uvd(adev, false);
1636
+
amdgpu_dpm_enable_vcn(adev, false);
1637
1637
1638
1638
return 0;
1639
1639
}
+2
-2
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+2
-2
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
···
1098
1098
int i, j, k, r;
1099
1099
1100
1100
if (adev->pm.dpm_enabled)
1101
-
amdgpu_dpm_enable_uvd(adev, true);
1101
+
amdgpu_dpm_enable_vcn(adev, true);
1102
1102
1103
1103
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1104
1104
if (adev->vcn.harvest_config & (1 << i))
···
1624
1624
}
1625
1625
1626
1626
if (adev->pm.dpm_enabled)
1627
-
amdgpu_dpm_enable_uvd(adev, false);
1627
+
amdgpu_dpm_enable_vcn(adev, false);
1628
1628
1629
1629
return 0;
1630
1630
}
+2
-2
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+2
-2
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
···
1122
1122
uint32_t tmp;
1123
1123
1124
1124
if (adev->pm.dpm_enabled)
1125
-
amdgpu_dpm_enable_uvd(adev, true);
1125
+
amdgpu_dpm_enable_vcn(adev, true);
1126
1126
1127
1127
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1128
1128
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
···
1396
1396
}
1397
1397
Done:
1398
1398
if (adev->pm.dpm_enabled)
1399
-
amdgpu_dpm_enable_uvd(adev, false);
1399
+
amdgpu_dpm_enable_vcn(adev, false);
1400
1400
1401
1401
return 0;
1402
1402
}
+2
-2
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+2
-2
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
···
1001
1001
int i, j, k, r;
1002
1002
1003
1003
if (adev->pm.dpm_enabled)
1004
-
amdgpu_dpm_enable_uvd(adev, true);
1004
+
amdgpu_dpm_enable_vcn(adev, true);
1005
1005
1006
1006
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1007
1007
if (adev->vcn.harvest_config & (1 << i))
···
1278
1278
}
1279
1279
1280
1280
if (adev->pm.dpm_enabled)
1281
-
amdgpu_dpm_enable_uvd(adev, false);
1281
+
amdgpu_dpm_enable_vcn(adev, false);
1282
1282
1283
1283
return 0;
1284
1284
}
+2
-2
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+2
-2
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
···
772
772
int i, j, k, r;
773
773
774
774
if (adev->pm.dpm_enabled)
775
-
amdgpu_dpm_enable_uvd(adev, true);
775
+
amdgpu_dpm_enable_vcn(adev, true);
776
776
777
777
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
778
778
if (adev->vcn.harvest_config & (1 << i))
···
1019
1019
}
1020
1020
1021
1021
if (adev->pm.dpm_enabled)
1022
-
amdgpu_dpm_enable_uvd(adev, false);
1022
+
amdgpu_dpm_enable_vcn(adev, false);
1023
1023
1024
1024
return 0;
1025
1025
}
+26
-11
drivers/gpu/drm/amd/pm/amdgpu_dpm.c
+26
-11
drivers/gpu/drm/amd/pm/amdgpu_dpm.c
···
70
70
return ret;
71
71
}
72
72
73
-
int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block_type, bool gate)
73
+
int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev,
74
+
uint32_t block_type,
75
+
bool gate,
76
+
int inst)
74
77
{
75
78
int ret = 0;
76
79
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
77
80
enum ip_power_state pwr_state = gate ? POWER_STATE_OFF : POWER_STATE_ON;
81
+
bool is_vcn = (block_type == AMD_IP_BLOCK_TYPE_UVD || block_type == AMD_IP_BLOCK_TYPE_VCN);
78
82
79
-
if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state) {
83
+
if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state &&
84
+
(!is_vcn || adev->vcn.num_vcn_inst == 1)) {
80
85
dev_dbg(adev->dev, "IP block%d already in the target %s state!",
81
86
block_type, gate ? "gate" : "ungate");
82
87
return 0;
···
103
98
(adev)->powerplay.pp_handle, block_type, gate, 0));
104
99
break;
105
100
case AMD_IP_BLOCK_TYPE_VCN:
106
-
if (pp_funcs && pp_funcs->set_powergating_by_smu) {
107
-
for (int i = 0; i < adev->vcn.num_vcn_inst; i++)
108
-
ret = (pp_funcs->set_powergating_by_smu(
109
-
(adev)->powerplay.pp_handle, block_type, gate, i));
110
-
}
101
+
if (pp_funcs && pp_funcs->set_powergating_by_smu)
102
+
ret = (pp_funcs->set_powergating_by_smu(
103
+
(adev)->powerplay.pp_handle, block_type, gate, inst));
111
104
break;
112
105
default:
113
106
break;
···
575
572
return;
576
573
}
577
574
578
-
ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
575
+
ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable, 0);
579
576
if (ret)
580
577
DRM_ERROR("Dpm %s uvd failed, ret = %d. \n",
581
578
enable ? "enable" : "disable", ret);
579
+
}
580
+
581
+
void amdgpu_dpm_enable_vcn(struct amdgpu_device *adev, bool enable)
582
+
{
583
+
int i, ret = 0;
584
+
585
+
for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
586
+
ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCN, !enable, i);
587
+
if (ret)
588
+
DRM_ERROR("Dpm %s uvd failed, ret = %d. \n",
589
+
enable ? "enable" : "disable", ret);
590
+
}
582
591
}
583
592
584
593
void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
···
612
597
return;
613
598
}
614
599
615
-
ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);
600
+
ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable, 0);
616
601
if (ret)
617
602
DRM_ERROR("Dpm %s vce failed, ret = %d. \n",
618
603
enable ? "enable" : "disable", ret);
···
622
607
{
623
608
int ret = 0;
624
609
625
-
ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_JPEG, !enable);
610
+
ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_JPEG, !enable, 0);
626
611
if (ret)
627
612
DRM_ERROR("Dpm %s jpeg failed, ret = %d. \n",
628
613
enable ? "enable" : "disable", ret);
···
632
617
{
633
618
int ret = 0;
634
619
635
-
ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VPE, !enable);
620
+
ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VPE, !enable, 0);
636
621
if (ret)
637
622
DRM_ERROR("Dpm %s vpe failed, ret = %d.\n",
638
623
enable ? "enable" : "disable", ret);
+2
-1
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
+2
-1
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
···
397
397
int amdgpu_dpm_set_apu_thermal_limit(struct amdgpu_device *adev, uint32_t limit);
398
398
399
399
int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev,
400
-
uint32_t block_type, bool gate);
400
+
uint32_t block_type, bool gate, int inst);
401
401
402
402
extern int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low);
403
403
···
446
446
447
447
void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev);
448
448
void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable);
449
+
void amdgpu_dpm_enable_vcn(struct amdgpu_device *adev, bool enable);
449
450
void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable);
450
451
void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable);
451
452
void amdgpu_dpm_enable_vpe(struct amdgpu_device *adev, bool enable);