tsiry-sandratraina.com / rockbox-zig
Rockbox open source high quality audio player as a Music Player Daemon
mpris rockbox mpd libadwaita audio rust zig deno
2
fork

Configure Feed

Select the types of activity you want to include in your feed.

firmware: refactor CACHEALIGN_BITS/SIZE defines

Mostly motivated by PP needing CACHEALIGN_SIZE in linker
scripts, which can't include system.h, so move these to
cpu.h instead. Also gets rid of the default 32 byte line
size that was used if the target didn't define alignment
itself. RK24xx, DM320, and JZ4740 were missing this but
have been confirmed (from datasheets) to use 32-byte cache
lines.

Add checks to make sure the macros are appropriately
(un)defined based on the HAVE_CPU_CACHE_ALIGN define,
and make sure their values are consistent when they
are defined.

Disable HAVE_CPU_CACHE_ALIGN for hosted targets since it
arguably doesn't matter if there's a cache, if we aren't
responsible for cache maintenance.

A few files in rbcodec use CACHEALIGN_SIZE, but these
can be converted to MEM_ALIGN_SIZE, which is identical
to CACHEALIGN_SIZE if the latter is defined. On other
targets, it aligns to at least sizeof(intptr_t).

Change-Id: If8cf8f6ec327dc3732f4cd5022a858546b9e63d6

Aidan MacDonald 7eeb4e43 e61bf405

+83 -86
+2 -2
apps/codecs.c
··· 159 159 CODEC_EXTENSION, codec_root_fn); 160 160 } 161 161 162 - /* Returns pointer to and size of free codec RAM. Aligns to CACHEALIGN_SIZE. */ 162 + /* Returns pointer to and size of free codec RAM. Aligns to MEM_ALIGN_SIZE. */ 163 163 void *codec_get_buffer_callback(size_t *size) 164 164 { 165 165 void *buf = &codecbuf[codec_size]; ··· 169 169 return NULL; 170 170 171 171 *size = s; 172 - ALIGN_BUFFER(buf, *size, CACHEALIGN_SIZE); 172 + ALIGN_BUFFER(buf, *size, MEM_ALIGN_SIZE); 173 173 174 174 return buf; 175 175 }
-1
apps/plugins/plugin.lds
··· 21 21 #else 22 22 #define NOCACHE_BASE 0x28000000 23 23 #endif /* CPU_* */ 24 - #define CACHEALIGN_SIZE 16 25 24 #endif /* CPU_PP */ 26 25 27 26 #if CONFIG_CPU==IMX31L
+1
firmware/export/as3525.h
··· 21 21 #define __AS3525_H__ 22 22 23 23 #define CACHEALIGN_BITS (5) 24 + #define CACHEALIGN_SIZE (32) 24 25 25 26 #define UART_CHANNELS 1 26 27
+36 -36
firmware/export/cpu.h
··· 25 25 26 26 #if CONFIG_CPU == MCF5249 27 27 #include "mcf5249.h" 28 - #endif 29 - #if CONFIG_CPU == MCF5250 28 + #elif CONFIG_CPU == MCF5250 30 29 #include "mcf5250.h" 31 - #endif 32 - #if (CONFIG_CPU == PP5020) || (CONFIG_CPU == PP5022) 30 + #elif (CONFIG_CPU == PP5020) || (CONFIG_CPU == PP5022) 33 31 #include "pp5020.h" 34 - #endif 35 - #if CONFIG_CPU == PP5002 32 + #elif CONFIG_CPU == PP5002 36 33 #include "pp5002.h" 37 - #endif 38 - #if CONFIG_CPU == PP5024 34 + #elif CONFIG_CPU == PP5024 39 35 #include "pp5024.h" 40 - #endif 41 - #if CONFIG_CPU == PP6100 36 + #elif CONFIG_CPU == PP6100 42 37 #include "pp6100.h" 43 - #endif 44 - #if CONFIG_CPU == S3C2440 38 + #elif CONFIG_CPU == S3C2440 45 39 #include "s3c2440.h" 46 - #endif 47 - #if CONFIG_CPU == DM320 40 + #elif CONFIG_CPU == DM320 48 41 #include "dm320.h" 49 - #endif 50 - #if CONFIG_CPU == IMX31L 42 + #elif CONFIG_CPU == IMX31L 51 43 #include "imx31l.h" 52 - #endif 53 - #ifdef CPU_TCC780X 44 + #elif defined(CPU_TCC780X) 54 45 #include "tcc780x.h" 55 - #endif 56 - #ifdef CPU_S5L87XX 46 + #elif defined(CPU_S5L87XX) 57 47 #include "s5l87xx.h" 58 - #endif 59 - #if CONFIG_CPU == JZ4732 48 + #elif CONFIG_CPU == JZ4732 60 49 #include "jz4740.h" 61 - #endif 62 - #if CONFIG_CPU == JZ4760B 50 + #elif CONFIG_CPU == JZ4760B 63 51 #include "jz4760b.h" 64 - #endif 65 - #if CONFIG_CPU == AS3525 52 + #elif CONFIG_CPU == AS3525 66 53 #include "as3525.h" 67 - #endif 68 - #if CONFIG_CPU == AS3525v2 54 + #elif CONFIG_CPU == AS3525v2 69 55 #include "as3525v2.h" 70 - #endif 71 - #if CONFIG_CPU == IMX233 56 + #elif CONFIG_CPU == IMX233 72 57 #include "imx233.h" 73 - #endif 74 - #if CONFIG_CPU == RK27XX 58 + #elif CONFIG_CPU == RK27XX 75 59 #include "rk27xx.h" 76 - #endif 77 - #if CONFIG_CPU == X1000 60 + #elif CONFIG_CPU == X1000 78 61 #include "x1000.h" 79 - #endif 80 - #if CONFIG_CPU == STM32H743 62 + #elif CONFIG_CPU == STM32H743 81 63 #include "stm32h743.h" 64 + #endif 65 + 66 + #if (CONFIG_PLATFORM & PLATFORM_NATIVE) && (defined(CPU_ARM) || defined(CPU_MIPS)) 67 + # define HAVE_CPU_CACHE_ALIGN 68 + #endif 69 + 70 + #if defined(HAVE_CPU_CACHE_ALIGN) 71 + # if !defined(CACHEALIGN_BITS) 72 + # error "CPU header must define CACHEALIGN_BITS" 73 + # elif !defined(CACHEALIGN_SIZE) 74 + # error "CPU header must define CACHEALIGN_SIZE" 75 + # elif CACHEALIGN_SIZE != (1u << CACHEALIGN_BITS) 76 + # error "CACHEALIGN_SIZE and CACHEALIGN_BITS are inconsistent" 77 + # endif 78 + #else 79 + # if defined(CACHEALIGN_BITS) && defined(CACHEALIGN_SIZE) 80 + # error "CACHEALIGN_BITS and CACHEALIGN_SIZE must not be defined for targets with no CPU cache" 81 + # endif 82 82 #endif 83 83 84 84 #endif /* __CPU_H */
+4
firmware/export/dm320.h
··· 36 36 extern unsigned long _ttbstart; 37 37 #endif 38 38 39 + /* See https://www.heyrick.co.uk/blog/files/datasheets/tms320dm320part1.pdf */ 40 + #define CACHEALIGN_BITS 5 41 + #define CACHEALIGN_SIZE 32 42 + 39 43 #define TTB_BASE_ADDR (_ttbstart) /* End of memory */ 40 44 #define FRAME ((short *) (&_lcdbuf)) /* Right after TTB */ 41 45 #ifdef MROBE_500
+3
firmware/export/jz4740.h
··· 40 40 #ifndef __JZ4740_H__ 41 41 #define __JZ4740_H__ 42 42 43 + #define CACHEALIGN_BITS (5) 44 + #define CACHEALIGN_SIZE (32) 45 + 43 46 #ifndef __ASSEMBLER__ 44 47 45 48 #define REG8(addr) (*(volatile unsigned char *)(addr))
+3
firmware/export/jz4760b.h
··· 37 37 #ifndef __JZ4760B_H__ 38 38 #define __JZ4760B_H__ 39 39 40 + #define CACHEALIGN_BITS (5) 41 + #define CACHEALIGN_SIZE (32) 42 + 40 43 #if defined(__ASSEMBLER__) 41 44 #ifndef __MIPS_ASSEMBLER 42 45 #define __MIPS_ASSEMBLER
+2 -1
firmware/export/pp5002.h
··· 23 23 24 24 /* Much info gleaned and/or copied from the iPodLinux project. */ 25 25 26 - #define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */ 26 + #define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */ 27 + #define CACHEALIGN_SIZE (16) 27 28 28 29 #define DRAM_START 0x28000000 29 30
+2 -1
firmware/export/pp5020.h
··· 23 23 24 24 /* All info gleaned and/or copied from the iPodLinux project. */ 25 25 26 - #define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */ 26 + #define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */ 27 + #define CACHEALIGN_SIZE (16) 27 28 28 29 /* PCM addresses for obtaining buffers will be what DMA is using (physical) */ 29 30 #define HAVE_PCM_DMA_ADDRESS
+4
firmware/export/rk27xx.h
··· 1 + /* See https://rockchip.fr/Rockchip%20RK27xx%20TRM%20V1.1.pdf */ 2 + #define CACHEALIGN_BITS 5 3 + #define CACHEALIGN_SIZE 32 4 + 1 5 /* ARM part only for now */ 2 6 #define AHB_SRAM 0x00000000 3 7
+1
firmware/export/s3c2440.h
··· 22 22 #define __S3C2440_H__ 23 23 24 24 #define CACHEALIGN_BITS (5) 25 + #define CACHEALIGN_SIZE (32) 25 26 26 27 #define LCD_BUFFER_SIZE (320*240*2) 27 28 #define TTB_SIZE (0x4000)
+4 -2
firmware/export/s5l87xx.h
··· 31 31 #define VOID_PTR_PTR_T void* volatile* 32 32 33 33 #if CONFIG_CPU==S5L8700 || CONFIG_CPU==S5L8701 34 - #define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */ 34 + #define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */ 35 + #define CACHEALIGN_SIZE (16) 35 36 #elif CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720 36 - #define CACHEALIGN_BITS (5) /* 2^5 = 32 bytes */ 37 + #define CACHEALIGN_BITS (5) /* 2^5 = 32 bytes */ 38 + #define CACHEALIGN_SIZE (32) 37 39 #endif 38 40 39 41 #if CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720
+1
firmware/export/stm32h743.h
··· 25 25 26 26 #define CACHE_SIZE (16 * 1024) 27 27 #define CACHEALIGN_BITS 5 28 + #define CACHEALIGN_SIZE 32 28 29 29 30 #define DCACHE_SIZE CACHE_SIZE 30 31 #define DCACHE_WAYS 0x4
+5 -25
firmware/export/system.h
··· 258 258 #define DISABLE_INTERRUPTS HIGHEST_IRQ_LEVEL 259 259 #endif 260 260 261 - /* Define this, if the CPU may take advantage of cache aligment. Is enabled 262 - * for all ARM CPUs. */ 263 - #ifdef CPU_ARM 264 - #define HAVE_CPU_CACHE_ALIGN 265 - #define MIN_STACK_ALIGN 8 266 - #endif 267 - 268 - #ifdef CPU_MIPS 269 - #define HAVE_CPU_CACHE_ALIGN 270 - #endif 271 - 272 261 /* Define this if target has support for generating backtraces */ 273 262 #if defined(CPU_ARM) || \ 274 263 (defined(CPU_MIPS) && (CONFIG_PLATFORM & PLATFORM_NATIVE)) ··· 277 266 #endif 278 267 #endif 279 268 280 - #ifndef MIN_STACK_ALIGN 281 - #define MIN_STACK_ALIGN (sizeof (uintptr_t)) 269 + /* ARM ABIs generally require 8-byte stack alignment */ 270 + #ifdef CPU_ARM 271 + #define MIN_STACK_ALIGN 8 282 272 #endif 283 273 284 - /* Calculate CACHEALIGN_SIZE from CACHEALIGN_BITS */ 285 - #ifdef CACHEALIGN_SIZE 286 - /* undefine, if defined. always calculate from CACHEALIGN_BITS */ 287 - #undef CACHEALIGN_SIZE 288 - #endif 289 - #ifdef CACHEALIGN_BITS 290 - /* CACHEALIGN_SIZE = 2 ^ CACHEALIGN_BITS */ 291 - #define CACHEALIGN_SIZE (1u << CACHEALIGN_BITS) 292 - #else 293 - /* FIXME: set to maximum known cache alignment of supported CPUs */ 294 - #define CACHEALIGN_BITS 5 295 - #define CACHEALIGN_SIZE 32 274 + #ifndef MIN_STACK_ALIGN 275 + #define MIN_STACK_ALIGN (sizeof (uintptr_t)) 296 276 #endif 297 277 298 278 #ifdef HAVE_CPU_CACHE_ALIGN
+1
firmware/export/tcc780x.h
··· 22 22 #define __TCC780X_H__ 23 23 24 24 #define CACHEALIGN_BITS (5) 25 + #define CACHEALIGN_SIZE (32) 25 26 26 27 #define TTB_SIZE (0x4000) 27 28 /* must be 16Kb (0x4000) aligned */
+1
firmware/export/x1000.h
··· 119 119 120 120 /* CPU cache parameters */ 121 121 #define CACHEALIGN_BITS 5 122 + #define CACHEALIGN_SIZE 32 122 123 #define CACHE_SIZE (16 * 1024) 123 124 124 125 #endif /* __X1000_H__ */
+3 -2
firmware/target/arm/pp/app-pp.lds
··· 1 + #define __ASSEMBLER__ 2 + #include "cpu.h" 3 + 1 4 /* Will have been included from app.lds */ 2 5 ENTRY(start) 3 6 ··· 19 22 #else 20 23 #define NOCACHE_BASE 0x28000000 21 24 #endif 22 - 23 - #define CACHEALIGN_SIZE 16 24 25 25 26 /* End of the audio buffer, where the codec buffer starts */ 26 27 #define ENDAUDIOADDR (DRAMORIG + DRAMSIZE)
+3 -2
firmware/target/arm/pp/boot-pp502x-bl-usb.lds
··· 1 + #define __ASSEMBLER__ 2 + #include "cpu.h" 3 + 1 4 /* Will have been included from boot.lds */ 2 5 ENTRY(start) 3 6 OUTPUT_FORMAT(elf32-littlearm) ··· 14 17 #define IRAMSIZE 0x20000 15 18 #define FLASHORIG 0x001f0000 16 19 #define FLASHSIZE 2M 17 - 18 - #define CACHEALIGN_SIZE 16 19 20 20 21 MEMORY 21 22 {
-1
firmware/target/mips/ingenic_jz47xx/system-target.h
··· 30 30 #include "system-mips.h" 31 31 32 32 #define CACHE_SIZE 16*1024 33 - #define CACHEALIGN_BITS 5 34 33 #include "mmu-mips.h" 35 34 36 35 #define CFG_UART_BASE UART1_BASE /* Base of the UART channel */
+3 -3
lib/rbcodec/codecs/lib/codeclib.c
··· 35 35 36 36 int codec_init(void) 37 37 { 38 - /* codec_get_buffer() aligns the resulting point to CACHEALIGN_SIZE. */ 38 + /* codec_get_buffer() aligns the resulting point to MEM_ALIGN_SIZE. */ 39 39 mem_ptr = 0; 40 40 mallocbuf = (unsigned char *)ci->codec_get_buffer((size_t *)&bufsize); 41 41 ··· 67 67 68 68 x=&mallocbuf[mem_ptr]; 69 69 70 - /* Keep memory aligned to CACHEALIGN_SIZE. */ 71 - mem_ptr += (size + (CACHEALIGN_SIZE-1)) & ~(CACHEALIGN_SIZE-1); 70 + /* Keep memory aligned to MEM_ALIGN_SIZE. */ 71 + mem_ptr += MEM_ALIGN_UP(size); 72 72 73 73 return(x); 74 74 }
+2 -2
lib/rbcodec/codecs/libtremor/oggmalloc.c
··· 72 72 void *iram_malloc(size_t size){ 73 73 void* x; 74 74 75 - /* always ensure alignment to CACHEALIGN_SIZE byte */ 76 - size = (size + (CACHEALIGN_SIZE-1)) & ~(CACHEALIGN_SIZE-1); 75 + /* align for best performance */ 76 + size = MEM_ALIGN_UP(size); 77 77 78 78 if(size>iram_remain) 79 79 return NULL;
-3
lib/rbcodec/platform.h
··· 117 117 # define MEM_ALIGN_ATTR 118 118 #endif 119 119 120 - #ifndef CACHEALIGN_SIZE 121 - # define CACHEALIGN_SIZE 1 122 - #endif 123 120 /* 124 121 #ifndef HAVE_CLIP_SAMPLE_16 125 122 static inline int32_t clip_sample_16(int32_t sample)
+2 -5
lib/rbcodec/test/warble.c
··· 428 428 429 429 static void *ci_codec_get_buffer(size_t *size) 430 430 { 431 - static char buffer[64 * 1024 * 1024]; 432 - char *ptr = buffer; 431 + static char buffer[64 * 1024 * 1024] MEM_ALIGN_ATTR; 433 432 *size = sizeof(buffer); 434 - if ((intptr_t)ptr & (CACHEALIGN_SIZE - 1)) 435 - ptr += CACHEALIGN_SIZE - ((intptr_t)ptr & (CACHEALIGN_SIZE - 1)); 436 - return ptr; 433 + return buffer; 437 434 } 438 435 439 436 static void ci_pcmbuf_insert(const void *ch1, const void *ch2, int count)