anil.recoil.org / ocaml-crypto
forked from gazagnaire.org/ocaml-crypto
upstream: https://github.com/mirage/mirage-crypto
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Initial RISC-V support (#127)

* mirage_crypto.h: add RISC-V support

See https://github.com/riscv/riscv-toolchain-conventions#cc-preprocessor-definitions
__riscv_xlen is 32 for RV32 and 64 for RV64

Signed-off-by: Edwin Török <edwin@etorok.net>

* entropy_cpu_stubs.c: Add RV64 support

On RV64 it is easy, just use rdcycle pseudo-instruction.
On RV32 would have to use rdcycle+rdcycleh, but don't have RV32 hardware.

Signed-off-by: Edwin Török <edwin@etorok.net>

authored by

Török Edwin and committed by
GitHub 729a0713 78c5b0a7

+13 -2
+11
src/native/entropy_cpu_stubs.c
··· 99 99 } 100 100 #endif 101 101 102 + #if defined (__riscv) && (64 == __riscv_xlen) 103 + static inline uint64_t rdcycle64(void) 104 + { 105 + uint64_t rval; 106 + __asm__ __volatile__ ("rdcycle %0" : "=r" (rval)); 107 + return rval; 108 + } 109 + #endif 110 + 102 111 CAMLprim value mc_cycle_counter (value __unused(unit)) { 103 112 #if defined (__i386__) || defined (__x86_64__) 104 113 return Val_long (__rdtsc ()); ··· 106 115 return Val_long (read_virtual_count ()); 107 116 #elif defined(__powerpc64__) 108 117 return Val_long (read_cycle_counter ()); 118 + #elif defined(__riscv) && (64 == __riscv_xlen) 119 + return Val_long (rdcycle64 ()); 109 120 #else 110 121 #error ("No known cycle-counting instruction.") 111 122 #endif
+2 -2
src/native/mirage_crypto.h
··· 47 47 48 48 #endif /* __mc_ACCELERATE__ */ 49 49 50 - #if defined (__x86_64__) || defined (__aarch64__) || defined (__powerpc64__) 50 + #if defined (__x86_64__) || defined (__aarch64__) || defined (__powerpc64__) || (64 == __riscv_xlen) 51 51 #define ARCH_64BIT 52 - #elif defined (__i386__) || defined (__arm__) 52 + #elif defined (__i386__) || defined (__arm__) || (32 == __riscv_xlen) 53 53 #define ARCH_32BIT 54 54 #else 55 55 #error "unsupported platform"