My working unpac space for OCaml projects in development
Merge pull request #4502 from zijianli1234/dev
- Modify the GCC version used for CI testing of the RISCV architecture
authored by
Yann Collet
and committed by
GitHub
08af53f4
27d09469
+32
-29
+1
-1
vendor/git/zstd-c/.github/workflows/dev-short-tests.yml
+1
-1
vendor/git/zstd-c/.github/workflows/dev-short-tests.yml
···
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{ name: PPC64LE, xcc_pkg: gcc-powerpc64le-linux-gnu, xcc: powerpc64le-linux-gnu-gcc, xemu_pkg: qemu-system-ppc, xemu: qemu-ppc64le-static },
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{ name: S390X, xcc_pkg: gcc-s390x-linux-gnu, xcc: s390x-linux-gnu-gcc, xemu_pkg: qemu-system-s390x, xemu: qemu-s390x-static },
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{ name: MIPS, xcc_pkg: gcc-mips-linux-gnu, xcc: mips-linux-gnu-gcc, xemu_pkg: qemu-system-mips, xemu: qemu-mips-static },
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-
{ name: RISC-V, xcc_pkg: gcc-riscv64-linux-gnu, xcc: riscv64-linux-gnu-gcc, xemu_pkg: qemu-system-riscv64,xemu: qemu-riscv64-static },
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+
{ name: RISC-V, xcc_pkg: gcc-14-riscv64-linux-gnu, xcc: riscv64-linux-gnu-gcc-14, xemu_pkg: qemu-system-riscv64,xemu: qemu-riscv64-static },
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{ name: M68K, xcc_pkg: gcc-m68k-linux-gnu, xcc: m68k-linux-gnu-gcc, xemu_pkg: qemu-system-m68k, xemu: qemu-m68k-static },
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{ name: SPARC, xcc_pkg: gcc-sparc64-linux-gnu, xcc: sparc64-linux-gnu-gcc, xemu_pkg: qemu-system-sparc, xemu: qemu-sparc64-static },
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]
+5
-10
vendor/git/zstd-c/lib/common/compiler.h
+5
-10
vendor/git/zstd-c/lib/common/compiler.h
···
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# if defined(__ARM_FEATURE_SVE2)
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# define ZSTD_ARCH_ARM_SVE2
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# endif
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-
#if defined(__riscv) && defined(__riscv_vector)
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-
#if defined(__GNUC__)
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#if (__GNUC__ > 14 || (__GNUC__ == 14 && __GNUC_MINOR__ >= 1))
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-
#define ZSTD_ARCH_RISCV_RVV
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#endif
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#elif defined(__clang__)
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#if __clang_major__ > 18 || (__clang_major__ == 18 && __clang_minor__ >= 1)
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#define ZSTD_ARCH_RISCV_RVV
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#endif
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#endif
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# if defined(__riscv) && defined(__riscv_vector)
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# if ((defined(__GNUC__) && !defined(__clang__) && __GNUC__ >= 14) || \
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(defined(__clang__) && __clang_major__ >= 19))
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#define ZSTD_ARCH_RISCV_RVV
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# endif
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#endif
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#
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# if defined(ZSTD_ARCH_X86_AVX2)
+2
vendor/git/zstd-c/lib/common/zstd_internal.h
+2
vendor/git/zstd-c/lib/common/zstd_internal.h
···
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vst1q_u8((uint8_t*)dst, vld1q_u8((const uint8_t*)src));
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#elif defined(ZSTD_ARCH_X86_SSE2)
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_mm_storeu_si128((__m128i*)dst, _mm_loadu_si128((const __m128i*)src));
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#elif defined(ZSTD_ARCH_RISCV_RVV)
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__riscv_vse8_v_u8m1((uint8_t*)dst, __riscv_vle8_v_u8m1((const uint8_t*)src, 16), 16);
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#elif defined(__clang__)
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ZSTD_memmove(dst, src, 16);
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#else
+2
-2
vendor/git/zstd-c/lib/compress/zstd_compress.c
+2
-2
vendor/git/zstd-c/lib/compress/zstd_compress.c
···
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return longLen;
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}
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-
#elif defined ZSTD_ARCH_RISCV_RVV
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+
#elif defined (ZSTD_ARCH_RISCV_RVV)
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#include <riscv_vector.h>
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/*
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* Convert `vl` sequences per iteration, using RVV intrinsics:
···
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}
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}
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-
#elif defined ZSTD_ARCH_RISCV_RVV
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#elif defined (ZSTD_ARCH_RISCV_RVV)
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BlockSummary ZSTD_get1BlockSummary(const ZSTD_Sequence* seqs, size_t nbSeqs)
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{
+22
-16
vendor/git/zstd-c/lib/compress/zstd_lazy.c
+22
-16
vendor/git/zstd-c/lib/compress/zstd_lazy.c
···
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#endif
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#if defined(ZSTD_ARCH_RISCV_RVV) && (__riscv_xlen == 64)
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FORCE_INLINE_TEMPLATE ZSTD_VecMask
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-
ZSTD_row_getRVVMask(int nbChunks, const BYTE* const src, const BYTE tag, const U32 head)
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ZSTD_row_getRVVMask(int rowEntries, const BYTE* const src, const BYTE tag, const U32 head)
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{
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ZSTD_VecMask matches;
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size_t vl;
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if (rowEntries == 16) {
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vl = __riscv_vsetvl_e8m1(16);
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vuint8m1_t chunk = __riscv_vle8_v_u8m1(src, vl);
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vbool8_t mask = __riscv_vmseq_vx_u8m1_b8(chunk, tag, vl);
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vuint16m1_t mask_u16 = __riscv_vreinterpret_v_b8_u16m1(mask);
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matches = __riscv_vmv_x_s_u16m1_u16(mask_u16);
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return ZSTD_rotateRight_U16((U16)matches, head);
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{
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vuint8m1_t chunk = __riscv_vle8_v_u8m1(src, vl);
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vbool8_t mask = __riscv_vmseq_vx_u8m1_b8(chunk, tag, vl);
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vuint16m1_t mask_u16 = __riscv_vreinterpret_v_b8_u16m1(mask);
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matches = __riscv_vmv_x_s_u16m1_u16(mask_u16);
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return ZSTD_rotateRight_U16((U16)matches, head);
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}
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} else if (rowEntries == 32) {
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vl = __riscv_vsetvl_e8m2(32);
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vuint8m2_t chunk = __riscv_vle8_v_u8m2(src, vl);
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vbool4_t mask = __riscv_vmseq_vx_u8m2_b4(chunk, tag, vl);
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vuint32m1_t mask_u32 = __riscv_vreinterpret_v_b4_u32m1(mask);
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matches = __riscv_vmv_x_s_u32m1_u32(mask_u32);
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return ZSTD_rotateRight_U32((U32)matches, head);
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{
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vuint8m2_t chunk = __riscv_vle8_v_u8m2(src, vl);
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vbool4_t mask = __riscv_vmseq_vx_u8m2_b4(chunk, tag, vl);
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vuint32m1_t mask_u32 = __riscv_vreinterpret_v_b4_u32m1(mask);
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matches = __riscv_vmv_x_s_u32m1_u32(mask_u32);
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return ZSTD_rotateRight_U32((U32)matches, head);
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}
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} else { // rowEntries = 64
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vl = __riscv_vsetvl_e8m4(64);
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vuint8m4_t chunk = __riscv_vle8_v_u8m4(src, vl);
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vbool2_t mask = __riscv_vmseq_vx_u8m4_b2(chunk, tag, vl);
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vuint64m1_t mask_u64 = __riscv_vreinterpret_v_b2_u64m1(mask);
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matches = __riscv_vmv_x_s_u64m1_u64(mask_u64);
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return ZSTD_rotateRight_U64(matches, head);
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{
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vuint8m4_t chunk = __riscv_vle8_v_u8m4(src, vl);
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vbool2_t mask = __riscv_vmseq_vx_u8m4_b2(chunk, tag, vl);
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vuint64m1_t mask_u64 = __riscv_vreinterpret_v_b2_u64m1(mask);
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matches = __riscv_vmv_x_s_u64m1_u64(mask_u64);
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return ZSTD_rotateRight_U64(matches, head);
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}
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}
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}
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#endif