cass.cityboundforest.com / pathdelver
A dungeon delver roguelike using Pathfinder 2nd edition rules
0
fork

Configure Feed

Select the types of activity you want to include in your feed.

Removing hardware.inc in favor of using the submodule

Cass Unterholzner 66905814 d11fd2f5

-1114
-1114
gb/hardware.inc
··· 1 - ;* 2 - ;* Game Boy Hardware definitions 3 - ;* https://github.com/gbdev/hardware.inc 4 - ;* 5 - ;* Based on Jones' hardware.inc 6 - ;* And based on Carsten Sorensen's ideas. 7 - ;* 8 - ;* To the extent possible under law, the authors of this work have 9 - ;* waived all copyright and related or neighboring rights to the work. 10 - ;* See https://creativecommons.org/publicdomain/zero/1.0/ for details. 11 - ;* 12 - ;* SPDX-License-Identifier: CC0-1.0 13 - ;* 14 - ;* Rev 1.1 - 15-Jul-97 : Added define check 15 - ;* Rev 1.2 - 18-Jul-97 : Added revision check macro 16 - ;* Rev 1.3 - 19-Jul-97 : Modified for RGBASM V1.05 17 - ;* Rev 1.4 - 27-Jul-97 : Modified for new subroutine prefixes 18 - ;* Rev 1.5 - 15-Aug-97 : Added _HRAM, PAD, CART defines 19 - ;* : and Nintendo Logo 20 - ;* Rev 1.6 - 30-Nov-97 : Added rDIV, rTIMA, rTMA, & rTAC 21 - ;* Rev 1.7 - 31-Jan-98 : Added _SCRN0, _SCRN1 22 - ;* Rev 1.8 - 15-Feb-98 : Added rSB, rSC 23 - ;* Rev 1.9 - 16-Feb-98 : Converted I/O registers to $FFXX format 24 - ;* Rev 2.0 - : Added GBC registers 25 - ;* Rev 2.1 - : Added MBC5 & cart RAM enable/disable defines 26 - ;* Rev 2.2 - : Fixed NR42,NR43, & NR44 equates 27 - ;* Rev 2.3 - : Fixed incorrect _HRAM equate 28 - ;* Rev 2.4 - 27-Apr-13 : Added some cart defines (AntonioND) 29 - ;* Rev 2.5 - 03-May-15 : Fixed format (AntonioND) 30 - ;* Rev 2.6 - 09-Apr-16 : Added GBC OAM and cart defines (AntonioND) 31 - ;* Rev 2.7 - 19-Jan-19 : Added rPCMXX (ISSOtm) 32 - ;* Rev 2.8 - 03-Feb-19 : Added audio registers flags (Álvaro Cuesta) 33 - ;* Rev 2.9 - 28-Feb-20 : Added utility rP1 constants 34 - ;* Rev 3.0 - 27-Aug-20 : Register ordering, byte-based sizes, OAM additions, general cleanup (Blitter Object) 35 - ;* Rev 4.0 - 03-May-21 : Updated to use RGBDS 0.5.0 syntax, changed IEF_LCDC to IEF_STAT (Eievui) 36 - ;* Rev 4.1 - 16-Aug-21 : Added more flags, bit number defines, and offset constants for OAM and window positions (rondnelson99) 37 - ;* Rev 4.2 - 04-Sep-21 : Added CH3- and CH4-specific audio registers flags (ISSOtm) 38 - ;* Rev 4.3 - 07-Nov-21 : Deprecate VRAM address constants (Eievui) 39 - ;* Rev 4.4 - 11-Jan-22 : Deprecate VRAM CART_SRAM_2KB constant (avivace) 40 - ;* Rev 4.5 - 03-Mar-22 : Added bit number definitions for OCPS, BCPS and LCDC (sukus) 41 - ;* Rev 4.6 - 15-Jun-22 : Added MBC3 registers and special values 42 - ;* Rev 4.7.0 - 27-Jun-22 : Added alternate names for some constants 43 - ;* Rev 4.7.1 - 05-Jul-22 : Added RPB_LED_ON constant 44 - ;* Rev 4.8.0 - 25-Oct-22 : Changed background addressing constants (zlago) 45 - ;* Rev 4.8.1 - 29-Apr-23 : Added rOPRI (rbong) 46 - ;* Rev 4.9.0 - 24-Jun-23 : Added definitions for interrupt vectors (sukus) 47 - ;* Rev 4.9.1 - 11-Sep-23 : Added repository link and CC0 waiver notice 48 - ;* Rev 4.9.2 - 18-Aug-24 : Corrected CART_ROM_MBC5_BAT to CART_ROM_MBC5_RAM (DevEd) 49 - 50 - 51 - ; NOTE: REVISION NUMBER CHANGES MUST BE REFLECTED 52 - ; IN `rev_Check_hardware_inc` BELOW! 53 - 54 - IF __RGBDS_MAJOR__ == 0 && __RGBDS_MINOR__ < 5 55 - FAIL "This version of 'hardware.inc' requires RGBDS version 0.5.0 or later." 56 - ENDC 57 - 58 - ; If all of these are already defined, don't do it again. 59 - 60 - IF !DEF(HARDWARE_INC) 61 - DEF HARDWARE_INC EQU 1 62 - 63 - ; Usage: rev_Check_hardware_inc <min_ver> 64 - ; Examples: rev_Check_hardware_inc 4.1.2 65 - ; rev_Check_hardware_inc 4.1 (equivalent to 4.1.0) 66 - ; rev_Check_hardware_inc 4 (equivalent to 4.0.0) 67 - MACRO rev_Check_hardware_inc 68 - DEF CUR_VER equs "4,9,2" ; ** UPDATE THIS LINE WHEN CHANGING THE REVISION NUMBER ** 69 - 70 - DEF MIN_VER equs STRRPL("\1", ".", ",") 71 - DEF INTERNAL_CHK equs """MACRO ___internal 72 - IF \\1 != \\4 || \\2 < \\5 || (\\2 == \\5 && \\3 < \\6) 73 - FAIL "Version \\1.\\2.\\3 of 'hardware.inc' is incompatible with requested version \\4.\\5.\\6" 74 - ENDC 75 - \nENDM""" 76 - INTERNAL_CHK 77 - ___internal {CUR_VER}, {MIN_VER},0,0 78 - PURGE CUR_VER, MIN_VER, INTERNAL_CHK, ___internal 79 - ENDM 80 - 81 - 82 - ;*************************************************************************** 83 - ;* 84 - ;* General memory region constants 85 - ;* 86 - ;*************************************************************************** 87 - 88 - DEF _VRAM EQU $8000 ; $8000->$9FFF 89 - DEF _SCRN0 EQU $9800 ; $9800->$9BFF 90 - DEF _SCRN1 EQU $9C00 ; $9C00->$9FFF 91 - DEF _SRAM EQU $A000 ; $A000->$BFFF 92 - DEF _RAM EQU $C000 ; $C000->$CFFF / $C000->$DFFF 93 - DEF _RAMBANK EQU $D000 ; $D000->$DFFF 94 - DEF _OAMRAM EQU $FE00 ; $FE00->$FE9F 95 - DEF _IO EQU $FF00 ; $FF00->$FF7F,$FFFF 96 - DEF _AUD3WAVERAM EQU $FF30 ; $FF30->$FF3F 97 - DEF _HRAM EQU $FF80 ; $FF80->$FFFE 98 - 99 - 100 - ;*************************************************************************** 101 - ;* 102 - ;* MBC registers 103 - ;* 104 - ;*************************************************************************** 105 - 106 - ; *** Common *** 107 - 108 - ; -- 109 - ; -- RAMG ($0000-$1FFF) 110 - ; -- Controls whether access to SRAM (and the MBC3 RTC registers) is allowed (W) 111 - ; -- 112 - DEF rRAMG EQU $0000 113 - 114 - DEF CART_SRAM_ENABLE EQU $0A 115 - DEF CART_SRAM_DISABLE EQU $00 116 - 117 - 118 - ; -- 119 - ; -- ROMB0 ($2000-$3FFF) 120 - ; -- Selects which ROM bank is mapped to the ROMX space ($4000-$7FFF) (W) 121 - ; -- 122 - ; -- The range of accepted values, as well as the behavior of writing $00, 123 - ; -- varies depending on the MBC. 124 - ; -- 125 - DEF rROMB0 EQU $2000 126 - 127 - ; -- 128 - ; -- RAMB ($4000-$5FFF) 129 - ; -- Selects which SRAM bank is mapped to the SRAM space ($A000-$BFFF) (W) 130 - ; -- 131 - ; -- The range of accepted values varies depending on the cartridge configuration. 132 - ; -- 133 - DEF rRAMB EQU $4000 134 - 135 - 136 - ; *** MBC3-specific registers *** 137 - 138 - ; Write one of these to rRAMG to map the corresponding RTC register to all SRAM space 139 - DEF RTC_S EQU $08 ; Seconds (0-59) 140 - DEF RTC_M EQU $09 ; Minutes (0-59) 141 - DEF RTC_H EQU $0A ; Hours (0-23) 142 - DEF RTC_DL EQU $0B ; Lower 8 bits of Day Counter ($00-$FF) 143 - DEF RTC_DH EQU $0C ; Bit 7 - Day Counter Carry Bit (1=Counter Overflow) 144 - ; Bit 6 - Halt (0=Active, 1=Stop Timer) 145 - ; Bit 0 - Most significant bit of Day Counter (Bit 8) 146 - 147 - 148 - ; -- 149 - ; -- RTCLATCH ($6000-$7FFF) 150 - ; -- Write $00 then $01 to latch the current time into the RTC registers (W) 151 - ; -- 152 - DEF rRTCLATCH EQU $6000 153 - 154 - 155 - ; *** MBC5-specific register *** 156 - 157 - ; -- 158 - ; -- ROMB1 ($3000-$3FFF) 159 - ; -- A 9th bit that "extends" ROMB0 if more than 256 banks are present (W) 160 - ; -- 161 - ; -- Also note that rROMB0 thus only spans $2000-$2FFF. 162 - ; -- 163 - DEF rROMB1 EQU $3000 164 - 165 - 166 - ; Bit 3 of RAMB enables the rumble motor (if any) 167 - DEF CART_RUMBLE_ON EQU 1 << 3 168 - 169 - 170 - ;*************************************************************************** 171 - ;* 172 - ;* Memory-mapped registers 173 - ;* 174 - ;*************************************************************************** 175 - 176 - ; -- 177 - ; -- P1 ($FF00) 178 - ; -- Register for reading joy pad info. (R/W) 179 - ; -- 180 - DEF rP1 EQU $FF00 181 - 182 - DEF P1F_5 EQU %00100000 ; P15 out port, set to 0 to get buttons 183 - DEF P1F_4 EQU %00010000 ; P14 out port, set to 0 to get dpad 184 - DEF P1F_3 EQU %00001000 ; P13 in port 185 - DEF P1F_2 EQU %00000100 ; P12 in port 186 - DEF P1F_1 EQU %00000010 ; P11 in port 187 - DEF P1F_0 EQU %00000001 ; P10 in port 188 - 189 - DEF P1F_GET_DPAD EQU P1F_5 190 - DEF P1F_GET_BTN EQU P1F_4 191 - DEF P1F_GET_NONE EQU P1F_4 | P1F_5 192 - 193 - 194 - ; -- 195 - ; -- SB ($FF01) 196 - ; -- Serial Transfer Data (R/W) 197 - ; -- 198 - DEF rSB EQU $FF01 199 - 200 - 201 - ; -- 202 - ; -- SC ($FF02) 203 - ; -- Serial I/O Control (R/W) 204 - ; -- 205 - DEF rSC EQU $FF02 206 - 207 - DEF SCF_START EQU %10000000 ; Transfer Start Flag (1=Transfer in progress, or requested) 208 - DEF SCF_SPEED EQU %00000010 ; Clock Speed (0=Normal, 1=Fast) ** CGB Mode Only ** 209 - DEF SCF_SOURCE EQU %00000001 ; Shift Clock (0=External Clock, 1=Internal Clock) 210 - 211 - DEF SCB_START EQU 7 212 - DEF SCB_SPEED EQU 1 213 - DEF SCB_SOURCE EQU 0 214 - 215 - ; -- 216 - ; -- DIV ($FF04) 217 - ; -- Divider register (R/W) 218 - ; -- 219 - DEF rDIV EQU $FF04 220 - 221 - 222 - ; -- 223 - ; -- TIMA ($FF05) 224 - ; -- Timer counter (R/W) 225 - ; -- 226 - DEF rTIMA EQU $FF05 227 - 228 - 229 - ; -- 230 - ; -- TMA ($FF06) 231 - ; -- Timer modulo (R/W) 232 - ; -- 233 - DEF rTMA EQU $FF06 234 - 235 - 236 - ; -- 237 - ; -- TAC ($FF07) 238 - ; -- Timer control (R/W) 239 - ; -- 240 - DEF rTAC EQU $FF07 241 - 242 - DEF TACF_START EQU %00000100 243 - DEF TACF_STOP EQU %00000000 244 - DEF TACF_4KHZ EQU %00000000 245 - DEF TACF_16KHZ EQU %00000011 246 - DEF TACF_65KHZ EQU %00000010 247 - DEF TACF_262KHZ EQU %00000001 248 - 249 - DEF TACB_START EQU 2 250 - 251 - 252 - ; -- 253 - ; -- IF ($FF0F) 254 - ; -- Interrupt Flag (R/W) 255 - ; -- 256 - DEF rIF EQU $FF0F 257 - 258 - 259 - ; -- 260 - ; -- AUD1SWEEP/NR10 ($FF10) 261 - ; -- Sweep register (R/W) 262 - ; -- 263 - ; -- Bit 6-4 - Sweep Time 264 - ; -- Bit 3 - Sweep Increase/Decrease 265 - ; -- 0: Addition (frequency increases???) 266 - ; -- 1: Subtraction (frequency increases???) 267 - ; -- Bit 2-0 - Number of sweep shift (# 0-7) 268 - ; -- Sweep Time: (n*7.8ms) 269 - ; -- 270 - DEF rNR10 EQU $FF10 271 - DEF rAUD1SWEEP EQU rNR10 272 - 273 - DEF AUD1SWEEP_UP EQU %00000000 274 - DEF AUD1SWEEP_DOWN EQU %00001000 275 - 276 - 277 - ; -- 278 - ; -- AUD1LEN/NR11 ($FF11) 279 - ; -- Sound length/Wave pattern duty (R/W) 280 - ; -- 281 - ; -- Bit 7-6 - Wave Pattern Duty (00:12.5% 01:25% 10:50% 11:75%) 282 - ; -- Bit 5-0 - Sound length data (# 0-63) 283 - ; -- 284 - DEF rNR11 EQU $FF11 285 - DEF rAUD1LEN EQU rNR11 286 - 287 - 288 - ; -- 289 - ; -- AUD1ENV/NR12 ($FF12) 290 - ; -- Envelope (R/W) 291 - ; -- 292 - ; -- Bit 7-4 - Initial value of envelope 293 - ; -- Bit 3 - Envelope UP/DOWN 294 - ; -- 0: Decrease 295 - ; -- 1: Range of increase 296 - ; -- Bit 2-0 - Number of envelope sweep (# 0-7) 297 - ; -- 298 - DEF rNR12 EQU $FF12 299 - DEF rAUD1ENV EQU rNR12 300 - 301 - 302 - ; -- 303 - ; -- AUD1LOW/NR13 ($FF13) 304 - ; -- Frequency low byte (W) 305 - ; -- 306 - DEF rNR13 EQU $FF13 307 - DEF rAUD1LOW EQU rNR13 308 - 309 - 310 - ; -- 311 - ; -- AUD1HIGH/NR14 ($FF14) 312 - ; -- Frequency high byte (W) 313 - ; -- 314 - ; -- Bit 7 - Initial (when set, sound restarts) 315 - ; -- Bit 6 - Counter/consecutive selection 316 - ; -- Bit 2-0 - Frequency's higher 3 bits 317 - ; -- 318 - DEF rNR14 EQU $FF14 319 - DEF rAUD1HIGH EQU rNR14 320 - 321 - 322 - ; -- 323 - ; -- AUD2LEN/NR21 ($FF16) 324 - ; -- Sound Length; Wave Pattern Duty (R/W) 325 - ; -- 326 - ; -- see AUD1LEN for info 327 - ; -- 328 - DEF rNR21 EQU $FF16 329 - DEF rAUD2LEN EQU rNR21 330 - 331 - 332 - ; -- 333 - ; -- AUD2ENV/NR22 ($FF17) 334 - ; -- Envelope (R/W) 335 - ; -- 336 - ; -- see AUD1ENV for info 337 - ; -- 338 - DEF rNR22 EQU $FF17 339 - DEF rAUD2ENV EQU rNR22 340 - 341 - 342 - ; -- 343 - ; -- AUD2LOW/NR23 ($FF18) 344 - ; -- Frequency low byte (W) 345 - ; -- 346 - DEF rNR23 EQU $FF18 347 - DEF rAUD2LOW EQU rNR23 348 - 349 - 350 - ; -- 351 - ; -- AUD2HIGH/NR24 ($FF19) 352 - ; -- Frequency high byte (W) 353 - ; -- 354 - ; -- see AUD1HIGH for info 355 - ; -- 356 - DEF rNR24 EQU $FF19 357 - DEF rAUD2HIGH EQU rNR24 358 - 359 - 360 - ; -- 361 - ; -- AUD3ENA/NR30 ($FF1A) 362 - ; -- Sound on/off (R/W) 363 - ; -- 364 - ; -- Bit 7 - Sound ON/OFF (1=ON,0=OFF) 365 - ; -- 366 - DEF rNR30 EQU $FF1A 367 - DEF rAUD3ENA EQU rNR30 368 - 369 - DEF AUD3ENA_OFF EQU %00000000 370 - DEF AUD3ENA_ON EQU %10000000 371 - 372 - 373 - ; -- 374 - ; -- AUD3LEN/NR31 ($FF1B) 375 - ; -- Sound length (R/W) 376 - ; -- 377 - ; -- Bit 7-0 - Sound length 378 - ; -- 379 - DEF rNR31 EQU $FF1B 380 - DEF rAUD3LEN EQU rNR31 381 - 382 - 383 - ; -- 384 - ; -- AUD3LEVEL/NR32 ($FF1C) 385 - ; -- Select output level 386 - ; -- 387 - ; -- Bit 6-5 - Select output level 388 - ; -- 00: 0/1 (mute) 389 - ; -- 01: 1/1 390 - ; -- 10: 1/2 391 - ; -- 11: 1/4 392 - ; -- 393 - DEF rNR32 EQU $FF1C 394 - DEF rAUD3LEVEL EQU rNR32 395 - 396 - DEF AUD3LEVEL_MUTE EQU %00000000 397 - DEF AUD3LEVEL_100 EQU %00100000 398 - DEF AUD3LEVEL_50 EQU %01000000 399 - DEF AUD3LEVEL_25 EQU %01100000 400 - 401 - 402 - ; -- 403 - ; -- AUD3LOW/NR33 ($FF1D) 404 - ; -- Frequency low byte (W) 405 - ; -- 406 - ; -- see AUD1LOW for info 407 - ; -- 408 - DEF rNR33 EQU $FF1D 409 - DEF rAUD3LOW EQU rNR33 410 - 411 - 412 - ; -- 413 - ; -- AUD3HIGH/NR34 ($FF1E) 414 - ; -- Frequency high byte (W) 415 - ; -- 416 - ; -- see AUD1HIGH for info 417 - ; -- 418 - DEF rNR34 EQU $FF1E 419 - DEF rAUD3HIGH EQU rNR34 420 - 421 - 422 - ; -- 423 - ; -- AUD4LEN/NR41 ($FF20) 424 - ; -- Sound length (R/W) 425 - ; -- 426 - ; -- Bit 5-0 - Sound length data (# 0-63) 427 - ; -- 428 - DEF rNR41 EQU $FF20 429 - DEF rAUD4LEN EQU rNR41 430 - 431 - 432 - ; -- 433 - ; -- AUD4ENV/NR42 ($FF21) 434 - ; -- Envelope (R/W) 435 - ; -- 436 - ; -- see AUD1ENV for info 437 - ; -- 438 - DEF rNR42 EQU $FF21 439 - DEF rAUD4ENV EQU rNR42 440 - 441 - 442 - ; -- 443 - ; -- AUD4POLY/NR43 ($FF22) 444 - ; -- Polynomial counter (R/W) 445 - ; -- 446 - ; -- Bit 7-4 - Selection of the shift clock frequency of the (scf) 447 - ; -- polynomial counter (0000-1101) 448 - ; -- freq=drf*1/2^scf (not sure) 449 - ; -- Bit 3 - Selection of the polynomial counter's step 450 - ; -- 0: 15 steps 451 - ; -- 1: 7 steps 452 - ; -- Bit 2-0 - Selection of the dividing ratio of frequencies (drf) 453 - ; -- 000: f/4 001: f/8 010: f/16 011: f/24 454 - ; -- 100: f/32 101: f/40 110: f/48 111: f/56 (f=4.194304 Mhz) 455 - ; -- 456 - DEF rNR43 EQU $FF22 457 - DEF rAUD4POLY EQU rNR43 458 - 459 - DEF AUD4POLY_15STEP EQU %00000000 460 - DEF AUD4POLY_7STEP EQU %00001000 461 - 462 - 463 - ; -- 464 - ; -- AUD4GO/NR44 ($FF23) 465 - ; -- 466 - ; -- Bit 7 - Initial (when set, sound restarts) 467 - ; -- Bit 6 - Counter/consecutive selection 468 - ; -- 469 - DEF rNR44 EQU $FF23 470 - DEF rAUD4GO EQU rNR44 471 - 472 - 473 - ; -- 474 - ; -- AUDVOL/NR50 ($FF24) 475 - ; -- Channel control / ON-OFF / Volume (R/W) 476 - ; -- 477 - ; -- Bit 7 - Vin->SO2 ON/OFF (left) 478 - ; -- Bit 6-4 - SO2 output level (left speaker) (# 0-7) 479 - ; -- Bit 3 - Vin->SO1 ON/OFF (right) 480 - ; -- Bit 2-0 - SO1 output level (right speaker) (# 0-7) 481 - ; -- 482 - DEF rNR50 EQU $FF24 483 - DEF rAUDVOL EQU rNR50 484 - 485 - DEF AUDVOL_VIN_LEFT EQU %10000000 ; SO2 486 - DEF AUDVOL_VIN_RIGHT EQU %00001000 ; SO1 487 - 488 - 489 - ; -- 490 - ; -- AUDTERM/NR51 ($FF25) 491 - ; -- Selection of Sound output terminal (R/W) 492 - ; -- 493 - ; -- Bit 7 - Output channel 4 to SO2 terminal (left) 494 - ; -- Bit 6 - Output channel 3 to SO2 terminal (left) 495 - ; -- Bit 5 - Output channel 2 to SO2 terminal (left) 496 - ; -- Bit 4 - Output channel 1 to SO2 terminal (left) 497 - ; -- Bit 3 - Output channel 4 to SO1 terminal (right) 498 - ; -- Bit 2 - Output channel 3 to SO1 terminal (right) 499 - ; -- Bit 1 - Output channel 2 to SO1 terminal (right) 500 - ; -- Bit 0 - Output channel 1 to SO1 terminal (right) 501 - ; -- 502 - DEF rNR51 EQU $FF25 503 - DEF rAUDTERM EQU rNR51 504 - 505 - ; SO2 506 - DEF AUDTERM_4_LEFT EQU %10000000 507 - DEF AUDTERM_3_LEFT EQU %01000000 508 - DEF AUDTERM_2_LEFT EQU %00100000 509 - DEF AUDTERM_1_LEFT EQU %00010000 510 - ; SO1 511 - DEF AUDTERM_4_RIGHT EQU %00001000 512 - DEF AUDTERM_3_RIGHT EQU %00000100 513 - DEF AUDTERM_2_RIGHT EQU %00000010 514 - DEF AUDTERM_1_RIGHT EQU %00000001 515 - 516 - 517 - ; -- 518 - ; -- AUDENA/NR52 ($FF26) 519 - ; -- Sound on/off (R/W) 520 - ; -- 521 - ; -- Bit 7 - All sound on/off (sets all audio regs to 0!) 522 - ; -- Bit 3 - Sound 4 ON flag (read only) 523 - ; -- Bit 2 - Sound 3 ON flag (read only) 524 - ; -- Bit 1 - Sound 2 ON flag (read only) 525 - ; -- Bit 0 - Sound 1 ON flag (read only) 526 - ; -- 527 - DEF rNR52 EQU $FF26 528 - DEF rAUDENA EQU rNR52 529 - 530 - DEF AUDENA_ON EQU %10000000 531 - DEF AUDENA_OFF EQU %00000000 ; sets all audio regs to 0! 532 - 533 - 534 - ; -- 535 - ; -- LCDC ($FF40) 536 - ; -- LCD Control (R/W) 537 - ; -- 538 - DEF rLCDC EQU $FF40 539 - 540 - DEF LCDCF_OFF EQU %00000000 ; LCD Control Operation 541 - DEF LCDCF_ON EQU %10000000 ; LCD Control Operation 542 - DEF LCDCF_WIN9800 EQU %00000000 ; Window Tile Map Display Select 543 - DEF LCDCF_WIN9C00 EQU %01000000 ; Window Tile Map Display Select 544 - DEF LCDCF_WINOFF EQU %00000000 ; Window Display 545 - DEF LCDCF_WINON EQU %00100000 ; Window Display 546 - DEF LCDCF_BLK21 EQU %00000000 ; BG & Window Tile Data Select 547 - DEF LCDCF_BLK01 EQU %00010000 ; BG & Window Tile Data Select 548 - DEF LCDCF_BG9800 EQU %00000000 ; BG Tile Map Display Select 549 - DEF LCDCF_BG9C00 EQU %00001000 ; BG Tile Map Display Select 550 - DEF LCDCF_OBJ8 EQU %00000000 ; OBJ Construction 551 - DEF LCDCF_OBJ16 EQU %00000100 ; OBJ Construction 552 - DEF LCDCF_OBJOFF EQU %00000000 ; OBJ Display 553 - DEF LCDCF_OBJON EQU %00000010 ; OBJ Display 554 - DEF LCDCF_BGOFF EQU %00000000 ; BG Display 555 - DEF LCDCF_BGON EQU %00000001 ; BG Display 556 - 557 - DEF LCDCB_ON EQU 7 ; LCD Control Operation 558 - DEF LCDCB_WIN9C00 EQU 6 ; Window Tile Map Display Select 559 - DEF LCDCB_WINON EQU 5 ; Window Display 560 - DEF LCDCB_BLKS EQU 4 ; BG & Window Tile Data Select 561 - DEF LCDCB_BG9C00 EQU 3 ; BG Tile Map Display Select 562 - DEF LCDCB_OBJ16 EQU 2 ; OBJ Construction 563 - DEF LCDCB_OBJON EQU 1 ; OBJ Display 564 - DEF LCDCB_BGON EQU 0 ; BG Display 565 - ; "Window Character Data Select" follows BG 566 - 567 - 568 - ; -- 569 - ; -- STAT ($FF41) 570 - ; -- LCDC Status (R/W) 571 - ; -- 572 - DEF rSTAT EQU $FF41 573 - 574 - DEF STATF_LYC EQU %01000000 ; LYC=LY Coincidence (Selectable) 575 - DEF STATF_MODE10 EQU %00100000 ; Mode 10 576 - DEF STATF_MODE01 EQU %00010000 ; Mode 01 (V-Blank) 577 - DEF STATF_MODE00 EQU %00001000 ; Mode 00 (H-Blank) 578 - DEF STATF_LYCF EQU %00000100 ; Coincidence Flag 579 - DEF STATF_HBL EQU %00000000 ; H-Blank 580 - DEF STATF_VBL EQU %00000001 ; V-Blank 581 - DEF STATF_OAM EQU %00000010 ; OAM-RAM is used by system 582 - DEF STATF_LCD EQU %00000011 ; Both OAM and VRAM used by system 583 - DEF STATF_BUSY EQU %00000010 ; When set, VRAM access is unsafe 584 - 585 - DEF STATB_LYC EQU 6 586 - DEF STATB_MODE10 EQU 5 587 - DEF STATB_MODE01 EQU 4 588 - DEF STATB_MODE00 EQU 3 589 - DEF STATB_LYCF EQU 2 590 - DEF STATB_BUSY EQU 1 591 - 592 - ; -- 593 - ; -- SCY ($FF42) 594 - ; -- Scroll Y (R/W) 595 - ; -- 596 - DEF rSCY EQU $FF42 597 - 598 - 599 - ; -- 600 - ; -- SCX ($FF43) 601 - ; -- Scroll X (R/W) 602 - ; -- 603 - DEF rSCX EQU $FF43 604 - 605 - 606 - ; -- 607 - ; -- LY ($FF44) 608 - ; -- LCDC Y-Coordinate (R) 609 - ; -- 610 - ; -- Values range from 0->153. 144->153 is the VBlank period. 611 - ; -- 612 - DEF rLY EQU $FF44 613 - 614 - 615 - ; -- 616 - ; -- LYC ($FF45) 617 - ; -- LY Compare (R/W) 618 - ; -- 619 - ; -- When LY==LYC, STATF_LYCF will be set in STAT 620 - ; -- 621 - DEF rLYC EQU $FF45 622 - 623 - 624 - ; -- 625 - ; -- DMA ($FF46) 626 - ; -- DMA Transfer and Start Address (W) 627 - ; -- 628 - DEF rDMA EQU $FF46 629 - 630 - 631 - ; -- 632 - ; -- BGP ($FF47) 633 - ; -- BG Palette Data (W) 634 - ; -- 635 - ; -- Bit 7-6 - Intensity for %11 636 - ; -- Bit 5-4 - Intensity for %10 637 - ; -- Bit 3-2 - Intensity for %01 638 - ; -- Bit 1-0 - Intensity for %00 639 - ; -- 640 - DEF rBGP EQU $FF47 641 - 642 - 643 - ; -- 644 - ; -- OBP0 ($FF48) 645 - ; -- Object Palette 0 Data (W) 646 - ; -- 647 - ; -- See BGP for info 648 - ; -- 649 - DEF rOBP0 EQU $FF48 650 - 651 - 652 - ; -- 653 - ; -- OBP1 ($FF49) 654 - ; -- Object Palette 1 Data (W) 655 - ; -- 656 - ; -- See BGP for info 657 - ; -- 658 - DEF rOBP1 EQU $FF49 659 - 660 - 661 - ; -- 662 - ; -- WY ($FF4A) 663 - ; -- Window Y Position (R/W) 664 - ; -- 665 - ; -- 0 <= WY <= 143 666 - ; -- When WY = 0, the window is displayed from the top edge of the LCD screen. 667 - ; -- 668 - DEF rWY EQU $FF4A 669 - 670 - 671 - ; -- 672 - ; -- WX ($FF4B) 673 - ; -- Window X Position (R/W) 674 - ; -- 675 - ; -- 7 <= WX <= 166 676 - ; -- When WX = 7, the window is displayed from the left edge of the LCD screen. 677 - ; -- Values of 0-6 and 166 are unreliable due to hardware bugs. 678 - ; -- 679 - DEF rWX EQU $FF4B 680 - 681 - DEF WX_OFS EQU 7 ; add this to a screen position to get a WX position 682 - 683 - 684 - ; -- 685 - ; -- SPEED ($FF4D) 686 - ; -- Select CPU Speed (R/W) 687 - ; -- 688 - DEF rKEY1 EQU $FF4D 689 - DEF rSPD EQU rKEY1 690 - 691 - DEF KEY1F_DBLSPEED EQU %10000000 ; 0=Normal Speed, 1=Double Speed (R) 692 - DEF KEY1F_PREPARE EQU %00000001 ; 0=No, 1=Prepare (R/W) 693 - 694 - 695 - ; -- 696 - ; -- VBK ($FF4F) 697 - ; -- Select Video RAM Bank (R/W) 698 - ; -- 699 - ; -- Bit 0 - Bank Specification (0: Specify Bank 0; 1: Specify Bank 1) 700 - ; -- 701 - DEF rVBK EQU $FF4F 702 - 703 - 704 - ; -- 705 - ; -- HDMA1 ($FF51) 706 - ; -- High byte for Horizontal Blanking/General Purpose DMA source address (W) 707 - ; -- CGB Mode Only 708 - ; -- 709 - DEF rHDMA1 EQU $FF51 710 - 711 - 712 - ; -- 713 - ; -- HDMA2 ($FF52) 714 - ; -- Low byte for Horizontal Blanking/General Purpose DMA source address (W) 715 - ; -- CGB Mode Only 716 - ; -- 717 - DEF rHDMA2 EQU $FF52 718 - 719 - 720 - ; -- 721 - ; -- HDMA3 ($FF53) 722 - ; -- High byte for Horizontal Blanking/General Purpose DMA destination address (W) 723 - ; -- CGB Mode Only 724 - ; -- 725 - DEF rHDMA3 EQU $FF53 726 - 727 - 728 - ; -- 729 - ; -- HDMA4 ($FF54) 730 - ; -- Low byte for Horizontal Blanking/General Purpose DMA destination address (W) 731 - ; -- CGB Mode Only 732 - ; -- 733 - DEF rHDMA4 EQU $FF54 734 - 735 - 736 - ; -- 737 - ; -- HDMA5 ($FF55) 738 - ; -- Transfer length (in tiles minus 1)/mode/start for Horizontal Blanking, General Purpose DMA (R/W) 739 - ; -- CGB Mode Only 740 - ; -- 741 - DEF rHDMA5 EQU $FF55 742 - 743 - DEF HDMA5F_MODE_GP EQU %00000000 ; General Purpose DMA (W) 744 - DEF HDMA5F_MODE_HBL EQU %10000000 ; HBlank DMA (W) 745 - DEF HDMA5B_MODE EQU 7 ; DMA mode select (W) 746 - 747 - ; -- Once DMA has started, use HDMA5F_BUSY to check when the transfer is complete 748 - DEF HDMA5F_BUSY EQU %10000000 ; 0=Busy (DMA still in progress), 1=Transfer complete (R) 749 - 750 - 751 - ; -- 752 - ; -- RP ($FF56) 753 - ; -- Infrared Communications Port (R/W) 754 - ; -- CGB Mode Only 755 - ; -- 756 - DEF rRP EQU $FF56 757 - 758 - DEF RPF_ENREAD EQU %11000000 759 - DEF RPF_DATAIN EQU %00000010 ; 0=Receiving IR Signal, 1=Normal 760 - DEF RPF_WRITE_HI EQU %00000001 761 - DEF RPF_WRITE_LO EQU %00000000 762 - 763 - DEF RPB_LED_ON EQU 0 764 - DEF RPB_DATAIN EQU 1 765 - 766 - 767 - ; -- 768 - ; -- BCPS/BGPI ($FF68) 769 - ; -- Background Color Palette Specification (aka Background Palette Index) (R/W) 770 - ; -- 771 - DEF rBCPS EQU $FF68 772 - DEF rBGPI EQU rBCPS 773 - 774 - DEF BCPSF_AUTOINC EQU %10000000 ; Auto Increment (0=Disabled, 1=Increment after Writing) 775 - DEF BCPSB_AUTOINC EQU 7 776 - DEF BGPIF_AUTOINC EQU BCPSF_AUTOINC 777 - DEF BGPIB_AUTOINC EQU BCPSB_AUTOINC 778 - 779 - 780 - ; -- 781 - ; -- BCPD/BGPD ($FF69) 782 - ; -- Background Color Palette Data (aka Background Palette Data) (R/W) 783 - ; -- 784 - DEF rBCPD EQU $FF69 785 - DEF rBGPD EQU rBCPD 786 - 787 - 788 - ; -- 789 - ; -- OCPS/OBPI ($FF6A) 790 - ; -- Object Color Palette Specification (aka Object Background Palette Index) (R/W) 791 - ; -- 792 - DEF rOCPS EQU $FF6A 793 - DEF rOBPI EQU rOCPS 794 - 795 - DEF OCPSF_AUTOINC EQU %10000000 ; Auto Increment (0=Disabled, 1=Increment after Writing) 796 - DEF OCPSB_AUTOINC EQU 7 797 - DEF OBPIF_AUTOINC EQU OCPSF_AUTOINC 798 - DEF OBPIB_AUTOINC EQU OCPSB_AUTOINC 799 - 800 - 801 - ; -- 802 - ; -- OCPD/OBPD ($FF6B) 803 - ; -- Object Color Palette Data (aka Object Background Palette Data) (R/W) 804 - ; -- 805 - DEF rOCPD EQU $FF6B 806 - DEF rOBPD EQU rOCPD 807 - 808 - 809 - ; -- 810 - ; -- OPRI ($FF6C) 811 - ; -- Object Priority Mode (R/W) 812 - ; -- CGB Only 813 - 814 - ; -- 815 - ; -- Priority can be changed only from the boot ROM 816 - ; -- 817 - DEF rOPRI EQU $FF6C 818 - 819 - DEF OPRI_OAM EQU 0 ; Prioritize objects by location in OAM (CGB Mode default) 820 - DEF OPRI_COORD EQU 1 ; Prioritize objects by x-coordinate (Non-CGB Mode default) 821 - 822 - 823 - 824 - ; -- 825 - ; -- SMBK/SVBK ($FF70) 826 - ; -- Select Main RAM Bank (R/W) 827 - ; -- 828 - ; -- Bit 2-0 - Bank Specification (0,1: Specify Bank 1; 2-7: Specify Banks 2-7) 829 - ; -- 830 - DEF rSVBK EQU $FF70 831 - DEF rSMBK EQU rSVBK 832 - 833 - 834 - ; -- 835 - ; -- PCM12 ($FF76) 836 - ; -- Sound channel 1&2 PCM amplitude (R) 837 - ; -- 838 - ; -- Bit 7-4 - Copy of sound channel 2's PCM amplitude 839 - ; -- Bit 3-0 - Copy of sound channel 1's PCM amplitude 840 - ; -- 841 - DEF rPCM12 EQU $FF76 842 - 843 - 844 - ; -- 845 - ; -- PCM34 ($FF77) 846 - ; -- Sound channel 3&4 PCM amplitude (R) 847 - ; -- 848 - ; -- Bit 7-4 - Copy of sound channel 4's PCM amplitude 849 - ; -- Bit 3-0 - Copy of sound channel 3's PCM amplitude 850 - ; -- 851 - DEF rPCM34 EQU $FF77 852 - 853 - 854 - ; -- 855 - ; -- IE ($FFFF) 856 - ; -- Interrupt Enable (R/W) 857 - ; -- 858 - DEF rIE EQU $FFFF 859 - 860 - DEF IEF_HILO EQU %00010000 ; Transition from High to Low of Pin number P10-P13 861 - DEF IEF_SERIAL EQU %00001000 ; Serial I/O transfer end 862 - DEF IEF_TIMER EQU %00000100 ; Timer Overflow 863 - DEF IEF_STAT EQU %00000010 ; STAT 864 - DEF IEF_VBLANK EQU %00000001 ; V-Blank 865 - 866 - DEF IEB_HILO EQU 4 867 - DEF IEB_SERIAL EQU 3 868 - DEF IEB_TIMER EQU 2 869 - DEF IEB_STAT EQU 1 870 - DEF IEB_VBLANK EQU 0 871 - 872 - 873 - ;*************************************************************************** 874 - ;* 875 - ;* Flags common to multiple sound channels 876 - ;* 877 - ;*************************************************************************** 878 - 879 - ; -- 880 - ; -- Square wave duty cycle 881 - ; -- 882 - ; -- Can be used with AUD1LEN and AUD2LEN 883 - ; -- See AUD1LEN for more info 884 - ; -- 885 - DEF AUDLEN_DUTY_12_5 EQU %00000000 ; 12.5% 886 - DEF AUDLEN_DUTY_25 EQU %01000000 ; 25% 887 - DEF AUDLEN_DUTY_50 EQU %10000000 ; 50% 888 - DEF AUDLEN_DUTY_75 EQU %11000000 ; 75% 889 - 890 - 891 - ; -- 892 - ; -- Audio envelope flags 893 - ; -- 894 - ; -- Can be used with AUD1ENV, AUD2ENV, AUD4ENV 895 - ; -- See AUD1ENV for more info 896 - ; -- 897 - DEF AUDENV_UP EQU %00001000 898 - DEF AUDENV_DOWN EQU %00000000 899 - 900 - 901 - ; -- 902 - ; -- Audio trigger flags 903 - ; -- 904 - ; -- Can be used with AUD1HIGH, AUD2HIGH, AUD3HIGH 905 - ; -- See AUD1HIGH for more info 906 - ; -- 907 - DEF AUDHIGH_RESTART EQU %10000000 908 - DEF AUDHIGH_LENGTH_ON EQU %01000000 909 - DEF AUDHIGH_LENGTH_OFF EQU %00000000 910 - 911 - 912 - ;*************************************************************************** 913 - ;* 914 - ;* CPU values on bootup (a=type, b=qualifier) 915 - ;* 916 - ;*************************************************************************** 917 - 918 - DEF BOOTUP_A_DMG EQU $01 ; Dot Matrix Game 919 - DEF BOOTUP_A_CGB EQU $11 ; Color Game Boy 920 - DEF BOOTUP_A_MGB EQU $FF ; Mini Game Boy (Pocket Game Boy) 921 - 922 - ; if a=BOOTUP_A_CGB, bit 0 in b can be checked to determine if real CGB or 923 - ; other system running in GBC mode 924 - DEF BOOTUP_B_CGB EQU %00000000 925 - DEF BOOTUP_B_AGB EQU %00000001 ; GBA, GBA SP, Game Boy Player, or New GBA SP 926 - 927 - 928 - ;*************************************************************************** 929 - ;* 930 - ;* Interrupt vector addresses 931 - ;* 932 - ;*************************************************************************** 933 - 934 - DEF INT_HANDLER_VBLANK EQU $0040 935 - DEF INT_HANDLER_STAT EQU $0048 936 - DEF INT_HANDLER_TIMER EQU $0050 937 - DEF INT_HANDLER_SERIAL EQU $0058 938 - DEF INT_HANDLER_JOYPAD EQU $0060 939 - 940 - 941 - ;*************************************************************************** 942 - ;* 943 - ;* Header 944 - ;* 945 - ;*************************************************************************** 946 - 947 - ;* 948 - ;* Nintendo scrolling logo 949 - ;* (Code won't work on a real Game Boy) 950 - ;* (if next lines are altered.) 951 - MACRO NINTENDO_LOGO 952 - DB $CE,$ED,$66,$66,$CC,$0D,$00,$0B,$03,$73,$00,$83,$00,$0C,$00,$0D 953 - DB $00,$08,$11,$1F,$88,$89,$00,$0E,$DC,$CC,$6E,$E6,$DD,$DD,$D9,$99 954 - DB $BB,$BB,$67,$63,$6E,$0E,$EC,$CC,$DD,$DC,$99,$9F,$BB,$B9,$33,$3E 955 - ENDM 956 - 957 - ; $0143 Color Game Boy compatibility code 958 - DEF CART_COMPATIBLE_DMG EQU $00 959 - DEF CART_COMPATIBLE_DMG_GBC EQU $80 960 - DEF CART_COMPATIBLE_GBC EQU $C0 961 - 962 - ; $0146 Game Boy/Super Game Boy indicator 963 - DEF CART_INDICATOR_GB EQU $00 964 - DEF CART_INDICATOR_SGB EQU $03 965 - 966 - ; $0147 Cartridge type 967 - DEF CART_ROM EQU $00 968 - DEF CART_ROM_MBC1 EQU $01 969 - DEF CART_ROM_MBC1_RAM EQU $02 970 - DEF CART_ROM_MBC1_RAM_BAT EQU $03 971 - DEF CART_ROM_MBC2 EQU $05 972 - DEF CART_ROM_MBC2_BAT EQU $06 973 - DEF CART_ROM_RAM EQU $08 974 - DEF CART_ROM_RAM_BAT EQU $09 975 - DEF CART_ROM_MMM01 EQU $0B 976 - DEF CART_ROM_MMM01_RAM EQU $0C 977 - DEF CART_ROM_MMM01_RAM_BAT EQU $0D 978 - DEF CART_ROM_MBC3_BAT_RTC EQU $0F 979 - DEF CART_ROM_MBC3_RAM_BAT_RTC EQU $10 980 - DEF CART_ROM_MBC3 EQU $11 981 - DEF CART_ROM_MBC3_RAM EQU $12 982 - DEF CART_ROM_MBC3_RAM_BAT EQU $13 983 - DEF CART_ROM_MBC5 EQU $19 984 - DEF CART_ROM_MBC5_RAM EQU $1A 985 - DEF CART_ROM_MBC5_RAM_BAT EQU $1B 986 - DEF CART_ROM_MBC5_RUMBLE EQU $1C 987 - DEF CART_ROM_MBC5_RAM_RUMBLE EQU $1D 988 - DEF CART_ROM_MBC5_RAM_BAT_RUMBLE EQU $1E 989 - DEF CART_ROM_MBC7_RAM_BAT_GYRO EQU $22 990 - DEF CART_ROM_POCKET_CAMERA EQU $FC 991 - DEF CART_ROM_BANDAI_TAMA5 EQU $FD 992 - DEF CART_ROM_HUDSON_HUC3 EQU $FE 993 - DEF CART_ROM_HUDSON_HUC1 EQU $FF 994 - 995 - ; $0148 ROM size 996 - ; these are kilobytes 997 - DEF CART_ROM_32KB EQU $00 ; 2 banks 998 - DEF CART_ROM_64KB EQU $01 ; 4 banks 999 - DEF CART_ROM_128KB EQU $02 ; 8 banks 1000 - DEF CART_ROM_256KB EQU $03 ; 16 banks 1001 - DEF CART_ROM_512KB EQU $04 ; 32 banks 1002 - DEF CART_ROM_1024KB EQU $05 ; 64 banks 1003 - DEF CART_ROM_2048KB EQU $06 ; 128 banks 1004 - DEF CART_ROM_4096KB EQU $07 ; 256 banks 1005 - DEF CART_ROM_8192KB EQU $08 ; 512 banks 1006 - DEF CART_ROM_1152KB EQU $52 ; 72 banks 1007 - DEF CART_ROM_1280KB EQU $53 ; 80 banks 1008 - DEF CART_ROM_1536KB EQU $54 ; 96 banks 1009 - 1010 - ; $0149 SRAM size 1011 - ; these are kilobytes 1012 - DEF CART_SRAM_NONE EQU 0 1013 - DEF CART_SRAM_8KB EQU 2 ; 1 bank 1014 - DEF CART_SRAM_32KB EQU 3 ; 4 banks 1015 - DEF CART_SRAM_128KB EQU 4 ; 16 banks 1016 - 1017 - ; $014A Destination code 1018 - DEF CART_DEST_JAPANESE EQU $00 1019 - DEF CART_DEST_NON_JAPANESE EQU $01 1020 - 1021 - 1022 - ;*************************************************************************** 1023 - ;* 1024 - ;* Keypad related 1025 - ;* 1026 - ;*************************************************************************** 1027 - 1028 - DEF PADF_DOWN EQU $80 1029 - DEF PADF_UP EQU $40 1030 - DEF PADF_LEFT EQU $20 1031 - DEF PADF_RIGHT EQU $10 1032 - DEF PADF_START EQU $08 1033 - DEF PADF_SELECT EQU $04 1034 - DEF PADF_B EQU $02 1035 - DEF PADF_A EQU $01 1036 - 1037 - DEF PADB_DOWN EQU $7 1038 - DEF PADB_UP EQU $6 1039 - DEF PADB_LEFT EQU $5 1040 - DEF PADB_RIGHT EQU $4 1041 - DEF PADB_START EQU $3 1042 - DEF PADB_SELECT EQU $2 1043 - DEF PADB_B EQU $1 1044 - DEF PADB_A EQU $0 1045 - 1046 - 1047 - ;*************************************************************************** 1048 - ;* 1049 - ;* Screen related 1050 - ;* 1051 - ;*************************************************************************** 1052 - 1053 - DEF SCRN_X EQU 160 ; Width of screen in pixels 1054 - DEF SCRN_Y EQU 144 ; Height of screen in pixels. Also corresponds to the value in LY at the beginning of VBlank. 1055 - DEF SCRN_X_B EQU 20 ; Width of screen in bytes 1056 - DEF SCRN_Y_B EQU 18 ; Height of screen in bytes 1057 - 1058 - DEF SCRN_VX EQU 256 ; Virtual width of screen in pixels 1059 - DEF SCRN_VY EQU 256 ; Virtual height of screen in pixels 1060 - DEF SCRN_VX_B EQU 32 ; Virtual width of screen in bytes 1061 - DEF SCRN_VY_B EQU 32 ; Virtual height of screen in bytes 1062 - 1063 - 1064 - ;*************************************************************************** 1065 - ;* 1066 - ;* OAM related 1067 - ;* 1068 - ;*************************************************************************** 1069 - 1070 - ; OAM attributes 1071 - ; each entry in OAM RAM is 4 bytes (sizeof_OAM_ATTRS) 1072 - RSRESET 1073 - DEF OAMA_Y RB 1 ; y pos plus 16 1074 - DEF OAMA_X RB 1 ; x pos plus 8 1075 - DEF OAMA_TILEID RB 1 ; tile id 1076 - DEF OAMA_FLAGS RB 1 ; flags (see below) 1077 - DEF sizeof_OAM_ATTRS RB 0 1078 - 1079 - DEF OAM_Y_OFS EQU 16 ; add this to a screen-relative Y position to get an OAM Y position 1080 - DEF OAM_X_OFS EQU 8 ; add this to a screen-relative X position to get an OAM X position 1081 - 1082 - DEF OAM_COUNT EQU 40 ; number of OAM entries in OAM RAM 1083 - 1084 - ; flags 1085 - DEF OAMF_PRI EQU %10000000 ; Priority 1086 - DEF OAMF_YFLIP EQU %01000000 ; Y flip 1087 - DEF OAMF_XFLIP EQU %00100000 ; X flip 1088 - DEF OAMF_PAL0 EQU %00000000 ; Palette number; 0,1 (DMG) 1089 - DEF OAMF_PAL1 EQU %00010000 ; Palette number; 0,1 (DMG) 1090 - DEF OAMF_BANK0 EQU %00000000 ; Bank number; 0,1 (GBC) 1091 - DEF OAMF_BANK1 EQU %00001000 ; Bank number; 0,1 (GBC) 1092 - 1093 - DEF OAMF_PALMASK EQU %00000111 ; Palette (GBC) 1094 - 1095 - DEF OAMB_PRI EQU 7 ; Priority 1096 - DEF OAMB_YFLIP EQU 6 ; Y flip 1097 - DEF OAMB_XFLIP EQU 5 ; X flip 1098 - DEF OAMB_PAL1 EQU 4 ; Palette number; 0,1 (DMG) 1099 - DEF OAMB_BANK1 EQU 3 ; Bank number; 0,1 (GBC) 1100 - 1101 - 1102 - ; Deprecated constants. Please avoid using. 1103 - 1104 - DEF IEF_LCDC EQU %00000010 ; LCDC (see STAT) 1105 - DEF _VRAM8000 EQU _VRAM 1106 - DEF _VRAM8800 EQU _VRAM+$800 1107 - DEF _VRAM9000 EQU _VRAM+$1000 1108 - DEF CART_SRAM_2KB EQU 1 ; 1 incomplete bank 1109 - DEF LCDCF_BG8800 EQU %00000000 ; BG & Window Tile Data Select 1110 - DEF LCDCF_BG8000 EQU %00010000 ; BG & Window Tile Data Select 1111 - DEF LCDCB_BG8000 EQU 4 ; BG & Window Tile Data Select 1112 - 1113 - 1114 - ENDC ;HARDWARE_INC