mirror of OpenBSD xenocara tree
github.com/openbsd/xenocara
openbsd
Import libdrm 2.4.107
+1042
-181
+18
lib/libdrm/README.rst
+18
lib/libdrm/README.rst
···
13
13
libdrm is a low-level library, typically used by graphics drivers such as
14
14
the Mesa drivers, the X drivers, libva and similar projects.
15
15
16
+
Syncing with the Linux kernel headers
17
+
-------------------------------------
18
+
19
+
The library should be regularly updated to match the recent changes in the
20
+
`include/uapi/drm/`.
21
+
22
+
libdrm maintains a human-readable version for the token format modifier, with
23
+
the simpler ones being extracted automatically from `drm_fourcc.h` header file
24
+
with the help of a python script. This might not always possible, as some of
25
+
the vendors require decoding/extracting them programmatically. For that
26
+
reason one can enhance the current vendor functions to include/provide the
27
+
newly added token formats, or, in case there's no such decoding
28
+
function, to add one that performs the tasks of extracting them.
29
+
30
+
For simpler format modifier tokens there's a script (gen_table_fourcc.py) that
31
+
creates a static table, by going over `drm_fourcc.h` header file. The script
32
+
could be further modified if it can't handle new (simpler) token format
33
+
modifiers instead of the generated static table.
16
34
17
35
Compiling
18
36
---------
+1
lib/libdrm/amdgpu/amdgpu-symbols.txt
+1
lib/libdrm/amdgpu/amdgpu-symbols.txt
+18
lib/libdrm/amdgpu/amdgpu.h
+18
lib/libdrm/amdgpu/amdgpu.h
···
1238
1238
unsigned size, void *value);
1239
1239
1240
1240
/**
1241
+
* Query information about video capabilities
1242
+
*
1243
+
* The return sizeof(struct drm_amdgpu_info_video_caps)
1244
+
*
1245
+
* \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
1246
+
* \param caps_type - \c [in] AMDGPU_INFO_VIDEO_CAPS_DECODE(ENCODE)
1247
+
* \param size - \c [in] Size of the returned value.
1248
+
* \param value - \c [out] Pointer to the return value.
1249
+
*
1250
+
* \return 0 on success\n
1251
+
* <0 - Negative POSIX Error code
1252
+
*
1253
+
*/
1254
+
int amdgpu_query_video_caps_info(amdgpu_device_handle dev, unsigned cap_type,
1255
+
unsigned size, void *value);
1256
+
1257
+
/**
1241
1258
* Read a set of consecutive memory-mapped registers.
1242
1259
* Not all registers are allowed to be read by userspace.
1243
1260
*
···
1263
1280
*/
1264
1281
#define AMDGPU_VA_RANGE_32_BIT 0x1
1265
1282
#define AMDGPU_VA_RANGE_HIGH 0x2
1283
+
#define AMDGPU_VA_RANGE_REPLAYABLE 0x4
1266
1284
1267
1285
/**
1268
1286
* Allocate virtual address range
+15
lib/libdrm/amdgpu/amdgpu_gpu_info.c
+15
lib/libdrm/amdgpu/amdgpu_gpu_info.c
···
331
331
return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request,
332
332
sizeof(struct drm_amdgpu_info));
333
333
}
334
+
335
+
drm_public int amdgpu_query_video_caps_info(amdgpu_device_handle dev, unsigned cap_type,
336
+
unsigned size, void *value)
337
+
{
338
+
struct drm_amdgpu_info request;
339
+
340
+
memset(&request, 0, sizeof(request));
341
+
request.return_pointer = (uintptr_t)value;
342
+
request.return_size = size;
343
+
request.query = AMDGPU_INFO_VIDEO_CAPS;
344
+
request.sensor_info.type = cap_type;
345
+
346
+
return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request,
347
+
sizeof(struct drm_amdgpu_info));
348
+
}
+84
-49
lib/libdrm/amdgpu/amdgpu_vamgr.c
+84
-49
lib/libdrm/amdgpu/amdgpu_vamgr.c
···
69
69
pthread_mutex_destroy(&mgr->bo_va_mutex);
70
70
}
71
71
72
-
static drm_private uint64_t
72
+
static drm_private int
73
+
amdgpu_vamgr_subtract_hole(struct amdgpu_bo_va_hole *hole, uint64_t start_va,
74
+
uint64_t end_va)
75
+
{
76
+
if (start_va > hole->offset && end_va - hole->offset < hole->size) {
77
+
struct amdgpu_bo_va_hole *n = calloc(1, sizeof(struct amdgpu_bo_va_hole));
78
+
if (!n)
79
+
return -ENOMEM;
80
+
81
+
n->size = start_va - hole->offset;
82
+
n->offset = hole->offset;
83
+
list_add(&n->list, &hole->list);
84
+
85
+
hole->size -= (end_va - hole->offset);
86
+
hole->offset = end_va;
87
+
} else if (start_va > hole->offset) {
88
+
hole->size = start_va - hole->offset;
89
+
} else if (end_va - hole->offset < hole->size) {
90
+
hole->size -= (end_va - hole->offset);
91
+
hole->offset = end_va;
92
+
} else {
93
+
list_del(&hole->list);
94
+
free(hole);
95
+
}
96
+
97
+
return 0;
98
+
}
99
+
100
+
static drm_private int
73
101
amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size,
74
-
uint64_t alignment, uint64_t base_required)
102
+
uint64_t alignment, uint64_t base_required,
103
+
bool search_from_top, uint64_t *va_out)
75
104
{
76
105
struct amdgpu_bo_va_hole *hole, *n;
77
-
uint64_t offset = 0, waste = 0;
106
+
uint64_t offset = 0;
107
+
int ret;
78
108
79
109
80
110
alignment = MAX2(alignment, mgr->va_alignment);
81
111
size = ALIGN(size, mgr->va_alignment);
82
112
83
113
if (base_required % alignment)
84
-
return AMDGPU_INVALID_VA_ADDRESS;
114
+
return -EINVAL;
85
115
86
116
pthread_mutex_lock(&mgr->bo_va_mutex);
87
-
LIST_FOR_EACH_ENTRY_SAFE_REV(hole, n, &mgr->va_holes, list) {
88
-
if (base_required) {
89
-
if (hole->offset > base_required ||
90
-
(hole->offset + hole->size) < (base_required + size))
91
-
continue;
92
-
waste = base_required - hole->offset;
93
-
offset = base_required;
94
-
} else {
95
-
offset = hole->offset;
96
-
waste = offset % alignment;
97
-
waste = waste ? alignment - waste : 0;
98
-
offset += waste;
99
-
if (offset >= (hole->offset + hole->size)) {
100
-
continue;
117
+
if (!search_from_top) {
118
+
LIST_FOR_EACH_ENTRY_SAFE_REV(hole, n, &mgr->va_holes, list) {
119
+
if (base_required) {
120
+
if (hole->offset > base_required ||
121
+
(hole->offset + hole->size) < (base_required + size))
122
+
continue;
123
+
offset = base_required;
124
+
} else {
125
+
uint64_t waste = hole->offset % alignment;
126
+
waste = waste ? alignment - waste : 0;
127
+
offset = hole->offset + waste;
128
+
if (offset >= (hole->offset + hole->size) ||
129
+
size > (hole->offset + hole->size) - offset) {
130
+
continue;
131
+
}
101
132
}
102
-
}
103
-
if (!waste && hole->size == size) {
104
-
offset = hole->offset;
105
-
list_del(&hole->list);
106
-
free(hole);
133
+
ret = amdgpu_vamgr_subtract_hole(hole, offset, offset + size);
107
134
pthread_mutex_unlock(&mgr->bo_va_mutex);
108
-
return offset;
135
+
*va_out = offset;
136
+
return ret;
109
137
}
110
-
if ((hole->size - waste) > size) {
111
-
if (waste) {
112
-
n = calloc(1, sizeof(struct amdgpu_bo_va_hole));
113
-
n->size = waste;
114
-
n->offset = hole->offset;
115
-
list_add(&n->list, &hole->list);
138
+
} else {
139
+
LIST_FOR_EACH_ENTRY_SAFE(hole, n, &mgr->va_holes, list) {
140
+
if (base_required) {
141
+
if (hole->offset > base_required ||
142
+
(hole->offset + hole->size) < (base_required + size))
143
+
continue;
144
+
offset = base_required;
145
+
} else {
146
+
if (size > hole->size)
147
+
continue;
148
+
149
+
offset = hole->offset + hole->size - size;
150
+
offset -= offset % alignment;
151
+
if (offset < hole->offset) {
152
+
continue;
153
+
}
116
154
}
117
-
hole->size -= (size + waste);
118
-
hole->offset += size + waste;
119
-
pthread_mutex_unlock(&mgr->bo_va_mutex);
120
-
return offset;
121
-
}
122
-
if ((hole->size - waste) == size) {
123
-
hole->size = waste;
155
+
156
+
ret = amdgpu_vamgr_subtract_hole(hole, offset, offset + size);
124
157
pthread_mutex_unlock(&mgr->bo_va_mutex);
125
-
return offset;
158
+
*va_out = offset;
159
+
return ret;
126
160
}
127
161
}
128
162
129
163
pthread_mutex_unlock(&mgr->bo_va_mutex);
130
-
return AMDGPU_INVALID_VA_ADDRESS;
164
+
return -ENOMEM;
131
165
}
132
166
133
167
static drm_private void
···
196
230
uint64_t flags)
197
231
{
198
232
struct amdgpu_bo_va_mgr *vamgr;
233
+
bool search_from_top = !!(flags & AMDGPU_VA_RANGE_REPLAYABLE);
234
+
int ret;
199
235
200
236
/* Clear the flag when the high VA manager is not initialized */
201
237
if (flags & AMDGPU_VA_RANGE_HIGH && !dev->vamgr_high_32.va_max)
···
216
252
va_base_alignment = MAX2(va_base_alignment, vamgr->va_alignment);
217
253
size = ALIGN(size, vamgr->va_alignment);
218
254
219
-
*va_base_allocated = amdgpu_vamgr_find_va(vamgr, size,
220
-
va_base_alignment, va_base_required);
255
+
ret = amdgpu_vamgr_find_va(vamgr, size,
256
+
va_base_alignment, va_base_required,
257
+
search_from_top, va_base_allocated);
221
258
222
-
if (!(flags & AMDGPU_VA_RANGE_32_BIT) &&
223
-
(*va_base_allocated == AMDGPU_INVALID_VA_ADDRESS)) {
259
+
if (!(flags & AMDGPU_VA_RANGE_32_BIT) && ret) {
224
260
/* fallback to 32bit address */
225
261
if (flags & AMDGPU_VA_RANGE_HIGH)
226
262
vamgr = &dev->vamgr_high_32;
227
263
else
228
264
vamgr = &dev->vamgr_32;
229
-
*va_base_allocated = amdgpu_vamgr_find_va(vamgr, size,
230
-
va_base_alignment, va_base_required);
265
+
ret = amdgpu_vamgr_find_va(vamgr, size,
266
+
va_base_alignment, va_base_required,
267
+
search_from_top, va_base_allocated);
231
268
}
232
269
233
-
if (*va_base_allocated != AMDGPU_INVALID_VA_ADDRESS) {
270
+
if (!ret) {
234
271
struct amdgpu_va* va;
235
272
va = calloc(1, sizeof(struct amdgpu_va));
236
273
if(!va){
···
243
280
va->range = va_range_type;
244
281
va->vamgr = vamgr;
245
282
*va_range_handle = va;
246
-
} else {
247
-
return -EINVAL;
248
283
}
249
284
250
-
return 0;
285
+
return ret;
251
286
}
252
287
253
288
drm_public int amdgpu_va_range_free(amdgpu_va_handle va_range_handle)
+2
-2
lib/libdrm/amdgpu/meson.build
+2
-2
lib/libdrm/amdgpu/meson.build
···
21
21
22
22
datadir_amdgpu = join_paths(get_option('prefix'), get_option('datadir'), 'libdrm')
23
23
24
-
libdrm_amdgpu = shared_library(
24
+
libdrm_amdgpu = library(
25
25
'drm_amdgpu',
26
26
[
27
27
files(
···
36
36
],
37
37
include_directories : [inc_root, inc_drm],
38
38
link_with : libdrm,
39
-
dependencies : [dep_pthread_stubs, dep_atomic_ops],
39
+
dependencies : [dep_pthread_stubs, dep_atomic_ops, dep_rt],
40
40
version : '1.0.0',
41
41
install : true,
42
42
)
+3
lib/libdrm/core-symbols.txt
+3
lib/libdrm/core-symbols.txt
+14
lib/libdrm/data/amdgpu.ids
+14
lib/libdrm/data/amdgpu.ids
···
135
135
67C2, 01, AMD Radeon (TM) Pro V7350x2
136
136
67C2, 02, AMD Radeon (TM) Pro V7300X
137
137
67C4, 00, AMD Radeon (TM) Pro WX 7100 Graphics
138
+
67C4, 80, AMD Radeon (TM) E9560/E9565 Graphics
138
139
67C7, 00, AMD Radeon (TM) Pro WX 5100 Graphics
140
+
67C7, 80, AMD Radeon (TM) Pro E9390 Graphics
139
141
67C0, 00, AMD Radeon (TM) Pro WX 7100 Graphics
140
142
67D0, 01, AMD Radeon (TM) Pro V7350x2
141
143
67D0, 02, AMD Radeon (TM) Pro V7300X
···
254
256
7300, CB, AMD Radeon (TM) R9 Fury Series
255
257
7300, CA, AMD Radeon (TM) R9 Fury Series
256
258
7312, 00, AMD Radeon Pro W5700
259
+
731E, C6, AMD Radeon RX 5700XTB
260
+
731E, C7, AMD Radeon RX 5700B
257
261
731F, C0, AMD Radeon RX 5700 XT 50th Anniversary
258
262
731F, C1, AMD Radeon RX 5700 XT
259
263
731F, C2, AMD Radeon RX 5600M
···
265
269
7340, C1, Radeon RX 5500M
266
270
7340, C5, Radeon RX 5500 XT
267
271
7340, C7, Radeon RX 5500
272
+
7340, C9, AMD Radeon RX 5500XTB
268
273
7340, CF, Radeon RX 5300
269
274
7341, 00, AMD Radeon Pro W5500
270
275
7347, 00, AMD Radeon Pro W5500M
276
+
73A3, 00, AMD Radeon PRO W6800
277
+
73AF, C0, AMD Radeon RX 6900 XT
278
+
73BF, C0, AMD Radeon RX 6900 XT
279
+
73BF, C1, AMD Radeon RX 6800 XT
280
+
73BF, C3, AMD Radeon RX 6800
281
+
73DF, C1, AMD Radeon RX 6700 XT
282
+
73DF, C5, AMD Radeon RX 6700 XT
283
+
73E1, 00, AMD Radeon PRO W6600M
284
+
73E3, 00, AMD Radeon PRO W6600
271
285
9874, C4, AMD Radeon R7 Graphics
272
286
9874, C5, AMD Radeon R6 Graphics
273
287
9874, C6, AMD Radeon R6 Graphics
+1
-1
lib/libdrm/exynos/meson.build
+1
-1
lib/libdrm/exynos/meson.build
+1
-1
lib/libdrm/freedreno/meson.build
+1
-1
lib/libdrm/freedreno/meson.build
+84
lib/libdrm/gen_table_fourcc.py
+84
lib/libdrm/gen_table_fourcc.py
···
1
+
#!/usr/bin/env python3
2
+
3
+
# Copyright 2021 Collabora, Ltd.
4
+
#
5
+
# Permission is hereby granted, free of charge, to any person obtaining
6
+
# a copy of this software and associated documentation files (the
7
+
# "Software"), to deal in the Software without restriction, including
8
+
# without limitation the rights to use, copy, modify, merge, publish,
9
+
# distribute, sublicense, and/or sell copies of the Software, and to
10
+
# permit persons to whom the Software is furnished to do so, subject to
11
+
# the following conditions:
12
+
#
13
+
# The above copyright notice and this permission notice (including the
14
+
# next paragraph) shall be included in all copies or substantial
15
+
# portions of the Software.
16
+
#
17
+
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18
+
# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19
+
# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
20
+
# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
21
+
# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
22
+
# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
23
+
# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24
+
# SOFTWARE.
25
+
26
+
# Helper script that reads drm_fourcc.h and writes a static table with the
27
+
# simpler format token modifiers
28
+
29
+
import sys
30
+
import re
31
+
32
+
filename = sys.argv[1]
33
+
towrite = sys.argv[2]
34
+
35
+
fm_re = {
36
+
'intel': r'^#define I915_FORMAT_MOD_(\w+)',
37
+
'others': r'^#define DRM_FORMAT_MOD_((?:ARM|SAMSUNG|QCOM|VIVANTE|NVIDIA|BROADCOM|ALLWINNER)\w+)\s',
38
+
'vendors': r'^#define DRM_FORMAT_MOD_VENDOR_(\w+)'
39
+
}
40
+
41
+
def print_fm_intel(f, f_mod):
42
+
f.write(' {{ DRM_MODIFIER_INTEL({}, {}) }},\n'.format(f_mod, f_mod))
43
+
44
+
# generic write func
45
+
def print_fm(f, vendor, mod, f_name):
46
+
f.write(' {{ DRM_MODIFIER({}, {}, {}) }},\n'.format(vendor, mod, f_name))
47
+
48
+
with open(filename, "r") as f:
49
+
data = f.read()
50
+
for k, v in fm_re.items():
51
+
fm_re[k] = re.findall(v, data, flags=re.M)
52
+
53
+
with open(towrite, "w") as f:
54
+
f.write('''\
55
+
/* AUTOMATICALLY GENERATED by gen_table_fourcc.py. You should modify
56
+
that script instead of adding here entries manually! */
57
+
static const struct drmFormatModifierInfo drm_format_modifier_table[] = {
58
+
''')
59
+
f.write(' { DRM_MODIFIER_INVALID(NONE, INVALID_MODIFIER) },\n')
60
+
f.write(' { DRM_MODIFIER_LINEAR(NONE, LINEAR) },\n')
61
+
62
+
for entry in fm_re['intel']:
63
+
print_fm_intel(f, entry)
64
+
65
+
for entry in fm_re['others']:
66
+
(vendor, mod) = entry.split('_', 1)
67
+
if vendor == 'ARM' and (mod == 'TYPE_AFBC' or mod == 'TYPE_MISC'):
68
+
continue
69
+
print_fm(f, vendor, mod, mod)
70
+
71
+
f.write('''\
72
+
};
73
+
''')
74
+
75
+
f.write('''\
76
+
static const struct drmFormatModifierVendorInfo drm_format_modifier_vendor_table[] = {
77
+
''')
78
+
79
+
for entry in fm_re['vendors']:
80
+
f.write(" {{ DRM_FORMAT_MOD_VENDOR_{}, \"{}\" }},\n".format(entry, entry))
81
+
82
+
f.write('''\
83
+
};
84
+
''')
+45
-6
lib/libdrm/include/drm/amdgpu_drm.h
+45
-6
lib/libdrm/include/drm/amdgpu_drm.h
···
502
502
#define AMDGPU_VM_MTYPE_MASK (0xf << 5)
503
503
/* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */
504
504
#define AMDGPU_VM_MTYPE_DEFAULT (0 << 5)
505
-
/* Use NC MTYPE instead of default MTYPE */
505
+
/* Use Non Coherent MTYPE instead of default MTYPE */
506
506
#define AMDGPU_VM_MTYPE_NC (1 << 5)
507
-
/* Use WC MTYPE instead of default MTYPE */
507
+
/* Use Write Combine MTYPE instead of default MTYPE */
508
508
#define AMDGPU_VM_MTYPE_WC (2 << 5)
509
-
/* Use CC MTYPE instead of default MTYPE */
509
+
/* Use Cache Coherent MTYPE instead of default MTYPE */
510
510
#define AMDGPU_VM_MTYPE_CC (3 << 5)
511
-
/* Use UC MTYPE instead of default MTYPE */
511
+
/* Use UnCached MTYPE instead of default MTYPE */
512
512
#define AMDGPU_VM_MTYPE_UC (4 << 5)
513
-
/* Use RW MTYPE instead of default MTYPE */
513
+
/* Use Read Write MTYPE instead of default MTYPE */
514
514
#define AMDGPU_VM_MTYPE_RW (5 << 5)
515
515
516
516
struct drm_amdgpu_gem_va {
···
667
667
};
668
668
};
669
669
670
-
/**
670
+
/*
671
671
* Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
672
672
*
673
673
*/
674
674
#define AMDGPU_IDS_FLAGS_FUSION 0x1
675
675
#define AMDGPU_IDS_FLAGS_PREEMPTION 0x2
676
+
#define AMDGPU_IDS_FLAGS_TMZ 0x4
676
677
677
678
/* indicate if acceleration can be working */
678
679
#define AMDGPU_INFO_ACCEL_WORKING 0x00
···
723
724
#define AMDGPU_INFO_FW_TA 0x13
724
725
/* Subquery id: Query DMCUB firmware version */
725
726
#define AMDGPU_INFO_FW_DMCUB 0x14
727
+
/* Subquery id: Query TOC firmware version */
728
+
#define AMDGPU_INFO_FW_TOC 0x15
726
729
727
730
/* number of bytes moved for TTM migration */
728
731
#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
···
779
782
#define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F
780
783
/* query ras mask of enabled features*/
781
784
#define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20
785
+
/* query video encode/decode caps */
786
+
#define AMDGPU_INFO_VIDEO_CAPS 0x21
787
+
/* Subquery id: Decode */
788
+
#define AMDGPU_INFO_VIDEO_CAPS_DECODE 0
789
+
/* Subquery id: Encode */
790
+
#define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1
782
791
783
792
/* RAS MASK: UMC (VRAM) */
784
793
#define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0)
···
875
884
struct {
876
885
__u32 type;
877
886
} sensor_info;
887
+
888
+
struct {
889
+
__u32 type;
890
+
} video_cap;
878
891
};
879
892
};
880
893
···
945
958
#define AMDGPU_VRAM_TYPE_DDR3 7
946
959
#define AMDGPU_VRAM_TYPE_DDR4 8
947
960
#define AMDGPU_VRAM_TYPE_GDDR6 9
961
+
#define AMDGPU_VRAM_TYPE_DDR5 10
948
962
949
963
struct drm_amdgpu_info_device {
950
964
/** PCI Device ID */
···
1070
1084
__u32 pad;
1071
1085
};
1072
1086
1087
+
/* query video encode/decode caps */
1088
+
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0
1089
+
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1
1090
+
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2
1091
+
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3
1092
+
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4
1093
+
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5
1094
+
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6
1095
+
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7
1096
+
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8
1097
+
1098
+
struct drm_amdgpu_info_video_codec_info {
1099
+
__u32 valid;
1100
+
__u32 max_width;
1101
+
__u32 max_height;
1102
+
__u32 max_pixels_per_frame;
1103
+
__u32 max_level;
1104
+
__u32 pad;
1105
+
};
1106
+
1107
+
struct drm_amdgpu_info_video_caps {
1108
+
struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT];
1109
+
};
1110
+
1073
1111
/*
1074
1112
* Supported GPU families
1075
1113
*/
···
1082
1120
#define AMDGPU_FAMILY_AI 141 /* Vega10 */
1083
1121
#define AMDGPU_FAMILY_RV 142 /* Raven */
1084
1122
#define AMDGPU_FAMILY_NV 143 /* Navi10 */
1123
+
#define AMDGPU_FAMILY_VGH 144 /* Van Gogh */
1085
1124
1086
1125
#if defined(__cplusplus)
1087
1126
}
+3
lib/libdrm/intel/intel_chipset.c
+3
lib/libdrm/intel/intel_chipset.c
···
35
35
uint16_t gen;
36
36
} pciids[] = {
37
37
/* Keep ids sorted by gen; latest gen first */
38
+
INTEL_ADLP_IDS(12),
39
+
INTEL_ADLS_IDS(12),
38
40
INTEL_RKL_IDS(12),
39
41
INTEL_DG1_IDS(12),
40
42
INTEL_TGL_12_IDS(12),
43
+
INTEL_JSL_IDS(11),
41
44
INTEL_EHL_IDS(11),
42
45
INTEL_ICL_11_IDS(11),
43
46
INTEL_CNL_IDS(10),
+1
-1
lib/libdrm/intel/meson.build
+1
-1
lib/libdrm/intel/meson.build
+1
-1
lib/libdrm/libkms/meson.build
+1
-1
lib/libdrm/libkms/meson.build
+10
-5
lib/libdrm/meson.build
+10
-5
lib/libdrm/meson.build
···
21
21
project(
22
22
'libdrm',
23
23
['c'],
24
-
version : '2.4.104',
24
+
version : '2.4.107',
25
25
license : 'MIT',
26
-
meson_version : '>= 0.43',
26
+
meson_version : '>= 0.46',
27
27
default_options : ['buildtype=debugoptimized', 'c_std=gnu99'],
28
28
)
29
29
···
50
50
# Check for atomics
51
51
intel_atomics = false
52
52
lib_atomics = false
53
+
54
+
python3 = import('python').find_installation()
55
+
format_mod_static_table = custom_target('format_mod_static_table',
56
+
output : 'generated_static_table_fourcc.h', input: 'include/drm/drm_fourcc.h',
57
+
command : [python3, files('gen_table_fourcc.py'), '@INPUT@', '@OUTPUT@'])
53
58
54
59
dep_atomic_ops = dependency('atomic_ops', required : false)
55
60
if cc.links('''
···
261
266
endif
262
267
263
268
with_man_pages = get_option('man-pages')
264
-
prog_rst2man = find_program('rst2man', required: with_man_pages == 'true')
269
+
prog_rst2man = find_program('rst2man', 'rst2man.py', required: with_man_pages == 'true')
265
270
with_man_pages = with_man_pages != 'false' and prog_rst2man.found()
266
271
267
272
config.set10('HAVE_VISIBILITY',
···
294
299
inc_root = include_directories('.')
295
300
inc_drm = include_directories('include/drm')
296
301
297
-
libdrm = shared_library(
302
+
libdrm = library(
298
303
'drm',
299
304
[files(
300
305
'xf86drm.c', 'xf86drmHash.c', 'xf86drmRandom.c', 'xf86drmSL.c',
301
306
'xf86drmMode.c'
302
307
),
303
-
config_file,
308
+
config_file, format_mod_static_table
304
309
],
305
310
c_args : libdrm_c_args,
306
311
dependencies : [dep_valgrind, dep_rt, dep_m],
+1
-1
lib/libdrm/nouveau/meson.build
+1
-1
lib/libdrm/nouveau/meson.build
+22
-8
lib/libdrm/nouveau/nouveau.c
+22
-8
lib/libdrm/nouveau/nouveau.c
···
46
46
#include "nvif/ioctl.h"
47
47
#include "nvif/unpack.h"
48
48
49
-
#ifdef DEBUG
49
+
drm_private FILE *nouveau_out = NULL;
50
50
drm_private uint32_t nouveau_debug = 0;
51
51
52
52
static void
53
-
debug_init(char *args)
53
+
debug_init(void)
54
54
{
55
-
if (args) {
56
-
int n = strtol(args, NULL, 0);
55
+
static bool once = false;
56
+
char *debug, *out;
57
+
58
+
if (once)
59
+
return;
60
+
once = true;
61
+
62
+
debug = getenv("NOUVEAU_LIBDRM_DEBUG");
63
+
if (debug) {
64
+
int n = strtol(debug, NULL, 0);
57
65
if (n >= 0)
58
66
nouveau_debug = n;
67
+
68
+
}
69
+
70
+
nouveau_out = stderr;
71
+
out = getenv("NOUVEAU_LIBDRM_OUT");
72
+
if (out) {
73
+
FILE *fout = fopen(out, "w");
74
+
if (fout)
75
+
nouveau_out = fout;
59
76
}
60
77
}
61
-
#endif
62
78
63
79
static int
64
80
nouveau_object_ioctl(struct nouveau_object *obj, void *data, uint32_t size)
···
327
343
struct nouveau_drm *drm;
328
344
drmVersionPtr ver;
329
345
330
-
#ifdef DEBUG
331
-
debug_init(getenv("NOUVEAU_LIBDRM_DEBUG"));
332
-
#endif
346
+
debug_init();
333
347
334
348
if (!(drm = calloc(1, sizeof(*drm))))
335
349
return -ENOMEM;
+7
-2
lib/libdrm/nouveau/pushbuf.c
+7
-2
lib/libdrm/nouveau/pushbuf.c
···
292
292
kref = krec->buffer + kpsh->bo_index;
293
293
bo = (void *)(unsigned long)kref->user_priv;
294
294
bgn = (uint32_t *)((char *)bo->map + kpsh->offset);
295
-
end = bgn + (kpsh->length /4);
295
+
end = bgn + ((kpsh->length & 0x7fffff) /4);
296
296
297
-
err("ch%d: psh %08x %010llx %010llx\n", chid, kpsh->bo_index,
297
+
err("ch%d: psh %s%08x %010llx %010llx\n", chid,
298
+
bo->map ? "" : "(unmapped) ", kpsh->bo_index,
298
299
(unsigned long long)kpsh->offset,
299
300
(unsigned long long)(kpsh->offset + kpsh->length));
301
+
if (!bo->map)
302
+
continue;
300
303
while (bgn < end)
301
304
err("\t0x%08x\n", *bgn++);
302
305
}
···
336
339
req.suffix0 = nvpb->suffix0;
337
340
req.suffix1 = nvpb->suffix1;
338
341
req.vram_available = 0; /* for valgrind */
342
+
if (dbg_on(1))
343
+
req.vram_available |= NOUVEAU_GEM_PUSHBUF_SYNC;
339
344
req.gart_available = 0;
340
345
341
346
if (dbg_on(0))
+1
-1
lib/libdrm/omap/meson.build
+1
-1
lib/libdrm/omap/meson.build
+1
-1
lib/libdrm/radeon/meson.build
+1
-1
lib/libdrm/radeon/meson.build
+1
-1
lib/libdrm/tegra/meson.build
+1
-1
lib/libdrm/tegra/meson.build
+108
-7
lib/libdrm/tests/amdgpu/amdgpu_test.c
+108
-7
lib/libdrm/tests/amdgpu/amdgpu_test.c
···
37
37
#include <sys/time.h>
38
38
#include <stdarg.h>
39
39
#include <stdint.h>
40
+
#ifdef __linux__
41
+
#include <linux/limits.h>
42
+
#elif __FreeBSD__
43
+
/* SPECNAMELEN in FreeBSD is defined here: */
44
+
#include <sys/param.h>
45
+
#endif
46
+
#ifdef MAJOR_IN_MKDEV
47
+
#include <sys/mkdev.h>
48
+
#endif
49
+
#ifdef MAJOR_IN_SYSMACROS
50
+
#include <sys/sysmacros.h>
51
+
#endif
40
52
41
53
#include "drm.h"
42
54
#include "xf86drmMode.h"
···
59
71
#define RAS_TESTS_STR "RAS Tests"
60
72
#define SYNCOBJ_TIMELINE_TESTS_STR "SYNCOBJ TIMELINE Tests"
61
73
#define SECURITY_TESTS_STR "Security Tests"
74
+
#define HOTUNPLUG_TESTS_STR "Hotunplug Tests"
62
75
63
76
/**
64
77
* Open handles for amdgpu devices
···
137
150
.pCleanupFunc = suite_security_tests_clean,
138
151
.pTests = security_tests,
139
152
},
153
+
{
154
+
.pName = HOTUNPLUG_TESTS_STR,
155
+
.pInitFunc = suite_hotunplug_tests_init,
156
+
.pCleanupFunc = suite_hotunplug_tests_clean,
157
+
.pTests = hotunplug_tests,
158
+
},
140
159
141
160
CU_SUITE_INFO_NULL,
142
161
};
···
198
217
.pName = SECURITY_TESTS_STR,
199
218
.pActive = suite_security_tests_enable,
200
219
},
220
+
{
221
+
.pName = HOTUNPLUG_TESTS_STR,
222
+
.pActive = suite_hotunplug_tests_enable,
223
+
},
201
224
};
202
225
203
226
···
339
362
340
363
/* Close AMD devices.
341
364
*/
342
-
static void amdgpu_close_devices()
365
+
void amdgpu_close_devices()
343
366
{
344
367
int i;
345
368
for (i = 0; i < MAX_CARDS_SUPPORTED; i++)
346
-
if (drm_amdgpu[i] >=0)
369
+
if (drm_amdgpu[i] >=0) {
347
370
close(drm_amdgpu[i]);
371
+
}
348
372
}
349
373
350
374
/* Print AMD devices information */
···
430
454
{
431
455
amdgpu_device_handle device_handle;
432
456
uint32_t major_version, minor_version, family_id;
433
-
int i;
457
+
drmDevicePtr devices[MAX_CARDS_SUPPORTED];
458
+
int i, drm_count;
434
459
int size = sizeof(suites_active_stat) / sizeof(suites_active_stat[0]);
435
460
436
461
if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
···
441
466
442
467
if (amdgpu_device_deinitialize(device_handle))
443
468
return;
469
+
470
+
drm_count = drmGetDevices2(0, devices, MAX_CARDS_SUPPORTED);
444
471
445
472
/* Set active status for suites based on their policies */
446
473
for (i = 0; i < size; ++i)
···
496
523
"gfx ring slow bad draw test (set amdgpu.lockup_timeout=50)", CU_FALSE))
497
524
fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
498
525
499
-
if (amdgpu_set_test_active(BO_TESTS_STR, "Metadata", CU_FALSE))
500
-
fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
501
-
502
526
if (amdgpu_set_test_active(BASIC_TESTS_STR, "bo eviction Test", CU_FALSE))
503
527
fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
504
528
···
524
548
//if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV)
525
549
if (amdgpu_set_test_active(BASIC_TESTS_STR, "GPU reset Test", CU_FALSE))
526
550
fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
551
+
552
+
/* You need at least 2 devices for this */
553
+
if (drm_count < 2)
554
+
if (amdgpu_set_test_active(HOTUNPLUG_TESTS_STR, "Unplug with exported fence", CU_FALSE))
555
+
fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
556
+
}
557
+
558
+
int test_device_index;
559
+
560
+
int amdgpu_open_device_on_test_index(int render_node)
561
+
{
562
+
int i;
563
+
564
+
if (amdgpu_open_devices(open_render_node) <= 0) {
565
+
perror("Cannot open AMDGPU device");
566
+
return -1;
567
+
}
568
+
569
+
if (test_device_index >= 0) {
570
+
/* Most tests run on device of drm_amdgpu[0].
571
+
* Swap the chosen device to drm_amdgpu[0].
572
+
*/
573
+
i = drm_amdgpu[0];
574
+
drm_amdgpu[0] = drm_amdgpu[test_device_index];
575
+
drm_amdgpu[test_device_index] = i;
576
+
}
577
+
578
+
return 0;
579
+
580
+
581
+
}
582
+
583
+
584
+
static bool amdgpu_node_is_drm(int maj, int min)
585
+
{
586
+
#ifdef __linux__
587
+
char path[64];
588
+
struct stat sbuf;
589
+
590
+
snprintf(path, sizeof(path), "/sys/dev/char/%d:%d/device/drm",
591
+
maj, min);
592
+
return stat(path, &sbuf) == 0;
593
+
#elif defined(__FreeBSD__)
594
+
char name[SPECNAMELEN];
595
+
596
+
if (!devname_r(makedev(maj, min), S_IFCHR, name, sizeof(name)))
597
+
return 0;
598
+
/* Handle drm/ and dri/ as both are present in different FreeBSD version
599
+
* FreeBSD on amd64/i386/powerpc external kernel modules create node in
600
+
* in /dev/drm/ and links in /dev/dri while a WIP in kernel driver creates
601
+
* only device nodes in /dev/dri/ */
602
+
return (!strncmp(name, "drm/", 4) || !strncmp(name, "dri/", 4));
603
+
#else
604
+
return maj == DRM_MAJOR;
605
+
#endif
606
+
}
607
+
608
+
char *amdgpu_get_device_from_fd(int fd)
609
+
{
610
+
#ifdef __linux__
611
+
struct stat sbuf;
612
+
char path[PATH_MAX + 1];
613
+
unsigned int maj, min;
614
+
615
+
if (fstat(fd, &sbuf))
616
+
return NULL;
617
+
618
+
maj = major(sbuf.st_rdev);
619
+
min = minor(sbuf.st_rdev);
620
+
621
+
if (!amdgpu_node_is_drm(maj, min) || !S_ISCHR(sbuf.st_mode))
622
+
return NULL;
623
+
624
+
snprintf(path, sizeof(path), "/sys/dev/char/%d:%d/device", maj, min);
625
+
return strdup(path);
626
+
#else
627
+
return NULL;
628
+
#endif
527
629
}
528
630
529
631
/* The main() function for setting up and running the tests.
···
541
643
int display_devices = 0;/* By default not to display devices' info */
542
644
CU_pSuite pSuite = NULL;
543
645
CU_pTest pTest = NULL;
544
-
int test_device_index;
545
646
int display_list = 0;
546
647
int force_run = 0;
547
648
+38
-6
lib/libdrm/tests/amdgpu/amdgpu_test.h
+38
-6
lib/libdrm/tests/amdgpu/amdgpu_test.h
···
273
273
unsigned ip_type,
274
274
bool secure);
275
275
276
+
277
+
278
+
/**
279
+
* Initialize hotunplug test suite
280
+
*/
281
+
int suite_hotunplug_tests_init();
282
+
283
+
/**
284
+
* Deinitialize hotunplug test suite
285
+
*/
286
+
int suite_hotunplug_tests_clean();
287
+
288
+
/**
289
+
* Decide if the suite is enabled by default or not.
290
+
*/
291
+
CU_BOOL suite_hotunplug_tests_enable(void);
292
+
293
+
/**
294
+
* Tests in uvd enc test suite
295
+
*/
296
+
extern CU_TestInfo hotunplug_tests[];
297
+
298
+
276
299
/**
277
300
* Helper functions
278
301
*/
···
449
472
return r;
450
473
}
451
474
452
-
static inline bool asic_is_arcturus(uint32_t asic_id)
475
+
476
+
static inline bool asic_is_gfx_pipe_removed(uint32_t family_id, uint32_t chip_id, uint32_t chip_rev)
453
477
{
454
-
switch(asic_id) {
455
-
/* Arcturus asic DID */
456
-
case 0x738C:
457
-
case 0x7388:
458
-
case 0x738E:
478
+
479
+
if (family_id != AMDGPU_FAMILY_AI)
480
+
return false;
481
+
482
+
switch (chip_id - chip_rev) {
483
+
/* Arcturus */
484
+
case 0x32:
485
+
/* Aldebaran */
486
+
case 0x3c:
459
487
return true;
460
488
default:
461
489
return false;
···
470
498
struct amdgpu_cs_ib_info *ib_info,
471
499
struct amdgpu_cs_request *ibs_request,
472
500
bool secure);
501
+
502
+
void amdgpu_close_devices();
503
+
int amdgpu_open_device_on_test_index(int render_node);
504
+
char *amdgpu_get_device_from_fd(int fd);
473
505
474
506
#endif /* #ifdef _AMDGPU_TEST_H_ */
+31
-17
lib/libdrm/tests/amdgpu/basic_tests.c
+31
-17
lib/libdrm/tests/amdgpu/basic_tests.c
···
46
46
static uint32_t major_version;
47
47
static uint32_t minor_version;
48
48
static uint32_t family_id;
49
+
static uint32_t chip_id;
50
+
static uint32_t chip_rev;
49
51
50
52
static void amdgpu_query_info_test(void);
51
53
static void amdgpu_command_submission_gfx(void);
···
341
343
};
342
344
343
345
static const uint32_t bufferclear_cs_shader_gfx9[] = {
344
-
0xD1FD0000, 0x04010C08, 0x7E020204, 0x7E040205,
345
-
0x7E060206, 0x7E080207, 0xE01C2000, 0x80000100,
346
-
0xBF810000
346
+
0x260000ff, 0x000003ff, 0xd1fd0000, 0x04010c08,
347
+
0x7e020280, 0x7e040204, 0x7e060205, 0x7e080206,
348
+
0x7e0a0207, 0xe01c2000, 0x80000200, 0xbf8c0000,
349
+
0xbf810000
347
350
};
348
351
349
352
static const uint32_t bufferclear_cs_shader_registers_gfx9[][2] = {
···
357
360
static const uint32_t bufferclear_cs_shader_registers_num_gfx9 = 5;
358
361
359
362
static const uint32_t buffercopy_cs_shader_gfx9[] = {
360
-
0xD1FD0000, 0x04010C08, 0xE00C2000, 0x80000100,
361
-
0xBF8C0F70, 0xE01C2000, 0x80010100, 0xBF810000
363
+
0x260000ff, 0x000003ff, 0xd1fd0000, 0x04010c08,
364
+
0x7e020280, 0xe00c2000, 0x80000200, 0xbf8c0f70,
365
+
0xe01c2000, 0x80010200, 0xbf810000
362
366
};
363
367
364
368
static const uint32_t preamblecache_gfx9[] = {
···
617
621
618
622
CU_BOOL suite_basic_tests_enable(void)
619
623
{
620
-
uint32_t asic_id;
621
624
622
625
if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
623
626
&minor_version, &device_handle))
624
627
return CU_FALSE;
625
628
626
-
asic_id = device_handle->info.asic_id;
629
+
630
+
family_id = device_handle->info.family_id;
631
+
chip_id = device_handle->info.chip_external_rev;
632
+
chip_rev = device_handle->info.chip_rev;
627
633
628
634
if (amdgpu_device_deinitialize(device_handle))
629
635
return CU_FALSE;
630
636
631
-
/* disable gfx engine basic test cases for Arturus due to no CPG */
632
-
if (asic_is_arcturus(asic_id)) {
637
+
/* disable gfx engine basic test cases for some asics have no CPG */
638
+
if (asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) {
633
639
if (amdgpu_set_test_active("Basic Tests",
634
640
"Command submission Test (GFX)",
635
641
CU_FALSE))
···
1066
1072
amdgpu_bo_list_handle bo_list[2];
1067
1073
amdgpu_va_handle va_handle[2];
1068
1074
int r, i;
1075
+
struct amdgpu_gpu_info gpu_info = {0};
1076
+
unsigned gc_ip_type;
1077
+
1078
+
r = amdgpu_query_gpu_info(device_handle, &gpu_info);
1079
+
CU_ASSERT_EQUAL(r, 0);
1080
+
1081
+
gc_ip_type = (asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) ?
1082
+
AMDGPU_HW_IP_COMPUTE : AMDGPU_HW_IP_GFX;
1069
1083
1070
1084
if (family_id == AMDGPU_FAMILY_SI) {
1071
1085
sdma_nop = SDMA_PACKET_SI(SDMA_NOP_SI, 0, 0, 0, 0);
···
1108
1122
r = amdgpu_cs_signal_semaphore(context_handle[0], AMDGPU_HW_IP_DMA, 0, 0, sem);
1109
1123
CU_ASSERT_EQUAL(r, 0);
1110
1124
1111
-
r = amdgpu_cs_wait_semaphore(context_handle[0], AMDGPU_HW_IP_GFX, 0, 0, sem);
1125
+
r = amdgpu_cs_wait_semaphore(context_handle[0], gc_ip_type, 0, 0, sem);
1112
1126
CU_ASSERT_EQUAL(r, 0);
1113
1127
ptr = ib_result_cpu[1];
1114
1128
ptr[0] = gfx_nop;
1115
1129
ib_info[1].ib_mc_address = ib_result_mc_address[1];
1116
1130
ib_info[1].size = 1;
1117
1131
1118
-
ibs_request[1].ip_type = AMDGPU_HW_IP_GFX;
1132
+
ibs_request[1].ip_type = gc_ip_type;
1119
1133
ibs_request[1].number_of_ibs = 1;
1120
1134
ibs_request[1].ibs = &ib_info[1];
1121
1135
ibs_request[1].resources = bo_list[1];
···
1125
1139
CU_ASSERT_EQUAL(r, 0);
1126
1140
1127
1141
fence_status.context = context_handle[0];
1128
-
fence_status.ip_type = AMDGPU_HW_IP_GFX;
1142
+
fence_status.ip_type = gc_ip_type;
1129
1143
fence_status.ip_instance = 0;
1130
1144
fence_status.fence = ibs_request[1].seq_no;
1131
1145
r = amdgpu_cs_query_fence_status(&fence_status,
···
1139
1153
ib_info[0].ib_mc_address = ib_result_mc_address[0];
1140
1154
ib_info[0].size = 1;
1141
1155
1142
-
ibs_request[0].ip_type = AMDGPU_HW_IP_GFX;
1156
+
ibs_request[0].ip_type = gc_ip_type;
1143
1157
ibs_request[0].number_of_ibs = 1;
1144
1158
ibs_request[0].ibs = &ib_info[0];
1145
1159
ibs_request[0].resources = bo_list[0];
1146
1160
ibs_request[0].fence_info.handle = NULL;
1147
1161
r = amdgpu_cs_submit(context_handle[0], 0,&ibs_request[0], 1);
1148
1162
CU_ASSERT_EQUAL(r, 0);
1149
-
r = amdgpu_cs_signal_semaphore(context_handle[0], AMDGPU_HW_IP_GFX, 0, 0, sem);
1163
+
r = amdgpu_cs_signal_semaphore(context_handle[0], gc_ip_type, 0, 0, sem);
1150
1164
CU_ASSERT_EQUAL(r, 0);
1151
1165
1152
-
r = amdgpu_cs_wait_semaphore(context_handle[1], AMDGPU_HW_IP_GFX, 0, 0, sem);
1166
+
r = amdgpu_cs_wait_semaphore(context_handle[1], gc_ip_type, 0, 0, sem);
1153
1167
CU_ASSERT_EQUAL(r, 0);
1154
1168
ptr = ib_result_cpu[1];
1155
1169
ptr[0] = gfx_nop;
1156
1170
ib_info[1].ib_mc_address = ib_result_mc_address[1];
1157
1171
ib_info[1].size = 1;
1158
1172
1159
-
ibs_request[1].ip_type = AMDGPU_HW_IP_GFX;
1173
+
ibs_request[1].ip_type = gc_ip_type;
1160
1174
ibs_request[1].number_of_ibs = 1;
1161
1175
ibs_request[1].ibs = &ib_info[1];
1162
1176
ibs_request[1].resources = bo_list[1];
···
1166
1180
CU_ASSERT_EQUAL(r, 0);
1167
1181
1168
1182
fence_status.context = context_handle[1];
1169
-
fence_status.ip_type = AMDGPU_HW_IP_GFX;
1183
+
fence_status.ip_type = gc_ip_type;
1170
1184
fence_status.ip_instance = 0;
1171
1185
fence_status.fence = ibs_request[1].seq_no;
1172
1186
r = amdgpu_cs_query_fence_status(&fence_status,
+2
-2
lib/libdrm/tests/amdgpu/bo_tests.c
+2
-2
lib/libdrm/tests/amdgpu/bo_tests.c
···
168
168
struct amdgpu_bo_info info = {0};
169
169
int r;
170
170
171
-
meta.size_metadata = 1;
171
+
meta.size_metadata = 4;
172
172
meta.umd_metadata[0] = 0xdeadbeef;
173
173
174
174
r = amdgpu_bo_set_metadata(buffer_handle, &meta);
···
177
177
r = amdgpu_bo_query_info(buffer_handle, &info);
178
178
CU_ASSERT_EQUAL(r, 0);
179
179
180
-
CU_ASSERT_EQUAL(info.metadata.size_metadata, 1);
180
+
CU_ASSERT_EQUAL(info.metadata.size_metadata, 4);
181
181
CU_ASSERT_EQUAL(info.metadata.umd_metadata[0], 0xdeadbeef);
182
182
}
183
183
+3
-4
lib/libdrm/tests/amdgpu/cs_tests.c
+3
-4
lib/libdrm/tests/amdgpu/cs_tests.c
···
64
64
65
65
CU_BOOL suite_cs_tests_enable(void)
66
66
{
67
-
uint32_t asic_id;
68
-
69
67
if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
70
68
&minor_version, &device_handle))
71
69
return CU_FALSE;
72
70
73
71
family_id = device_handle->info.family_id;
74
-
asic_id = device_handle->info.asic_id;
72
+
chip_id = device_handle->info.chip_external_rev;
73
+
chip_rev = device_handle->info.chip_rev;
75
74
76
75
if (amdgpu_device_deinitialize(device_handle))
77
76
return CU_FALSE;
78
77
79
78
80
79
if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI ||
81
-
asic_is_arcturus(asic_id)) {
80
+
asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) {
82
81
printf("\n\nThe ASIC NOT support UVD, suite disabled\n");
83
82
return CU_FALSE;
84
83
}
+12
-6
lib/libdrm/tests/amdgpu/deadlock_tests.c
+12
-6
lib/libdrm/tests/amdgpu/deadlock_tests.c
···
106
106
static pthread_t stress_thread;
107
107
static uint32_t *ptr;
108
108
109
+
static uint32_t family_id;
110
+
static uint32_t chip_rev;
111
+
static uint32_t chip_id;
112
+
109
113
int use_uc_mtype = 0;
110
114
111
115
static void amdgpu_deadlock_helper(unsigned ip_type);
···
124
128
CU_BOOL suite_deadlock_tests_enable(void)
125
129
{
126
130
CU_BOOL enable = CU_TRUE;
127
-
uint32_t asic_id;
128
131
129
132
if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
130
133
&minor_version, &device_handle))
131
134
return CU_FALSE;
135
+
136
+
family_id = device_handle->info.family_id;
137
+
chip_id = device_handle->info.chip_external_rev;
138
+
chip_rev = device_handle->info.chip_rev;
132
139
133
140
/*
134
141
* Only enable for ASICs supporting GPU reset and for which it's enabled
135
142
* by default (currently GFX8/9 dGPUS)
136
143
*/
137
-
if (device_handle->info.family_id != AMDGPU_FAMILY_VI &&
138
-
device_handle->info.family_id != AMDGPU_FAMILY_AI &&
139
-
device_handle->info.family_id != AMDGPU_FAMILY_CI) {
144
+
if (family_id != AMDGPU_FAMILY_VI &&
145
+
family_id != AMDGPU_FAMILY_AI &&
146
+
family_id != AMDGPU_FAMILY_CI) {
140
147
printf("\n\nGPU reset is not enabled for the ASIC, deadlock suite disabled\n");
141
148
enable = CU_FALSE;
142
149
}
143
150
144
-
asic_id = device_handle->info.asic_id;
145
-
if (asic_is_arcturus(asic_id)) {
151
+
if (asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) {
146
152
if (amdgpu_set_test_active("Deadlock Tests",
147
153
"gfx ring block test (set amdgpu.lockup_timeout=50)",
148
154
CU_FALSE))
+445
lib/libdrm/tests/amdgpu/hotunplug_tests.c
+445
lib/libdrm/tests/amdgpu/hotunplug_tests.c
···
1
+
/*
2
+
* Copyright 2021 Advanced Micro Devices, Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*
22
+
*/
23
+
24
+
#include <stdlib.h>
25
+
#include <unistd.h>
26
+
#include <sys/types.h>
27
+
#include <sys/stat.h>
28
+
#include <fcntl.h>
29
+
#if HAVE_ALLOCA_H
30
+
# include <alloca.h>
31
+
#endif
32
+
33
+
#include "CUnit/Basic.h"
34
+
35
+
#include "amdgpu_test.h"
36
+
#include "amdgpu_drm.h"
37
+
#include "amdgpu_internal.h"
38
+
#include "xf86drm.h"
39
+
#include <pthread.h>
40
+
41
+
#define GFX_COMPUTE_NOP 0xffff1000
42
+
43
+
static amdgpu_device_handle device_handle;
44
+
static uint32_t major_version;
45
+
static uint32_t minor_version;
46
+
static char *sysfs_remove = NULL;
47
+
static bool do_cs;
48
+
49
+
CU_BOOL suite_hotunplug_tests_enable(void)
50
+
{
51
+
CU_BOOL enable = CU_TRUE;
52
+
drmDevicePtr device;
53
+
54
+
if (drmGetDevice2(drm_amdgpu[0], DRM_DEVICE_GET_PCI_REVISION, &device)) {
55
+
printf("\n\nGPU Failed to get DRM device PCI info!\n");
56
+
return CU_FALSE;
57
+
}
58
+
59
+
if (device->bustype != DRM_BUS_PCI) {
60
+
printf("\n\nGPU device is not on PCI bus!\n");
61
+
amdgpu_device_deinitialize(device_handle);
62
+
return CU_FALSE;
63
+
}
64
+
65
+
/* Disable until the hot-unplug support in kernel gets into drm-next */
66
+
if (major_version < 0xff)
67
+
enable = false;
68
+
69
+
if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
70
+
&minor_version, &device_handle))
71
+
return CU_FALSE;
72
+
73
+
/* TODO Once DRM version for unplug feature ready compare here agains it*/
74
+
75
+
if (amdgpu_device_deinitialize(device_handle))
76
+
return CU_FALSE;
77
+
78
+
return enable;
79
+
}
80
+
81
+
int suite_hotunplug_tests_init(void)
82
+
{
83
+
/* We need to open/close device at each test manually */
84
+
amdgpu_close_devices();
85
+
86
+
return CUE_SUCCESS;
87
+
}
88
+
89
+
int suite_hotunplug_tests_clean(void)
90
+
{
91
+
92
+
93
+
return CUE_SUCCESS;
94
+
}
95
+
96
+
static int amdgpu_hotunplug_trigger(const char *pathname)
97
+
{
98
+
int fd, len;
99
+
100
+
fd = open(pathname, O_WRONLY);
101
+
if (fd < 0)
102
+
return -errno;
103
+
104
+
len = write(fd, "1", 1);
105
+
close(fd);
106
+
107
+
return len;
108
+
}
109
+
110
+
static int amdgpu_hotunplug_setup_test()
111
+
{
112
+
int r;
113
+
char *tmp_str;
114
+
115
+
if (amdgpu_open_device_on_test_index(open_render_node) < 0) {
116
+
printf("\n\n Failed to reopen device file!\n");
117
+
return CUE_SINIT_FAILED;
118
+
119
+
120
+
121
+
}
122
+
123
+
r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
124
+
&minor_version, &device_handle);
125
+
126
+
if (r) {
127
+
if ((r == -EACCES) && (errno == EACCES))
128
+
printf("\n\nError:%s. "
129
+
"Hint:Try to run this test program as root.",
130
+
strerror(errno));
131
+
return CUE_SINIT_FAILED;
132
+
}
133
+
134
+
tmp_str = amdgpu_get_device_from_fd(drm_amdgpu[0]);
135
+
if (!tmp_str){
136
+
printf("\n\n Device path not found!\n");
137
+
return CUE_SINIT_FAILED;
138
+
}
139
+
140
+
sysfs_remove = realloc(tmp_str, strlen(tmp_str) * 2);
141
+
strcat(sysfs_remove, "/remove");
142
+
143
+
return 0;
144
+
}
145
+
146
+
static int amdgpu_hotunplug_teardown_test()
147
+
{
148
+
if (amdgpu_device_deinitialize(device_handle))
149
+
return CUE_SCLEAN_FAILED;
150
+
151
+
amdgpu_close_devices();
152
+
153
+
if (sysfs_remove)
154
+
free(sysfs_remove);
155
+
156
+
return 0;
157
+
}
158
+
159
+
static inline int amdgpu_hotunplug_remove()
160
+
{
161
+
return amdgpu_hotunplug_trigger(sysfs_remove);
162
+
}
163
+
164
+
static inline int amdgpu_hotunplug_rescan()
165
+
{
166
+
return amdgpu_hotunplug_trigger("/sys/bus/pci/rescan");
167
+
}
168
+
169
+
static int amdgpu_cs_sync(amdgpu_context_handle context,
170
+
unsigned int ip_type,
171
+
int ring,
172
+
unsigned int seqno)
173
+
{
174
+
struct amdgpu_cs_fence fence = {
175
+
.context = context,
176
+
.ip_type = ip_type,
177
+
.ring = ring,
178
+
.fence = seqno,
179
+
};
180
+
uint32_t expired;
181
+
182
+
return amdgpu_cs_query_fence_status(&fence,
183
+
AMDGPU_TIMEOUT_INFINITE,
184
+
0, &expired);
185
+
}
186
+
187
+
static void *amdgpu_nop_cs()
188
+
{
189
+
amdgpu_bo_handle ib_result_handle;
190
+
void *ib_result_cpu;
191
+
uint64_t ib_result_mc_address;
192
+
uint32_t *ptr;
193
+
int i, r;
194
+
amdgpu_bo_list_handle bo_list;
195
+
amdgpu_va_handle va_handle;
196
+
amdgpu_context_handle context;
197
+
struct amdgpu_cs_request ibs_request;
198
+
struct amdgpu_cs_ib_info ib_info;
199
+
200
+
r = amdgpu_cs_ctx_create(device_handle, &context);
201
+
CU_ASSERT_EQUAL(r, 0);
202
+
203
+
r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
204
+
AMDGPU_GEM_DOMAIN_GTT, 0,
205
+
&ib_result_handle, &ib_result_cpu,
206
+
&ib_result_mc_address, &va_handle);
207
+
CU_ASSERT_EQUAL(r, 0);
208
+
209
+
ptr = ib_result_cpu;
210
+
for (i = 0; i < 16; ++i)
211
+
ptr[i] = GFX_COMPUTE_NOP;
212
+
213
+
r = amdgpu_bo_list_create(device_handle, 1, &ib_result_handle, NULL, &bo_list);
214
+
CU_ASSERT_EQUAL(r, 0);
215
+
216
+
memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info));
217
+
ib_info.ib_mc_address = ib_result_mc_address;
218
+
ib_info.size = 16;
219
+
220
+
memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
221
+
ibs_request.ip_type = AMDGPU_HW_IP_GFX;
222
+
ibs_request.ring = 0;
223
+
ibs_request.number_of_ibs = 1;
224
+
ibs_request.ibs = &ib_info;
225
+
ibs_request.resources = bo_list;
226
+
227
+
while (do_cs)
228
+
amdgpu_cs_submit(context, 0, &ibs_request, 1);
229
+
230
+
amdgpu_cs_sync(context, AMDGPU_HW_IP_GFX, 0, ibs_request.seq_no);
231
+
amdgpu_bo_list_destroy(bo_list);
232
+
amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
233
+
ib_result_mc_address, 4096);
234
+
235
+
amdgpu_cs_ctx_free(context);
236
+
237
+
return (void *)0;
238
+
}
239
+
240
+
static pthread_t* amdgpu_create_cs_thread()
241
+
{
242
+
int r;
243
+
pthread_t *thread = malloc(sizeof(*thread));
244
+
if (!thread)
245
+
return NULL;
246
+
247
+
do_cs = true;
248
+
249
+
r = pthread_create(thread, NULL, amdgpu_nop_cs, NULL);
250
+
CU_ASSERT_EQUAL(r, 0);
251
+
252
+
/* Give thread enough time to start*/
253
+
usleep(100000);
254
+
return thread;
255
+
}
256
+
257
+
static void amdgpu_destroy_cs_thread(pthread_t *thread)
258
+
{
259
+
void *status;
260
+
261
+
do_cs = false;
262
+
263
+
pthread_join(*thread, &status);
264
+
CU_ASSERT_EQUAL(status, 0);
265
+
266
+
free(thread);
267
+
}
268
+
269
+
270
+
static void amdgpu_hotunplug_test(bool with_cs)
271
+
{
272
+
int r;
273
+
pthread_t *thread = NULL;
274
+
275
+
r = amdgpu_hotunplug_setup_test();
276
+
CU_ASSERT_EQUAL(r , 0);
277
+
278
+
if (with_cs) {
279
+
thread = amdgpu_create_cs_thread();
280
+
CU_ASSERT_NOT_EQUAL(thread, NULL);
281
+
}
282
+
283
+
r = amdgpu_hotunplug_remove();
284
+
CU_ASSERT_EQUAL(r > 0, 1);
285
+
286
+
if (with_cs)
287
+
amdgpu_destroy_cs_thread(thread);
288
+
289
+
r = amdgpu_hotunplug_teardown_test();
290
+
CU_ASSERT_EQUAL(r , 0);
291
+
292
+
r = amdgpu_hotunplug_rescan();
293
+
CU_ASSERT_EQUAL(r > 0, 1);
294
+
}
295
+
296
+
static void amdgpu_hotunplug_simple(void)
297
+
{
298
+
amdgpu_hotunplug_test(false);
299
+
}
300
+
301
+
static void amdgpu_hotunplug_with_cs(void)
302
+
{
303
+
amdgpu_hotunplug_test(true);
304
+
}
305
+
306
+
static void amdgpu_hotunplug_with_exported_bo(void)
307
+
{
308
+
int r;
309
+
uint32_t dma_buf_fd;
310
+
unsigned int *ptr;
311
+
amdgpu_bo_handle bo_handle;
312
+
313
+
struct amdgpu_bo_alloc_request request = {
314
+
.alloc_size = 4096,
315
+
.phys_alignment = 4096,
316
+
.preferred_heap = AMDGPU_GEM_DOMAIN_GTT,
317
+
.flags = 0,
318
+
};
319
+
320
+
r = amdgpu_hotunplug_setup_test();
321
+
CU_ASSERT_EQUAL(r , 0);
322
+
323
+
amdgpu_bo_alloc(device_handle, &request, &bo_handle);
324
+
CU_ASSERT_EQUAL(r, 0);
325
+
326
+
r = amdgpu_bo_export(bo_handle, amdgpu_bo_handle_type_dma_buf_fd, &dma_buf_fd);
327
+
CU_ASSERT_EQUAL(r, 0);
328
+
329
+
ptr = mmap(NULL, 4096, PROT_READ | PROT_WRITE, MAP_SHARED, dma_buf_fd, 0);
330
+
CU_ASSERT_NOT_EQUAL(ptr, MAP_FAILED);
331
+
332
+
r = amdgpu_hotunplug_remove();
333
+
CU_ASSERT_EQUAL(r > 0, 1);
334
+
335
+
amdgpu_bo_free(bo_handle);
336
+
337
+
r = amdgpu_hotunplug_teardown_test();
338
+
CU_ASSERT_EQUAL(r , 0);
339
+
340
+
*ptr = 0xdeafbeef;
341
+
342
+
munmap(ptr, 4096);
343
+
close (dma_buf_fd);
344
+
345
+
r = amdgpu_hotunplug_rescan();
346
+
CU_ASSERT_EQUAL(r > 0, 1);
347
+
}
348
+
349
+
static void amdgpu_hotunplug_with_exported_fence(void)
350
+
{
351
+
amdgpu_bo_handle ib_result_handle;
352
+
void *ib_result_cpu;
353
+
uint64_t ib_result_mc_address;
354
+
uint32_t *ptr, sync_obj_handle, sync_obj_handle2;
355
+
int i, r;
356
+
amdgpu_bo_list_handle bo_list;
357
+
amdgpu_va_handle va_handle;
358
+
uint32_t major2, minor2;
359
+
amdgpu_device_handle device2;
360
+
amdgpu_context_handle context;
361
+
struct amdgpu_cs_request ibs_request;
362
+
struct amdgpu_cs_ib_info ib_info;
363
+
struct amdgpu_cs_fence fence_status = {0};
364
+
int shared_fd;
365
+
366
+
r = amdgpu_hotunplug_setup_test();
367
+
CU_ASSERT_EQUAL(r , 0);
368
+
369
+
r = amdgpu_device_initialize(drm_amdgpu[1], &major2, &minor2, &device2);
370
+
CU_ASSERT_EQUAL(r, 0);
371
+
372
+
r = amdgpu_cs_ctx_create(device_handle, &context);
373
+
CU_ASSERT_EQUAL(r, 0);
374
+
375
+
r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
376
+
AMDGPU_GEM_DOMAIN_GTT, 0,
377
+
&ib_result_handle, &ib_result_cpu,
378
+
&ib_result_mc_address, &va_handle);
379
+
CU_ASSERT_EQUAL(r, 0);
380
+
381
+
ptr = ib_result_cpu;
382
+
for (i = 0; i < 16; ++i)
383
+
ptr[i] = GFX_COMPUTE_NOP;
384
+
385
+
r = amdgpu_bo_list_create(device_handle, 1, &ib_result_handle, NULL, &bo_list);
386
+
CU_ASSERT_EQUAL(r, 0);
387
+
388
+
memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info));
389
+
ib_info.ib_mc_address = ib_result_mc_address;
390
+
ib_info.size = 16;
391
+
392
+
memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
393
+
ibs_request.ip_type = AMDGPU_HW_IP_GFX;
394
+
ibs_request.ring = 0;
395
+
ibs_request.number_of_ibs = 1;
396
+
ibs_request.ibs = &ib_info;
397
+
ibs_request.resources = bo_list;
398
+
399
+
CU_ASSERT_EQUAL(amdgpu_cs_submit(context, 0, &ibs_request, 1), 0);
400
+
401
+
fence_status.context = context;
402
+
fence_status.ip_type = AMDGPU_HW_IP_GFX;
403
+
fence_status.ip_instance = 0;
404
+
fence_status.fence = ibs_request.seq_no;
405
+
406
+
CU_ASSERT_EQUAL(amdgpu_cs_fence_to_handle(device_handle, &fence_status,
407
+
AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ,
408
+
&sync_obj_handle),
409
+
0);
410
+
411
+
CU_ASSERT_EQUAL(amdgpu_cs_export_syncobj(device_handle, sync_obj_handle, &shared_fd), 0);
412
+
413
+
CU_ASSERT_EQUAL(amdgpu_cs_import_syncobj(device2, shared_fd, &sync_obj_handle2), 0);
414
+
415
+
CU_ASSERT_EQUAL(amdgpu_cs_destroy_syncobj(device_handle, sync_obj_handle), 0);
416
+
417
+
CU_ASSERT_EQUAL(amdgpu_bo_list_destroy(bo_list), 0);
418
+
CU_ASSERT_EQUAL(amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
419
+
ib_result_mc_address, 4096), 0);
420
+
CU_ASSERT_EQUAL(amdgpu_cs_ctx_free(context), 0);
421
+
422
+
r = amdgpu_hotunplug_remove();
423
+
CU_ASSERT_EQUAL(r > 0, 1);
424
+
425
+
CU_ASSERT_EQUAL(amdgpu_cs_syncobj_wait(device2, &sync_obj_handle2, 1, 100000000, 0, NULL), 0);
426
+
427
+
CU_ASSERT_EQUAL(amdgpu_cs_destroy_syncobj(device2, sync_obj_handle2), 0);
428
+
429
+
amdgpu_device_deinitialize(device2);
430
+
431
+
r = amdgpu_hotunplug_teardown_test();
432
+
CU_ASSERT_EQUAL(r , 0);
433
+
434
+
r = amdgpu_hotunplug_rescan();
435
+
CU_ASSERT_EQUAL(r > 0, 1);
436
+
}
437
+
438
+
439
+
CU_TestInfo hotunplug_tests[] = {
440
+
{ "Unplug card and rescan the bus to plug it back", amdgpu_hotunplug_simple },
441
+
{ "Same as first test but with command submission", amdgpu_hotunplug_with_cs },
442
+
{ "Unplug with exported bo", amdgpu_hotunplug_with_exported_bo },
443
+
{ "Unplug with exported fence", amdgpu_hotunplug_with_exported_fence },
444
+
CU_TEST_INFO_NULL,
445
+
};
+1
lib/libdrm/tests/amdgpu/meson.build
+1
lib/libdrm/tests/amdgpu/meson.build
···
25
25
'amdgpu_test.c', 'basic_tests.c', 'bo_tests.c', 'cs_tests.c',
26
26
'vce_tests.c', 'uvd_enc_tests.c', 'vcn_tests.c', 'deadlock_tests.c',
27
27
'vm_tests.c', 'ras_tests.c', 'syncobj_tests.c', 'security_tests.c',
28
+
'hotunplug_tests.c'
28
29
),
29
30
dependencies : [dep_cunit, dep_threads, dep_atomic_ops],
30
31
include_directories : [inc_root, inc_drm, include_directories('../../amdgpu')],
+2
-1
lib/libdrm/tests/amdgpu/security_tests.c
+2
-1
lib/libdrm/tests/amdgpu/security_tests.c
···
432
432
&minor_version, &device_handle))
433
433
return CU_FALSE;
434
434
435
-
if (device_handle->info.family_id != AMDGPU_FAMILY_RV) {
435
+
436
+
if (!(device_handle->dev_info.ids_flags & AMDGPU_IDS_FLAGS_TMZ)) {
436
437
printf("\n\nDon't support TMZ (trust memory zone), security suite disabled\n");
437
438
enable = CU_FALSE;
438
439
}
+19
-3
lib/libdrm/tests/amdgpu/syncobj_tests.c
+19
-3
lib/libdrm/tests/amdgpu/syncobj_tests.c
···
33
33
static uint32_t major_version;
34
34
static uint32_t minor_version;
35
35
36
+
static uint32_t family_id;
37
+
static uint32_t chip_id;
38
+
static uint32_t chip_rev;
39
+
36
40
static void amdgpu_syncobj_timeline_test(void);
37
41
38
42
CU_BOOL suite_syncobj_timeline_tests_enable(void)
···
100
104
int i, r;
101
105
uint64_t seq_no;
102
106
static uint32_t *ptr;
107
+
struct amdgpu_gpu_info gpu_info = {0};
108
+
unsigned gc_ip_type;
109
+
110
+
r = amdgpu_query_gpu_info(device_handle, &gpu_info);
111
+
CU_ASSERT_EQUAL(r, 0);
112
+
113
+
family_id = device_handle->info.family_id;
114
+
chip_id = device_handle->info.chip_external_rev;
115
+
chip_rev = device_handle->info.chip_rev;
116
+
117
+
gc_ip_type = (asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) ?
118
+
AMDGPU_HW_IP_COMPUTE : AMDGPU_HW_IP_GFX;
103
119
104
120
r = amdgpu_cs_ctx_create(device_handle, &context_handle);
105
121
CU_ASSERT_EQUAL(r, 0);
···
125
141
chunk_data.ib_data._pad = 0;
126
142
chunk_data.ib_data.va_start = ib_result_mc_address;
127
143
chunk_data.ib_data.ib_bytes = 16 * 4;
128
-
chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX :
144
+
chunk_data.ib_data.ip_type = wait_or_signal ? gc_ip_type :
129
145
AMDGPU_HW_IP_DMA;
130
146
chunk_data.ib_data.ip_instance = 0;
131
147
chunk_data.ib_data.ring = 0;
132
-
chunk_data.ib_data.flags = 0;
148
+
chunk_data.ib_data.flags = AMDGPU_IB_FLAG_EMIT_MEM_SYNC;
133
149
134
150
chunks[1].chunk_id = wait_or_signal ?
135
151
AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
···
151
167
152
168
memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
153
169
fence_status.context = context_handle;
154
-
fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX:
170
+
fence_status.ip_type = wait_or_signal ? gc_ip_type :
155
171
AMDGPU_HW_IP_DMA;
156
172
fence_status.ip_instance = 0;
157
173
fence_status.ring = 0;
+1
-1
lib/libdrm/tests/amdgpu/vce_tests.c
+1
-1
lib/libdrm/tests/amdgpu/vce_tests.c
···
116
116
return CU_FALSE;
117
117
118
118
if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI ||
119
-
asic_is_arcturus(asic_id)) {
119
+
asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) {
120
120
printf("\n\nThe ASIC NOT support VCE, suite disabled\n");
121
121
return CU_FALSE;
122
122
}
+4
-4
lib/libdrm/tests/amdgpu/vcn_tests.c
+4
-4
lib/libdrm/tests/amdgpu/vcn_tests.c
···
102
102
return CU_FALSE;
103
103
104
104
family_id = device_handle->info.family_id;
105
-
chip_rev = device_handle->info.chip_rev;
106
-
chip_id = device_handle->info.chip_external_rev;
107
105
asic_id = device_handle->info.asic_id;
108
106
chip_rev = device_handle->info.chip_rev;
109
107
chip_id = device_handle->info.chip_external_rev;
···
116
114
if (r != 0 || !info.available_rings ||
117
115
(family_id < AMDGPU_FAMILY_RV &&
118
116
(family_id == AMDGPU_FAMILY_AI &&
119
-
chip_id != (chip_rev + 0x32)))) { /* Arcturus */
117
+
(chip_id - chip_rev) < 0x32))) { /* Arcturus */
120
118
printf("\n\nThe ASIC NOT support VCN, suite disabled\n");
121
119
return CU_FALSE;
122
120
}
···
142
140
reg.cntl = 0x81c6;
143
141
}
144
142
} else if (family_id == AMDGPU_FAMILY_NV) {
145
-
if (chip_id == (chip_rev + 0x28)) {
143
+
if (chip_id == (chip_rev + 0x28) ||
144
+
chip_id == (chip_rev + 0x32) ||
145
+
chip_id == (chip_rev + 0x3c)) {
146
146
reg.data0 = 0x10;
147
147
reg.data1 = 0x11;
148
148
reg.cmd = 0xf;
+8
-1
lib/libdrm/tests/amdgpu/vm_tests.c
+8
-1
lib/libdrm/tests/amdgpu/vm_tests.c
···
30
30
static amdgpu_device_handle device_handle;
31
31
static uint32_t major_version;
32
32
static uint32_t minor_version;
33
+
static uint32_t family_id;
34
+
static uint32_t chip_id;
35
+
static uint32_t chip_rev;
33
36
34
37
static void amdgpu_vmid_reserve_test(void);
35
38
static void amdgpu_vm_unaligned_map(void);
···
110
113
r = amdgpu_query_gpu_info(device_handle, &gpu_info);
111
114
CU_ASSERT_EQUAL(r, 0);
112
115
113
-
gc_ip_type = (asic_is_arcturus(gpu_info.asic_id)) ?
116
+
family_id = device_handle->info.family_id;
117
+
chip_id = device_handle->info.chip_external_rev;
118
+
chip_rev = device_handle->info.chip_rev;
119
+
120
+
gc_ip_type = (asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) ?
114
121
AMDGPU_HW_IP_COMPUTE : AMDGPU_HW_IP_GFX;
115
122
116
123
r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+30
-45
lib/libdrm/tests/modetest/modetest.c
+30
-45
lib/libdrm/tests/modetest/modetest.c
···
265
265
266
266
static const char *modifier_to_string(uint64_t modifier)
267
267
{
268
-
switch (modifier) {
269
-
case DRM_FORMAT_MOD_INVALID:
270
-
return "INVALID";
271
-
case DRM_FORMAT_MOD_LINEAR:
272
-
return "LINEAR";
273
-
case I915_FORMAT_MOD_X_TILED:
274
-
return "X_TILED";
275
-
case I915_FORMAT_MOD_Y_TILED:
276
-
return "Y_TILED";
277
-
case I915_FORMAT_MOD_Yf_TILED:
278
-
return "Yf_TILED";
279
-
case I915_FORMAT_MOD_Y_TILED_CCS:
280
-
return "Y_TILED_CCS";
281
-
case I915_FORMAT_MOD_Yf_TILED_CCS:
282
-
return "Yf_TILED_CCS";
283
-
case DRM_FORMAT_MOD_SAMSUNG_64_32_TILE:
284
-
return "SAMSUNG_64_32_TILE";
285
-
case DRM_FORMAT_MOD_VIVANTE_TILED:
286
-
return "VIVANTE_TILED";
287
-
case DRM_FORMAT_MOD_VIVANTE_SUPER_TILED:
288
-
return "VIVANTE_SUPER_TILED";
289
-
case DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED:
290
-
return "VIVANTE_SPLIT_TILED";
291
-
case DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED:
292
-
return "VIVANTE_SPLIT_SUPER_TILED";
293
-
case DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED:
294
-
return "NVIDIA_TEGRA_TILED";
295
-
case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0):
296
-
return "NVIDIA_16BX2_BLOCK(0)";
297
-
case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1):
298
-
return "NVIDIA_16BX2_BLOCK(1)";
299
-
case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2):
300
-
return "NVIDIA_16BX2_BLOCK(2)";
301
-
case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3):
302
-
return "NVIDIA_16BX2_BLOCK(3)";
303
-
case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4):
304
-
return "NVIDIA_16BX2_BLOCK(4)";
305
-
case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5):
306
-
return "NVIDIA_16BX2_BLOCK(5)";
307
-
case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED:
308
-
return "MOD_BROADCOM_VC4_T_TILED";
309
-
case DRM_FORMAT_MOD_QCOM_COMPRESSED:
310
-
return "QCOM_COMPRESSED";
311
-
default:
312
-
return "(UNKNOWN MODIFIER)";
268
+
static char mod_string[4096];
269
+
270
+
char *modifier_name = drmGetFormatModifierName(modifier);
271
+
char *vendor_name = drmGetFormatModifierVendor(modifier);
272
+
memset(mod_string, 0x00, sizeof(mod_string));
273
+
274
+
if (!modifier_name) {
275
+
if (vendor_name)
276
+
snprintf(mod_string, sizeof(mod_string), "%s_%s",
277
+
vendor_name, "UNKNOWN_MODIFIER");
278
+
else
279
+
snprintf(mod_string, sizeof(mod_string), "%s_%s",
280
+
"UNKNOWN_VENDOR", "UNKNOWN_MODIFIER");
281
+
/* safe, as free is no-op for NULL */
282
+
free(vendor_name);
283
+
return mod_string;
284
+
}
285
+
286
+
if (modifier == DRM_FORMAT_MOD_LINEAR) {
287
+
snprintf(mod_string, sizeof(mod_string), "%s", modifier_name);
288
+
free(modifier_name);
289
+
free(vendor_name);
290
+
return mod_string;
313
291
}
292
+
293
+
snprintf(mod_string, sizeof(mod_string), "%s_%s",
294
+
vendor_name, modifier_name);
295
+
296
+
free(modifier_name);
297
+
free(vendor_name);
298
+
return mod_string;
314
299
}
315
300
316
301
static void dump_in_formats(struct device *dev, uint32_t blob_id)
+1
lib/libdrm/tests/util/kms.c
+1
lib/libdrm/tests/util/kms.c
+2
-3
lib/libdrm/tests/util/pattern.c
+2
-3
lib/libdrm/tests/util/pattern.c
···
985
985
unsigned int stride)
986
986
{
987
987
const struct util_rgb_info *rgb = &info->rgb;
988
-
void *mem_base = mem;
989
988
unsigned int x, y;
990
989
991
990
/* TODO: Give this actual fp16 precision */
···
1113
1112
unsigned int width, unsigned int height,
1114
1113
unsigned int stride)
1115
1114
{
1116
-
int i, j;
1115
+
unsigned int i, j;
1117
1116
1118
1117
for (i = 0; i < height / 2; i++) {
1119
1118
uint32_t *row = mem;
···
1141
1140
unsigned int width, unsigned int height,
1142
1141
unsigned int stride)
1143
1142
{
1144
-
int i, j;
1143
+
unsigned int i, j;
1145
1144
1146
1145
for (i = 0; i < height / 2; i++) {
1147
1146
uint64_t *row = mem;