mirror of OpenBSD xenocara tree
github.com/openbsd/xenocara
openbsd
Import libdrm 2.4.123
+855
-153
+8
-9
lib/libdrm/.gitlab-ci.yml
+8
-9
lib/libdrm/.gitlab-ci.yml
···
12
12
# main repository, it's recommended to remove the image from the source
13
13
# repository's container registry, so that the image from the main
14
14
# repository's registry will be used there as well.
15
-
.templates_sha: &template_sha 567700e483aabed992d0a4fea84994a0472deff6 # see https://docs.gitlab.com/ee/ci/yaml/#includefile
15
+
.templates_sha: &template_sha b61a03cabbf308e81289f7aaaf0b5a80a34ffb99 # see https://docs.gitlab.com/ee/ci/yaml/#includefile
16
16
17
17
include:
18
18
- project: 'freedesktop/ci-templates'
···
39
39
.os-debian:
40
40
variables:
41
41
BUILD_OS: debian
42
-
FDO_DISTRIBUTION_VERSION: buster
42
+
FDO_DISTRIBUTION_VERSION: bookworm
43
43
FDO_DISTRIBUTION_PACKAGES: 'build-essential docbook-xsl libatomic-ops-dev libcairo2-dev libcunit1-dev libpciaccess-dev meson ninja-build pkg-config python3 python3-pip python3-wheel python3-setuptools python3-docutils valgrind'
44
-
FDO_DISTRIBUTION_EXEC: 'pip3 install meson==0.59.0'
45
44
# bump this tag every time you change something which requires rebuilding the
46
45
# base image
47
-
FDO_DISTRIBUTION_TAG: "2023-09-01.0"
46
+
FDO_DISTRIBUTION_TAG: "2024-06-25.0"
48
47
49
48
.debian-x86_64:
50
49
extends:
···
67
66
.os-freebsd:
68
67
variables:
69
68
BUILD_OS: freebsd
70
-
FDO_DISTRIBUTION_VERSION: "13.2"
69
+
FDO_DISTRIBUTION_VERSION: "14.1"
71
70
FDO_DISTRIBUTION_PACKAGES: 'meson ninja pkgconf libpciaccess py39-docutils cairo'
72
71
# bump this tag every time you change something which requires rebuilding the
73
72
# base image
74
-
FDO_DISTRIBUTION_TAG: "2023-07-20.0"
73
+
FDO_DISTRIBUTION_TAG: "2026-26-25.0"
75
74
76
75
.freebsd-x86_64:
77
76
extends:
···
190
189
variables:
191
190
GIT_DEPTH: 10
192
191
script:
193
-
- meson build
194
-
--auto-features=enabled
192
+
- meson setup build
193
+
--fatal-meson-warnings --auto-features=enabled
195
194
-D udev=true
196
195
- ninja -C build
197
196
- ninja -C build test
···
213
212
# the workspace to see details about the failed tests.
214
213
- |
215
214
set +e
216
-
/app/vmctl exec "pkg info; cd $CI_PROJECT_NAME ; meson build --auto-features=enabled -D etnaviv=disabled -D nouveau=disabled -D valgrind=disabled && ninja -C build"
215
+
/app/vmctl exec "pkg info; cd $CI_PROJECT_NAME ; meson setup build --fatal-meson-warnings --auto-features=enabled -D etnaviv=disabled -D nouveau=disabled -D valgrind=disabled && ninja -C build"
217
216
set -ex
218
217
scp -r vm:$CI_PROJECT_NAME/build/meson-logs .
219
218
/app/vmctl exec "ninja -C $CI_PROJECT_NAME/build install"
+85
lib/libdrm/Android.bp
+85
lib/libdrm/Android.bp
···
1
+
//
2
+
// Copyright © 2011-2012 Intel Corporation
3
+
//
4
+
// Permission is hereby granted, free of charge, to any person obtaining a
5
+
// copy of this software and associated documentation files (the "Software"),
6
+
// to deal in the Software without restriction, including without limitation
7
+
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
// and/or sell copies of the Software, and to permit persons to whom the
9
+
// Software is furnished to do so, subject to the following conditions:
10
+
//
11
+
// The above copyright notice and this permission notice (including the next
12
+
// paragraph) shall be included in all copies or substantial portions of the
13
+
// Software.
14
+
//
15
+
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16
+
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17
+
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18
+
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19
+
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20
+
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21
+
// IN THE SOFTWARE.
22
+
//
23
+
24
+
subdirs = ["*"]
25
+
build = ["Android.sources.bp"]
26
+
27
+
cc_defaults {
28
+
name: "libdrm_defaults",
29
+
cflags: [
30
+
// XXX: Consider moving these to config.h analogous to autoconf.
31
+
"-DMAJOR_IN_SYSMACROS=1",
32
+
"-DHAVE_VISIBILITY=1",
33
+
"-DHAVE_LIBDRM_ATOMIC_PRIMITIVES=1",
34
+
35
+
"-Wall",
36
+
"-Werror",
37
+
"-Wno-deprecated-declarations",
38
+
"-Wno-format",
39
+
"-Wno-gnu-variable-sized-type-not-at-end",
40
+
"-Wno-implicit-function-declaration",
41
+
"-Wno-int-conversion",
42
+
"-Wno-missing-field-initializers",
43
+
"-Wno-pointer-arith",
44
+
"-Wno-unused-parameter",
45
+
"-Wno-unused-variable",
46
+
],
47
+
export_system_include_dirs: ["."],
48
+
}
49
+
50
+
cc_library_headers {
51
+
name: "libdrm_headers",
52
+
vendor_available: true,
53
+
host_supported: true,
54
+
defaults: ["libdrm_defaults"],
55
+
export_include_dirs: ["include/drm", "android"],
56
+
apex_available: [
57
+
"//apex_available:platform",
58
+
"com.android.virt",
59
+
],
60
+
}
61
+
62
+
// Library for the device
63
+
cc_library {
64
+
name: "libdrm",
65
+
recovery_available: true,
66
+
vendor_available: true,
67
+
host_supported: true,
68
+
defaults: [
69
+
"libdrm_defaults",
70
+
"libdrm_sources",
71
+
],
72
+
73
+
export_include_dirs: ["include/drm", "android"],
74
+
75
+
cflags: [
76
+
"-Wno-enum-conversion",
77
+
"-Wno-pointer-arith",
78
+
"-Wno-sign-compare",
79
+
"-Wno-tautological-compare",
80
+
],
81
+
apex_available: [
82
+
"//apex_available:platform",
83
+
"com.android.virt",
84
+
],
85
+
}
+12
lib/libdrm/Android.sources.bp
+12
lib/libdrm/Android.sources.bp
+25
lib/libdrm/Android.sources.bp.mk
+25
lib/libdrm/Android.sources.bp.mk
···
1
+
# Usage: make -f path/to/Android.sources.bp.mk NAMES=<> >Android.sources.bp
2
+
#
3
+
# It will read the Makefile.sources in the current directory, and
4
+
# write <NAME>_FILES to stdout as an Android.bp cc_defaults module.
5
+
6
+
.PHONY: all
7
+
all:
8
+
@# Do nothing
9
+
10
+
include Makefile.sources
11
+
12
+
empty :=
13
+
indent := $(empty) $(empty)
14
+
15
+
$(info // Autogenerated with Android.sources.bp.mk)
16
+
$(foreach NAME,$(NAMES), \
17
+
$(eval lower_name := $(shell echo $(PREFIX)$(NAME) | tr 'A-Z' 'a-z')) \
18
+
$(info ) \
19
+
$(info cc_defaults {) \
20
+
$(info $(indent)name: "$(lower_name)_sources",) \
21
+
$(info $(indent)srcs: [) \
22
+
$(foreach f,$(filter %.c,$($(NAME)_FILES)), \
23
+
$(info $(indent)$(indent)"$(f)",)) \
24
+
$(info $(indent)],) \
25
+
$(info }))
+16
lib/libdrm/amdgpu/Android.bp
+16
lib/libdrm/amdgpu/Android.bp
···
1
+
build = ["Android.sources.bp"]
2
+
3
+
cc_library_shared {
4
+
name: "libdrm_amdgpu",
5
+
6
+
cflags: [
7
+
"-DAMDGPU_ASIC_ID_TABLE=\"/vendor/etc/hwdata/amdgpu.ids\""
8
+
],
9
+
10
+
defaults: [
11
+
"libdrm_defaults",
12
+
"libdrm_amdgpu_sources",
13
+
],
14
+
vendor: true,
15
+
shared_libs: ["libdrm"],
16
+
}
+15
lib/libdrm/amdgpu/Android.sources.bp
+15
lib/libdrm/amdgpu/Android.sources.bp
···
1
+
// Autogenerated with Android.sources.bp.mk
2
+
3
+
cc_defaults {
4
+
name: "libdrm_amdgpu_sources",
5
+
srcs: [
6
+
"amdgpu_asic_id.c",
7
+
"amdgpu_bo.c",
8
+
"amdgpu_cs.c",
9
+
"amdgpu_device.c",
10
+
"amdgpu_gpu_info.c",
11
+
"amdgpu_vamgr.c",
12
+
"amdgpu_vm.c",
13
+
"handle_table.c",
14
+
],
15
+
}
+5
lib/libdrm/amdgpu/amdgpu-symbols.txt
+5
lib/libdrm/amdgpu/amdgpu-symbols.txt
···
56
56
amdgpu_device_deinitialize
57
57
amdgpu_device_get_fd
58
58
amdgpu_device_initialize
59
+
amdgpu_device_initialize2
59
60
amdgpu_find_bo_by_cpu_mapping
60
61
amdgpu_get_marketing_name
61
62
amdgpu_query_buffer_size_alignment
···
71
72
amdgpu_query_sensor_info
72
73
amdgpu_query_video_caps_info
73
74
amdgpu_read_mm_registers
75
+
amdgpu_va_manager_alloc
76
+
amdgpu_va_manager_init
77
+
amdgpu_va_manager_deinit
74
78
amdgpu_va_range_alloc
79
+
amdgpu_va_range_alloc2
75
80
amdgpu_va_range_free
76
81
amdgpu_va_get_start_addr
77
82
amdgpu_va_range_query
+51
lib/libdrm/amdgpu/amdgpu.h
+51
lib/libdrm/amdgpu/amdgpu.h
···
139
139
typedef struct amdgpu_va *amdgpu_va_handle;
140
140
141
141
/**
142
+
* Define handle dealing with VA allocation. An amdgpu_device
143
+
* owns one of these, but they can also be used without a device.
144
+
*/
145
+
typedef struct amdgpu_va_manager *amdgpu_va_manager_handle;
146
+
147
+
/**
142
148
* Define handle for semaphore
143
149
*/
144
150
typedef struct amdgpu_semaphore *amdgpu_semaphore_handle;
···
527
533
uint32_t *minor_version,
528
534
amdgpu_device_handle *device_handle);
529
535
536
+
/**
537
+
* Same as amdgpu_device_initialize() except when deduplicate_device
538
+
* is false *and* fd points to a device that was already initialized.
539
+
* In this case, amdgpu_device_initialize would return the same
540
+
* amdgpu_device_handle while here amdgpu_device_initialize2 would
541
+
* return a new handle.
542
+
* amdgpu_device_initialize() should be preferred in most situations;
543
+
* the only use-case where not-deduplicating devices make sense is
544
+
* when one wants to have isolated device handles in the same process.
545
+
*/
546
+
int amdgpu_device_initialize2(int fd, bool deduplicate_device,
547
+
uint32_t *major_version,
548
+
uint32_t *minor_version,
549
+
amdgpu_device_handle *device_handle);
530
550
/**
531
551
*
532
552
* When access to such library does not needed any more the special
···
1409
1429
enum amdgpu_gpu_va_range type,
1410
1430
uint64_t *start,
1411
1431
uint64_t *end);
1432
+
1433
+
/**
1434
+
* Allocate a amdgpu_va_manager object.
1435
+
* The returned object has be initialized with the amdgpu_va_manager_init
1436
+
* before use.
1437
+
* On release, amdgpu_va_manager_deinit needs to be called, then the memory
1438
+
* can be released using free().
1439
+
*/
1440
+
amdgpu_va_manager_handle amdgpu_va_manager_alloc(void);
1441
+
1442
+
void amdgpu_va_manager_init(amdgpu_va_manager_handle va_mgr,
1443
+
uint64_t low_va_offset, uint64_t low_va_max,
1444
+
uint64_t high_va_offset, uint64_t high_va_max,
1445
+
uint32_t virtual_address_alignment);
1446
+
1447
+
void amdgpu_va_manager_deinit(amdgpu_va_manager_handle va_mgr);
1448
+
1449
+
/**
1450
+
* Similar to #amdgpu_va_range_alloc() but allocates VA
1451
+
* directly from an amdgpu_va_manager_handle instead of using
1452
+
* the manager from an amdgpu_device.
1453
+
*/
1454
+
1455
+
int amdgpu_va_range_alloc2(amdgpu_va_manager_handle va_mgr,
1456
+
enum amdgpu_gpu_va_range va_range_type,
1457
+
uint64_t size,
1458
+
uint64_t va_base_alignment,
1459
+
uint64_t va_base_required,
1460
+
uint64_t *va_base_allocated,
1461
+
amdgpu_va_handle *va_range_handle,
1462
+
uint64_t flags);
1412
1463
1413
1464
/**
1414
1465
* VA mapping/unmapping for the buffer object
+11
-4
lib/libdrm/amdgpu/amdgpu_cs.c
+11
-4
lib/libdrm/amdgpu/amdgpu_cs.c
···
598
598
uint32_t ring,
599
599
amdgpu_semaphore_handle sem)
600
600
{
601
+
int ret;
602
+
601
603
if (!ctx || !sem)
602
604
return -EINVAL;
603
605
if (ip_type >= AMDGPU_HW_IP_NUM)
604
606
return -EINVAL;
605
607
if (ring >= AMDGPU_CS_MAX_RINGS)
606
608
return -EINVAL;
609
+
610
+
pthread_mutex_lock(&ctx->sequence_mutex);
607
611
/* sem has been signaled */
608
-
if (sem->signal_fence.context)
609
-
return -EINVAL;
610
-
pthread_mutex_lock(&ctx->sequence_mutex);
612
+
if (sem->signal_fence.context) {
613
+
ret = -EINVAL;
614
+
goto unlock;
615
+
}
611
616
sem->signal_fence.context = ctx;
612
617
sem->signal_fence.ip_type = ip_type;
613
618
sem->signal_fence.ip_instance = ip_instance;
614
619
sem->signal_fence.ring = ring;
615
620
sem->signal_fence.fence = ctx->last_seq[ip_type][ip_instance][ring];
616
621
update_references(NULL, &sem->refcount);
622
+
ret = 0;
623
+
unlock:
617
624
pthread_mutex_unlock(&ctx->sequence_mutex);
618
-
return 0;
625
+
return ret;
619
626
}
620
627
621
628
drm_public int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx,
+57
-46
lib/libdrm/amdgpu/amdgpu_device.c
+57
-46
lib/libdrm/amdgpu/amdgpu_device.c
···
95
95
96
96
static void amdgpu_device_free_internal(amdgpu_device_handle dev)
97
97
{
98
-
amdgpu_device_handle *node = &dev_list;
99
-
100
-
pthread_mutex_lock(&dev_mutex);
101
-
while (*node != dev && (*node)->next)
102
-
node = &(*node)->next;
103
-
*node = (*node)->next;
104
-
pthread_mutex_unlock(&dev_mutex);
98
+
/* Remove dev from dev_list, if it was added there. */
99
+
if (dev == dev_list) {
100
+
dev_list = dev->next;
101
+
} else {
102
+
for (amdgpu_device_handle node = dev_list; node; node = node->next) {
103
+
if (node->next == dev) {
104
+
node->next = dev->next;
105
+
break;
106
+
}
107
+
}
108
+
}
105
109
106
110
close(dev->fd);
107
111
if ((dev->flink_fd >= 0) && (dev->fd != dev->flink_fd))
108
112
close(dev->flink_fd);
109
113
110
-
amdgpu_vamgr_deinit(&dev->vamgr_32);
111
-
amdgpu_vamgr_deinit(&dev->vamgr);
112
-
amdgpu_vamgr_deinit(&dev->vamgr_high_32);
113
-
amdgpu_vamgr_deinit(&dev->vamgr_high);
114
+
amdgpu_vamgr_deinit(&dev->va_mgr.vamgr_32);
115
+
amdgpu_vamgr_deinit(&dev->va_mgr.vamgr_low);
116
+
amdgpu_vamgr_deinit(&dev->va_mgr.vamgr_high_32);
117
+
amdgpu_vamgr_deinit(&dev->va_mgr.vamgr_high);
114
118
handle_table_fini(&dev->bo_handles);
115
119
handle_table_fini(&dev->bo_flink_names);
116
120
pthread_mutex_destroy(&dev->bo_table_mutex);
···
140
144
*dst = src;
141
145
}
142
146
143
-
drm_public int amdgpu_device_initialize(int fd,
144
-
uint32_t *major_version,
145
-
uint32_t *minor_version,
146
-
amdgpu_device_handle *device_handle)
147
+
static int _amdgpu_device_initialize(int fd,
148
+
uint32_t *major_version,
149
+
uint32_t *minor_version,
150
+
amdgpu_device_handle *device_handle,
151
+
bool deduplicate_device)
147
152
{
148
-
struct amdgpu_device *dev;
153
+
struct amdgpu_device *dev = NULL;
149
154
drmVersionPtr version;
150
155
int r;
151
156
int flag_auth = 0;
152
157
int flag_authexist=0;
153
158
uint32_t accel_working = 0;
154
-
uint64_t start, max;
155
159
156
160
*device_handle = NULL;
157
161
158
162
pthread_mutex_lock(&dev_mutex);
163
+
159
164
r = amdgpu_get_auth(fd, &flag_auth);
160
165
if (r) {
161
166
fprintf(stderr, "%s: amdgpu_get_auth (1) failed (%i)\n",
···
164
169
return r;
165
170
}
166
171
167
-
for (dev = dev_list; dev; dev = dev->next)
168
-
if (fd_compare(dev->fd, fd) == 0)
169
-
break;
172
+
if (deduplicate_device)
173
+
for (dev = dev_list; dev; dev = dev->next)
174
+
if (fd_compare(dev->fd, fd) == 0)
175
+
break;
170
176
171
177
if (dev) {
172
178
r = amdgpu_get_auth(dev->fd, &flag_authexist);
···
238
244
goto cleanup;
239
245
}
240
246
241
-
start = dev->dev_info.virtual_address_offset;
242
-
max = MIN2(dev->dev_info.virtual_address_max, 0x100000000ULL);
243
-
amdgpu_vamgr_init(&dev->vamgr_32, start, max,
244
-
dev->dev_info.virtual_address_alignment);
245
-
246
-
start = max;
247
-
max = MAX2(dev->dev_info.virtual_address_max, 0x100000000ULL);
248
-
amdgpu_vamgr_init(&dev->vamgr, start, max,
249
-
dev->dev_info.virtual_address_alignment);
250
-
251
-
start = dev->dev_info.high_va_offset;
252
-
max = MIN2(dev->dev_info.high_va_max, (start & ~0xffffffffULL) +
253
-
0x100000000ULL);
254
-
amdgpu_vamgr_init(&dev->vamgr_high_32, start, max,
255
-
dev->dev_info.virtual_address_alignment);
256
-
257
-
start = max;
258
-
max = MAX2(dev->dev_info.high_va_max, (start & ~0xffffffffULL) +
259
-
0x100000000ULL);
260
-
amdgpu_vamgr_init(&dev->vamgr_high, start, max,
261
-
dev->dev_info.virtual_address_alignment);
247
+
amdgpu_va_manager_init(&dev->va_mgr,
248
+
dev->dev_info.virtual_address_offset,
249
+
dev->dev_info.virtual_address_max,
250
+
dev->dev_info.high_va_offset,
251
+
dev->dev_info.high_va_max,
252
+
dev->dev_info.virtual_address_alignment);
262
253
263
254
amdgpu_parse_asic_ids(dev);
264
255
265
256
*major_version = dev->major_version;
266
257
*minor_version = dev->minor_version;
267
258
*device_handle = dev;
268
-
dev->next = dev_list;
269
-
dev_list = dev;
259
+
if (deduplicate_device) {
260
+
dev->next = dev_list;
261
+
dev_list = dev;
262
+
}
270
263
pthread_mutex_unlock(&dev_mutex);
271
264
272
265
return 0;
···
279
272
return r;
280
273
}
281
274
275
+
drm_public int amdgpu_device_initialize(int fd,
276
+
uint32_t *major_version,
277
+
uint32_t *minor_version,
278
+
amdgpu_device_handle *device_handle)
279
+
{
280
+
return _amdgpu_device_initialize(fd, major_version, minor_version, device_handle, true);
281
+
}
282
+
283
+
drm_public int amdgpu_device_initialize2(int fd, bool deduplicate_device,
284
+
uint32_t *major_version,
285
+
uint32_t *minor_version,
286
+
amdgpu_device_handle *device_handle)
287
+
{
288
+
return _amdgpu_device_initialize(fd, major_version, minor_version, device_handle, deduplicate_device);
289
+
}
290
+
282
291
drm_public int amdgpu_device_deinitialize(amdgpu_device_handle dev)
283
292
{
293
+
pthread_mutex_lock(&dev_mutex);
284
294
amdgpu_device_reference(&dev, NULL);
295
+
pthread_mutex_unlock(&dev_mutex);
285
296
return 0;
286
297
}
287
298
···
306
317
307
318
switch (info) {
308
319
case amdgpu_sw_info_address32_hi:
309
-
if (dev->vamgr_high_32.va_max)
310
-
*val32 = (dev->vamgr_high_32.va_max - 1) >> 32;
320
+
if (dev->va_mgr.vamgr_high_32.va_max)
321
+
*val32 = (dev->va_mgr.vamgr_high_32.va_max - 1) >> 32;
311
322
else
312
-
*val32 = (dev->vamgr_32.va_max - 1) >> 32;
323
+
*val32 = (dev->va_mgr.vamgr_32.va_max - 1) >> 32;
313
324
return 0;
314
325
}
315
326
return -EINVAL;
+13
-8
lib/libdrm/amdgpu/amdgpu_internal.h
+13
-8
lib/libdrm/amdgpu/amdgpu_internal.h
···
63
63
struct amdgpu_bo_va_mgr *vamgr;
64
64
};
65
65
66
+
struct amdgpu_va_manager {
67
+
/** The VA manager for the lower virtual address space */
68
+
struct amdgpu_bo_va_mgr vamgr_low;
69
+
/** The VA manager for the 32bit address space */
70
+
struct amdgpu_bo_va_mgr vamgr_32;
71
+
/** The VA manager for the high virtual address space */
72
+
struct amdgpu_bo_va_mgr vamgr_high;
73
+
/** The VA manager for the 32bit high address space */
74
+
struct amdgpu_bo_va_mgr vamgr_high_32;
75
+
};
76
+
66
77
struct amdgpu_device {
67
78
atomic_t refcount;
68
79
struct amdgpu_device *next;
···
80
91
pthread_mutex_t bo_table_mutex;
81
92
struct drm_amdgpu_info_device dev_info;
82
93
struct amdgpu_gpu_info info;
83
-
/** The VA manager for the lower virtual address space */
84
-
struct amdgpu_bo_va_mgr vamgr;
85
-
/** The VA manager for the 32bit address space */
86
-
struct amdgpu_bo_va_mgr vamgr_32;
87
-
/** The VA manager for the high virtual address space */
88
-
struct amdgpu_bo_va_mgr vamgr_high;
89
-
/** The VA manager for the 32bit high address space */
90
-
struct amdgpu_bo_va_mgr vamgr_high_32;
94
+
95
+
struct amdgpu_va_manager va_mgr;
91
96
};
92
97
93
98
struct amdgpu_bo {
+64
-7
lib/libdrm/amdgpu/amdgpu_vamgr.c
+64
-7
lib/libdrm/amdgpu/amdgpu_vamgr.c
···
229
229
amdgpu_va_handle *va_range_handle,
230
230
uint64_t flags)
231
231
{
232
+
return amdgpu_va_range_alloc2(&dev->va_mgr, va_range_type, size,
233
+
va_base_alignment, va_base_required,
234
+
va_base_allocated, va_range_handle,
235
+
flags);
236
+
}
237
+
238
+
drm_public int amdgpu_va_range_alloc2(amdgpu_va_manager_handle va_mgr,
239
+
enum amdgpu_gpu_va_range va_range_type,
240
+
uint64_t size,
241
+
uint64_t va_base_alignment,
242
+
uint64_t va_base_required,
243
+
uint64_t *va_base_allocated,
244
+
amdgpu_va_handle *va_range_handle,
245
+
uint64_t flags)
246
+
{
232
247
struct amdgpu_bo_va_mgr *vamgr;
233
248
bool search_from_top = !!(flags & AMDGPU_VA_RANGE_REPLAYABLE);
234
249
int ret;
235
250
236
251
/* Clear the flag when the high VA manager is not initialized */
237
-
if (flags & AMDGPU_VA_RANGE_HIGH && !dev->vamgr_high_32.va_max)
252
+
if (flags & AMDGPU_VA_RANGE_HIGH && !va_mgr->vamgr_high_32.va_max)
238
253
flags &= ~AMDGPU_VA_RANGE_HIGH;
239
254
240
255
if (flags & AMDGPU_VA_RANGE_HIGH) {
241
256
if (flags & AMDGPU_VA_RANGE_32_BIT)
242
-
vamgr = &dev->vamgr_high_32;
257
+
vamgr = &va_mgr->vamgr_high_32;
243
258
else
244
-
vamgr = &dev->vamgr_high;
259
+
vamgr = &va_mgr->vamgr_high;
245
260
} else {
246
261
if (flags & AMDGPU_VA_RANGE_32_BIT)
247
-
vamgr = &dev->vamgr_32;
262
+
vamgr = &va_mgr->vamgr_32;
248
263
else
249
-
vamgr = &dev->vamgr;
264
+
vamgr = &va_mgr->vamgr_low;
250
265
}
251
266
252
267
va_base_alignment = MAX2(va_base_alignment, vamgr->va_alignment);
···
259
274
if (!(flags & AMDGPU_VA_RANGE_32_BIT) && ret) {
260
275
/* fallback to 32bit address */
261
276
if (flags & AMDGPU_VA_RANGE_HIGH)
262
-
vamgr = &dev->vamgr_high_32;
277
+
vamgr = &va_mgr->vamgr_high_32;
263
278
else
264
-
vamgr = &dev->vamgr_32;
279
+
vamgr = &va_mgr->vamgr_32;
265
280
ret = amdgpu_vamgr_find_va(vamgr, size,
266
281
va_base_alignment, va_base_required,
267
282
search_from_top, va_base_allocated);
···
300
315
{
301
316
return va_handle->address;
302
317
}
318
+
319
+
drm_public amdgpu_va_manager_handle amdgpu_va_manager_alloc(void)
320
+
{
321
+
amdgpu_va_manager_handle r = calloc(1, sizeof(struct amdgpu_va_manager));
322
+
return r;
323
+
}
324
+
325
+
drm_public void amdgpu_va_manager_init(struct amdgpu_va_manager *va_mgr,
326
+
uint64_t low_va_offset, uint64_t low_va_max,
327
+
uint64_t high_va_offset, uint64_t high_va_max,
328
+
uint32_t virtual_address_alignment)
329
+
{
330
+
uint64_t start, max;
331
+
332
+
start = low_va_offset;
333
+
max = MIN2(low_va_max, 0x100000000ULL);
334
+
amdgpu_vamgr_init(&va_mgr->vamgr_32, start, max,
335
+
virtual_address_alignment);
336
+
337
+
start = max;
338
+
max = MAX2(low_va_max, 0x100000000ULL);
339
+
amdgpu_vamgr_init(&va_mgr->vamgr_low, start, max,
340
+
virtual_address_alignment);
341
+
342
+
start = high_va_offset;
343
+
max = MIN2(high_va_max, (start & ~0xffffffffULL) + 0x100000000ULL);
344
+
amdgpu_vamgr_init(&va_mgr->vamgr_high_32, start, max,
345
+
virtual_address_alignment);
346
+
347
+
start = max;
348
+
max = MAX2(high_va_max, (start & ~0xffffffffULL) + 0x100000000ULL);
349
+
amdgpu_vamgr_init(&va_mgr->vamgr_high, start, max,
350
+
virtual_address_alignment);
351
+
}
352
+
353
+
drm_public void amdgpu_va_manager_deinit(struct amdgpu_va_manager *va_mgr)
354
+
{
355
+
amdgpu_vamgr_deinit(&va_mgr->vamgr_32);
356
+
amdgpu_vamgr_deinit(&va_mgr->vamgr_low);
357
+
amdgpu_vamgr_deinit(&va_mgr->vamgr_high_32);
358
+
amdgpu_vamgr_deinit(&va_mgr->vamgr_high);
359
+
}
+1
-1
lib/libdrm/amdgpu/meson.build
+1
-1
lib/libdrm/amdgpu/meson.build
+6
lib/libdrm/data/Android.bp
+6
lib/libdrm/data/Android.bp
+78
lib/libdrm/data/amdgpu.ids
+78
lib/libdrm/data/amdgpu.ids
···
29
29
131B, 00, AMD Radeon R4 Graphics
30
30
131C, 00, AMD Radeon R7 Graphics
31
31
131D, 00, AMD Radeon R6 Graphics
32
+
1435, AE, AMD Custom GPU 0932
33
+
1506, C1, AMD Radeon 610M
34
+
1506, C2, AMD Radeon 610M
35
+
1506, C3, AMD Radeon 610M
36
+
1506, C4, AMD Radeon 610M
37
+
15BF, 00, AMD Radeon 780M
38
+
15BF, 01, AMD Radeon 760M
39
+
15BF, 02, AMD Radeon 780M
40
+
15BF, 03, AMD Radeon 760M
41
+
15BF, C1, AMD Radeon 780M
42
+
15BF, C2, AMD Radeon 780M
43
+
15BF, C3, AMD Radeon 760M
44
+
15BF, C4, AMD Radeon 780M
45
+
15BF, C5, AMD Radeon 740M
46
+
15BF, C6, AMD Radeon 780M
47
+
15BF, C7, AMD Radeon 780M
48
+
15BF, C8, AMD Radeon 760M
49
+
15BF, C9, AMD Radeon 780M
50
+
15BF, CA, AMD Radeon 740M
51
+
15BF, CB, AMD Radeon 760M
52
+
15BF, CD, AMD Radeon 760M
53
+
15BF, CF, AMD Radeon 780M
54
+
15BF, D0, AMD Radeon 780M
55
+
15BF, D1, AMD Radeon 780M
56
+
15BF, D2, AMD Radeon 760M
57
+
15BF, D3, AMD Radeon 780M
58
+
15BF, D4, AMD Radeon 780M
59
+
15BF, D5, AMD Radeon 760M
60
+
15BF, D6, AMD Radeon 760M
61
+
15BF, D7, AMD Radeon 780M
62
+
15BF, D8, AMD Radeon 740M
63
+
15BF, D9, AMD Radeon 780M
64
+
15BF, DA, AMD Radeon 780M
65
+
15BF, DB, AMD Radeon 760M
66
+
15BF, DC, AMD Radeon 780M
67
+
15BF, DD, AMD Radeon 780M
68
+
15BF, DE, AMD Radeon 740M
69
+
15BF, DF, AMD Radeon 760M
70
+
15BF, F0, AMD Radeon 760M
71
+
15C8, C1, AMD Radeon 740M
72
+
15C8, C2, AMD Radeon 740M
73
+
15C8, C3, AMD Radeon 740M
74
+
15C8, C4, AMD Radeon 740M
75
+
15C8, D1, AMD Radeon 740M
76
+
15C8, D2, AMD Radeon 740M
77
+
15C8, D3, AMD Radeon 740M
78
+
15C8, D4, AMD Radeon 740M
32
79
15D8, 00, AMD Radeon RX Vega 8 Graphics WS
33
80
15D8, 91, AMD Radeon Vega 3 Graphics
34
81
15D8, 91, AMD Ryzen Embedded R1606G with Radeon Vega Gfx
···
101
148
15DD, E1, AMD Radeon Vega 3 Graphics
102
149
15DD, E2, AMD Radeon Vega 3 Graphics
103
150
163F, AE, AMD Custom GPU 0405
151
+
163F, E1, AMD Custom GPU 0405
152
+
164E, D8, AMD Radeon 610M
153
+
164E, D9, AMD Radeon 610M
154
+
164E, DA, AMD Radeon 610M
155
+
164E, DB, AMD Radeon 610M
156
+
164E, DC, AMD Radeon 610M
157
+
1681, 06, AMD Radeon 680M
158
+
1681, 07, AMD Radeon 660M
159
+
1681, 0A, AMD Radeon 680M
160
+
1681, 0B, AMD Radeon 660M
161
+
1681, C7, AMD Radeon 680M
162
+
1681, C8, AMD Radeon 680M
163
+
1681, C9, AMD Radeon 660M
104
164
6600, 00, AMD Radeon HD 8600 / 8700M
105
165
6600, 81, AMD Radeon R7 M370
106
166
6601, 00, AMD Radeon HD 8500M / 8700M
···
368
428
73DF, C3, AMD Radeon RX 6800M
369
429
73DF, C5, AMD Radeon RX 6700 XT
370
430
73DF, CF, AMD Radeon RX 6700M
431
+
73DF, D5, AMD Radeon RX 6750 GRE 12GB
371
432
73DF, D7, AMD TDC-235
433
+
73DF, DF, AMD Radeon RX 6700
434
+
73DF, E5, AMD Radeon RX 6750 GRE 12GB
435
+
73DF, FF, AMD Radeon RX 6700
436
+
73E0, 00, AMD Radeon RX 6600M
372
437
73E1, 00, AMD Radeon Pro W6600M
373
438
73E3, 00, AMD Radeon Pro W6600
374
439
73EF, C0, AMD Radeon RX 6800S
···
380
445
73FF, C3, AMD Radeon RX 6600M
381
446
73FF, C7, AMD Radeon RX 6600
382
447
73FF, CB, AMD Radeon RX 6600S
448
+
73FF, CF, AMD Radeon RX 6600 LE
449
+
73FF, DF, AMD Radeon RX 6750 GRE 10GB
383
450
7408, 00, AMD Instinct MI250X
384
451
740C, 01, AMD Instinct MI250X / MI250
385
452
740F, 02, AMD Instinct MI210
···
394
461
743F, C7, AMD Radeon RX 6400
395
462
743F, C8, AMD Radeon RX 6500M
396
463
743F, CC, AMD Radeon 6550S
464
+
743F, CE, AMD Radeon RX 6450M
397
465
743F, CF, AMD Radeon RX 6300M
466
+
743F, D3, AMD Radeon RX 6550M
398
467
743F, D7, AMD Radeon RX 6400
399
468
7448, 00, AMD Radeon Pro W7900
469
+
744A, 00, AMD Radeon Pro W7900 Dual Slot
400
470
744C, C8, AMD Radeon RX 7900 XTX
401
471
744C, CC, AMD Radeon RX 7900 XT
402
472
744C, CE, AMD Radeon RX 7900 GRE
473
+
744C, CF, AMD Radeon RX 7900M
403
474
745E, CC, AMD Radeon Pro W7800
475
+
7460, 00, AMD Radeon Pro V710
476
+
7461, 00, AMD Radeon Pro V710
477
+
7470, 00, AMD Radeon Pro W7700
404
478
747E, C8, AMD Radeon RX 7800 XT
405
479
747E, FF, AMD Radeon RX 7700 XT
406
480
7480, 00, AMD Radeon Pro W7600
481
+
7480, C0, AMD Radeon RX 7600 XT
407
482
7480, C1, AMD Radeon RX 7700S
408
483
7480, C3, AMD Radeon RX 7600S
409
484
7480, C7, AMD Radeon RX 7600M XT
410
485
7480, CF, AMD Radeon RX 7600
411
486
7483, CF, AMD Radeon RX 7600M
412
487
7489, 00, AMD Radeon Pro W7500
488
+
74A0, 00, AMD Instinct MI300A
489
+
74A1, 00, AMD Instinct MI300X
490
+
74B5, 00, AMD Instinct MI300X VF
413
491
9830, 00, AMD Radeon HD 8400 / R3 Series
414
492
9831, 00, AMD Radeon HD 8400E
415
493
9832, 00, AMD Radeon HD 8330
-1
lib/libdrm/exynos/exynos_drm.c
-1
lib/libdrm/exynos/exynos_drm.c
-1
lib/libdrm/exynos/exynos_fimg2d.c
-1
lib/libdrm/exynos/exynos_fimg2d.c
+2
-2
lib/libdrm/exynos/meson.build
+2
-2
lib/libdrm/exynos/meson.build
···
26
26
include_directories : [inc_root, inc_drm],
27
27
link_with : libdrm,
28
28
dependencies : [dep_threads],
29
-
version : '1.0.0',
29
+
version : '1.@0@.0'.format(patch_ver),
30
30
install : true,
31
31
)
32
32
···
56
56
args : [
57
57
'--lib', libdrm_exynos,
58
58
'--symbols-file', files('exynos-symbols.txt'),
59
-
'--nm', prog_nm.path(),
59
+
'--nm', prog_nm.full_path(),
60
60
],
61
61
)
-2
lib/libdrm/freedreno/kgsl/kgsl_bo.c
-2
lib/libdrm/freedreno/kgsl/kgsl_bo.c
+2
-2
lib/libdrm/freedreno/meson.build
+2
-2
lib/libdrm/freedreno/meson.build
···
46
46
include_directories : [inc_root, inc_drm],
47
47
dependencies : [dep_valgrind, dep_threads, dep_rt, dep_atomic_ops],
48
48
link_with : libdrm,
49
-
version : '1.0.0',
49
+
version : '1.@0@.0'.format(patch_ver),
50
50
install : true,
51
51
)
52
52
···
77
77
args : [
78
78
'--lib', libdrm_freedreno,
79
79
'--symbols-file', files('freedreno-symbols.txt'),
80
-
'--nm', prog_nm.path(),
80
+
'--nm', prog_nm.full_path(),
81
81
],
82
82
)
+25
-1
lib/libdrm/include/drm/amdgpu_drm.h
+25
-1
lib/libdrm/include/drm/amdgpu_drm.h
···
392
392
#define AMDGPU_TILING_NUM_BANKS_SHIFT 21
393
393
#define AMDGPU_TILING_NUM_BANKS_MASK 0x3
394
394
395
-
/* GFX9 and later: */
395
+
/* GFX9 - GFX11: */
396
396
#define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0
397
397
#define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f
398
398
#define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5
···
405
405
#define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1
406
406
#define AMDGPU_TILING_SCANOUT_SHIFT 63
407
407
#define AMDGPU_TILING_SCANOUT_MASK 0x1
408
+
409
+
/* GFX12 and later: */
410
+
#define AMDGPU_TILING_GFX12_SWIZZLE_MODE_SHIFT 0
411
+
#define AMDGPU_TILING_GFX12_SWIZZLE_MODE_MASK 0x7
412
+
/* These are DCC recompression setting for memory management: */
413
+
#define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_SHIFT 3
414
+
#define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 /* 0:64B, 1:128B, 2:256B */
415
+
#define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_SHIFT 5
416
+
#define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_MASK 0x7 /* CB_COLOR0_INFO.NUMBER_TYPE */
417
+
#define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_SHIFT 8
418
+
#define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_MASK 0x3f /* [0:4]:CB_COLOR0_INFO.FORMAT, [5]:MM */
408
419
409
420
/* Set/Get helpers for tiling flags. */
410
421
#define AMDGPU_TILING_SET(field, value) \
···
743
754
#define AMDGPU_IDS_FLAGS_TMZ 0x4
744
755
#define AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD 0x8
745
756
757
+
/*
758
+
* Query h/w info: Flag identifying VF/PF/PT mode
759
+
*
760
+
*/
761
+
#define AMDGPU_IDS_FLAGS_MODE_MASK 0x300
762
+
#define AMDGPU_IDS_FLAGS_MODE_SHIFT 0x8
763
+
#define AMDGPU_IDS_FLAGS_MODE_PF 0x0
764
+
#define AMDGPU_IDS_FLAGS_MODE_VF 0x1
765
+
#define AMDGPU_IDS_FLAGS_MODE_PT 0x2
766
+
746
767
/* indicate if acceleration can be working */
747
768
#define AMDGPU_INFO_ACCEL_WORKING 0x00
748
769
/* get the crtc_id from the mode object id? */
···
865
886
#define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK 0xa
866
887
/* Subquery id: Query GPU peak pstate memory clock */
867
888
#define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK 0xb
889
+
/* Subquery id: Query input GPU power */
890
+
#define AMDGPU_INFO_SENSOR_GPU_INPUT_POWER 0xc
868
891
/* Number of VRAM page faults on CPU access. */
869
892
#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
870
893
#define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F
···
1266
1289
#define AMDGPU_FAMILY_GC_10_3_6 149 /* GC 10.3.6 */
1267
1290
#define AMDGPU_FAMILY_GC_10_3_7 151 /* GC 10.3.7 */
1268
1291
#define AMDGPU_FAMILY_GC_11_5_0 150 /* GC 11.5.0 */
1292
+
#define AMDGPU_FAMILY_GC_12_0_0 152 /* GC 12.0.0 */
1269
1293
1270
1294
#if defined(__cplusplus)
1271
1295
}
+24
-5
lib/libdrm/include/drm/drm_fourcc.h
+24
-5
lib/libdrm/include/drm/drm_fourcc.h
···
54
54
* Format modifiers may change any property of the buffer, including the number
55
55
* of planes and/or the required allocation size. Format modifiers are
56
56
* vendor-namespaced, and as such the relationship between a fourcc code and a
57
-
* modifier is specific to the modifer being used. For example, some modifiers
57
+
* modifier is specific to the modifier being used. For example, some modifiers
58
58
* may preserve meaning - such as number of planes - from the fourcc code,
59
59
* whereas others may not.
60
60
*
···
79
79
* format.
80
80
* - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
81
81
* see modifiers as opaque tokens they can check for equality and intersect.
82
-
* These users musn't need to know to reason about the modifier value
82
+
* These users mustn't need to know to reason about the modifier value
83
83
* (i.e. they are not expected to extract information out of the modifier).
84
84
*
85
85
* Vendors should document their modifier usage in as much detail as
···
540
540
* This is a tiled layout using 4Kb tiles in row-major layout.
541
541
* Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
542
542
* are arranged in four groups (two wide, two high) with column-major layout.
543
-
* Each group therefore consits out of four 256 byte units, which are also laid
543
+
* Each group therefore consists out of four 256 byte units, which are also laid
544
544
* out as 2x2 column-major.
545
545
* 256 byte units are made out of four 64 byte blocks of pixels, producing
546
546
* either a square block or a 2:1 unit.
···
1103
1103
*/
1104
1104
1105
1105
/*
1106
-
* The top 4 bits (out of the 56 bits alloted for specifying vendor specific
1106
+
* The top 4 bits (out of the 56 bits allotted for specifying vendor specific
1107
1107
* modifiers) denote the category for modifiers. Currently we have three
1108
1108
* categories of modifiers ie AFBC, MISC and AFRC. We can have a maximum of
1109
1109
* sixteen different categories.
···
1419
1419
* Amlogic FBC Memory Saving mode
1420
1420
*
1421
1421
* Indicates the storage is packed when pixel size is multiple of word
1422
-
* boudaries, i.e. 8bit should be stored in this mode to save allocation
1422
+
* boundaries, i.e. 8bit should be stored in this mode to save allocation
1423
1423
* memory.
1424
1424
*
1425
1425
* This mode reduces body layout to 3072 bytes per 64x32 superblock with
···
1476
1476
#define AMD_FMT_MOD_TILE_VER_GFX10 2
1477
1477
#define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3
1478
1478
#define AMD_FMT_MOD_TILE_VER_GFX11 4
1479
+
#define AMD_FMT_MOD_TILE_VER_GFX12 5
1479
1480
1480
1481
/*
1481
1482
* 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical
···
1486
1487
/*
1487
1488
* 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has
1488
1489
* GFX9 as canonical version.
1490
+
*
1491
+
* 64K_D_2D on GFX12 is identical to 64K_D on GFX11.
1489
1492
*/
1490
1493
#define AMD_FMT_MOD_TILE_GFX9_64K_D 10
1491
1494
#define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25
···
1493
1496
#define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27
1494
1497
#define AMD_FMT_MOD_TILE_GFX11_256K_R_X 31
1495
1498
1499
+
/* Gfx12 swizzle modes:
1500
+
* 0 - LINEAR
1501
+
* 1 - 256B_2D - 2D block dimensions
1502
+
* 2 - 4KB_2D
1503
+
* 3 - 64KB_2D
1504
+
* 4 - 256KB_2D
1505
+
* 5 - 4KB_3D - 3D block dimensions
1506
+
* 6 - 64KB_3D
1507
+
* 7 - 256KB_3D
1508
+
*/
1509
+
#define AMD_FMT_MOD_TILE_GFX12_64K_2D 3
1510
+
#define AMD_FMT_MOD_TILE_GFX12_256K_2D 4
1511
+
1496
1512
#define AMD_FMT_MOD_DCC_BLOCK_64B 0
1497
1513
#define AMD_FMT_MOD_DCC_BLOCK_128B 1
1498
1514
#define AMD_FMT_MOD_DCC_BLOCK_256B 2
···
1523
1539
#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1
1524
1540
#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18
1525
1541
#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3
1542
+
1543
+
#define AMD_FMT_MOD_GFX12_DCC_MAX_COMPRESSED_BLOCK_SHIFT 3
1544
+
#define AMD_FMT_MOD_GFX12_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 /* 0:64B, 1:128B, 2:256B */
1526
1545
1527
1546
/*
1528
1547
* DCC supports embedding some clear colors directly in the DCC surface.
+20
-9
lib/libdrm/include/drm/drm_mode.h
+20
-9
lib/libdrm/include/drm/drm_mode.h
···
36
36
/**
37
37
* DOC: overview
38
38
*
39
-
* DRM exposes many UAPI and structure definition to have a consistent
40
-
* and standardized interface with user.
39
+
* DRM exposes many UAPI and structure definitions to have a consistent
40
+
* and standardized interface with users.
41
41
* Userspace can refer to these structure definitions and UAPI formats
42
-
* to communicate to driver
42
+
* to communicate to drivers.
43
43
*/
44
44
45
45
#define DRM_CONNECTOR_NAME_LEN 32
···
540
540
/* the PROP_ATOMIC flag is used to hide properties from userspace that
541
541
* is not aware of atomic properties. This is mostly to work around
542
542
* older userspace (DDX drivers) that read/write each prop they find,
543
-
* witout being aware that this could be triggering a lengthy modeset.
543
+
* without being aware that this could be triggering a lengthy modeset.
544
544
*/
545
545
#define DRM_MODE_PROP_ATOMIC 0x80000000
546
546
···
664
664
};
665
665
666
666
#define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */
667
-
#define DRM_MODE_FB_MODIFIERS (1<<1) /* enables ->modifer[] */
667
+
#define DRM_MODE_FB_MODIFIERS (1<<1) /* enables ->modifier[] */
668
668
669
669
/**
670
670
* struct drm_mode_fb_cmd2 - Frame-buffer metadata.
···
858
858
};
859
859
860
860
/**
861
+
* struct drm_plane_size_hint - Plane size hints
862
+
*
863
+
* The plane SIZE_HINTS property blob contains an
864
+
* array of struct drm_plane_size_hint.
865
+
*/
866
+
struct drm_plane_size_hint {
867
+
__u16 width;
868
+
__u16 height;
869
+
};
870
+
871
+
/**
861
872
* struct hdr_metadata_infoframe - HDR Metadata Infoframe Data.
862
873
*
863
874
* HDR Metadata Infoframe as per CTA 861.G spec. This is expected
···
881
892
* These are coded as unsigned 16-bit values in units of
882
893
* 0.00002, where 0x0000 represents zero and 0xC350
883
894
* represents 1.0000.
884
-
* @display_primaries.x: X cordinate of color primary.
885
-
* @display_primaries.y: Y cordinate of color primary.
895
+
* @display_primaries.x: X coordinate of color primary.
896
+
* @display_primaries.y: Y coordinate of color primary.
886
897
*/
887
898
struct {
888
899
__u16 x, y;
···
892
903
* These are coded as unsigned 16-bit values in units of
893
904
* 0.00002, where 0x0000 represents zero and 0xC350
894
905
* represents 1.0000.
895
-
* @white_point.x: X cordinate of whitepoint of color primary.
896
-
* @white_point.y: Y cordinate of whitepoint of color primary.
906
+
* @white_point.x: X coordinate of whitepoint of color primary.
907
+
* @white_point.y: Y coordinate of whitepoint of color primary.
897
908
*/
898
909
struct {
899
910
__u16 x, y;
+36
lib/libdrm/intel/Android.bp
+36
lib/libdrm/intel/Android.bp
···
1
+
//
2
+
// Copyright © 2011 Intel Corporation
3
+
//
4
+
// Permission is hereby granted, free of charge, to any person obtaining a
5
+
// copy of this software and associated documentation files (the "Software"),
6
+
// to deal in the Software without restriction, including without limitation
7
+
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
// and/or sell copies of the Software, and to permit persons to whom the
9
+
// Software is furnished to do so, subject to the following conditions:
10
+
//
11
+
// The above copyright notice and this permission notice (including the next
12
+
// paragraph) shall be included in all copies or substantial portions of the
13
+
// Software.
14
+
//
15
+
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16
+
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17
+
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18
+
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19
+
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20
+
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21
+
// IN THE SOFTWARE.
22
+
//
23
+
24
+
build = ["Android.sources.bp"]
25
+
26
+
cc_library_shared {
27
+
name: "libdrm_intel",
28
+
defaults: [
29
+
"libdrm_defaults",
30
+
"libdrm_intel_sources",
31
+
],
32
+
vendor: true,
33
+
34
+
// Removed dependency to libpciaccess: not used on Android
35
+
shared_libs: ["libdrm"],
36
+
}
+12
lib/libdrm/intel/Android.sources.bp
+12
lib/libdrm/intel/Android.sources.bp
+2
-2
lib/libdrm/intel/meson.build
+2
-2
lib/libdrm/intel/meson.build
···
32
32
dependencies : [dep_pciaccess, dep_threads, dep_rt, dep_valgrind, dep_atomic_ops],
33
33
c_args : libdrm_c_args,
34
34
gnu_symbol_visibility : 'hidden',
35
-
version : '1.0.0',
35
+
version : '1.@0@.0'.format(patch_ver),
36
36
install : true,
37
37
)
38
38
···
104
104
args : [
105
105
'--lib', libdrm_intel,
106
106
'--symbols-file', files('intel-symbols.txt'),
107
-
'--nm', prog_nm.path(),
107
+
'--nm', prog_nm.full_path(),
108
108
],
109
109
)
+21
-5
lib/libdrm/meson.build
+21
-5
lib/libdrm/meson.build
···
18
18
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
19
19
# SOFTWARE.
20
20
21
+
# The versioning should always stay at 2.4.x. If bumping away from this,
22
+
# you must ensure that all users of patch_ver are changed such that DSO versions
23
+
# continuously increment (e.g. blindly bumping from 2.4.122 to 2.5.0 would
24
+
# roll the libdrm DSO versioning from libdrm.so.2.122.0 back to libdrm.so.2.0.0
25
+
# which would be bad)
21
26
project(
22
27
'libdrm',
23
28
['c'],
24
-
version : '2.4.120',
29
+
version : '2.4.123',
25
30
license : 'MIT',
26
31
meson_version : '>= 0.59',
27
32
default_options : ['buildtype=debugoptimized', 'c_std=c11'],
28
33
)
34
+
35
+
patch_ver = meson.project_version().split('.')[2]
29
36
30
37
if ['windows', 'darwin'].contains(host_machine.system())
31
38
error('unsupported OS: @0@'.format(host_machine.system()))
···
46
53
47
54
android = cc.compiles('''int func() { return __ANDROID__; }''')
48
55
56
+
# Solaris / Illumos
57
+
if host_machine.system() == 'sunos'
58
+
add_global_arguments('-D__EXTENSIONS__', language : 'c')
59
+
add_global_arguments('-D_POSIX_C_SOURCE=3', language : 'c')
60
+
endif
61
+
49
62
symbols_check = find_program('symbols-check.py')
50
63
prog_nm = find_program('nm')
51
64
···
154
167
else
155
168
dep_rt = []
156
169
endif
157
-
dep_m = cc.find_library('m', required : false)
158
170
159
171
# The header is not required on Linux, and is in fact deprecated in glibc 2.30+
160
172
if ['linux'].contains(host_machine.system())
···
229
241
230
242
if target_machine.endian() == 'big'
231
243
config.set('HAVE_BIG_ENDIAN', 1)
244
+
endif
245
+
246
+
if android
247
+
config.set('BIONIC_IOCTL_NO_SIGNEDNESS_OVERLOAD', 1)
232
248
endif
233
249
234
250
config_file = configure_file(
235
251
configuration : config,
236
252
output : 'config.h',
237
253
)
238
-
add_project_arguments('-include', '@0@'.format(config_file), language : 'c')
254
+
add_project_arguments('-include', meson.current_build_dir() / 'config.h', language : 'c')
239
255
240
256
inc_root = include_directories('.')
241
257
inc_drm = include_directories('include/drm')
···
251
267
if android
252
268
libdrm_kw = {}
253
269
else
254
-
libdrm_kw = {'version' : '2.4.0'}
270
+
libdrm_kw = { 'version' : '2.@0@.0'.format(patch_ver) }
255
271
endif
256
272
257
273
libdrm = library(
258
274
'drm',
259
275
libdrm_files,
260
276
c_args : libdrm_c_args,
261
-
dependencies : [dep_valgrind, dep_rt, dep_m],
277
+
dependencies : [dep_valgrind, dep_rt],
262
278
include_directories : inc_drm,
263
279
install : true,
264
280
kwargs : libdrm_kw,
+11
lib/libdrm/nouveau/Android.bp
+11
lib/libdrm/nouveau/Android.bp
+11
lib/libdrm/nouveau/Android.sources.bp
+11
lib/libdrm/nouveau/Android.sources.bp
+1
-1
lib/libdrm/nouveau/meson.build
+1
-1
lib/libdrm/nouveau/meson.build
+12
lib/libdrm/omap/Android.bp
+12
lib/libdrm/omap/Android.bp
+8
lib/libdrm/omap/Android.sources.bp
+8
lib/libdrm/omap/Android.sources.bp
+2
-2
lib/libdrm/omap/meson.build
+2
-2
lib/libdrm/omap/meson.build
···
26
26
gnu_symbol_visibility : 'hidden',
27
27
link_with : libdrm,
28
28
dependencies : [dep_threads, dep_atomic_ops],
29
-
version : '1.0.0',
29
+
version : '1.@0@.0'.format(patch_ver),
30
30
install : true,
31
31
)
32
32
···
56
56
args : [
57
57
'--lib', libdrm_omap,
58
58
'--symbols-file', files('omap-symbols.txt'),
59
-
'--nm', prog_nm.path(),
59
+
'--nm', prog_nm.full_path(),
60
60
],
61
61
)
-1
lib/libdrm/omap/omap_drm.c
-1
lib/libdrm/omap/omap_drm.c
+11
lib/libdrm/radeon/Android.bp
+11
lib/libdrm/radeon/Android.bp
+13
lib/libdrm/radeon/Android.sources.bp
+13
lib/libdrm/radeon/Android.sources.bp
+1
-1
lib/libdrm/radeon/meson.build
+1
-1
lib/libdrm/radeon/meson.build
+4
lib/libdrm/symbols-check.py
+4
lib/libdrm/symbols-check.py
···
7
7
8
8
# This list contains symbols that _might_ be exported for some platforms
9
9
PLATFORM_SYMBOLS = [
10
+
'_GLOBAL_OFFSET_TABLE_',
10
11
'__bss_end__',
11
12
'__bss_start__',
12
13
'__bss_start',
···
16
17
'_end',
17
18
'_fini',
18
19
'_init',
20
+
'_fbss',
21
+
'_fdata',
22
+
'_ftext',
19
23
]
20
24
21
25
+14
lib/libdrm/tegra/Android.bp
+14
lib/libdrm/tegra/Android.bp
+1
-1
lib/libdrm/tegra/job.c
+1
-1
lib/libdrm/tegra/job.c
+2
-2
lib/libdrm/tegra/meson.build
+2
-2
lib/libdrm/tegra/meson.build
···
31
31
dependencies : [dep_threads, dep_atomic_ops],
32
32
c_args : libdrm_c_args,
33
33
gnu_symbol_visibility : 'hidden',
34
-
version : '0.0.0',
34
+
version : '0.@0@.0'.format(patch_ver),
35
35
install : true,
36
36
)
37
37
···
59
59
args : [
60
60
'--lib', libdrm_tegra,
61
61
'--symbols-file', files('tegra-symbols.txt'),
62
-
'--nm', prog_nm.path(),
62
+
'--nm', prog_nm.full_path(),
63
63
],
64
64
)
+6
lib/libdrm/tests/Android.bp
+6
lib/libdrm/tests/Android.bp
+4
-4
lib/libdrm/tests/amdgpu/shader_code.h
+4
-4
lib/libdrm/tests/amdgpu/shader_code.h
···
75
75
struct shader_test_ps_shader {
76
76
const uint32_t *shader;
77
77
unsigned shader_size;
78
-
const uint32_t patchinfo_code_size;
78
+
uint32_t patchinfo_code_size;
79
79
const uint32_t *patchinfo_code;
80
80
const uint32_t *patchinfo_code_offset;
81
81
const struct reg_info *sh_reg;
82
-
const uint32_t num_sh_reg;
82
+
uint32_t num_sh_reg;
83
83
const struct reg_info *context_reg;
84
-
const uint32_t num_context_reg;
84
+
uint32_t num_context_reg;
85
85
};
86
86
87
87
struct shader_test_vs_shader {
···
111
111
#define SHADER_PS_INFO(_ps, _n) \
112
112
{ps_##_ps##_shader_gfx##_n, sizeof(ps_##_ps##_shader_gfx##_n), \
113
113
ps_##_ps##_shader_patchinfo_code_size_gfx##_n, \
114
-
ps_##_ps##_shader_patchinfo_code_gfx##_n, \
114
+
&(ps_##_ps##_shader_patchinfo_code_gfx##_n)[0][0][0], \
115
115
ps_##_ps##_shader_patchinfo_offset_gfx##_n, \
116
116
ps_##_ps##_sh_registers_gfx##_n, ps_##_ps##_num_sh_registers_gfx##_n, \
117
117
ps_##_ps##_context_registers_gfx##_n, ps_##_ps##_num_context_registers_gfx##_n}
+10
-10
lib/libdrm/tests/amdgpu/shader_code_gfx10.h
+10
-10
lib/libdrm/tests/amdgpu/shader_code_gfx10.h
···
41
41
0xF8001C0F, 0x00000100, 0xBF810000
42
42
};
43
43
44
-
static const uint32_t ps_const_shader_patchinfo_code_size_gfx10 = 6;
44
+
#define ps_const_shader_patchinfo_code_size_gfx10 6
45
45
46
46
static const uint32_t ps_const_shader_patchinfo_code_gfx10[][10][6] = {
47
47
{{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001890, 0x00000000 },
···
61
61
0x00000004
62
62
};
63
63
64
-
static const uint32_t ps_const_num_sh_registers_gfx10 = 2;
64
+
#define ps_const_num_sh_registers_gfx10 2
65
65
66
66
static const struct reg_info ps_const_sh_registers_gfx10[] = {
67
67
{0x2C0A, 0x000C0000},//{ mmSPI_SHADER_PGM_RSRC1_PS, 0x000C0000 },
···
79
79
{0xA1C5, 0x00000004}, //{ mmSPI_SHADER_COL_FORMAT, 0x00000004 /* SI_EXPORT_FMT_FP16_ABGR */ }
80
80
};
81
81
82
-
static const uint32_t ps_const_num_context_registers_gfx10 = 7;
82
+
#define ps_const_num_context_registers_gfx10 7
83
83
84
84
static const uint32_t ps_tex_shader_gfx10[] = {
85
85
0xBEFC030C, 0xBE8E047E, 0xBEFE0A7E, 0xC8080000,
···
93
93
0x0000000C
94
94
};
95
95
96
-
static const uint32_t ps_tex_shader_patchinfo_code_size_gfx10 = 6;
96
+
#define ps_tex_shader_patchinfo_code_size_gfx10 6
97
97
98
98
static const uint32_t ps_tex_shader_patchinfo_code_gfx10[][10][6] = {
99
99
{{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001890, 0x00000000 },
···
115
115
{0x2C0B, 0x00000018 }, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000018 }
116
116
};
117
117
118
-
static const uint32_t ps_tex_num_sh_registers_gfx10 = 2;
118
+
#define ps_tex_num_sh_registers_gfx10 2
119
119
120
120
// Holds Context Register Information
121
121
static const struct reg_info ps_tex_context_registers_gfx10[] =
···
129
129
{0xA1C5, 0x00000004}, //{ mmSPI_SHADER_COL_FORMAT, 0x00000004 /* SI_EXPORT_FMT_FP16_ABGR */ }
130
130
};
131
131
132
-
static const uint32_t ps_tex_num_context_registers_gfx10 = 7;
132
+
#define ps_tex_num_context_registers_gfx10 7
133
133
134
134
static const uint32_t vs_RectPosTexFast_shader_gfx10[] = {
135
135
0x7E000B00, 0x060000F3, 0x7E020202, 0x7E040206,
···
148
148
{0x2C4B, 0x00000018 }, //{ mmSPI_SHADER_PGM_RSRC2_VS, 0x00000018 }
149
149
};
150
150
151
-
static const uint32_t vs_RectPosTexFast_num_sh_registers_gfx10 = 2;
151
+
#define vs_RectPosTexFast_num_sh_registers_gfx10 2
152
152
153
153
// Holds Context Register Information
154
154
static const struct reg_info vs_RectPosTexFast_context_registers_gfx10[] =
···
157
157
{0xA1C3, 0x00000000}, //{ mmSPI_SHADER_POS_FORMAT, 0x00000000 /* Always 0 for now */}
158
158
};
159
159
160
-
static const uint32_t vs_RectPosTexFast_num_context_registers_gfx10 = 2;
160
+
#define vs_RectPosTexFast_num_context_registers_gfx10 2
161
161
162
162
static const uint32_t preamblecache_gfx10[] = {
163
163
0xc0026900, 0x81, 0x80000000, 0x40004000, 0xc0026900, 0x8c, 0xaa99aaaa, 0x0,
···
196
196
0xc0026900, 0x2b0, 0x0, 0x0, 0xc0016900, 0x2f8, 0x0
197
197
};
198
198
199
-
static const uint32_t sh_reg_base_gfx10 = 0x2C00;
200
-
static const uint32_t context_reg_base_gfx10 = 0xA000;
199
+
#define sh_reg_base_gfx10 0x2C00
200
+
#define context_reg_base_gfx10 0xA000
201
201
202
202
#endif
+11
-11
lib/libdrm/tests/amdgpu/shader_code_gfx11.h
+11
-11
lib/libdrm/tests/amdgpu/shader_code_gfx11.h
···
101
101
0xBF9F0000
102
102
};
103
103
104
-
static const uint32_t ps_const_shader_patchinfo_code_size_gfx11 = 6;
104
+
#define ps_const_shader_patchinfo_code_size_gfx11 6
105
105
106
106
static const uint32_t ps_const_shader_patchinfo_code_gfx11[][10][6] = {
107
107
{{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000890, 0x00000000 }, // SI_EXPORT_FMT_ZERO
···
121
121
0x00000006
122
122
};
123
123
124
-
static const uint32_t ps_const_num_sh_registers_gfx11 = 2;
124
+
#define ps_const_num_sh_registers_gfx11 2
125
125
126
126
static const struct reg_info ps_const_sh_registers_gfx11[] = {
127
127
{0x2C0A, 0x020C0000}, //{ mmSPI_SHADER_PGM_RSRC1_PS, 0x020C0000 },
···
138
138
{0xA1C5, 0x00000004 }, //{ mmSPI_SHADER_COL_FORMAT, 0x00000004 /* SI_EXPORT_FMT_FP16_ABGR */ }
139
139
};
140
140
141
-
static const uint32_t ps_const_num_context_registers_gfx11 = 7;
141
+
#define ps_const_num_context_registers_gfx11 7
142
142
143
143
static const uint32_t ps_tex_shader_gfx11[] =
144
144
{
···
174
174
};
175
175
176
176
// Denotes the Patch Info Code Length
177
-
static const uint32_t ps_tex_shader_patchinfo_code_size_gfx11 = 6;
177
+
#define ps_tex_shader_patchinfo_code_size_gfx11 6
178
178
179
179
static const uint32_t ps_tex_shader_patchinfo_code_gfx11[][10][6] =
180
180
{
···
197
197
{0x2C0B, 0x00000018 } //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000018 }
198
198
};
199
199
200
-
static const uint32_t ps_tex_num_sh_registers_gfx11 = 2;
200
+
#define ps_tex_num_sh_registers_gfx11 2
201
201
202
202
// Holds Context Register Information
203
203
static const struct reg_info ps_tex_context_registers_gfx11[] =
···
211
211
{0xA1C5, 0x00000004 } //{ mmSPI_SHADER_COL_FORMAT, 0x00000004 /* SI_EXPORT_FMT_FP16_ABGR */ }
212
212
};
213
213
214
-
static const uint32_t ps_tex_num_context_registers_gfx11 = 7;
215
-
214
+
#define ps_tex_num_context_registers_gfx11 7
216
215
217
216
static const uint32_t vs_RectPosTexFast_shader_gfx11[] =
218
217
{
···
261
260
{0x2C8B, 0x0008001C}, //{ mmSPI_SHADER_PGM_RSRC2_GS, 0x0008001C }
262
261
};
263
262
264
-
static const uint32_t vs_RectPosTexFast_num_sh_registers_gfx11 = 2;
263
+
#define vs_RectPosTexFast_num_sh_registers_gfx11 2
265
264
266
265
// Holds Context Register Information
267
266
static const struct reg_info vs_RectPosTexFast_context_registers_gfx11[] =
···
274
273
{0xA2CE, 0x00000001}, //{ mmVGT_GS_MAX_VERT_OUT, 0x00000001 }
275
274
};
276
275
277
-
static const uint32_t vs_RectPosTexFast_num_context_registers_gfx11 = 6;
276
+
#define vs_RectPosTexFast_num_context_registers_gfx11 6
278
277
279
278
static const uint32_t preamblecache_gfx11[] = {
280
279
0xc0026900, 0x81, 0x80000000, 0x40004000, 0xc0026900, 0x8c, 0xaa99aaaa, 0x0,
···
314
313
0xc0046900, 0x1d5, 0x0, 0x0, 0x0, 0x0, 0xc0016900, 0x104, 0x4a00005,
315
314
0xc0016900, 0x1f, 0xf2a0055, 0xc0017900, 0x266, 0x4
316
315
};
317
-
static const uint32_t sh_reg_base_gfx11 = 0x2C00;
318
-
static const uint32_t context_reg_base_gfx11 = 0xA000;
316
+
317
+
#define sh_reg_base_gfx11 0x2C00
318
+
#define context_reg_base_gfx11 0xA000
319
319
320
320
#endif
+11
-10
lib/libdrm/tests/amdgpu/shader_code_gfx9.h
+11
-10
lib/libdrm/tests/amdgpu/shader_code_gfx9.h
···
51
51
0xC4001C0F, 0x00000100, 0xBF810000
52
52
};
53
53
54
-
static const uint32_t ps_const_shader_patchinfo_code_size_gfx9 = 6;
54
+
#define ps_const_shader_patchinfo_code_size_gfx9 6
55
55
56
56
static const uint32_t ps_const_shader_patchinfo_code_gfx9[][10][6] = {
57
57
{{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001890, 0x00000000 },
···
71
71
0x00000004
72
72
};
73
73
74
-
static const uint32_t ps_const_num_sh_registers_gfx9 = 2;
74
+
#define ps_const_num_sh_registers_gfx9 2
75
75
76
76
static const struct reg_info ps_const_sh_registers_gfx9[] = {
77
77
{0x2C0A, 0x000C0040},//{ mmSPI_SHADER_PGM_RSRC1_PS, 0x000C0040 },
78
78
{0x2C0B, 0x00000008}, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000008 }
79
79
};
80
80
81
-
static const uint32_t ps_const_num_context_registers_gfx9 = 7;
81
+
#define ps_const_num_context_registers_gfx9 7
82
82
83
83
static const struct reg_info ps_const_context_registers_gfx9[] = {
84
84
{0xA1B4, 0x00000002}, //{ mmSPI_PS_INPUT_ADDR, 0x00000002 },
···
102
102
0x0000000B
103
103
};
104
104
105
-
static const uint32_t ps_tex_shader_patchinfo_code_size_gfx9 = 6;
105
+
#define ps_tex_shader_patchinfo_code_size_gfx9 6
106
106
107
107
static const uint32_t ps_tex_shader_patchinfo_code_gfx9[][10][6] = {
108
108
{{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001890, 0x00000000 },
···
118
118
}
119
119
};
120
120
121
-
static const uint32_t ps_tex_num_sh_registers_gfx9 = 2;
121
+
#define ps_tex_num_sh_registers_gfx9 2
122
+
122
123
static const struct reg_info ps_tex_sh_registers_gfx9[] = {
123
124
{0x2C0A, 0x000C0081},//{ mmSPI_SHADER_PGM_RSRC1_PS, 0x000C0081 },
124
125
{0x2C0B, 0x00000018}, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000018 }
125
126
};
126
127
127
-
static const uint32_t ps_tex_num_context_registers_gfx9 = 7;
128
+
#define ps_tex_num_context_registers_gfx9 7
128
129
129
130
static const struct reg_info ps_tex_context_registers_gfx9[] = {
130
131
{0xA1B4, 0x00000002}, //{ mmSPI_PS_INPUT_ADDR, 0x00000002 },
···
153
154
{0x2C4B, 0x00000018}, //{ mmSPI_SHADER_PGM_RSRC2_VS, 0x00000018 }
154
155
};
155
156
156
-
static const uint32_t vs_RectPosTexFast_num_sh_registers_gfx9 = 2;
157
+
#define vs_RectPosTexFast_num_sh_registers_gfx9 2
157
158
158
159
// Holds Context Register Information
159
160
static const struct reg_info vs_RectPosTexFast_context_registers_gfx9[] =
···
162
163
{0xA1C3, 0x00000000}, //{ mmSPI_SHADER_POS_FORMAT, 0x00000000 /* Always 0 for now */}
163
164
};
164
165
165
-
static const uint32_t vs_RectPosTexFast_num_context_registers_gfx9 = 2;
166
+
#define vs_RectPosTexFast_num_context_registers_gfx9 2
166
167
167
168
static const uint32_t preamblecache_gfx9[] = {
168
169
0xc0026900, 0x81, 0x80000000, 0x40004000, 0xc0026900, 0x8c, 0xaa99aaaa, 0x0,
···
198
199
0xc0026900, 0x2b0, 0x0, 0x0, 0xc0016900, 0x2f8, 0x0
199
200
};
200
201
201
-
static const uint32_t sh_reg_base_gfx9 = 0x2C00;
202
-
static const uint32_t context_reg_base_gfx9 = 0xA000;
202
+
#define sh_reg_base_gfx9 0x2C00
203
+
#define context_reg_base_gfx9 0xA000
203
204
204
205
#endif
+28
lib/libdrm/tests/amdgpu/shader_test_util.c
+28
lib/libdrm/tests/amdgpu/shader_test_util.c
···
4
4
#include <sys/types.h>
5
5
#include <sys/stat.h>
6
6
#include <string.h>
7
+
#include <assert.h>
7
8
8
9
#include "CUnit/Basic.h"
9
10
#include "amdgpu_test.h"
···
303
304
case AMDGPU_TEST_GFX_V11:
304
305
amdgpu_dispatch_init_gfx11(test_priv);
305
306
break;
307
+
case AMDGPU_TEST_GFX_MAX:
308
+
assert(1 && "Not Support gfx, never go here");
309
+
break;
306
310
}
307
311
}
308
312
···
337
341
ptr[i++] = 0x30000219;
338
342
ptr[i++] = 0xffffffff;
339
343
ptr[i++] = 0xffffffff;
344
+
break;
345
+
case AMDGPU_TEST_GFX_MAX:
346
+
assert(1 && "Not Support gfx, never go here");
340
347
break;
341
348
}
342
349
···
541
548
case AMDGPU_TEST_GFX_V11:
542
549
amdgpu_dispatch_write2hw_gfx11(test_priv);
543
550
break;
551
+
case AMDGPU_TEST_GFX_MAX:
552
+
assert(1 && "Not Support gfx, never go here");
553
+
break;
544
554
}
545
555
}
546
556
···
1168
1178
case AMDGPU_TEST_GFX_V11:
1169
1179
amdgpu_draw_setup_and_write_drawblt_surf_info_gfx11(test_priv);
1170
1180
break;
1181
+
case AMDGPU_TEST_GFX_MAX:
1182
+
assert(1 && "Not Support gfx, never go here");
1183
+
break;
1171
1184
}
1172
1185
}
1173
1186
···
1298
1311
case AMDGPU_TEST_GFX_V11:
1299
1312
amdgpu_draw_setup_and_write_drawblt_state_gfx11(test_priv);
1300
1313
break;
1314
+
case AMDGPU_TEST_GFX_MAX:
1315
+
assert(1 && "Not Support gfx, never go here");
1316
+
break;
1301
1317
}
1302
1318
}
1303
1319
···
1546
1562
case AMDGPU_TEST_GFX_V11:
1547
1563
amdgpu_draw_vs_RectPosTexFast_write2hw_gfx11(test_priv);
1548
1564
break;
1565
+
case AMDGPU_TEST_GFX_MAX:
1566
+
assert(1 && "Not Support gfx, never go here");
1567
+
break;
1549
1568
}
1550
1569
}
1551
1570
···
1679
1698
case AMDGPU_TEST_GFX_V11:
1680
1699
amdgpu_draw_ps_write2hw_gfx11(test_priv);
1681
1700
break;
1701
+
case AMDGPU_TEST_GFX_MAX:
1702
+
assert(1 && "Not Support gfx, never go here");
1703
+
break;
1682
1704
}
1683
1705
}
1684
1706
···
1717
1739
ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
1718
1740
ptr[i++] = 0x242;
1719
1741
ptr[i++] = 0x11;
1742
+
break;
1743
+
case AMDGPU_TEST_GFX_MAX:
1744
+
assert(1 && "Not Support gfx, never go here");
1720
1745
break;
1721
1746
}
1722
1747
···
2009
2034
i += 2;
2010
2035
ptr_cmd[i++] = 0x400;
2011
2036
i++;
2037
+
break;
2038
+
case AMDGPU_TEST_GFX_MAX:
2039
+
assert(1 && "Not Support gfx, never go here");
2012
2040
break;
2013
2041
}
2014
2042
-1
lib/libdrm/tests/exynos/exynos_fimg2d_test.c
-1
lib/libdrm/tests/exynos/exynos_fimg2d_test.c
+12
lib/libdrm/tests/modetest/Android.bp
+12
lib/libdrm/tests/modetest/Android.bp
+10
lib/libdrm/tests/modetest/Android.sources.bp
+10
lib/libdrm/tests/modetest/Android.sources.bp
+8
lib/libdrm/tests/proptest/Android.bp
+8
lib/libdrm/tests/proptest/Android.bp
+35
lib/libdrm/tests/util/Android.bp
+35
lib/libdrm/tests/util/Android.bp
···
1
+
//
2
+
// Copyright © 2015 NVIDIA Corporation
3
+
//
4
+
// Permission is hereby granted, free of charge, to any person obtaining a
5
+
// copy of this software and associated documentation files (the "Software"),
6
+
// to deal in the Software without restriction, including without limitation
7
+
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
// and/or sell copies of the Software, and to permit persons to whom the
9
+
// Software is furnished to do so, subject to the following conditions:
10
+
//
11
+
// The above copyright notice and this permission notice (including the next
12
+
// paragraph) shall be included in all copies or substantial portions of the
13
+
// Software.
14
+
//
15
+
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16
+
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17
+
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18
+
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19
+
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20
+
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21
+
// IN THE SOFTWARE.
22
+
//
23
+
24
+
build = ["Android.sources.bp"]
25
+
26
+
cc_library_static {
27
+
name: "libdrm_util",
28
+
defaults: [
29
+
"libdrm_defaults",
30
+
"libdrm_util_sources",
31
+
],
32
+
shared_libs: ["libdrm"],
33
+
header_libs: ["libdrm_test_headers"],
34
+
export_header_lib_headers: ["libdrm_test_headers"],
35
+
}
+10
lib/libdrm/tests/util/Android.sources.bp
+10
lib/libdrm/tests/util/Android.sources.bp