"Das U-Boot" Source Tree
rockchip: rk3128: Add DRAM driver
- based on sdram_rk322x.c
- phy is different
- replaced magic numbers
- removed DM/DT to fit in SRAM
- supports LPDDR2/DDR3 (all types as per DS)
- addtionally set trfc/trefi based on detected cap
- use sdram_common
- set axi priorities as vendor blob does
- provide serveral dram timings to make it "future proof"
(hopefully nobody will have fiddle to make it still fit in SRAM
when adding a new board)
Signed-off-by: Alex Bee <knaerzche@gmail.com>
authored by
Alex Bee
and committed by
joshua stein
285273b0
ae39917a
+1641
-2
+620
arch/arm/include/asm/arch-rockchip/sdram_rk3128.h
+620
arch/arm/include/asm/arch-rockchip/sdram_rk3128.h
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later
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+
3
+
#ifndef _ASM_ARCH_SDRAM_RK3128_H
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#define _ASM_ARCH_SDRAM_RK3128_H
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+
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#include <asm/arch-rockchip/sdram_common.h>
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#define NUM_DQS 4
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#define PHY_REG(base, n) ((base) + 4 * (n))
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#define PHY_DRV_ODT_SET(n) (((n) << 4) | (n))
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#define QOS_PRIORITY(n) (((n) << 2) | (n))
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enum rk3128_dram_config {
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#if IS_ENABLED(CONFIG_RAM_ROCKCHIP_LPDDR2)
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DRAM_LPDDR2_300_MHZ,
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DRAM_LPDDR2_400_MHZ,
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#else
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DRAM_DDR3_300_MHZ,
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DRAM_DDR3_456_MHZ,
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DRAM_DDR3_528_MHZ,
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#endif
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DRAM_INVALID,
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};
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enum {
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PHY_RON_DISABLE = 0,
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PHY_RON_309OHM = 1,
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PHY_RON_155OHM,
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PHY_RON_103OHM = 3,
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PHY_RON_63OHM = 5,
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PHY_RON_45OHM = 7,
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PHY_RON_77OHM,
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PHY_RON_62OHM,
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PHY_RON_52OHM,
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PHY_RON_44OHM,
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PHY_RON_39OHM,
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PHY_RON_34OHM,
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PHY_RON_31OHM,
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PHY_RON_28OHM,
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PHY_RON_MASK = 15,
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};
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+
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enum {
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PHY_RTT_DISABLE = 0,
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PHY_RTT_861OHM = 1,
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PHY_RTT_431OHM,
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PHY_RTT_287OHM,
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PHY_RTT_216OHM,
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PHY_RTT_172OHM,
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PHY_RTT_145OHM,
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PHY_RTT_124OHM,
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PHY_RTT_215OHM,
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PHY_RTT_144OHM = 10,
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PHY_RTT_123OHM,
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PHY_RTT_108OHM,
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PHY_RTT_96OHM,
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PHY_RTT_86OHM,
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PHY_RTT_78OHM,
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PHY_RTT_MASK = 15,
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};
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enum {
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DQS_DLL_NO_DELAY = 0,
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DQS_DLL_22P5_DELAY,
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DQS_DLL_45_DELAY,
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DQS_DLL_67P5_DELAY,
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DQS_DLL_90_DELAY,
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DQS_DLL_112P5_DELAY,
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DQS_DLL_135_DELAY,
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DQS_DLL_157P5_DELAY,
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};
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enum {
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LPDDR2_TREFI_3_9_us = 39,
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LPDDR2_TREFI_7_8_us = 78,
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};
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enum {
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DDR3_TRFC_512Mb = 90,
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DDR3_TRFC_1Gb = 110,
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DDR3_TRFC_2Gb = 160,
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DDR3_TRFC_4Gb = 300,
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DDR3_TRFC_8Gb = 350,
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+
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LPDDR2_TRFC_512Mb = 90,
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LPDDR2_TRFC_4Gb = 130,
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LPDDR2_TRFC_8Gb = 210,
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};
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90
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/* GRF_SOC_CON0 */
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enum {
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MOBILE_DDR_SEL = BIT(7),
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DDR_8_BIT_SEL = BIT(13),
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DDR_16_BIT_SEL = BIT(14),
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};
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+
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/* GRF_SOC_CON2 */
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enum {
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PCTL_SELF_REFRESH_ENTER = BIT(1),
100
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PHY_LOWPWR_DISBALE = BIT(2),
101
+
MSCH4_MAINDDR3 = BIT(7),
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+
};
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+
104
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/* PTCL */
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enum {
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/* PCTL_TRP */
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TRP_PREA_EXTRA_SHIFT = 16,
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TRP_PREA_EXTRA_MASK = GENMASK(19, TRP_PREA_EXTRA_SHIFT),
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TRP_LPDDR2_8_BK = 3,
110
+
111
+
/* PCTL_DFISTCFG0 */
112
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DFI_INIT_START = BIT(0),
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DFI_FREQ_RATIO_EN = BIT(1),
114
+
DFI_DATA_BYTE_DISABLE_EN = BIT(2),
115
+
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/* PCTL_DFISTCFG1 */
117
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DFI_DRAM_CLK_SR_EN = BIT(0),
118
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DFI_DRAM_CLK_DPD_EN = BIT(1),
119
+
120
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/* PCTL_DFISTCFG2 */
121
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DFI_PARITY_INTR_EN = BIT(0),
122
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DFI_PARITY_EN = BIT(1),
123
+
124
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/* PCTL_DFILPCFG0 */
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DFI_LP_EN_PD_SHIFT = 0,
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DFI_LP_EN_PD = BIT(DFI_LP_EN_PD_SHIFT),
127
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DFI_LP_EN_SR_SHIFT = 8,
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DFI_LP_EN_SR = BIT(DFI_LP_EN_SR_SHIFT),
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DFI_TLP_RESP_SHIFT = 16,
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DFI_TLP_RESP = 7 << DFI_TLP_RESP_SHIFT,
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+
132
+
/* PCTL_DFITPHYUPDTYPE0 */
133
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TPHYUPD_TYPE0 = 1,
134
+
135
+
/* PCTL_DFITPHYRDLAT */
136
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TPHY_RDLAT = 13,
137
+
138
+
/* PCTL_DFITPHYWRDATA */
139
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TPHY_WRDATA = 1,
140
+
141
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/* PCTL_DFIUPDCFG */
142
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DFI_PHYUPD_DISABLE = 0 << 1,
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DFI_CTRLUPD_DISABLE = 0,
144
+
145
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/* PCTL_DFIODTCFG */
146
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RANK0_ODT_READ_SEL_SHIFT = 1,
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RANK0_ODT_READ_SEL = BIT(RANK0_ODT_READ_SEL_SHIFT),
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RANK0_ODT_WRITE_SEL_SHIFT = 3,
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RANK0_ODT_WRITE_SEL = BIT(RANK0_ODT_WRITE_SEL_SHIFT),
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RANK1_ODT_READ_SEL_SHIFT = 8,
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RANK1_ODT_READ_SEL = BIT(RANK1_ODT_READ_SEL_SHIFT),
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RANK1_ODT_WRITE_SEL_SHIFT = 11,
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RANK1_ODT_WRITE_SEL = BIT(RANK1_ODT_WRITE_SEL_SHIFT),
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+
155
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/* PCTL_DFIODTCFG1 */
156
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ODT_LEN_BL8_W_SHIFT = 16,
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ODT_LEN_BL8_W_MASK = GENMASK(18, ODT_LEN_BL8_W_SHIFT),
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ODT_LEN_BL8_W = 7 << ODT_LEN_BL8_W_SHIFT,
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ODT_LEN_BL8_W_0 = 0 << ODT_LEN_BL8_W_SHIFT,
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ODT_LEN_BL8_R_SHIFT = 24,
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ODT_LEN_BL8_R_MASK = GENMASK(26, ODT_LEN_BL8_R_SHIFT),
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ODT_LEN_BL8_R = 7 << ODT_LEN_BL8_R_SHIFT,
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ODT_LEN_BL8_R_0 = 0 << ODT_LEN_BL8_R_SHIFT,
164
+
165
+
/* PCTL_MCFG */
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MEM_BL_4 = 0 << 0,
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MEM_BL_8 = BIT(0),
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TWO_T_SHIFT = 3,
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TWO_T_EN = BIT(TWO_T_SHIFT),
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DDR3_EN = BIT(5),
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DDR2_EN = 0 << 5,
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LPDDR2_S4 = BIT(6),
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PD_IDLE_SHIFT = 8,
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PD_IDLE_DISABLE = 0 << PD_IDLE_SHIFT,
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PD_IDLE_MASK = GENMASK(15, PD_IDLE_SHIFT),
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PD_TYPE_ACT_PD = BIT(16),
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PD_EXIT_SLOW_EXIT_MODE = 0 << 17,
178
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PD_EXIT_FAST_EXIT_MODE = BIT(17),
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TFAW_CFG_5_TDDR = BIT(18),
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TFAW_CFG_6_TDDR = 2 << 18,
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MDDR_LPDDR2_BL_4 = BIT(20),
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MDDR_LPDDR2_BL_8 = 2 << 20,
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LPDDR2_EN = 3 << 22,
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MDDR_CLOCK_STOP_IDLE_DIS = 0 << 24,
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+
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/* PCTL_MCFG1 */
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HW_EXIT_IDLE_EN_MASK = 1,
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HW_EXIT_IDLE_EN_SHIFT = 31,
189
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SR_IDLE_MASK = GENMASK(8, 0),
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SR_IDLE_SHIFT = 0,
191
+
192
+
/* PCTL_SCFG */
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HW_LOW_POWER_EN = BIT(0),
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+
195
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/* PCTL_POWCTL */
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POWER_UP_START = BIT(0),
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+
198
+
/* PCTL_POWSTAT */
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POWER_UP_DONE = BIT(0),
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+
201
+
/*PCTL_PPCFG*/
202
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PPMEM_EN_SHIFT = 0,
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PPMEM_EN_MASK = GENMASK(0, PPMEM_EN_SHIFT),
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PPMEM_EN = BIT(PPMEM_EN_SHIFT),
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PPMEM_DIS = 0 << PPMEM_EN_SHIFT,
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+
207
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/* PCTL_MCMD */
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START_CMD = BIT(31),
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RANK_SEL_SHIFT = 20,
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RANK_SEL_CS0 = 1,
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RANK_SEL_CS1 = 2,
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RANK_SEL_CS0_CS1 = 3,
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BANK_ADDR_SHIFT = 17,
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BANK_ADDR_MASK = GENMASK(2, 0),
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CMD_ADDR_SHIFT = 4,
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CMD_ADDR_MASK = GENMASK(12, 0),
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LPDDR23_MA_SHIFT = 4,
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LPDDR23_MA_MASK = GENMASK(7, 0),
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LPDDR23_OP_SHIFT = 12,
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LPDDR23_OP_MASK = GENMASK(7, 0),
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DDR3_DLL_RESET = BIT(8),
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DESELECT_CMD = 0,
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+
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PREA_CMD = 1,
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+
REF_CMD,
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MRS_CMD,
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ZQCS_CMD,
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ZQCL_CMD,
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RSTL_CMD,
230
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MPR_CMD = 8,
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DFICTRLUPD_CMD = 10,
232
+
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MR0 = 0,
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MR1,
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MR2,
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MR3,
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+
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/* PCTL_STAT */
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INIT_MEM = 0,
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CONFIG,
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CONFIG_REQ,
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ACCESS,
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ACCESS_REQ,
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LOW_POWER,
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LOW_POWER_ENTRY_REQ,
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LOW_POWER_EXIT_REQ,
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PCTL_STAT_MASK = 7,
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+
249
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/* PCTL_SCTL */
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INIT_STATE = 0,
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CFG_STATE,
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GO_STATE,
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SLEEP_STATE,
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WAKEUP_STATE,
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};
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+
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/* DDRPHY */
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enum {
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/* DDRPHY_REG00 */
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RESET_ANALOG_LOGIC_SHIFT = 2,
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RESET_ANALOG_LOGIC_MASK = 1 << RESET_ANALOG_LOGIC_SHIFT,
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+
RESET_ANALOG_LOGIC_ACT = 0 << RESET_ANALOG_LOGIC_SHIFT,
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+
RESET_ANALOG_LOGIC_DIS = 1 << RESET_ANALOG_LOGIC_SHIFT,
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+
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RESET_DIGITAL_CORE_SHIFT = 3,
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+
RESET_DIGITAL_CORE_MASK = 1 << RESET_DIGITAL_CORE_SHIFT,
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+
RESET_DIGITAL_CORE_ACT = 0 << RESET_DIGITAL_CORE_SHIFT,
268
+
RESET_DIGITAL_CORE_DIS = 1 << RESET_DIGITAL_CORE_SHIFT,
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+
270
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CHANNEL_SELECT_SHIFT = 4,
271
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CHANNEL_SELECT_MASK = 15 << CHANNEL_SELECT_SHIFT,
272
+
CHANNEL_SELECT_DQ_16_BIT = 3 << CHANNEL_SELECT_SHIFT,
273
+
CHANNEL_SELECT_DQ_32_BIT = 15 << CHANNEL_SELECT_SHIFT,
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+
275
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/* DDRPHY_REG01 */
276
+
MEMORY_SELECT_DDR3 = 0,
277
+
MEMORY_SELECT_DDR2,
278
+
MEMORY_SELECT_LPDDR2,
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PHY_BL_4 = 0 << 2,
280
+
PHY_BL_8 = BIT(2),
281
+
282
+
/* DDRPHY_REG02 */
283
+
DQS_SQU_CAL_START = BIT(0),
284
+
DQS_SQU_NO_CAL = 0 << 0,
285
+
DQS_SQU_CAL_MASK = 1,
286
+
287
+
/* DDRPHY_REG13 */
288
+
CMD_DLL_DELAY_SHIFT = 0,
289
+
CMD_DLL_DELAY_MASK = 7 << CMD_DLL_DELAY_SHIFT,
290
+
CMD_DLL_DELAY_NO_DELAY = 0 << CMD_DLL_DELAY_SHIFT,
291
+
CMD_DLL_DELAY_22P5 = 1 << CMD_DLL_DELAY_SHIFT,
292
+
CMD_DLL_DELAY_45 = 2 << CMD_DLL_DELAY_SHIFT,
293
+
CMD_DLL_DELAY_67P5 = 3 << CMD_DLL_DELAY_SHIFT,
294
+
CMD_DLL_DELAY_90 = 4 << CMD_DLL_DELAY_SHIFT,
295
+
CMD_DLL_DELAY_112P5 = 5 << CMD_DLL_DELAY_SHIFT,
296
+
CMD_DLL_DELAY_135 = 6 << CMD_DLL_DELAY_SHIFT,
297
+
CMD_DLL_DELAY_157P5 = 7 << CMD_DLL_DELAY_SHIFT,
298
+
299
+
CMD_DLL_SHIFT = 3,
300
+
CMD_DLL_MASK = 1 << CMD_DLL_SHIFT,
301
+
CMD_DLL_ENABLE = 1 << CMD_DLL_SHIFT,
302
+
303
+
CMD_DLL_CLOCK_PHASE_SHIFT = 4,
304
+
CMD_DLL_CLOCK_PHASE_MASK = 1 << CMD_DLL_CLOCK_PHASE_SHIFT,
305
+
CMD_DLL_CLOCK_PHASE_NO_DELAY = 0 << CMD_DLL_CLOCK_PHASE_SHIFT,
306
+
CMD_DLL_CLOCK_PHASE_180_DELAY = 1 << CMD_DLL_CLOCK_PHASE_SHIFT,
307
+
308
+
/* DDRPHY_REG14 */
309
+
CK_DLL_DELAY_SHIFT = 0,
310
+
CK_DLL_DELAY_MASK = 7 << CK_DLL_DELAY_SHIFT,
311
+
CK_DLL_DELAY_NO_DELAY = 0 << CK_DLL_DELAY_SHIFT,
312
+
CK_DLL_DELAY_22P5 = 1 << CK_DLL_DELAY_SHIFT,
313
+
CK_DLL_DELAY_45 = 2 << CK_DLL_DELAY_SHIFT,
314
+
CK_DLL_DELAY_67P5 = 3 << CK_DLL_DELAY_SHIFT,
315
+
CK_DLL_DELAY_90 = 4 << CK_DLL_DELAY_SHIFT,
316
+
CK_DLL_DELAY_112P5 = 5 << CK_DLL_DELAY_SHIFT,
317
+
CK_DLL_DELAY_135 = 6 << CK_DLL_DELAY_SHIFT,
318
+
CK_DLL_DELAY_157P5 = 7 << CK_DLL_DELAY_SHIFT,
319
+
320
+
CK_DLL_CLOCK_PHASE_SHIFT = 4,
321
+
CK_DLL_CLOCK_PHASE_MASK = 1 << CK_DLL_CLOCK_PHASE_SHIFT,
322
+
CK_DLL_CLOCK_PHASE_NO_DELAY = 0 << CK_DLL_CLOCK_PHASE_SHIFT,
323
+
CK_DLL_CLOCK_PHASE_180_DELAY = 1 << CK_DLL_CLOCK_PHASE_SHIFT,
324
+
325
+
/* DDRPHY_REG26, DDRPHY_REG36, DDRPHY_REG46, DDRPHY_REG56*/
326
+
DQ_DLL_DELAY_SHIFT = 0,
327
+
DQ_DLL_DELAY_MASK = 7 << DQ_DLL_DELAY_SHIFT,
328
+
DQ_DLL_DELAY_NO_DELAY = 0 << DQ_DLL_DELAY_SHIFT,
329
+
DQ_DLL_DELAY_22P5 = 1 << DQ_DLL_DELAY_SHIFT,
330
+
DQ_DLL_DELAY_45 = 2 << DQ_DLL_DELAY_SHIFT,
331
+
DQ_DLL_DELAY_67P5 = 3 << DQ_DLL_DELAY_SHIFT,
332
+
DQ_DLL_DELAY_90 = 4 << DQ_DLL_DELAY_SHIFT,
333
+
DQ_DLL_DELAY_112P5 = 5 << DQ_DLL_DELAY_SHIFT,
334
+
DQ_DLL_DELAY_135 = 6 << DQ_DLL_DELAY_SHIFT,
335
+
DQ_DLL_DELAY_157P5 = 7 << DQ_DLL_DELAY_SHIFT,
336
+
337
+
DQ_DLL_SHIFT = 3,
338
+
DQ_DLL_MASK = 1 << DQ_DLL_SHIFT,
339
+
DQ_DLL_ENABLE = 1 << DQ_DLL_SHIFT,
340
+
341
+
DQ_CLOCK_PHASE_SHIFT = 4,
342
+
DQ_CLOCK_PHASE_MASK = 1 << DQ_CLOCK_PHASE_SHIFT,
343
+
DQ_CLOCK_PHASE_NO_DELAY = 0 << DQ_CLOCK_PHASE_SHIFT,
344
+
DQ_CLOCK_PHASE_180_DELAY = 1 << DQ_CLOCK_PHASE_SHIFT,
345
+
346
+
/* DDRPHY_REG27, DDRPHY_REG37, DDRPHY_REG47, DDRPHY_REG57*/
347
+
DQS_DLL_DELAY_SHIFT = 0,
348
+
DQS_DLL_DELAY_MASK = 7 << DQS_DLL_DELAY_SHIFT,
349
+
DQS_DLL_DELAY_NO_DELAY = 0 << DQS_DLL_DELAY_SHIFT,
350
+
DQS_DLL_DELAY_22P5 = 1 << DQS_DLL_DELAY_SHIFT,
351
+
DQS_DLL_DELAY_45 = 2 << DQS_DLL_DELAY_SHIFT,
352
+
DQS_DLL_DELAY_67P5 = 3 << DQS_DLL_DELAY_SHIFT,
353
+
DQS_DLL_DELAY_90 = 4 << DQS_DLL_DELAY_SHIFT,
354
+
DQS_DLL_DELAY_112P5 = 5 << DQS_DLL_DELAY_SHIFT,
355
+
DQS_DLL_DELAY_135 = 6 << DQS_DLL_DELAY_SHIFT,
356
+
DQS_DLL_DELAY_157P5 = 7 << DQS_DLL_DELAY_SHIFT,
357
+
358
+
DQS_DLL_CLOCK_PHASE_SHIFT = 4,
359
+
DQS_DLL_CLOCK_PHASE_MASK = 1 << DQS_DLL_CLOCK_PHASE_SHIFT,
360
+
DQS_DLL_CLOCK_PHASE_NO_DELAY = 0 << DQS_DLL_CLOCK_PHASE_SHIFT,
361
+
DQS_DLL_CLOCK_PHASE_180_DELAY = 1 << DQS_DLL_CLOCK_PHASE_SHIFT,
362
+
363
+
/* DDRPHY_REG28, DDRPHY_REG38, DDRPHY_REG48, DDRPHY_REG58*/
364
+
RX_DQS_DLL_DELAY_SHIFT = 0,
365
+
RX_DQS_DLL_DELAY_MASK = 3 << RX_DQS_DLL_DELAY_SHIFT,
366
+
RX_DQS_DLL_NO_DELAY = 0 << RX_DQS_DLL_DELAY_SHIFT,
367
+
RX_DQS_DLL_DELAY_22P5 = 1 << RX_DQS_DLL_DELAY_SHIFT,
368
+
RX_DQS_DLL_DELAY_45 = 2 << RX_DQS_DLL_DELAY_SHIFT,
369
+
RX_DQS_DLL_DELAY_67P5 = 3 << RX_DQS_DLL_DELAY_SHIFT,
370
+
371
+
/* PHY_REGA4 */
372
+
RIGHT_CHN_B_TX_DQ_BYPASS_SHIFT = 4,
373
+
RIGHT_CHN_B_TX_DQ_BYPASS_MASK = 1 << RIGHT_CHN_B_TX_DQ_BYPASS_SHIFT,
374
+
RIGHT_CHN_B_TX_DQ_BYPASS_SET = 1 << RIGHT_CHN_B_TX_DQ_BYPASS_SHIFT,
375
+
376
+
LEFT_CHN_B_TX_DQ_BYPASS_SHIFT = 3,
377
+
LEFT_CHN_B_TX_DQ_BYPASS_MASK = 1 << LEFT_CHN_B_TX_DQ_BYPASS_SHIFT,
378
+
LEFT_CHN_B_TX_DQ_BYPASS_SET = 1 << LEFT_CHN_B_TX_DQ_BYPASS_SHIFT,
379
+
380
+
RIGHT_CHN_A_TX_DQ_BYPASS_SHIFT = 2,
381
+
RIGHT_CHN_A_TX_DQ_BYPASS_MASK = 1 << RIGHT_CHN_A_TX_DQ_BYPASS_SHIFT,
382
+
RIGHT_CHN_A_TX_DQ_BYPASS_SET = 1 << RIGHT_CHN_A_TX_DQ_BYPASS_SHIFT,
383
+
384
+
LEFT_CHN_A_TX_DQ_BYPASS_SHIFT = 1,
385
+
LEFT_CHN_A_TX_DQ_BYPASS_MASK = 1 << LEFT_CHN_A_TX_DQ_BYPASS_SHIFT,
386
+
LEFT_CHN_A_TX_DQ_BYPASS_SET = 1 << LEFT_CHN_A_TX_DQ_BYPASS_SHIFT,
387
+
388
+
CK_DLL_DLL_BYPASS_SHIFT = 0,
389
+
CK_DLL_DLL_BYPASS_MASK = 1 << CK_DLL_DLL_BYPASS_SHIFT,
390
+
CK_DLL_DLL_BYPASS_SET = 1 << CK_DLL_DLL_BYPASS_SHIFT,
391
+
392
+
/* PHY_REGFF */
393
+
CHN_A_TRAINING_DONE_SHIFT = 0,
394
+
CHN_A_TRAINING_DONE_MASK = 3 << CHN_A_TRAINING_DONE_SHIFT,
395
+
CHN_A_HIGH_8BIT_TRAINING_DONE = 2 << CHN_A_TRAINING_DONE_SHIFT,
396
+
CHN_A_LOW_8BIT_TRAINING_DONE = 1 << CHN_A_TRAINING_DONE_SHIFT,
397
+
CHN_B_TRAINING_DONE_SHIFT = 2,
398
+
CHN_B_TRAINING_DONE_MASK = 3 << CHN_B_TRAINING_DONE_SHIFT,
399
+
CHN_B_HIGH_8BIT_TRAINING_DONE = 2 << CHN_B_TRAINING_DONE_SHIFT,
400
+
CHN_B_LOW_8BIT_TRAINING_DONE = 1 << CHN_B_TRAINING_DONE_SHIFT,
401
+
};
402
+
403
+
typedef union {
404
+
unsigned int noc_timing;
405
+
struct {
406
+
unsigned int acttoact:6;
407
+
unsigned int rdtomiss:6;
408
+
unsigned int wrtomiss:6;
409
+
unsigned int burstlen:3;
410
+
unsigned int rdtowr:5;
411
+
unsigned int wrtord:5;
412
+
unsigned int bwratio:1;
413
+
};
414
+
} rk3128_noc_timing;
415
+
416
+
struct rk3128_pctl_timing {
417
+
unsigned short togcnt1u;
418
+
unsigned short tinit;
419
+
unsigned short trsth;
420
+
unsigned short togcnt100n;
421
+
unsigned short trefi;
422
+
unsigned short tmrd;
423
+
unsigned short trfc;
424
+
unsigned short trp;
425
+
unsigned short trtw;
426
+
unsigned short tal;
427
+
unsigned short tcl;
428
+
unsigned short tcwl;
429
+
unsigned short tras;
430
+
unsigned short trc;
431
+
unsigned short trcd;
432
+
unsigned short trrd;
433
+
unsigned short trtp;
434
+
unsigned short twr;
435
+
unsigned short twtr;
436
+
unsigned short texsr;
437
+
unsigned short txp;
438
+
unsigned short txpdll;
439
+
unsigned short tzqcs;
440
+
unsigned short tzqcsi;
441
+
unsigned short tdqs;
442
+
unsigned short tcksre;
443
+
unsigned short tcksrx;
444
+
unsigned short tcke;
445
+
unsigned short tmod;
446
+
unsigned short trstl;
447
+
unsigned short tzqcl;
448
+
unsigned short tmrr;
449
+
unsigned short tckesr;
450
+
unsigned short tdpd;
451
+
};
452
+
453
+
struct rk3128_phy_timing {
454
+
unsigned short mr[4];
455
+
unsigned short bl;
456
+
unsigned short cl_al;
457
+
};
458
+
459
+
struct rk3128_ddr_timing {
460
+
struct sdram_base_params base;
461
+
struct rk3128_pctl_timing pctl_timing;
462
+
struct rk3128_phy_timing phy_timing;
463
+
rk3128_noc_timing noc_timing;
464
+
};
465
+
466
+
struct rk3128_service_sys {
467
+
unsigned int id_coreid;
468
+
unsigned int id_revisionid;
469
+
unsigned int ddrconf;
470
+
unsigned int ddrtiming;
471
+
unsigned int ddrmode;
472
+
unsigned int readlatency;
473
+
};
474
+
475
+
struct rk3128_ddr_pctl {
476
+
unsigned int scfg;
477
+
unsigned int sctl;
478
+
unsigned int stat;
479
+
unsigned int intrstat;
480
+
unsigned int reserved0[12];
481
+
unsigned int mcmd;
482
+
unsigned int powctl;
483
+
unsigned int powstat;
484
+
unsigned int cmdtstat;
485
+
unsigned int cmdtstaten;
486
+
unsigned int reserved1[3];
487
+
unsigned int mrrcfg0;
488
+
unsigned int mrrstat0;
489
+
unsigned int mrrstat1;
490
+
unsigned int reserved2[4];
491
+
unsigned int mcfg1;
492
+
unsigned int mcfg;
493
+
unsigned int ppcfg;
494
+
unsigned int mstat;
495
+
unsigned int lpddr2zqcfg;
496
+
unsigned int reserved3;
497
+
unsigned int dtupdes;
498
+
unsigned int dtuna;
499
+
unsigned int dtune;
500
+
unsigned int dtuprd0;
501
+
unsigned int dtuprd1;
502
+
unsigned int dtuprd2;
503
+
unsigned int dtuprd3;
504
+
unsigned int dtuawdt;
505
+
unsigned int reserved4[3];
506
+
unsigned int togcnt1u;
507
+
unsigned int tinit;
508
+
unsigned int trsth;
509
+
unsigned int togcnt100n;
510
+
unsigned int trefi;
511
+
unsigned int tmrd;
512
+
unsigned int trfc;
513
+
unsigned int trp;
514
+
unsigned int trtw;
515
+
unsigned int tal;
516
+
unsigned int tcl;
517
+
unsigned int tcwl;
518
+
unsigned int tras;
519
+
unsigned int trc;
520
+
unsigned int trcd;
521
+
unsigned int trrd;
522
+
unsigned int trtp;
523
+
unsigned int twr;
524
+
unsigned int twtr;
525
+
unsigned int texsr;
526
+
unsigned int txp;
527
+
unsigned int txpdll;
528
+
unsigned int tzqcs;
529
+
unsigned int tzqcsi;
530
+
unsigned int tdqs;
531
+
unsigned int tcksre;
532
+
unsigned int tcksrx;
533
+
unsigned int tcke;
534
+
unsigned int tmod;
535
+
unsigned int trstl;
536
+
unsigned int tzqcl;
537
+
unsigned int tmrr;
538
+
unsigned int tckesr;
539
+
unsigned int reserved5[47];
540
+
unsigned int dtuwactl;
541
+
unsigned int dturactl;
542
+
unsigned int dtucfg;
543
+
unsigned int dtuectl;
544
+
unsigned int dtuwd0;
545
+
unsigned int dtuwd1;
546
+
unsigned int dtuwd2;
547
+
unsigned int dtuwd3;
548
+
unsigned int dtuwdm;
549
+
unsigned int dturd0;
550
+
unsigned int dturd1;
551
+
unsigned int dturd2;
552
+
unsigned int dturd3;
553
+
unsigned int dtulfsrwd;
554
+
unsigned int dtulfsrrd;
555
+
unsigned int dtueaf;
556
+
unsigned int dfitctrldelay;
557
+
unsigned int dfiodtcfg;
558
+
unsigned int dfiodtcfg1;
559
+
unsigned int dfiodtrankmap;
560
+
unsigned int dfitphywrdata;
561
+
unsigned int dfitphywrlat;
562
+
unsigned int reserved7[2];
563
+
unsigned int dfitrddataen;
564
+
unsigned int dfitphyrdlat;
565
+
unsigned int reserved8[2];
566
+
unsigned int dfitphyupdtype0;
567
+
unsigned int dfitphyupdtype1;
568
+
unsigned int dfitphyupdtype2;
569
+
unsigned int dfitphyupdtype3;
570
+
unsigned int dfitctrlupdmin;
571
+
unsigned int dfitctrlupdmax;
572
+
unsigned int dfitctrlupddly;
573
+
unsigned int reserved9;
574
+
unsigned int dfiupdcfg;
575
+
unsigned int dfitrefmski;
576
+
unsigned int dfitctrlupdi;
577
+
unsigned int reserved10[4];
578
+
unsigned int dfitrcfg0;
579
+
unsigned int dfitrstat0;
580
+
unsigned int dfitrwrlvlen;
581
+
unsigned int dfitrrdlvlen;
582
+
unsigned int dfitrrdlvlgateen;
583
+
unsigned int dfiststat0;
584
+
unsigned int dfistcfg0;
585
+
unsigned int dfistcfg1;
586
+
unsigned int reserved11;
587
+
unsigned int dfitdramclken;
588
+
unsigned int dfitdramclkdis;
589
+
unsigned int dfistcfg2;
590
+
unsigned int dfistparclr;
591
+
unsigned int dfistparlog;
592
+
unsigned int reserved12[3];
593
+
unsigned int dfilpcfg0;
594
+
unsigned int reserved13[3];
595
+
unsigned int dfitrwrlvlresp0;
596
+
unsigned int dfitrwrlvlresp1;
597
+
unsigned int dfitrwrlvlresp2;
598
+
unsigned int dfitrrdlvlresp0;
599
+
unsigned int dfitrrdlvlresp1;
600
+
unsigned int dfitrrdlvlresp2;
601
+
unsigned int dfitrwrlvldelay0;
602
+
unsigned int dfitrwrlvldelay1;
603
+
unsigned int dfitrwrlvldelay2;
604
+
unsigned int dfitrrdlvldelay0;
605
+
unsigned int dfitrrdlvldelay1;
606
+
unsigned int dfitrrdlvldelay2;
607
+
unsigned int dfitrrdlvlgatedelay0;
608
+
unsigned int dfitrrdlvlgatedelay1;
609
+
unsigned int dfitrrdlvlgatedelay2;
610
+
unsigned int dfitrcmd;
611
+
unsigned int reserved14[46];
612
+
unsigned int ipvr;
613
+
unsigned int iptr;
614
+
};
615
+
616
+
check_member(rk3128_ddr_pctl, iptr, 0x03fc);
617
+
618
+
int rk3128_sdram_init(enum rk3128_dram_config);
619
+
620
+
#endif
+1
arch/arm/mach-rockchip/Kconfig
+1
arch/arm/mach-rockchip/Kconfig
+80
drivers/ram/rockchip/sdram-rk3128-ddr3.inc
+80
drivers/ram/rockchip/sdram-rk3128-ddr3.inc
···
1
+
[DRAM_DDR3_300_MHZ] = {
2
+
{ 300,
3
+
DDR3,
4
+
1,
5
+
0,
6
+
0,
7
+
},
8
+
{
9
+
0x012c, 0x00c8, 0x01f4, 0x001e, 0x004e,
10
+
0x0004, 0x005a, 0x0006, 0x0003, 0x0000,
11
+
0x0006, 0x0005, 0x000c, 0x0010, 0x0006,
12
+
0x0004, 0x0004, 0x0005, 0x0004, 0x0200,
13
+
0x0003, 0x000a, 0x0040, 0x2710, 0x0001,
14
+
0x0005, 0x0005, 0x0003, 0x000c, 0x001e,
15
+
0x0100, 0x0000, 0x0004, 0x0000,
16
+
},
17
+
{
18
+
{
19
+
0x0220, 0x00040, 0x0000, 0x0000
20
+
},
21
+
0x0001, 0x0060
22
+
},
23
+
{
24
+
0x24716310
25
+
},
26
+
},
27
+
[DRAM_DDR3_456_MHZ] = {
28
+
{
29
+
456,
30
+
DDR3,
31
+
1,
32
+
0,
33
+
0,
34
+
},
35
+
{
36
+
0x001c8, 0x000c8, 0x001f4, 0x0002d, 0x0004e,
37
+
0x00004, 0x00089, 0x00008, 0x00004, 0x00000,
38
+
0x00008, 0x00006, 0x00012, 0x00019, 0x00008,
39
+
0x00005, 0x00004, 0x00007, 0x00004, 0x00200,
40
+
0x00004, 0x0000b, 0x00040, 0x02710, 0x00001,
41
+
0x00005, 0x00005, 0x00004, 0x0000c, 0x0002e,
42
+
0x00100, 0x00000, 0x00005, 0x00000,
43
+
},
44
+
{
45
+
{
46
+
0x00640, 0x00040, 0x00008, 0x00000,
47
+
},
48
+
0x00001, 0x00080,
49
+
},
50
+
{
51
+
0x2891d419,
52
+
},
53
+
},
54
+
[DRAM_DDR3_528_MHZ] = {
55
+
{
56
+
528,
57
+
DDR3,
58
+
1,
59
+
0,
60
+
0,
61
+
},
62
+
{
63
+
0x00210, 0x000c8, 0x001f4, 0x00034, 0x0004e,
64
+
0x00004, 0x0009f, 0x00008, 0x00004, 0x00000,
65
+
0x00008, 0x00006, 0x00014, 0x0001c, 0x00008,
66
+
0x00006, 0x00004, 0x00008, 0x00004, 0x00200,
67
+
0x00004, 0x0000d, 0x00040, 0x02710, 0x00001,
68
+
0x00006, 0x00006, 0x00004, 0x0000c, 0x00035,
69
+
0x00100, 0x00000, 0x00005, 0x00000,
70
+
},
71
+
{
72
+
{
73
+
0x00840, 0x00040, 0x00008, 0x00000,
74
+
},
75
+
0x00001, 0x00080,
76
+
},
77
+
{
78
+
0x2891e41c,
79
+
},
80
+
},
+54
drivers/ram/rockchip/sdram-rk3128-lpddr2.inc
+54
drivers/ram/rockchip/sdram-rk3128-lpddr2.inc
···
1
+
[DRAM_LPDDR2_300_MHZ] = {
2
+
{
3
+
300,
4
+
LPDDR2,
5
+
1,
6
+
0,
7
+
0,
8
+
},
9
+
{
10
+
0x0012c, 0x000c8, 0x00000, 0x0001e, 0x00026,
11
+
0x00005, 0x0003f, 0x00009, 0x00009, 0x00000,
12
+
0x00005, 0x00002, 0x0000d, 0x00016, 0x00008,
13
+
0x00003, 0x00003, 0x00005, 0x00003, 0x00042,
14
+
0x00003, 0x00000, 0x0001b, 0x00000, 0x00001,
15
+
0x00001, 0x00002, 0x00003, 0x00000, 0x00000,
16
+
0x0006c, 0x00002, 0x00005, 0x001f4,
17
+
},
18
+
{
19
+
{
20
+
0x00000, 0x00062, 0x00003, 0x00001,
21
+
},
22
+
0x00001, 0x00050,
23
+
},
24
+
{
25
+
0x18e99496,
26
+
},
27
+
},
28
+
[DRAM_LPDDR2_400_MHZ] = {
29
+
{
30
+
400,
31
+
LPDDR2,
32
+
1,
33
+
0,
34
+
0,
35
+
},
36
+
{ 0x0190, 0x00c8, 0x0000, 0x0028, 0x0026,
37
+
0x0005, 0x0054, 0x000b, 0x0009, 0x0000,
38
+
0x0006, 0x0003, 0x0011, 0x001c, 0x000a,
39
+
0x0004, 0x0003, 0x0006, 0x0003, 0x0058,
40
+
0x0003, 0x0000, 0x0024, 0x0000, 0x0001,
41
+
0x0001, 0x0002, 0x0003, 0x0000, 0x0000,
42
+
0x0090, 0x0002, 0x0006, 0x01f4,
43
+
},
44
+
{
45
+
{
46
+
0x0000, 0x0082, 0x0004, 0x0001,
47
+
},
48
+
0x0001,
49
+
0x0060,
50
+
},
51
+
{
52
+
0x1ce9f59c,
53
+
},
54
+
},
+886
-2
drivers/ram/rockchip/sdram_rk3128.c
+886
-2
drivers/ram/rockchip/sdram_rk3128.c
···
3
3
* (C) Copyright 2017 Rockchip Electronics Co., Ltd.
4
4
*/
5
5
6
-
#include <config.h>
7
6
#include <dm.h>
8
-
#include <log.h>
9
7
#include <ram.h>
8
+
#include <debug_uart.h>
10
9
#include <syscon.h>
11
10
#include <asm/arch-rockchip/clock.h>
11
+
#include <asm/arch-rockchip/cru_rk3128.h>
12
12
#include <asm/arch-rockchip/grf_rk3128.h>
13
+
#include <asm/arch-rockchip/hardware.h>
13
14
#include <asm/arch-rockchip/sdram.h>
15
+
#include <asm/arch-rockchip/sdram_rk3128.h>
16
+
17
+
#include <linux/delay.h>
14
18
15
19
struct dram_info {
20
+
#if IS_ENABLED(CONFIG_TPL_BUILD)
21
+
struct rk3128_cru *cru;
22
+
struct rk3128_ddr_pctl *pctl;
23
+
struct rk3128_ddr_timing *ddr_timing;
24
+
struct rk3128_service_sys *axi_bus;
25
+
struct sdram_cap_info cap_info;
26
+
void __iomem *phy_base;
27
+
#else
16
28
struct ram_info info;
29
+
#endif
17
30
struct rk3128_grf *grf;
18
31
};
19
32
33
+
#if IS_ENABLED(CONFIG_TPL_BUILD)
34
+
35
+
#define CPU_AXI_BUS_BASE 0x10128000
36
+
#define CRU_BASE 0x20000000
37
+
#define GRF_BASE 0x20008000
38
+
#define DDR_PCTL_BASE 0x20004000
39
+
#define DDR_PHY_BASE 0x2000a000
40
+
41
+
#define AXI_VIO_QOS_PRIO CPU_AXI_BUS_BASE + 0x7188
42
+
#define AXI_VIP_QOS_PRIO CPU_AXI_BUS_BASE + 0x7208
43
+
44
+
// from ddr_rk3126.c
45
+
#define READLATENCY 0x3f
46
+
#define PHY_DLL_DISABLE_FREQ 266
47
+
#define PHY_CLK_DRV PHY_RON_44OHM
48
+
#define PHY_CMD_DRV PHY_RON_44OHM
49
+
#define PHY_DQS_DRV PHY_RON_44OHM
50
+
51
+
struct rk3128_ddr_timing rk3128_ddr_timings[] = {
52
+
#if IS_ENABLED(CONFIG_RAM_ROCKCHIP_LPDDR2)
53
+
# include "sdram-rk3128-lpddr2.inc"
54
+
#else
55
+
# include "sdram-rk3128-ddr3.inc"
56
+
#endif
57
+
};
58
+
59
+
/*
60
+
* from RK312X TRM "7.2.3 Memory Scheduler"
61
+
*
62
+
* [7:6] bank(n:n bit bank)
63
+
* [5:4] row(12+n)
64
+
* [3] cs(0:1 cs, 1:2 cs)
65
+
* [2:1] bank(n:n bit bank)
66
+
* [0] col(9+n)
67
+
*/
68
+
static const char ddr_cfg_2_rbc[] = {
69
+
((0 << 6) | (0 << 4) | (0 << 3) | (1 << 2) | 1),
70
+
((0 << 6) | (1 << 4) | (0 << 3) | (1 << 2) | 1),
71
+
((0 << 6) | (2 << 4) | (0 << 3) | (1 << 2) | 1),
72
+
((0 << 6) | (3 << 4) | (0 << 3) | (1 << 2) | 1),
73
+
((0 << 6) | (1 << 4) | (0 << 3) | (1 << 2) | 2),
74
+
((0 << 6) | (2 << 4) | (0 << 3) | (1 << 2) | 2),
75
+
((0 << 6) | (3 << 4) | (0 << 3) | (1 << 2) | 2),
76
+
((0 << 6) | (0 << 4) | (0 << 3) | (1 << 2) | 0),
77
+
((0 << 6) | (1 << 4) | (0 << 3) | (1 << 2) | 0),
78
+
((0 << 6) | (2 << 4) | (0 << 3) | (1 << 2) | 0),
79
+
((0 << 6) | (3 << 4) | (0 << 3) | (1 << 2) | 0),
80
+
((0 << 6) | (2 << 4) | (0 << 3) | (0 << 2) | 1),
81
+
((1 << 6) | (1 << 4) | (0 << 3) | (0 << 2) | 2),
82
+
((1 << 6) | (1 << 4) | (0 << 3) | (0 << 2) | 1),
83
+
((0 << 6) | (3 << 4) | (1 << 3) | (1 << 2) | 1),
84
+
((0 << 6) | (3 << 4) | (1 << 3) | (1 << 2) | 0),
85
+
};
86
+
87
+
static int rkclk_set_dpll(struct dram_info *dram_info)
88
+
{
89
+
struct rk3128_pll *pll = &dram_info->cru->pll[1];
90
+
struct pll_div dpll_cfg;
91
+
/* PLL runs at 2 * phy freq */
92
+
unsigned int pll_freq = dram_info->ddr_timing->base.ddr_freq * 2;
93
+
unsigned int timeout = 1000;
94
+
95
+
dpll_cfg.refdiv = 1;
96
+
if (pll_freq <= 400) {
97
+
dpll_cfg.postdiv1 = 6;
98
+
dpll_cfg.postdiv2 = 1;
99
+
} else if (pll_freq <= 600) {
100
+
dpll_cfg.postdiv1 = 4;
101
+
dpll_cfg.postdiv2 = 1;
102
+
} else if (pll_freq <= 800) {
103
+
dpll_cfg.postdiv1 = 3;
104
+
dpll_cfg.postdiv2 = 1;
105
+
} else {
106
+
dpll_cfg.postdiv1 = 2;
107
+
dpll_cfg.postdiv2 = 1;
108
+
}
109
+
110
+
dpll_cfg.fbdiv = (pll_freq * dpll_cfg.refdiv * dpll_cfg.postdiv1 * dpll_cfg.postdiv2) / 24;
111
+
112
+
rk_clrsetreg(&dram_info->cru->cru_mode_con, DPLL_MODE_MASK,
113
+
DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
114
+
115
+
rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
116
+
117
+
rk_clrsetreg(&pll->con0,
118
+
PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
119
+
(dpll_cfg.postdiv1 << PLL_POSTDIV1_SHIFT) |
120
+
dpll_cfg.fbdiv);
121
+
rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
122
+
(dpll_cfg.postdiv2 << PLL_POSTDIV2_SHIFT |
123
+
dpll_cfg.refdiv << PLL_REFDIV_SHIFT));
124
+
125
+
while (timeout > 0) {
126
+
udelay(1);
127
+
if (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
128
+
break;
129
+
timeout--;
130
+
}
131
+
132
+
if (timeout == 0) {
133
+
debug("Failed to wait for DPLL lock");
134
+
return -1;
135
+
}
136
+
137
+
rk_clrsetreg(&dram_info->cru->cru_mode_con, DPLL_MODE_MASK,
138
+
DPLL_MODE_NORM << DPLL_MODE_SHIFT);
139
+
return 0;
140
+
}
141
+
142
+
static void phy_softreset(struct dram_info *dram_info)
143
+
{
144
+
clrsetbits_le32(PHY_REG(dram_info->phy_base, 0x00),
145
+
RESET_DIGITAL_CORE_MASK | RESET_ANALOG_LOGIC_MASK,
146
+
RESET_DIGITAL_CORE_ACT | RESET_ANALOG_LOGIC_ACT);
147
+
udelay(10);
148
+
149
+
clrsetbits_le32(PHY_REG(dram_info->phy_base, 0x00),
150
+
RESET_ANALOG_LOGIC_MASK, RESET_ANALOG_LOGIC_DIS);
151
+
udelay(5);
152
+
153
+
clrsetbits_le32(PHY_REG(dram_info->phy_base, 0x00),
154
+
RESET_DIGITAL_CORE_MASK, RESET_DIGITAL_CORE_DIS);
155
+
udelay(1);
156
+
}
157
+
158
+
static void phy_pctrl_reset(struct dram_info *dram_info)
159
+
{
160
+
rk_clrsetreg(&dram_info->cru->cru_softrst_con[5],
161
+
1 << DDRCTRL_PSRST_SHIFT | 1 << DDRCTRL_SRST_SHIFT |
162
+
1 << DDRPHY_PSRST_SHIFT | 1 << DDRPHY_SRST_SHIFT,
163
+
1 << DDRCTRL_PSRST_SHIFT | 1 << DDRCTRL_SRST_SHIFT |
164
+
1 << DDRPHY_PSRST_SHIFT | 1 << DDRPHY_SRST_SHIFT);
165
+
udelay(10);
166
+
167
+
rk_clrreg(&dram_info->cru->cru_softrst_con[5],
168
+
1 << DDRPHY_PSRST_SHIFT |
169
+
1 << DDRPHY_SRST_SHIFT);
170
+
udelay(10);
171
+
172
+
rk_clrreg(&dram_info->cru->cru_softrst_con[5],
173
+
1 << DDRCTRL_PSRST_SHIFT |
174
+
1 << DDRCTRL_SRST_SHIFT);
175
+
udelay(10);
176
+
177
+
phy_softreset(dram_info);
178
+
}
179
+
180
+
void pctl_copy_to_reg(unsigned int *dest, const unsigned short *src,
181
+
unsigned int n)
182
+
{
183
+
unsigned int i;
184
+
185
+
for (i = 0; i < n / sizeof(unsigned short); i++) {
186
+
writel_relaxed(*src, dest);
187
+
src++;
188
+
dest++;
189
+
}
190
+
}
191
+
192
+
static void move_to_access_state(struct dram_info *dram_info)
193
+
{
194
+
struct rk3128_ddr_pctl *pctl = dram_info->pctl;
195
+
unsigned int state;
196
+
197
+
while (1) {
198
+
state = readl(&pctl->stat) & PCTL_STAT_MASK;
199
+
switch (state) {
200
+
case LOW_POWER:
201
+
writel(WAKEUP_STATE, &pctl->sctl);
202
+
while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS)
203
+
;
204
+
break;
205
+
case INIT_MEM:
206
+
writel(CFG_STATE, &pctl->sctl);
207
+
while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG)
208
+
;
209
+
fallthrough;
210
+
case CONFIG:
211
+
writel(GO_STATE, &pctl->sctl);
212
+
while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS)
213
+
;
214
+
break;
215
+
case ACCESS:
216
+
return;
217
+
default:
218
+
break;
219
+
}
220
+
}
221
+
}
222
+
223
+
static void move_to_config_state(struct dram_info *dram_info)
224
+
{
225
+
struct rk3128_ddr_pctl *pctl = dram_info->pctl;
226
+
unsigned int state;
227
+
228
+
while (1) {
229
+
state = readl(&pctl->stat) & PCTL_STAT_MASK;
230
+
switch (state) {
231
+
case LOW_POWER:
232
+
writel(WAKEUP_STATE, &pctl->sctl);
233
+
while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS)
234
+
;
235
+
fallthrough;
236
+
case ACCESS:
237
+
fallthrough;
238
+
case INIT_MEM:
239
+
writel(CFG_STATE, &pctl->sctl);
240
+
while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG)
241
+
;
242
+
break;
243
+
case CONFIG:
244
+
return;
245
+
default:
246
+
break;
247
+
}
248
+
}
249
+
}
250
+
251
+
static void move_to_lowpower_state(struct dram_info *dram_info)
252
+
{
253
+
struct rk3128_ddr_pctl *pctl = dram_info->pctl;
254
+
unsigned int state;
255
+
256
+
while (1) {
257
+
state = readl(&pctl->stat) & PCTL_STAT_MASK;
258
+
switch (state) {
259
+
case INIT_MEM:
260
+
writel(CFG_STATE, &pctl->sctl);
261
+
while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG)
262
+
;
263
+
fallthrough;
264
+
case CONFIG:
265
+
writel(GO_STATE, &pctl->sctl);
266
+
while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS)
267
+
;
268
+
fallthrough;
269
+
case ACCESS:
270
+
writel(SLEEP_STATE, &pctl->sctl);
271
+
while ((readl(&pctl->stat) & PCTL_STAT_MASK) != LOW_POWER)
272
+
;
273
+
break;
274
+
case LOW_POWER:
275
+
return;
276
+
default:
277
+
break;
278
+
}
279
+
}
280
+
}
281
+
282
+
static void send_command(struct rk3128_ddr_pctl *pctl,
283
+
unsigned int rank, unsigned int cmd, unsigned int arg)
284
+
{
285
+
writel((START_CMD | (rank << RANK_SEL_SHIFT) | arg | cmd), &pctl->mcmd);
286
+
udelay(1);
287
+
while (readl(&pctl->mcmd) & START_CMD)
288
+
;
289
+
}
290
+
291
+
static void set_bw(struct dram_info *dram_info, unsigned int bw)
292
+
{
293
+
struct rk3128_ddr_pctl *pctl = dram_info->pctl;
294
+
struct rk3128_grf *grf = dram_info->grf;
295
+
296
+
if (bw == 1) {
297
+
clrsetbits_le32(&pctl->ppcfg, PPMEM_EN_MASK, PPMEM_EN);
298
+
clrsetbits_le32(PHY_REG(dram_info->phy_base, 0x00),
299
+
CHANNEL_SELECT_MASK,
300
+
CHANNEL_SELECT_DQ_16_BIT);
301
+
rk_clrsetreg(&grf->soc_con0, DDR_8_BIT_SEL | DDR_16_BIT_SEL,
302
+
DDR_16_BIT_SEL);
303
+
clrbits_le32(PHY_REG(dram_info->phy_base, 0x46), DQ_DLL_ENABLE);
304
+
clrbits_le32(PHY_REG(dram_info->phy_base, 0x56), DQ_DLL_ENABLE);
305
+
} else {
306
+
clrbits_le32(&pctl->ppcfg, PPMEM_EN);
307
+
clrsetbits_le32(PHY_REG(dram_info->phy_base, 0x00),
308
+
CHANNEL_SELECT_MASK,
309
+
CHANNEL_SELECT_DQ_32_BIT);
310
+
rk_clrreg(&grf->soc_con0, DDR_16_BIT_SEL | DDR_8_BIT_SEL);
311
+
setbits_le32(PHY_REG(dram_info->phy_base, 0x46), DQ_DLL_ENABLE);
312
+
setbits_le32(PHY_REG(dram_info->phy_base, 0x56), DQ_DLL_ENABLE);
313
+
}
314
+
}
315
+
316
+
static void phy_drv_odt_set(struct dram_info *dram_info)
317
+
{
318
+
struct rk3128_ddr_timing *ddr_timing = dram_info->ddr_timing;
319
+
struct sdram_base_params *base = &ddr_timing->base;
320
+
unsigned int odt, i;
321
+
322
+
if (base->dramtype == DDR3)
323
+
odt = PHY_RTT_216OHM;
324
+
else
325
+
odt = PHY_RTT_DISABLE;
326
+
327
+
for (i = 0; i < NUM_DQS; i++)
328
+
clrsetbits_le32(PHY_REG(dram_info->phy_base, 0x21 + (i * 0x10)),
329
+
PHY_DRV_ODT_SET(PHY_RTT_MASK),
330
+
PHY_DRV_ODT_SET(odt));
331
+
}
332
+
333
+
static void phy_dll_set(struct dram_info *dram_info)
334
+
{
335
+
struct rk3128_ddr_timing *ddr_timing = dram_info->ddr_timing;
336
+
struct sdram_base_params *base = &ddr_timing->base;
337
+
unsigned int mask, value, i;
338
+
339
+
/* CMD DLL delay step */
340
+
clrsetbits_le32(PHY_REG(dram_info->phy_base, 0x13),
341
+
CMD_DLL_CLOCK_PHASE_MASK | CMD_DLL_MASK |
342
+
CMD_DLL_DELAY_MASK,
343
+
CMD_DLL_CLOCK_PHASE_180_DELAY | CMD_DLL_ENABLE |
344
+
CMD_DLL_DELAY_90);
345
+
346
+
/* CK DLL delay step */
347
+
clrsetbits_le32(PHY_REG(dram_info->phy_base, 0x14),
348
+
CK_DLL_DELAY_MASK | CK_DLL_CLOCK_PHASE_MASK,
349
+
CK_DLL_DELAY_NO_DELAY | CK_DLL_CLOCK_PHASE_NO_DELAY);
350
+
351
+
/* DM DQ DLL */
352
+
mask = DQ_DLL_DELAY_MASK | DQ_DLL_MASK | DQ_CLOCK_PHASE_MASK;
353
+
value = DQ_DLL_DELAY_90 | DQ_DLL_ENABLE | DQ_CLOCK_PHASE_180_DELAY;
354
+
for (i = 0; i < NUM_DQS; i++)
355
+
clrsetbits_le32(PHY_REG(dram_info->phy_base, 0x26 + (i * 0x10)),
356
+
mask, value);
357
+
358
+
/* TX DQS DLL */
359
+
mask = DQS_DLL_DELAY_MASK | DQS_DLL_CLOCK_PHASE_MASK;
360
+
value = DQS_DLL_DELAY_NO_DELAY | DQS_DLL_CLOCK_PHASE_NO_DELAY;
361
+
for (i = 0; i < NUM_DQS; i++)
362
+
clrsetbits_le32(PHY_REG(dram_info->phy_base, 0x27 + (i * 0x10)),
363
+
mask, value);
364
+
365
+
if (base->ddr_freq <= PHY_DLL_DISABLE_FREQ)
366
+
setbits_le32(PHY_REG(dram_info->phy_base, 0xa4),
367
+
RIGHT_CHN_B_TX_DQ_BYPASS_SET |
368
+
LEFT_CHN_B_TX_DQ_BYPASS_SET |
369
+
RIGHT_CHN_A_TX_DQ_BYPASS_SET |
370
+
LEFT_CHN_A_TX_DQ_BYPASS_SET |
371
+
CK_DLL_DLL_BYPASS_SET);
372
+
else
373
+
clrbits_le32(PHY_REG(dram_info->phy_base, 0xa4),
374
+
RIGHT_CHN_B_TX_DQ_BYPASS_SET |
375
+
LEFT_CHN_B_TX_DQ_BYPASS_SET |
376
+
RIGHT_CHN_A_TX_DQ_BYPASS_SET |
377
+
LEFT_CHN_A_TX_DQ_BYPASS_SET |
378
+
CK_DLL_DLL_BYPASS_SET);
379
+
380
+
/* read DQS delay phase */
381
+
mask = RX_DQS_DLL_DELAY_MASK;
382
+
if (base->ddr_freq < 350)
383
+
value = RX_DQS_DLL_DELAY_67P5;
384
+
else if (base->ddr_freq < 600)
385
+
value = RX_DQS_DLL_DELAY_45;
386
+
else
387
+
value = RX_DQS_DLL_DELAY_22P5;
388
+
389
+
for (i = 0; i < NUM_DQS; i++)
390
+
clrsetbits_le32(PHY_REG(dram_info->phy_base, 0x28 + (i * 0x10)),
391
+
mask, value);
392
+
}
393
+
394
+
static void phy_cfg(struct dram_info *dram_info)
395
+
{
396
+
struct rk3128_ddr_timing *ddr_timing = dram_info->ddr_timing;
397
+
struct rk3128_service_sys *axi_bus = dram_info->axi_bus;
398
+
struct sdram_base_params *base = &ddr_timing->base;
399
+
unsigned int i, burst_len =
400
+
((ddr_timing->noc_timing.burstlen << 1) == 4)
401
+
? PHY_BL_4 : PHY_BL_8;
402
+
403
+
writel(ddr_timing->noc_timing.noc_timing, &axi_bus->ddrtiming);
404
+
writel(READLATENCY, &axi_bus->readlatency);
405
+
406
+
if (base->dramtype == LPDDR2)
407
+
writel(MEMORY_SELECT_LPDDR2 | burst_len,
408
+
PHY_REG(dram_info->phy_base, 0x01));
409
+
else
410
+
writel(MEMORY_SELECT_DDR3 | burst_len,
411
+
PHY_REG(dram_info->phy_base, 0x01));
412
+
413
+
writel(ddr_timing->phy_timing.cl_al,
414
+
PHY_REG(dram_info->phy_base, 0x0b));
415
+
writel(ddr_timing->pctl_timing.tcwl,
416
+
PHY_REG(dram_info->phy_base, 0x0c));
417
+
418
+
clrsetbits_le32(PHY_REG(dram_info->phy_base, 0x11),
419
+
PHY_DRV_ODT_SET(PHY_RON_MASK),
420
+
PHY_DRV_ODT_SET(PHY_CMD_DRV));
421
+
422
+
clrsetbits_le32(PHY_REG(dram_info->phy_base, 0x16),
423
+
PHY_DRV_ODT_SET(PHY_RON_MASK),
424
+
PHY_DRV_ODT_SET(PHY_CLK_DRV));
425
+
426
+
for (i = 0; i < NUM_DQS; i++)
427
+
clrsetbits_le32(PHY_REG(dram_info->phy_base, 0x20 + (i * 0x10)),
428
+
PHY_DRV_ODT_SET(PHY_RON_MASK),
429
+
PHY_DRV_ODT_SET(PHY_DQS_DRV));
430
+
431
+
phy_drv_odt_set(dram_info);
432
+
}
433
+
434
+
static int memory_init(struct dram_info *dram_info)
435
+
{
436
+
struct rk3128_ddr_pctl *pctl = dram_info->pctl;
437
+
struct rk3128_ddr_timing *ddr_timing = dram_info->ddr_timing;
438
+
unsigned int timeout = 1000;
439
+
440
+
writel(POWER_UP_START, &pctl->powctl);
441
+
while (timeout > 0) {
442
+
udelay(1);
443
+
if (readl(&pctl->powstat) & POWER_UP_DONE)
444
+
break;
445
+
timeout--;
446
+
}
447
+
448
+
if (timeout == 0) {
449
+
debug("PCTL failed to power up");
450
+
return -1;
451
+
}
452
+
453
+
if (IS_ENABLED(CONFIG_RAM_ROCKCHIP_LPDDR2)) {
454
+
send_command(pctl, RANK_SEL_CS0_CS1, MRS_CMD,
455
+
(63 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT |
456
+
(0 & LPDDR23_OP_MASK) <<
457
+
LPDDR23_OP_SHIFT);
458
+
459
+
udelay(10);
460
+
send_command(pctl, RANK_SEL_CS0, MRS_CMD,
461
+
(10 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT |
462
+
(0xff & LPDDR23_OP_MASK) <<
463
+
LPDDR23_OP_SHIFT);
464
+
465
+
udelay(1);
466
+
send_command(pctl, RANK_SEL_CS1, MRS_CMD,
467
+
(10 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT |
468
+
(0xff & LPDDR23_OP_MASK) <<
469
+
LPDDR23_OP_SHIFT);
470
+
471
+
udelay(1);
472
+
send_command(pctl, RANK_SEL_CS0_CS1, MRS_CMD,
473
+
(1 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT |
474
+
(ddr_timing->phy_timing.mr[1] &
475
+
LPDDR23_OP_MASK) << LPDDR23_OP_SHIFT);
476
+
477
+
send_command(pctl, RANK_SEL_CS0_CS1, MRS_CMD,
478
+
(2 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT |
479
+
(ddr_timing->phy_timing.mr[2] &
480
+
LPDDR23_OP_MASK) << LPDDR23_OP_SHIFT);
481
+
482
+
send_command(pctl, RANK_SEL_CS0_CS1, MRS_CMD,
483
+
(3 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT |
484
+
(ddr_timing->phy_timing.mr[3] &
485
+
LPDDR23_OP_MASK) << LPDDR23_OP_SHIFT);
486
+
} else {
487
+
send_command(pctl, RANK_SEL_CS0_CS1, DESELECT_CMD, 0);
488
+
udelay(1);
489
+
490
+
send_command(pctl, RANK_SEL_CS0_CS1, PREA_CMD, 0);
491
+
send_command(pctl, RANK_SEL_CS0_CS1, DESELECT_CMD, 0);
492
+
udelay(1);
493
+
494
+
send_command(pctl, RANK_SEL_CS0_CS1, MRS_CMD,
495
+
(MR2 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |
496
+
(ddr_timing->phy_timing.mr[2] & CMD_ADDR_MASK)
497
+
<< CMD_ADDR_SHIFT);
498
+
499
+
send_command(pctl, RANK_SEL_CS0_CS1, MRS_CMD,
500
+
(MR3 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |
501
+
(ddr_timing->phy_timing.mr[3] & CMD_ADDR_MASK)
502
+
<< CMD_ADDR_SHIFT);
503
+
504
+
send_command(pctl, RANK_SEL_CS0_CS1, MRS_CMD,
505
+
(MR1 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |
506
+
(ddr_timing->phy_timing.mr[1] & CMD_ADDR_MASK)
507
+
<< CMD_ADDR_SHIFT);
508
+
509
+
send_command(pctl, RANK_SEL_CS0_CS1, MRS_CMD,
510
+
(MR0 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |
511
+
(((ddr_timing->phy_timing.mr[0] | DDR3_DLL_RESET) &
512
+
CMD_ADDR_MASK) << CMD_ADDR_SHIFT));
513
+
514
+
send_command(pctl, RANK_SEL_CS0_CS1, ZQCL_CMD, 0);
515
+
}
516
+
517
+
return 0;
518
+
}
519
+
520
+
static int data_training(struct dram_info *dram_info)
521
+
{
522
+
struct rk3128_ddr_pctl *pctl = dram_info->pctl;
523
+
unsigned int trefi, ret, timeout = 100;
524
+
unsigned int bw =
525
+
readl(PHY_REG(dram_info->phy_base, 0x00)) & CHANNEL_SELECT_MASK;
526
+
527
+
/* disable auto refresh */
528
+
trefi = readl(&pctl->trefi);
529
+
writel(0, &pctl->trefi);
530
+
setbits_le32(PHY_REG(dram_info->phy_base, 0x02), DQS_SQU_CAL_START);
531
+
532
+
while (timeout > 0) {
533
+
udelay(1);
534
+
ret = readl(PHY_REG(dram_info->phy_base, 0xff));
535
+
if (bw == CHANNEL_SELECT_DQ_32_BIT &&
536
+
(ret & CHN_B_TRAINING_DONE_MASK) == CHN_B_TRAINING_DONE_MASK)
537
+
break;
538
+
else if (bw == CHANNEL_SELECT_DQ_16_BIT &&
539
+
(ret & CHN_A_TRAINING_DONE_MASK) == CHN_A_TRAINING_DONE_MASK)
540
+
break;
541
+
timeout--;
542
+
}
543
+
544
+
clrbits_le32(PHY_REG(dram_info->phy_base, 0x02), DQS_SQU_CAL_START);
545
+
546
+
/*
547
+
* since data training will take about 20us, so send some auto
548
+
* refresh(about 7.8us) to complement the lost time
549
+
*/
550
+
send_command(pctl, RANK_SEL_CS0_CS1, PREA_CMD, 0);
551
+
send_command(pctl, RANK_SEL_CS0_CS1, REF_CMD, 0);
552
+
553
+
writel(trefi, &pctl->trefi);
554
+
555
+
return timeout > 0 ? 0 : -1;
556
+
}
557
+
558
+
static void pctl_cfg(struct dram_info *dram_info)
559
+
{
560
+
struct rk3128_grf *grf = dram_info->grf;
561
+
struct rk3128_ddr_pctl *pctl = dram_info->pctl;
562
+
struct rk3128_ddr_timing *ddr_timing = dram_info->ddr_timing;
563
+
struct sdram_base_params *base = &dram_info->ddr_timing->base;
564
+
unsigned int burst_len = (ddr_timing->noc_timing.burstlen << 1);
565
+
566
+
setbits_le32(&pctl->dfistcfg0,
567
+
DFI_INIT_START | DFI_DATA_BYTE_DISABLE_EN);
568
+
setbits_le32(&pctl->dfistcfg1, DFI_DRAM_CLK_SR_EN);
569
+
setbits_le32(&pctl->dfistcfg2,
570
+
DFI_PARITY_INTR_EN | DFI_PARITY_EN);
571
+
572
+
writel(TPHYUPD_TYPE0, &pctl->dfitphyupdtype0);
573
+
writel(TPHY_RDLAT, &pctl->dfitphyrdlat);
574
+
writel(TPHY_WRDATA, &pctl->dfitphywrdata);
575
+
576
+
/* phyupd and ctrlupd disabled */
577
+
writel(DFI_PHYUPD_DISABLE | DFI_CTRLUPD_DISABLE, &pctl->dfiupdcfg);
578
+
579
+
pctl_copy_to_reg(&pctl->togcnt1u, &ddr_timing->pctl_timing.togcnt1u,
580
+
sizeof(struct rk3128_pctl_timing));
581
+
582
+
if (IS_ENABLED(CONFIG_RAM_ROCKCHIP_LPDDR2)) {
583
+
clrsetbits_le32(&pctl->trp,
584
+
TRP_PREA_EXTRA_MASK,
585
+
DIV_ROUND_UP(TRP_LPDDR2_8_BK * base->ddr_freq, 1000)
586
+
<< TRP_PREA_EXTRA_SHIFT);
587
+
588
+
setbits_le32(&pctl->dfistcfg1, DFI_DRAM_CLK_DPD_EN);
589
+
590
+
/* cs0 and cs1 write odt disable */
591
+
clrbits_le32(&pctl->dfiodtcfg,
592
+
RANK0_ODT_READ_SEL | RANK0_ODT_WRITE_SEL |
593
+
RANK1_ODT_READ_SEL | RANK1_ODT_WRITE_SEL);
594
+
595
+
/* disable odt write length */
596
+
clrbits_le32(&pctl->dfiodtcfg1,
597
+
ODT_LEN_BL8_W_MASK | ODT_LEN_BL8_R_MASK);
598
+
599
+
writel(MDDR_CLOCK_STOP_IDLE_DIS | LPDDR2_EN | LPDDR2_S4 |
600
+
(burst_len == 4 ? MDDR_LPDDR2_BL_4 : MDDR_LPDDR2_BL_8) |
601
+
TFAW_CFG_6_TDDR | PD_EXIT_FAST_EXIT_MODE |
602
+
PD_TYPE_ACT_PD | PD_IDLE_DISABLE,
603
+
&pctl->mcfg);
604
+
605
+
writel(DFI_LP_EN_PD | DFI_LP_EN_SR | DFI_TLP_RESP,
606
+
&pctl->dfilpcfg0);
607
+
608
+
writel((readl(&pctl->tcl) - 3), &pctl->dfitrddataen);
609
+
writel(readl(&pctl->tcwl), &pctl->dfitphywrlat);
610
+
611
+
rk_setreg(&grf->soc_con0, MOBILE_DDR_SEL);
612
+
rk_clrreg(&grf->soc_con2, MSCH4_MAINDDR3);
613
+
} else {
614
+
/* cs0 and cs1 write odt enable */
615
+
setbits_le32(&pctl->dfiodtcfg,
616
+
RANK0_ODT_READ_SEL | RANK0_ODT_WRITE_SEL |
617
+
RANK1_ODT_READ_SEL | RANK1_ODT_WRITE_SEL);
618
+
619
+
/* odt write length */
620
+
clrsetbits_le32(&pctl->dfiodtcfg1,
621
+
ODT_LEN_BL8_W_MASK | ODT_LEN_BL8_R_MASK,
622
+
ODT_LEN_BL8_W | ODT_LEN_BL8_R);
623
+
624
+
writel(MDDR_CLOCK_STOP_IDLE_DIS | DDR3_EN | MEM_BL_8 |
625
+
TFAW_CFG_5_TDDR | PD_EXIT_SLOW_EXIT_MODE |
626
+
PD_TYPE_ACT_PD | PD_IDLE_DISABLE, &pctl->mcfg);
627
+
628
+
writel(DFI_LP_EN_PD | DFI_LP_EN_SR | DFI_TLP_RESP,
629
+
&pctl->dfilpcfg0);
630
+
631
+
writel((readl(&pctl->tcl) - 3), &pctl->dfitrddataen);
632
+
writel((readl(&pctl->tcwl) - 1), &pctl->dfitphywrlat);
633
+
634
+
rk_clrreg(&grf->soc_con0, MOBILE_DDR_SEL);
635
+
rk_setreg(&grf->soc_con2, MSCH4_MAINDDR3);
636
+
}
637
+
638
+
setbits_le32(&pctl->scfg, HW_LOW_POWER_EN);
639
+
}
640
+
641
+
void pctl_cfg_trfc(struct dram_info *dram_info)
642
+
{
643
+
struct rk3128_ddr_pctl *pctl = dram_info->pctl;
644
+
struct sdram_base_params *base = &dram_info->ddr_timing->base;
645
+
struct sdram_cap_info *cap_info = &dram_info->cap_info;
646
+
unsigned int trfc, die_cap;
647
+
unsigned int cs0_cap =
648
+
(u32)sdram_get_cs_cap(cap_info, 0, base->dramtype);
649
+
650
+
die_cap = (cs0_cap >> (20 + (cap_info->bw - cap_info->dbw)));
651
+
if (IS_ENABLED(CONFIG_RAM_ROCKCHIP_LPDDR2)) {
652
+
unsigned int texsr, trefi = LPDDR2_TREFI_7_8_us;
653
+
trfc = LPDDR2_TRFC_512Mb;
654
+
655
+
if (die_cap > DIE_CAP_1GBIT)
656
+
trefi = LPDDR2_TREFI_3_9_us;
657
+
658
+
if (die_cap > DIE_CAP_512MBIT)
659
+
trfc = LPDDR2_TRFC_4Gb;
660
+
if (die_cap > DIE_CAP_4GBIT)
661
+
trfc = LPDDR2_TRFC_8Gb;
662
+
663
+
texsr = MAX(2, DIV_ROUND_UP(((trfc + 10) * base->ddr_freq), 1000));
664
+
writel(trefi, &pctl->trefi);
665
+
writel(texsr, &pctl->texsr);
666
+
667
+
} else {
668
+
if (die_cap <= DIE_CAP_512MBIT)
669
+
trfc = DDR3_TRFC_512Mb;
670
+
else if (die_cap <= DIE_CAP_1GBIT)
671
+
trfc = DDR3_TRFC_1Gb;
672
+
else if (die_cap <= DIE_CAP_2GBIT)
673
+
trfc = DDR3_TRFC_2Gb;
674
+
else if (die_cap <= DIE_CAP_4GBIT)
675
+
trfc = DDR3_TRFC_4Gb;
676
+
else
677
+
trfc = DDR3_TRFC_8Gb;
678
+
}
679
+
680
+
trfc = DIV_ROUND_UP((trfc * base->ddr_freq), 1000);
681
+
writel(trfc, &pctl->trfc);
682
+
}
683
+
684
+
void dram_cfg_rbc(struct dram_info *dram_info)
685
+
{
686
+
struct rk3128_service_sys *axi_bus = dram_info->axi_bus;
687
+
struct sdram_cap_info *cap_info = &dram_info->cap_info;
688
+
char noc_config;
689
+
int i = 0;
690
+
691
+
move_to_config_state(dram_info);
692
+
693
+
if (cap_info->rank == 2 && cap_info->cs1_row == cap_info->cs0_row) {
694
+
if (cap_info->col + cap_info->bw == 12) {
695
+
i = 14;
696
+
goto finish;
697
+
} else if (cap_info->col + cap_info->bw == 11) {
698
+
i = 15;
699
+
goto finish;
700
+
}
701
+
}
702
+
noc_config = ((cap_info->cs0_row - 13) << 4) | ((cap_info->bk - 2) << 2) |
703
+
(cap_info->col + cap_info->bw - 11);
704
+
for (i = 0; i < 11; i++) {
705
+
if (noc_config == ddr_cfg_2_rbc[i])
706
+
break;
707
+
}
708
+
709
+
if (i < 11)
710
+
goto finish;
711
+
712
+
noc_config = ((cap_info->bk - 2) << 6) | ((cap_info->cs0_row - 13) << 4) |
713
+
(cap_info->col + cap_info->bw - 11);
714
+
715
+
for (i = 11; i < 14; i++) {
716
+
if (noc_config == ddr_cfg_2_rbc[i])
717
+
break;
718
+
}
719
+
if (i < 14)
720
+
goto finish;
721
+
else
722
+
i = 0;
723
+
724
+
finish:
725
+
writel(i, &axi_bus->ddrconf);
726
+
move_to_access_state(dram_info);
727
+
}
728
+
729
+
static int detect_bw(struct dram_info *dram_info)
730
+
{
731
+
struct sdram_cap_info *cap_info = &dram_info->cap_info;
732
+
733
+
set_bw(dram_info, 2);
734
+
if (data_training(dram_info) == 0) {
735
+
cap_info->bw = 2;
736
+
} else {
737
+
set_bw(dram_info, 1);
738
+
move_to_lowpower_state(dram_info);
739
+
phy_softreset(dram_info);
740
+
move_to_config_state(dram_info);
741
+
if (data_training(dram_info)) {
742
+
debug("Failed to detect bandwidth");
743
+
return -1;
744
+
}
745
+
cap_info->bw = 1;
746
+
}
747
+
748
+
return 0;
749
+
}
750
+
751
+
static void detect_rank(struct dram_info *dram_info)
752
+
{
753
+
struct sdram_cap_info *cap_info = &dram_info->cap_info;
754
+
755
+
writel(0, CFG_SYS_SDRAM_BASE);
756
+
writel(PATTERN, CFG_SYS_SDRAM_BASE + (1u << 30));
757
+
writel(~PATTERN, CFG_SYS_SDRAM_BASE + (1u << 30) + 4);
758
+
759
+
if ((readl(CFG_SYS_SDRAM_BASE + (1u << 30)) == PATTERN) &&
760
+
(readl(CFG_SYS_SDRAM_BASE) == 0))
761
+
cap_info->rank = 2;
762
+
else
763
+
cap_info->rank = 1;
764
+
}
765
+
766
+
static int detect_cap(struct dram_info *dram_info)
767
+
{
768
+
struct rk3128_service_sys *axi_bus = dram_info->axi_bus;
769
+
struct rk3128_ddr_timing *ddr_timing = dram_info->ddr_timing;
770
+
struct sdram_cap_info *cap_info = &dram_info->cap_info;
771
+
struct sdram_base_params *base = &ddr_timing->base;
772
+
int ret = 0;
773
+
unsigned int coltmp, rowtmp = 16, bktmp = 3;
774
+
775
+
ret = detect_bw(dram_info);
776
+
if (ret)
777
+
goto out;
778
+
779
+
move_to_config_state(dram_info);
780
+
if (cap_info->bw == 2) {
781
+
writel(6, &axi_bus->ddrconf);
782
+
coltmp = 11;
783
+
} else {
784
+
writel(3, &axi_bus->ddrconf);
785
+
coltmp = 10;
786
+
};
787
+
788
+
move_to_access_state(dram_info);
789
+
if (sdram_detect_col(cap_info, coltmp) != 0) {
790
+
ret = -1;
791
+
goto out;
792
+
}
793
+
sdram_detect_bank(cap_info, coltmp, bktmp);
794
+
795
+
move_to_config_state(dram_info);
796
+
797
+
writel(10, &axi_bus->ddrconf);
798
+
799
+
move_to_access_state(dram_info);
800
+
801
+
detect_rank(dram_info);
802
+
803
+
coltmp = cap_info->bw == 1 ? 10 : 9;
804
+
if (sdram_detect_row(cap_info, coltmp, bktmp, rowtmp) != 0) {
805
+
ret = -1;
806
+
goto out;
807
+
}
808
+
809
+
// assume cs1_row == cs0_row
810
+
if (cap_info->rank > 1)
811
+
cap_info->cs1_row = cap_info->cs0_row;
812
+
813
+
sdram_detect_dbw(cap_info, base->dramtype);
814
+
815
+
move_to_config_state(dram_info);
816
+
// re-configure trfc/trefi based on actual per die capacity
817
+
pctl_cfg_trfc(dram_info);
818
+
move_to_access_state(dram_info);
819
+
820
+
sdram_print_ddr_info(cap_info, base, 0);
821
+
822
+
out:
823
+
return ret;
824
+
}
825
+
826
+
static void sdram_all_config(struct dram_info *dram_info)
827
+
{
828
+
struct rk3128_ddr_timing *ddr_timing = dram_info->ddr_timing;
829
+
struct rk3128_grf *grf = dram_info->grf;
830
+
struct sdram_base_params *base = &ddr_timing->base;
831
+
struct sdram_cap_info *cap_info = &dram_info->cap_info;
832
+
unsigned int sys_reg2 = 0;
833
+
unsigned int sys_reg3 = 0;
834
+
835
+
sdram_org_config(cap_info, base, &sys_reg2, &sys_reg3, 0);
836
+
writel(sys_reg2, &grf->os_reg[1]);
837
+
writel(sys_reg3, &grf->os_reg[2]);
838
+
}
839
+
840
+
int rk3128_sdram_init(enum rk3128_dram_config dram_config)
841
+
{
842
+
struct dram_info dram_info;
843
+
struct rk3128_ddr_timing *ddr_timing = &rk3128_ddr_timings[dram_config];
844
+
struct sdram_base_params *base = &ddr_timing->base;
845
+
846
+
debug("\nIn\n");
847
+
848
+
if (base->dramtype != DDR3 && base->dramtype != LPDDR2) {
849
+
printascii("\nOnly DDR3 and LPDDR2 are supported.\n");
850
+
return -1;
851
+
}
852
+
853
+
dram_info.axi_bus = (void __iomem *)CPU_AXI_BUS_BASE;
854
+
dram_info.ddr_timing = ddr_timing;
855
+
dram_info.cru = (void __iomem *)CRU_BASE;
856
+
dram_info.grf = (void __iomem *)GRF_BASE;
857
+
dram_info.pctl = (void __iomem *)DDR_PCTL_BASE;
858
+
dram_info.phy_base = (void __iomem *)DDR_PHY_BASE;
859
+
860
+
if (rkclk_set_dpll(&dram_info))
861
+
return -1;
862
+
863
+
phy_pctrl_reset(&dram_info);
864
+
865
+
phy_dll_set(&dram_info);
866
+
867
+
pctl_cfg(&dram_info);
868
+
869
+
phy_cfg(&dram_info);
870
+
871
+
if (memory_init(&dram_info))
872
+
return -1;
873
+
874
+
if (detect_cap(&dram_info))
875
+
return -1;
876
+
877
+
dram_cfg_rbc(&dram_info);
878
+
879
+
sdram_all_config(&dram_info);
880
+
881
+
/* set vio/vip axi qos to max priority */
882
+
writel(QOS_PRIORITY(3), AXI_VIO_QOS_PRIO);
883
+
writel(QOS_PRIORITY(3), AXI_VIP_QOS_PRIO);
884
+
885
+
if (!IS_ENABLED(CONFIG_RAM_ROCKCHIP_DEBUG)) {
886
+
struct sdram_cap_info *cap_info = &dram_info.cap_info;
887
+
888
+
if (IS_ENABLED(CONFIG_RAM_ROCKCHIP_LPDDR2))
889
+
printascii("\nLPDRR2, ");
890
+
else
891
+
printascii("\nDDR3, ");
892
+
printdec(base->ddr_freq);
893
+
printascii(" MHz, ");
894
+
printdec((sdram_get_cs_cap(cap_info, 3, base->dramtype) >> 20));
895
+
printascii("MB\n");
896
+
}
897
+
898
+
debug("\nOut\n");
899
+
900
+
return 0;
901
+
}
902
+
#else
20
903
static int rk3128_dmc_probe(struct udevice *dev)
21
904
{
22
905
struct dram_info *priv = dev_get_priv(dev);
···
56
939
.probe = rk3128_dmc_probe,
57
940
.priv_auto = sizeof(struct dram_info),
58
941
};
942
+
#endif