"Das U-Boot" Source Tree
Merge tag 'xilinx-for-v2026.04-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next
AMD/Xilinx/FPGA changes for v2026.04-rc1
xilinx:
- Sync ESRT with detected GUID
- DT cleanups
- Add logic for FRU information multiple times
- Enable more drivers pca9541, usb5744
- Enable more commands
- Cleanup firmware DT bindings
firmware:
- Add enhancement SMC format support
clk/versal:
- Various cleanups
- Add support for Versal Gen 2
i2c:
- cdns: Add timeout for RXDV status bit polling
spi:
- cadence: Remove cdns,is-dma DT property
- cadence: Remove duplicated return
- cadence_versal: Update flash reset delay
memtop:
- Update max memory reserved spaces to 64
Versal Gen 2:
- Aligned addresses with default memory map
- Add support for reading multiboot value
MB-V:
- Make SPL smaller
- Add support for SPI
- Move SPL to run out of BRAM
ZynqMP:
- Change default load address for BL32
+188
-106
+1
-2
arch/arm/dts/versal-mini-ospi.dtsi
+1
-2
arch/arm/dts/versal-mini-ospi.dtsi
···
29
29
};
30
30
31
31
ospi: spi@f1010000 {
32
-
compatible = "cdns,qspi-nor";
32
+
compatible = "xlnx,versal-ospi-1.0", "cdns,qspi-nor";
33
33
status = "okay";
34
34
reg = <0 0xf1010000 0 0x10000 0 0xc0000000 0 0x20000000>;
35
35
clock-names = "ref_clk", "pclk";
···
38
38
num-cs = <1>;
39
39
cdns,fifo-depth = <256>;
40
40
cdns,fifo-width = <4>;
41
-
cdns,is-dma = <1>;
42
41
cdns,trigger-address = <0xc0000000>;
43
42
#address-cells = <1>;
44
43
#size-cells = <0>;
+1
-2
arch/arm/dts/versal-net-mini-ospi.dtsi
+1
-2
arch/arm/dts/versal-net-mini-ospi.dtsi
···
43
43
};
44
44
45
45
ospi: spi@f1010000 {
46
-
compatible = "cdns,qspi-nor";
46
+
compatible = "xlnx,versal-ospi-1.0", "cdns,qspi-nor";
47
47
status = "okay";
48
48
reg = <0 0xf1010000 0 0x10000>, <0 0xc0000000 0 0x20000000>;
49
49
clock-names = "ref_clk", "pclk";
···
52
52
num-cs = <1>;
53
53
cdns,fifo-depth = <256>;
54
54
cdns,fifo-width = <4>;
55
-
cdns,is-dma = <1>;
56
55
cdns,is-stig-pgm = <1>;
57
56
cdns,trigger-address = <0xc0000000>;
58
57
#address-cells = <1>;
-3
arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso
-3
arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso
+3
-1
arch/arm/mach-versal2/include/mach/hardware.h
+3
-1
arch/arm/mach-versal2/include/mach/hardware.h
···
1
1
/* SPDX-License-Identifier: GPL-2.0 */
2
2
/*
3
3
* Copyright (C) 2016 - 2022, Xilinx, Inc.
4
-
* Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc.
4
+
* Copyright (C) 2022 - 2025, Advanced Micro Devices, Inc.
5
5
*/
6
6
7
7
#ifndef __ASSEMBLY__
···
73
73
#define JTAG_MODE 0x00000000
74
74
#define BOOT_MODE_USE_ALT 0x100
75
75
#define BOOT_MODE_ALT_SHIFT 12
76
+
#define PMC_MULTI_BOOT_REG 0xF1110004
77
+
#define PMC_MULTI_BOOT_MASK 0x1FFF
76
78
77
79
enum versal2_platform {
78
80
VERSAL2_SILICON = 0,
+1
-1
arch/arm/mach-zynqmp/Kconfig
+1
-1
arch/arm/mach-zynqmp/Kconfig
···
138
138
139
139
config BL32_LOAD_ADDR
140
140
hex "Load address of BL32 image (mostly secure OS)"
141
-
default 0
141
+
default 0x60000000
142
142
help
143
143
The load address for the BL32 image. This value is used to build the
144
144
FIT image header that places BL32 in memory where it will run.
+22
board/amd/versal2/board.c
+22
board/amd/versal2/board.c
···
21
21
#include <dm/device.h>
22
22
#include <dm/uclass.h>
23
23
#include <versalpl.h>
24
+
#include <zynqmp_firmware.h>
24
25
#include "../../xilinx/common/board.h"
25
26
26
27
#include <linux/bitfield.h>
···
180
181
return bootmode;
181
182
}
182
183
184
+
static u32 versal2_multi_boot(void)
185
+
{
186
+
u8 bootmode = versal2_get_bootmode();
187
+
u32 reg = 0;
188
+
189
+
/* Mostly workaround for QEMU CI pipeline */
190
+
if (bootmode == JTAG_MODE)
191
+
return 0;
192
+
193
+
if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) && current_el() != 3)
194
+
reg = zynqmp_pm_get_pmc_multi_boot_reg();
195
+
else
196
+
reg = readl(PMC_MULTI_BOOT_REG);
197
+
198
+
return reg & PMC_MULTI_BOOT_MASK;
199
+
}
200
+
183
201
static int boot_targets_setup(void)
184
202
{
185
203
u8 bootmode;
···
319
337
int board_late_init(void)
320
338
{
321
339
int ret;
340
+
u32 multiboot;
322
341
323
342
if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
324
343
debug("Saved variables - Skipping\n");
···
327
346
328
347
if (!IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG))
329
348
return 0;
349
+
350
+
multiboot = versal2_multi_boot();
351
+
env_set_hex("multiboot", multiboot);
330
352
331
353
if (IS_ENABLED(CONFIG_DISTRO_DEFAULTS)) {
332
354
ret = boot_targets_setup();
+21
-2
board/xilinx/common/board.c
+21
-2
board/xilinx/common/board.c
···
70
70
#define EEPROM_HDR_ETH_ALEN ETH_ALEN
71
71
#define EEPROM_HDR_UUID_LEN 16
72
72
73
+
#define EEPROM_FRU_READ_RETRY 5
74
+
73
75
struct xilinx_board_description {
74
76
u32 header;
75
77
char manufacturer[EEPROM_HDR_MANUFACTURER_LEN + 1];
···
207
209
debug("%s: I2C EEPROM read pass data at %p\n", __func__,
208
210
fru_content);
209
211
210
-
ret = dm_i2c_read(dev, 0, (uchar *)fru_content,
211
-
eeprom_size);
212
+
i = 0;
213
+
do {
214
+
ret = dm_i2c_read(dev, 0, (uchar *)fru_content,
215
+
eeprom_size);
216
+
if (!ret)
217
+
break;
218
+
} while (++i < EEPROM_FRU_READ_RETRY && ret == -ETIMEDOUT);
219
+
212
220
if (ret) {
213
221
debug("%s: I2C EEPROM read failed\n", __func__);
214
222
goto end;
···
765
773
766
774
/* Copy image type GUID */
767
775
memcpy(&fw_images[0].image_type_id, &img_entry->image_type_guid, 16);
776
+
777
+
if (IS_ENABLED(CONFIG_EFI_ESRT)) {
778
+
efi_status_t ret;
779
+
780
+
/* Rebuild the ESRT to reflect any updated FW images. */
781
+
ret = efi_esrt_populate();
782
+
if (ret != EFI_SUCCESS) {
783
+
log_warning("ESRT update failed\n");
784
+
return ret;
785
+
}
786
+
}
768
787
769
788
return 0;
770
789
}
+10
-4
board/xilinx/mbv/board.c
+10
-4
board/xilinx/mbv/board.c
···
1
1
// SPDX-License-Identifier: GPL-2.0+
2
2
/*
3
-
* (C) Copyright 2023, Advanced Micro Devices, Inc.
3
+
* (C) Copyright 2023-2025, Advanced Micro Devices, Inc.
4
4
*
5
5
* Michal Simek <michal.simek@amd.com>
6
6
*/
···
8
8
#include <spl.h>
9
9
10
10
#ifdef CONFIG_SPL
11
-
u32 spl_boot_device(void)
11
+
void board_boot_order(u32 *spl_boot_list)
12
12
{
13
-
/* RISC-V QEMU only supports RAM as SPL boot device */
14
-
return BOOT_DEVICE_RAM;
13
+
u32 i = 0;
14
+
15
+
if (CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT))
16
+
spl_boot_list[i++] = BOOT_DEVICE_SPI;
17
+
18
+
if (CONFIG_IS_ENABLED(RAM_SUPPORT))
19
+
spl_boot_list[i++] = BOOT_DEVICE_RAM;
20
+
15
21
}
16
22
#endif
+1
-1
common/memtop.c
+1
-1
common/memtop.c
+5
configs/amd_versal2_virt_defconfig
+5
configs/amd_versal2_virt_defconfig
···
11
11
CONFIG_DM_RESET=y
12
12
CONFIG_SYS_BOOTM_LEN=0x6400000
13
13
CONFIG_SYS_LOAD_ADDR=0x8000000
14
+
CONFIG_XILINX_OF_BOARD_DTB_ADDR=0x1000000
14
15
CONFIG_CMD_FRU=y
15
16
CONFIG_SYS_MEMTEST_START=0x00000000
16
17
CONFIG_SYS_MEMTEST_END=0x00001000
···
75
76
CONFIG_SIMPLE_PM_BUS=y
76
77
CONFIG_CLK_CCF=y
77
78
CONFIG_CLK_SCMI=y
79
+
CONFIG_CLK_VERSAL=y
78
80
CONFIG_DFU_RAM=y
79
81
CONFIG_ARM_FFA_TRANSPORT=y
80
82
CONFIG_FPGA_XILINX=y
···
82
84
CONFIG_DM_I2C=y
83
85
CONFIG_SYS_I2C_CADENCE=y
84
86
CONFIG_I2C_MUX=y
87
+
CONFIG_I2C_MUX_PCA9541=y
85
88
CONFIG_I2C_MUX_PCA954x=y
86
89
CONFIG_DM_MAILBOX=y
87
90
CONFIG_ZYNQMP_IPI=y
···
136
139
CONFIG_ZYNQMP_GQSPI=y
137
140
CONFIG_SPI_STACKED_PARALLEL=y
138
141
CONFIG_SYSRESET=y
142
+
CONFIG_SYSRESET_CMD_POWEROFF=y
139
143
CONFIG_SYSRESET_PSCI=y
140
144
CONFIG_TEE=y
141
145
CONFIG_OPTEE=y
···
147
151
CONFIG_USB_DWC3=y
148
152
CONFIG_USB_DWC3_GENERIC=y
149
153
CONFIG_USB_ULPI=y
154
+
CONFIG_USB_ONBOARD_HUB=y
150
155
CONFIG_USB_GADGET=y
151
156
CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
152
157
CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
+9
-10
configs/xilinx_mbv32_defconfig
+9
-10
configs/xilinx_mbv32_defconfig
···
6
6
CONFIG_ENV_SIZE=0x20000
7
7
CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32"
8
8
CONFIG_SPL_STACK=0x80200000
9
-
CONFIG_SPL_BSS_START_ADDR=0x84000000
10
-
CONFIG_SPL_BSS_MAX_SIZE=0x80000
9
+
CONFIG_SPL_TEXT_BASE=0x0
10
+
CONFIG_SPL_BSS_START_ADDR=0xf000
11
+
CONFIG_SPL_BSS_MAX_SIZE=0x1000
11
12
CONFIG_SYS_BOOTM_LEN=0x800000
12
13
CONFIG_SYS_LOAD_ADDR=0x80200000
13
-
CONFIG_SPL_SIZE_LIMIT=0x40000
14
+
CONFIG_SPL_SIZE_LIMIT=0x10000
14
15
CONFIG_SPL=y
15
-
CONFIG_DEBUG_UART_BASE=0x40600000
16
-
CONFIG_DEBUG_UART_CLOCK=100000000
17
16
CONFIG_SYS_CLK_FREQ=100000000
18
17
CONFIG_BOOT_SCRIPT_OFFSET=0x0
19
-
CONFIG_DEBUG_UART=y
20
18
CONFIG_TARGET_XILINX_MBV=y
19
+
# CONFIG_RISCV_ISA_F is not set
21
20
# CONFIG_SPL_SMP is not set
22
21
CONFIG_REMAKE_ELF=y
23
22
CONFIG_FIT=y
···
27
26
CONFIG_DISPLAY_BOARDINFO=y
28
27
# CONFIG_BOARD_INIT is not set
29
28
# CONFIG_BOARD_LATE_INIT is not set
30
-
CONFIG_SPL_MAX_SIZE=0x40000
29
+
CONFIG_SPL_MAX_SIZE=0xf000
31
30
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
32
31
CONFIG_SPL_HAVE_INIT_STACK=y
33
32
CONFIG_SPL_SYS_MALLOC=y
33
+
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
34
+
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80000000
35
+
CONFIG_SPL_SYS_MALLOC_SIZE=0x200000
34
36
# CONFIG_CMD_MII is not set
35
37
CONFIG_CMD_SNTP=y
36
38
CONFIG_CMD_TIMER=y
···
39
41
CONFIG_DM_MTD=y
40
42
CONFIG_DM_RTC=y
41
43
CONFIG_RTC_EMULATION=y
42
-
CONFIG_DEBUG_UART_ANNOUNCE=y
43
-
CONFIG_DEBUG_UART_SKIP_INIT=y
44
44
CONFIG_XILINX_UARTLITE=y
45
45
CONFIG_XILINX_TIMER=y
46
46
# CONFIG_BINMAN_FDT is not set
47
47
CONFIG_BINMAN_DTB="./arch/riscv/dts/xilinx-binman.dtb"
48
48
CONFIG_PANIC_HANG=y
49
-
CONFIG_SPL_GZIP=y
+1
configs/xilinx_versal_virt_defconfig
+1
configs/xilinx_versal_virt_defconfig
+1
configs/xilinx_zynqmp_virt_defconfig
+1
configs/xilinx_zynqmp_virt_defconfig
+1
-1
drivers/clk/Kconfig
+1
-1
drivers/clk/Kconfig
···
224
224
225
225
config CLK_VERSAL
226
226
bool "Enable clock driver support for Versal"
227
-
depends on (ARCH_VERSAL || ARCH_VERSAL_NET)
227
+
depends on (ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2)
228
228
depends on ZYNQMP_FIRMWARE
229
229
help
230
230
This clock driver adds support for clock realted settings for
+37
-12
drivers/clk/clk_versal.c
+37
-12
drivers/clk/clk_versal.c
···
106
106
struct versal_clock *clk;
107
107
};
108
108
109
-
static ulong pl_alt_ref_clk __section(".data");
110
-
static ulong ref_clk __section(".data");
109
+
static ulong __data pl_alt_ref_clk;
110
+
static ulong __data ref_clk;
111
111
112
112
struct versal_pm_query_data {
113
113
u32 qid;
···
116
116
u32 arg3;
117
117
};
118
118
119
-
static struct versal_clock *clock __section(".data");
120
-
static unsigned int clock_max_idx __section(".data");
119
+
static struct versal_clock __data *clock;
120
+
static unsigned int __data clock_max_idx;
121
121
122
122
#define PM_QUERY_DATA 35
123
123
···
134
134
qdata.arg3, 0, 0, ret_payload);
135
135
136
136
return qdata.qid == PM_QID_CLOCK_GET_NAME ? 0 : ret;
137
+
}
138
+
139
+
static int versal_pm_query_enhanced(struct versal_pm_query_data qdata,
140
+
u32 *ret_payload)
141
+
{
142
+
int ret;
143
+
144
+
ret = smc_call_handler(PM_QUERY_DATA, qdata.qid, qdata.arg1, qdata.arg2,
145
+
qdata.arg3, 0, 0, ret_payload);
146
+
147
+
if (qdata.qid == PM_QID_CLOCK_GET_NAME) {
148
+
ret_payload[0] = ret_payload[1];
149
+
ret_payload[1] = ret_payload[2];
150
+
ret_payload[2] = ret_payload[3];
151
+
ret_payload[3] = ret_payload[4];
152
+
ret_payload[4] = 0;
153
+
}
154
+
155
+
return ret;
137
156
}
138
157
139
158
static inline int versal_is_valid_clock(u32 clk_id)
···
712
731
static ulong versal_clk_get_rate(struct clk *clk)
713
732
{
714
733
struct versal_clk_priv *priv = dev_get_priv(clk->dev);
715
-
u32 id = clk->id;
734
+
u32 id = clk_get_id(clk);
716
735
u32 clk_id;
717
736
u64 clk_rate = 0;
718
737
719
-
debug("%s\n", __func__);
738
+
if (id >= clock_max_idx)
739
+
return -ENODEV;
720
740
721
741
clk_id = priv->clk[id].clk_id;
722
742
···
728
748
static ulong versal_clk_set_rate(struct clk *clk, ulong rate)
729
749
{
730
750
struct versal_clk_priv *priv = dev_get_priv(clk->dev);
731
-
u32 id = clk->id;
751
+
u32 id = clk_get_id(clk);
732
752
u32 clk_id;
733
753
u64 clk_rate = 0;
734
754
u32 div;
735
755
int ret;
736
756
737
-
debug("%s\n", __func__);
757
+
if (id >= clock_max_idx)
758
+
return -ENODEV;
738
759
739
760
clk_id = priv->clk[id].clk_id;
740
761
···
758
779
} while (((clk_id >> NODE_SUBCLASS_SHIFT) &
759
780
NODE_CLASS_MASK) != NODE_SUBCLASS_CLOCK_REF);
760
781
761
-
printf("Clock didn't has Divisors:0x%x\n", priv->clk[id].clk_id);
782
+
printf("Clock has no divider: 0x%x\n", clk_id);
762
783
763
784
return clk_rate;
764
785
}
···
766
787
static int versal_clk_enable(struct clk *clk)
767
788
{
768
789
struct versal_clk_priv *priv = dev_get_priv(clk->dev);
790
+
u32 id = clk_get_id(clk);
769
791
u32 clk_id;
770
792
771
-
clk_id = priv->clk[clk->id].clk_id;
793
+
if (id >= clock_max_idx)
794
+
return -ENODEV;
795
+
796
+
clk_id = priv->clk[id].clk_id;
772
797
773
-
if (versal_clock_gate(clk_id)) {
798
+
if (versal_clock_gate(clk_id))
774
799
return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0,
775
800
0, 0, NULL);
776
-
}
777
801
778
802
return 0;
779
803
}
···
789
813
790
814
static const struct udevice_id versal_clk_ids[] = {
791
815
{ .compatible = "xlnx,versal-clk", .data = (ulong)versal_pm_query_legacy },
816
+
{ .compatible = "xlnx,versal2-clk", .data = (ulong)versal_pm_query_enhanced },
792
817
{ }
793
818
};
794
819
+36
drivers/firmware/firmware-zynqmp.c
+36
drivers/firmware/firmware-zynqmp.c
···
16
16
#include <zynqmp_firmware.h>
17
17
#include <asm/cache.h>
18
18
#include <asm/ptrace.h>
19
+
#include <linux/bitfield.h>
19
20
20
21
#if defined(CONFIG_ZYNQMP_IPI)
21
22
#include <mailbox.h>
···
247
248
return ret_payload[1];
248
249
}
249
250
251
+
#if defined(CONFIG_ARCH_VERSAL) || defined(CONFIG_ARCH_VERSAL2)
250
252
u32 zynqmp_pm_get_pmc_multi_boot_reg(void)
251
253
{
252
254
int ret;
···
270
272
271
273
return ret_payload[1];
272
274
}
275
+
#endif
273
276
274
277
int zynqmp_pm_feature(const u32 api_id)
275
278
{
···
451
454
return (ret_payload) ? ret_payload[0] : 0;
452
455
}
453
456
457
+
static int smc_call_enhanced(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
458
+
u32 arg3, u32 arg4, u32 arg5, u32 *ret_payload)
459
+
{
460
+
struct pt_regs regs;
461
+
u32 module_id = FIELD_GET(PLM_MODULE_ID_MASK, api_id);
462
+
463
+
if (module_id == 0)
464
+
module_id = PM_MODULE_ID;
465
+
466
+
regs.regs[0] = PM_SIP_SVC | PASS_THROUGH_FW_CMD_ID;
467
+
regs.regs[1] = ((u64)arg0 << 32U) |
468
+
FIELD_PREP(PLM_MODULE_ID_MASK, module_id) |
469
+
(api_id & API_ID_MASK);
470
+
regs.regs[2] = arg1 | ((u64)arg2 << 32);
471
+
regs.regs[3] = arg3 | ((u64)arg4 << 32);
472
+
regs.regs[4] = arg5;
473
+
474
+
smc_call(®s);
475
+
476
+
if (ret_payload) {
477
+
ret_payload[0] = regs.regs[0];
478
+
ret_payload[1] = upper_32_bits(regs.regs[0]);
479
+
ret_payload[2] = (u32)regs.regs[1];
480
+
ret_payload[3] = upper_32_bits(regs.regs[1]);
481
+
ret_payload[4] = (u32)regs.regs[2];
482
+
ret_payload[5] = upper_32_bits((u32)regs.regs[2]);
483
+
ret_payload[6] = (u32)regs.regs[3];
484
+
}
485
+
486
+
return regs.regs[0];
487
+
}
488
+
454
489
int __maybe_unused xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
455
490
u32 arg3, u32 arg4, u32 arg5, u32 *ret_payload)
456
491
{
···
494
529
{ .compatible = "xlnx,zynqmp-firmware", .data = (ulong)smc_call_legacy },
495
530
{ .compatible = "xlnx,versal-firmware", .data = (ulong)smc_call_legacy},
496
531
{ .compatible = "xlnx,versal-net-firmware", .data = (ulong)smc_call_legacy },
532
+
{ .compatible = "xlnx,versal2-firmware", .data = (ulong)smc_call_enhanced},
497
533
{ }
498
534
};
499
535
+11
drivers/i2c/i2c-cdns.c
+11
drivers/i2c/i2c-cdns.c
···
85
85
86
86
#define CDNS_I2C_ARB_LOST_MAX_RETRIES 10
87
87
88
+
#define CDNS_I2C_RXDV_TIMEOUT_MS 1000
89
+
88
90
#ifdef DEBUG
89
91
static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c)
90
92
{
···
349
351
hold_quirk = (i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx;
350
352
351
353
while (recv_count && !is_arbitration_lost(regs)) {
354
+
int err = wait_for_bit_le32(®s->status, CDNS_I2C_STATUS_RXDV,
355
+
true, CDNS_I2C_RXDV_TIMEOUT_MS, false);
356
+
if (err)
357
+
return err;
358
+
352
359
while (readl(®s->status) & CDNS_I2C_STATUS_RXDV) {
353
360
if (recv_count < i2c_bus->fifo_depth &&
354
361
!i2c_bus->hold_flag) {
···
452
459
ret = cdns_i2c_write_data(i2c_bus, msg->addr, msg->buf,
453
460
msg->len);
454
461
}
462
+
463
+
if (ret == -ETIMEDOUT)
464
+
return ret;
465
+
455
466
if (ret == -EAGAIN) {
456
467
msg = message;
457
468
nmsgs = num_msgs;
+3
-4
drivers/spi/cadence_ospi_versal.c
+3
-4
drivers/spi/cadence_ospi_versal.c
···
15
15
#include <zynqmp_firmware.h>
16
16
#include <asm/arch/hardware.h>
17
17
#include "cadence_qspi.h"
18
-
#include <dt-bindings/power/xlnx-versal-power.h>
19
18
20
19
int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv,
21
20
const struct spi_mem_op *op)
···
178
177
179
178
/* Disable Tri-state */
180
179
writel((readl(BANK0_TRI) & ~BIT(FLASH_RESET_GPIO)), BANK0_TRI);
181
-
udelay(1);
180
+
udelay(5);
182
181
183
182
/* Set value 0 to pin */
184
183
writel((readl(BANK0_OUTPUT) & ~BIT(FLASH_RESET_GPIO)), BANK0_OUTPUT);
185
-
udelay(10);
184
+
udelay(150);
186
185
187
186
/* Set value 1 to pin */
188
187
writel((readl(BANK0_OUTPUT) | BIT(FLASH_RESET_GPIO)), BANK0_OUTPUT);
189
-
udelay(10);
188
+
udelay(1200);
190
189
191
190
return 0;
192
191
}
+16
-7
drivers/spi/cadence_qspi.c
+16
-7
drivers/spi/cadence_qspi.c
···
20
20
#include <linux/time.h>
21
21
#include <zynqmp_firmware.h>
22
22
#include "cadence_qspi.h"
23
-
#include <dt-bindings/power/xlnx-versal-power.h>
24
23
25
24
#define CQSPI_STIG_READ 0
26
25
#define CQSPI_STIG_WRITE 1
···
29
28
30
29
/* Quirks */
31
30
#define CQSPI_DISABLE_STIG_MODE BIT(0)
31
+
#define CQSPI_DMA_MODE BIT(1)
32
32
33
33
__weak int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv,
34
34
const struct spi_mem_op *op)
···
210
210
211
211
priv->regbase = plat->regbase;
212
212
priv->ahbbase = plat->ahbbase;
213
-
priv->is_dma = plat->is_dma;
214
213
priv->is_decoded_cs = plat->is_decoded_cs;
215
214
priv->fifo_depth = plat->fifo_depth;
216
215
priv->fifo_width = plat->fifo_width;
···
227
226
priv->tslch_ns = plat->tslch_ns;
228
227
priv->quirks = plat->quirks;
229
228
229
+
if (priv->quirks & CQSPI_DMA_MODE) {
230
+
priv->is_dma = true;
231
+
debug("Cadence QSPI: DMA mode enabled\n");
232
+
}
233
+
230
234
if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE))
231
235
xilinx_pm_request(PM_REQUEST_NODE, PM_DEV_OSPI,
232
236
ZYNQMP_PM_CAPABILITY_ACCESS, ZYNQMP_PM_MAX_QOS,
···
265
269
266
270
/* Reset ospi flash device */
267
271
return cadence_qspi_flash_reset(bus);
268
-
269
-
return 0;
270
272
}
271
273
272
274
static int cadence_spi_remove(struct udevice *dev)
···
411
413
/* Use DAC mode only when MMIO window is at least 8M wide */
412
414
if (plat->ahbsize >= SZ_8M)
413
415
priv->use_dac_mode = true;
414
-
415
-
plat->is_dma = dev_read_bool(bus, "cdns,is-dma");
416
416
417
417
/* All other parameters are embedded in the child node */
418
418
subnode = cadence_qspi_get_subnode(bus);
···
473
473
.quirks = CQSPI_DISABLE_STIG_MODE,
474
474
};
475
475
476
+
static const struct cqspi_driver_platdata cdns_xilinx_qspi = {
477
+
.quirks = CQSPI_DMA_MODE,
478
+
};
479
+
476
480
static const struct udevice_id cadence_spi_ids[] = {
477
481
{
478
482
.compatible = "cdns,qspi-nor",
···
482
486
.compatible = "ti,am654-ospi"
483
487
},
484
488
{
485
-
.compatible = "amd,versal2-ospi"
489
+
.compatible = "amd,versal2-ospi",
490
+
.data = (ulong)&cdns_xilinx_qspi,
491
+
},
492
+
{
493
+
.compatible = "xlnx,versal-ospi-1.0",
494
+
.data = (ulong)&cdns_xilinx_qspi,
486
495
},
487
496
{ }
488
497
};
-2
drivers/spi/cadence_qspi.h
-2
drivers/spi/cadence_qspi.h
-54
include/dt-bindings/power/xlnx-versal-power.h
-54
include/dt-bindings/power/xlnx-versal-power.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0 */
2
-
/*
3
-
* Copyright (C) 2019 - 2021 Xilinx, Inc.
4
-
*/
5
-
6
-
#ifndef _DT_BINDINGS_VERSAL_POWER_H
7
-
#define _DT_BINDINGS_VERSAL_POWER_H
8
-
9
-
#define PM_DEV_RPU0_0 (0x18110005U)
10
-
#define PM_DEV_RPU0_1 (0x18110006U)
11
-
#define PM_DEV_OCM_0 (0x18314007U)
12
-
#define PM_DEV_OCM_1 (0x18314008U)
13
-
#define PM_DEV_OCM_2 (0x18314009U)
14
-
#define PM_DEV_OCM_3 (0x1831400aU)
15
-
#define PM_DEV_TCM_0_A (0x1831800bU)
16
-
#define PM_DEV_TCM_0_B (0x1831800cU)
17
-
#define PM_DEV_TCM_1_A (0x1831800dU)
18
-
#define PM_DEV_TCM_1_B (0x1831800eU)
19
-
#define PM_DEV_USB_0 (0x18224018U)
20
-
#define PM_DEV_GEM_0 (0x18224019U)
21
-
#define PM_DEV_GEM_1 (0x1822401aU)
22
-
#define PM_DEV_SPI_0 (0x1822401bU)
23
-
#define PM_DEV_SPI_1 (0x1822401cU)
24
-
#define PM_DEV_I2C_0 (0x1822401dU)
25
-
#define PM_DEV_I2C_1 (0x1822401eU)
26
-
#define PM_DEV_CAN_FD_0 (0x1822401fU)
27
-
#define PM_DEV_CAN_FD_1 (0x18224020U)
28
-
#define PM_DEV_UART_0 (0x18224021U)
29
-
#define PM_DEV_UART_1 (0x18224022U)
30
-
#define PM_DEV_GPIO (0x18224023U)
31
-
#define PM_DEV_TTC_0 (0x18224024U)
32
-
#define PM_DEV_TTC_1 (0x18224025U)
33
-
#define PM_DEV_TTC_2 (0x18224026U)
34
-
#define PM_DEV_TTC_3 (0x18224027U)
35
-
#define PM_DEV_SWDT_FPD (0x18224029U)
36
-
#define PM_DEV_OSPI (0x1822402aU)
37
-
#define PM_DEV_QSPI (0x1822402bU)
38
-
#define PM_DEV_GPIO_PMC (0x1822402cU)
39
-
#define PM_DEV_I2C_PMC (0x1822402dU)
40
-
#define PM_DEV_SDIO_0 (0x1822402eU)
41
-
#define PM_DEV_SDIO_1 (0x1822402fU)
42
-
#define PM_DEV_RTC (0x18224034U)
43
-
#define PM_DEV_ADMA_0 (0x18224035U)
44
-
#define PM_DEV_ADMA_1 (0x18224036U)
45
-
#define PM_DEV_ADMA_2 (0x18224037U)
46
-
#define PM_DEV_ADMA_3 (0x18224038U)
47
-
#define PM_DEV_ADMA_4 (0x18224039U)
48
-
#define PM_DEV_ADMA_5 (0x1822403aU)
49
-
#define PM_DEV_ADMA_6 (0x1822403bU)
50
-
#define PM_DEV_ADMA_7 (0x1822403cU)
51
-
#define PM_DEV_AMS_ROOT (0x18224055U)
52
-
#define PM_DEV_AI (0x18224072U)
53
-
54
-
#endif
+8
include/zynqmp_firmware.h
+8
include/zynqmp_firmware.h
···
521
521
522
522
extern smc_call_handler_t __data smc_call_handler;
523
523
524
+
#define PM_MODULE_ID 2
525
+
526
+
#define PASS_THROUGH_FW_CMD_ID GENMASK(11, 0)
527
+
#define PLM_MODULE_ID_MASK GENMASK(15, 8)
528
+
#define API_ID_MASK GENMASK(7, 0)
529
+
530
+
#define PM_DEV_OSPI (0x1822402aU)
531
+
524
532
#endif /* _ZYNQMP_FIRMWARE_H_ */