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"Das U-Boot" Source Tree
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Merge tag 'v2026.01-rc4' into next

Prepare v2026.01-rc4

Tom Rini 59202e5a 8e12d6cc

+7926 -376
+4
.mailmap
··· 28 28 Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com> <appana.durga.rao@xilinx.com> 29 29 Ashok Reddy Soma <ashok.reddy.soma@amd.com> <ashok.reddy.soma@xilinx.com> 30 30 Atish Patra <atishp@atishpatra.org> <atish.patra@wdc.com> 31 + Bernhard Messerklinger <bernhard.messerklinger@at.abb.com> <bernhard.messerklinger@br-automation.com> 31 32 Bharat Kumar Gogada <bharat.kumar.gogada@amd.com> <bharat.kumar.gogada@xilinx.com> 32 33 Bharat Kumar Gogada <bharat.kumar.gogada@amd.com> <bharatku@xilinx.com> 33 34 Bhargava Sreekantappa Gayathri <bhargava.sreekantappa-gayathri@amd.com> <bhargava.sreekantappa-gayathri@xilinx.com> ··· 74 75 Kalyani Akula <kalyani.akula@amd.com> <kalyani.akula@xilinx.com> 75 76 Klaus Goger <klaus.goger@cherry.de> <klaus.goger@theobroma-systems.com> 76 77 Masahisa Kojima <kojima.masahisa@socionext.com> <masahisa.kojima@linaro.org> 78 + Linus Walleij <linusw@kernel.org> <linus.walleij@linaro.org> 77 79 Love Kumar <love.kumar@amd.com> <love.kumar@xilinx.com> 78 80 Lukasz Majewski <lukma@denx.de> 79 81 Marek Behún <kabel@kernel.org> <marek.behun@nic.cz> ··· 156 158 Wolfgang Denk <wd@denx.de> <wd@pollux.denx.de> 157 159 Wolfgang Denk <wd@denx.de> <wd@xpert.denx.de> 158 160 Wolfgang Denk <wd@denx.de> <wdenk> 161 + Wolfgang Wallner <wolfgang.wallner@at.abb.com> <wolfgang.wallner@br-automation.com> 162 + Yao Zi <me@ziyao.cc> <ziyao@disroot.org> 159 163 York Sun <york.sun@nxp.com> 160 164 York Sun <yorksun@freescale.com> 161 165 Łukasz Majewski <l.majewski@samsung.com>
+3 -4
MAINTAINERS
··· 820 820 821 821 ARM U8500 822 822 M: Stephan Gerhold <stephan@gerhold.net> 823 - R: Linus Walleij <linus.walleij@linaro.org> 823 + R: Linus Walleij <linusw@kernel.org> 824 824 S: Maintained 825 825 F: arch/arm/dts/ste-* 826 826 F: arch/arm/mach-u8500/ ··· 1039 1039 1040 1040 CLOCK 1041 1041 M: Lukasz Majewski <lukma@denx.de> 1042 - M: Sean Anderson <seanga2@gmail.com> 1043 1042 S: Maintained 1044 1043 T: git https://source.denx.de/u-boot/custodians/u-boot-clk.git 1045 1044 F: drivers/clk/ ··· 1617 1616 F: include/k210/ 1618 1617 1619 1618 RISC-V T-HEAD TH1520 1620 - M: Yao Zi <ziyao@disroot.org> 1619 + M: Yao Zi <me@ziyao.cc> 1621 1620 S: Maintained 1622 1621 F: arch/riscv/cpu/th1520/ 1623 1622 F: drivers/clk/thead/clk-th1520-ap.c ··· 1660 1659 N: scmi 1661 1660 1662 1661 SEAMA 1663 - M: Linus Walleij <linus.walleij@linaro.org> 1662 + M: Linus Walleij <linusw@kernel.org> 1664 1663 S: Maintained 1665 1664 F: cmd/seama.c 1666 1665 F: doc/usage/cmd/seama.rst
+10 -1
Makefile
··· 3 3 VERSION = 2026 4 4 PATCHLEVEL = 01 5 5 SUBLEVEL = 6 - EXTRAVERSION = -rc3 6 + EXTRAVERSION = -rc4 7 7 NAME = 8 8 9 9 # *DOCUMENTATION* ··· 1497 1497 # override the address back to make u-boot-elf.srec 1498 1498 # compatible with the recovery tools. 1499 1499 OBJCOPYFLAGS_u-boot-elf.srec += --change-addresses=0x50000000 1500 + endif 1501 + 1502 + ifeq ($(CONFIG_POSITION_INDEPENDENT)$(CONFIG_RCAR_GEN5),yy) 1503 + # The flash_writer tool and previous recovery tools 1504 + # require the SREC load address to be 0x8e30_0000 . 1505 + # The PIE U-Boot build sets the address to 0x0, so 1506 + # override the address back to make u-boot-elf.srec 1507 + # compatible with the recovery tools. 1508 + OBJCOPYFLAGS_u-boot-elf.srec += --change-addresses=0x8e300000 1500 1509 endif 1501 1510 1502 1511 u-boot-elf.srec: u-boot.elf FORCE
+5 -5
arch/arm/config.mk
··· 58 58 59 59 # Only test once 60 60 ifeq ($(CONFIG_$(PHASE_)SYS_THUMB_BUILD),y) 61 - archprepare: checkthumb checkgcc6 61 + archprepare: checkthumb checkgcc10 62 62 63 63 checkthumb: 64 64 @if test "$(call cc-name)" = "gcc" -a \ ··· 69 69 false; \ 70 70 fi 71 71 else 72 - archprepare: checkgcc6 72 + archprepare: checkgcc10 73 73 endif 74 74 75 - checkgcc6: 75 + checkgcc10: 76 76 @if test "$(call cc-name)" = "gcc" -a \ 77 - "$(call cc-version)" -lt "0600"; then \ 78 - echo '*** Your GCC is older than 6.0 and is not supported'; \ 77 + "$(call cc-version)" -lt "1000"; then \ 78 + echo '*** Your GCC is older than 10.0 and is not supported'; \ 79 79 false; \ 80 80 fi 81 81
+7
arch/arm/dts/Makefile
··· 918 918 r7s72100-genmai.dtb \ 919 919 r7s72100-gr-peach.dtb 920 920 921 + dtb-$(CONFIG_RCAR_GEN5) += \ 922 + r8a78000-ironhide.dtb 923 + 924 + ifdef CONFIG_RCAR_GEN5 925 + DTC_FLAGS += -R 4 -p 0x1000 926 + endif 927 + 921 928 dtb-$(CONFIG_TARGET_AT91SAM9261EK) += at91sam9261ek.dtb 922 929 923 930 dtb-$(CONFIG_TARGET_PM9261) += at91sam9261ek.dtb
+6 -6
arch/arm/dts/imx8ulp-evk-u-boot.dtsi
··· 10 10 compatible = "fsl,imx8ulp-mu"; 11 11 reg = <0 0x27020000 0 0x10000>; 12 12 status = "okay"; 13 - bootph-pre-ram; 13 + bootph-all; 14 14 }; 15 15 }; 16 16 17 17 &soc { 18 - bootph-pre-ram; 18 + bootph-all; 19 19 }; 20 20 21 21 &per_bridge3 { 22 - bootph-pre-ram; 22 + bootph-all; 23 23 }; 24 24 25 25 &per_bridge4 { ··· 27 27 }; 28 28 29 29 &iomuxc1 { 30 - bootph-pre-ram; 30 + bootph-all; 31 31 }; 32 32 33 33 &pinctrl_lpuart5 { 34 - bootph-pre-ram; 34 + bootph-all; 35 35 }; 36 36 37 37 &lpuart5 { 38 - bootph-pre-ram; 38 + bootph-all; 39 39 }; 40 40 41 41 &usdhc0 {
+4
arch/arm/dts/imx8ulp-evk.dts
··· 119 119 >; 120 120 }; 121 121 }; 122 + 123 + &wdog3 { 124 + status = "disabled"; 125 + };
+1 -1
arch/arm/dts/imx91-11x11-evk.dts
··· 503 503 MX91_PAD_ENET1_TD0__GPIO4_IO5 0x31e 504 504 MX91_PAD_ENET1_TD1__GPIO4_IO4 0x31e 505 505 MX91_PAD_ENET1_TD2__GPIO4_IO3 0x31e 506 - MX91_PAD_ENET1_TD3__GPIO4_IO3 0x31e 506 + MX91_PAD_ENET1_TD3__GPIO4_IO2 0x31e 507 507 MX91_PAD_ENET1_TXC__GPIO4_IO7 0x31e 508 508 MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x31e 509 509 >;
+2 -2
arch/arm/dts/imx91-pinfunc.h
··· 330 330 #define MX91_PAD_ENET1_TD3__CAN2_TX 0x00a0 0x0250 0x0000 0x02 0x00 331 331 #define MX91_PAD_ENET1_TD3__HSIOMIX_OTG_ID2 0x00a0 0x0250 0x0000 0x03 0x00 332 332 #define MX91_PAD_ENET1_TD3__FLEXIO2_FLEXIO2 0x00a0 0x0250 0x0000 0x04 0x00 333 - #define MX91_PAD_ENET1_TD3__GPIO4_IO3 0x00a0 0x0250 0x0000 0x05 0x00 333 + #define MX91_PAD_ENET1_TD3__GPIO4_IO2 0x00a0 0x0250 0x0000 0x05 0x00 334 334 #define MX91_PAD_ENET1_TD3__LPI2C2_SCL 0x00a0 0x0250 0x03e8 0x06 0x00 335 335 336 336 #define MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x00a4 0x0254 0x0000 0x00 0x00 ··· 680 680 #define MX91_PAD_I2C2_SCL__LPUART2_DCB_B 0x0178 0x0328 0x0000 0x02 0x00 681 681 #define MX91_PAD_I2C2_SCL__TPM2_CH2 0x0178 0x0328 0x0000 0x03 0x00 682 682 #define MX91_PAD_I2C2_SCL__SAI1_RX_SYNC 0x0178 0x0328 0x0000 0x04 0x00 683 - #define MX91_PAD_I2C2_SCL__GPIO1_IO3 0x0178 0x0328 0x0000 0x05 0x00 683 + #define MX91_PAD_I2C2_SCL__GPIO1_IO2 0x0178 0x0328 0x0000 0x05 0x00 684 684 #define MX91_PAD_I2C2_SCL__I3C1_PUR_B 0x0178 0x0328 0x0000 0x06 0x00 685 685 686 686 #define MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x017c 0x032c 0x03ec 0x00 0x01
-2
arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi
··· 23 23 24 24 &rpc { 25 25 bootph-all; 26 - status = "disabled"; 27 - 28 26 flash@0 { 29 27 bootph-all; 30 28 spi-tx-bus-width = <1>;
+8
arch/arm/dts/r8a78000-ironhide-u-boot.dtsi
··· 1 + // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + /* 3 + * Device Tree Source extras for U-Boot for the Ironhide board 4 + * 5 + * Copyright (C) 2025 Renesas Electronics Corp. 6 + */ 7 + 8 + #include "r8a78000-u-boot.dtsi"
+257
arch/arm/dts/r8a78000-ironhide.dts
··· 1 + // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + /* 3 + * Device Tree Source for the Ironhide board 4 + * 5 + * Copyright (C) 2025 Renesas Electronics Corp. 6 + */ 7 + 8 + /dts-v1/; 9 + #include "r8a78000.dtsi" 10 + #include <dt-bindings/net/ti-dp83869.h> 11 + 12 + / { 13 + model = "Renesas Ironhide board based on r8a78000"; 14 + compatible = "renesas,ironhide", "renesas,r8a78000"; 15 + 16 + aliases { 17 + i2c0 = &i2c0; 18 + i2c1 = &i2c1; 19 + i2c2 = &i2c2; 20 + i2c3 = &i2c3; 21 + i2c4 = &i2c4; 22 + i2c5 = &i2c5; 23 + i2c6 = &i2c6; 24 + i2c7 = &i2c7; 25 + i2c8 = &i2c8; 26 + mmc0 = &mmc0; 27 + serial0 = &hscif0; 28 + }; 29 + 30 + chosen { 31 + stdout-path = "serial0:1843200n8"; 32 + }; 33 + 34 + memory@40000000 { 35 + device_type = "memory"; 36 + reg = <0x0 0x40000000 0x0 0x80000000>; 37 + }; 38 + 39 + memory@1080000000 { 40 + device_type = "memory"; 41 + reg = <0x10 0x80000000 0x0 0x80000000>; 42 + }; 43 + 44 + memory@1200000000 { 45 + device_type = "memory"; 46 + reg = <0x12 0x00000000 0x1 0x00000000>; 47 + }; 48 + 49 + memory@1400000000 { 50 + device_type = "memory"; 51 + reg = <0x14 0x00000000 0x1 0x00000000>; 52 + }; 53 + 54 + memory@1600000000 { 55 + device_type = "memory"; 56 + reg = <0x16 0x00000000 0x1 0x00000000>; 57 + }; 58 + 59 + memory@1800000000 { 60 + device_type = "memory"; 61 + reg = <0x18 0x00000000 0x1 0x00000000>; 62 + }; 63 + 64 + memory@1a00000000 { 65 + device_type = "memory"; 66 + reg = <0x1a 0x00000000 0x1 0x00000000>; 67 + }; 68 + 69 + memory@1c00000000 { 70 + device_type = "memory"; 71 + reg = <0x1c 0x00000000 0x1 0x00000000>; 72 + }; 73 + 74 + memory@1e00000000 { 75 + device_type = "memory"; 76 + reg = <0x1e 0x00000000 0x1 0x00000000>; 77 + }; 78 + 79 + reg_1p8v: regulator-1p8v { 80 + compatible = "regulator-fixed"; 81 + regulator-name = "fixed-1.8V"; 82 + regulator-min-microvolt = <1800000>; 83 + regulator-max-microvolt = <1800000>; 84 + regulator-boot-on; 85 + regulator-always-on; 86 + }; 87 + 88 + reg_3p3v: regulator-3p3v { 89 + compatible = "regulator-fixed"; 90 + regulator-name = "fixed-3.3V"; 91 + regulator-min-microvolt = <3300000>; 92 + regulator-max-microvolt = <3300000>; 93 + regulator-boot-on; 94 + regulator-always-on; 95 + }; 96 + }; 97 + 98 + &extal_clk { 99 + clock-frequency = <16666600>; 100 + }; 101 + 102 + &extalr_clk { 103 + clock-frequency = <32768>; 104 + }; 105 + 106 + &hscif0 { 107 + pinctrl-0 = <&hscif0_pins>; 108 + pinctrl-names = "default"; 109 + uart-has-rtscts; 110 + status = "okay"; 111 + }; 112 + 113 + &i2c0 { 114 + pinctrl-0 = <&i2c0_pins>; 115 + pinctrl-names = "default"; 116 + clock-frequency = <400000>; 117 + status = "okay"; 118 + 119 + eeprom@50 { 120 + compatible = "rohm,br24g01", "atmel,24c01"; 121 + reg = <0x50>; 122 + pagesize = <8>; 123 + }; 124 + }; 125 + 126 + &i2c1 { 127 + pinctrl-0 = <&i2c1_pins>; 128 + pinctrl-names = "default"; 129 + clock-frequency = <400000>; 130 + status = "okay"; 131 + }; 132 + 133 + &eth_pcs { 134 + phys = <&mp_phy 2 1>; 135 + status = "okay"; 136 + }; 137 + 138 + &mmc0 { 139 + pinctrl-0 = <&mmc0_pins>; 140 + pinctrl-1 = <&mmc0_pins>; 141 + pinctrl-names = "default", "state_uhs"; 142 + 143 + bus-width = <8>; 144 + full-pwr-cycle-in-suspend; 145 + mmc-hs200-1_8v; 146 + mmc-hs400-1_8v; 147 + no-sd; 148 + no-sdio; 149 + non-removable; 150 + 151 + vmmc-supply = <&reg_3p3v>; 152 + vqmmc-supply = <&reg_1p8v>; 153 + 154 + status = "okay"; 155 + }; 156 + 157 + &ufs0 { 158 + status = "okay"; 159 + }; 160 + 161 + &ufs1 { 162 + status = "okay"; 163 + }; 164 + 165 + &mp_phy { 166 + status = "okay"; 167 + }; 168 + 169 + &pfc { 170 + pinctrl-0 = <&scif_clk_pins>; 171 + pinctrl-names = "default"; 172 + 173 + eth25g2_pins: eth25g2 { 174 + groups = "eth25g2_mdio", "eth25g2_link", "eth25g2_phyint"; 175 + function = "eth25g2"; 176 + drive-strength = <24>; 177 + }; 178 + 179 + ethes0_pins: ethes0 { 180 + groups = "ethes0_match", "ethes0_capture", "ethes0_pps"; 181 + function = "ethes0"; 182 + drive-strength = <24>; 183 + }; 184 + 185 + hscif0_pins: hscif0 { 186 + groups = "hscif0_data", "hscif0_ctrl"; 187 + function = "hscif0"; 188 + }; 189 + 190 + i2c0_pins: i2c0 { 191 + groups = "i2c0"; 192 + function = "i2c0"; 193 + }; 194 + 195 + i2c1_pins: i2c1 { 196 + groups = "i2c1"; 197 + function = "i2c1"; 198 + }; 199 + 200 + mmc0_pins: mmc0 { 201 + groups = "mmc0_data8", "mmc0_ctrl", "mmc0_ds"; 202 + function = "mmc0"; 203 + drive-strength = <24>; 204 + }; 205 + 206 + rsw3_pins: rsw3 { 207 + groups = "rsw3_match", "rsw3_capture", "rsw3_pps"; 208 + function = "rsw3"; 209 + drive-strength = <24>; 210 + }; 211 + 212 + scif_clk_pins: scif-clk { 213 + groups = "scif_clk"; 214 + function = "scif_clk"; 215 + }; 216 + }; 217 + 218 + &rswitch3 { 219 + pinctrl-0 = <&rsw3_pins>, <&eth25g2_pins>, <&ethes0_pins>; 220 + pinctrl-names = "default"; 221 + status = "okay"; 222 + 223 + ethernet-ports { 224 + #address-cells = <1>; 225 + #size-cells = <0>; 226 + 227 + /* 228 + * NOTE: Only port@4 is configured for R-Car X5H board. 229 + * Other ports (0-3, 5-12) are currently unused or not 230 + * connected. 231 + */ 232 + port@4 { 233 + reg = <4>; 234 + renesas,connect_to_xpcs; 235 + phy-handle = <&dp83869_phy>; 236 + phy-mode = "sgmii"; 237 + phys = <&eth_pcs 5>; 238 + 239 + mdio { 240 + #address-cells = <1>; 241 + #size-cells = <0>; 242 + 243 + dp83869_phy: ethernet-phy@2 { 244 + reg = <2>; 245 + ti,sgmii-interface; 246 + ti,max-output-impedance; 247 + ti,refclk-output-enable; 248 + ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>; 249 + }; 250 + }; 251 + }; 252 + }; 253 + }; 254 + 255 + &scif_clk { 256 + clock-frequency = <26000000>; 257 + };
+139
arch/arm/dts/r8a78000-u-boot.dtsi
··· 1 + // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + /* 3 + * Device Tree Source extras for U-Boot on R-Car R8A78000 SoC 4 + * 5 + * Copyright (C) 2025 Renesas Electronics Corp. 6 + */ 7 + 8 + / { 9 + soc { 10 + bootph-all; 11 + }; 12 + 13 + /* Placeholder clock until the clock provider is in place */ 14 + clk_stub_gpio: clk-stub-gpio { 15 + compatible = "fixed-clock"; 16 + #clock-cells = <0>; 17 + clock-frequency = <1000000>; 18 + }; 19 + 20 + clk_stub_i2c0: clk-stub-i2c0 { 21 + compatible = "fixed-clock"; 22 + #clock-cells = <0>; 23 + clock-frequency = <150000000>; 24 + }; 25 + 26 + clk_stub_i2c1: clk-stub-i2c1 { 27 + compatible = "fixed-clock"; 28 + #clock-cells = <0>; 29 + clock-frequency = <133333333>; 30 + }; 31 + 32 + clk_stub_mmc: clk-stub-mmc { 33 + compatible = "renesas,compound-clock"; 34 + #clock-cells = <0>; 35 + clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_SDHI0>, 36 + <&scmi_clk 1691>; 37 + clock-names = "mdlc", "per"; 38 + }; 39 + }; 40 + 41 + &cpg { 42 + bootph-all; 43 + }; 44 + 45 + &extal_clk { 46 + bootph-all; 47 + }; 48 + 49 + &extalr_clk { 50 + bootph-all; 51 + }; 52 + 53 + &gpio0 { 54 + clocks = <&clk_stub_gpio>; 55 + }; 56 + 57 + &gpio1 { 58 + clocks = <&clk_stub_gpio>; 59 + }; 60 + 61 + &gpio2 { 62 + clocks = <&clk_stub_gpio>; 63 + }; 64 + 65 + &gpio3 { 66 + clocks = <&clk_stub_gpio>; 67 + }; 68 + 69 + &gpio4 { 70 + clocks = <&clk_stub_gpio>; 71 + }; 72 + 73 + &gpio5 { 74 + clocks = <&clk_stub_gpio>; 75 + }; 76 + 77 + &gpio6 { 78 + clocks = <&clk_stub_gpio>; 79 + }; 80 + 81 + &gpio7 { 82 + clocks = <&clk_stub_gpio>; 83 + }; 84 + 85 + &gpio8 { 86 + clocks = <&clk_stub_gpio>; 87 + }; 88 + 89 + &gpio9 { 90 + clocks = <&clk_stub_gpio>; 91 + }; 92 + 93 + &gpio10 { 94 + clocks = <&clk_stub_gpio>; 95 + }; 96 + 97 + &i2c0 { 98 + clocks = <&clk_stub_i2c0>; 99 + }; 100 + 101 + &i2c1 { 102 + clocks = <&clk_stub_i2c1>; 103 + }; 104 + 105 + &i2c2 { 106 + clocks = <&clk_stub_i2c1>; 107 + }; 108 + 109 + &i2c3 { 110 + clocks = <&clk_stub_i2c1>; 111 + }; 112 + 113 + &i2c4 { 114 + clocks = <&clk_stub_i2c1>; 115 + }; 116 + 117 + &i2c5 { 118 + clocks = <&clk_stub_i2c1>; 119 + }; 120 + 121 + &i2c6 { 122 + clocks = <&clk_stub_i2c1>; 123 + }; 124 + 125 + &i2c7 { 126 + clocks = <&clk_stub_i2c1>; 127 + }; 128 + 129 + &i2c8 { 130 + clocks = <&clk_stub_i2c1>; 131 + }; 132 + 133 + &mmc0 { 134 + clocks = <&clk_stub_mmc>; 135 + }; 136 + 137 + &prr { 138 + bootph-all; 139 + };
+1164
arch/arm/dts/r8a78000.dtsi
··· 1 + // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + /* 3 + * Device Tree Source for the R-Car X5H (R8A78000) SoC 4 + * 5 + * Copyright (C) 2025 Renesas Electronics Corp. 6 + */ 7 + 8 + #include <dt-bindings/clock/r8a78000-clock-scmi.h> 9 + #include <dt-bindings/interrupt-controller/arm-gic.h> 10 + #include <dt-bindings/power/r8a78000-power-scmi.h> 11 + #include <dt-bindings/reset/r8a78000-reset-scmi.h> 12 + 13 + / { 14 + compatible = "renesas,r8a78000"; 15 + #address-cells = <2>; 16 + #size-cells = <2>; 17 + interrupt-parent = <&gic>; 18 + 19 + cpus { 20 + #address-cells = <2>; 21 + #size-cells = <0>; 22 + 23 + cpu-map { 24 + cluster0 { 25 + core0 { 26 + cpu = <&a720_0>; 27 + }; 28 + core1 { 29 + cpu = <&a720_1>; 30 + }; 31 + core2 { 32 + cpu = <&a720_2>; 33 + }; 34 + core3 { 35 + cpu = <&a720_3>; 36 + }; 37 + }; 38 + 39 + cluster1 { 40 + core0 { 41 + cpu = <&a720_4>; 42 + }; 43 + core1 { 44 + cpu = <&a720_5>; 45 + }; 46 + core2 { 47 + cpu = <&a720_6>; 48 + }; 49 + core3 { 50 + cpu = <&a720_7>; 51 + }; 52 + }; 53 + 54 + cluster2 { 55 + core0 { 56 + cpu = <&a720_8>; 57 + }; 58 + core1 { 59 + cpu = <&a720_9>; 60 + }; 61 + core2 { 62 + cpu = <&a720_10>; 63 + }; 64 + core3 { 65 + cpu = <&a720_11>; 66 + }; 67 + }; 68 + 69 + cluster3 { 70 + core0 { 71 + cpu = <&a720_12>; 72 + }; 73 + core1 { 74 + cpu = <&a720_13>; 75 + }; 76 + core2 { 77 + cpu = <&a720_14>; 78 + }; 79 + core3 { 80 + cpu = <&a720_15>; 81 + }; 82 + }; 83 + 84 + cluster4 { 85 + core0 { 86 + cpu = <&a720_16>; 87 + }; 88 + core1 { 89 + cpu = <&a720_17>; 90 + }; 91 + core2 { 92 + cpu = <&a720_18>; 93 + }; 94 + core3 { 95 + cpu = <&a720_19>; 96 + }; 97 + }; 98 + 99 + cluster5 { 100 + core0 { 101 + cpu = <&a720_20>; 102 + }; 103 + core1 { 104 + cpu = <&a720_21>; 105 + }; 106 + core2 { 107 + cpu = <&a720_22>; 108 + }; 109 + core3 { 110 + cpu = <&a720_23>; 111 + }; 112 + }; 113 + 114 + cluster6 { 115 + core0 { 116 + cpu = <&a720_24>; 117 + }; 118 + core1 { 119 + cpu = <&a720_25>; 120 + }; 121 + core2 { 122 + cpu = <&a720_26>; 123 + }; 124 + core3 { 125 + cpu = <&a720_27>; 126 + }; 127 + }; 128 + 129 + cluster7 { 130 + core0 { 131 + cpu = <&a720_28>; 132 + }; 133 + core1 { 134 + cpu = <&a720_29>; 135 + }; 136 + core2 { 137 + cpu = <&a720_30>; 138 + }; 139 + core3 { 140 + cpu = <&a720_31>; 141 + }; 142 + }; 143 + }; 144 + 145 + a720_0: cpu@0 { 146 + compatible = "arm,cortex-a720ae"; 147 + reg = <0x0 0x0>; 148 + device_type = "cpu"; 149 + next-level-cache = <&L2_CA720_0>; 150 + }; 151 + 152 + a720_1: cpu@100 { 153 + compatible = "arm,cortex-a720ae"; 154 + reg = <0x0 0x100>; 155 + device_type = "cpu"; 156 + next-level-cache = <&L2_CA720_1>; 157 + }; 158 + 159 + a720_2: cpu@200 { 160 + compatible = "arm,cortex-a720ae"; 161 + reg = <0x0 0x200>; 162 + device_type = "cpu"; 163 + next-level-cache = <&L2_CA720_2>; 164 + }; 165 + 166 + a720_3: cpu@300 { 167 + compatible = "arm,cortex-a720ae"; 168 + reg = <0x0 0x300>; 169 + device_type = "cpu"; 170 + next-level-cache = <&L2_CA720_3>; 171 + }; 172 + 173 + a720_4: cpu@10000 { 174 + compatible = "arm,cortex-a720ae"; 175 + reg = <0x0 0x10000>; 176 + device_type = "cpu"; 177 + next-level-cache = <&L2_CA720_4>; 178 + }; 179 + 180 + a720_5: cpu@10100 { 181 + compatible = "arm,cortex-a720ae"; 182 + reg = <0x0 0x10100>; 183 + device_type = "cpu"; 184 + next-level-cache = <&L2_CA720_5>; 185 + }; 186 + 187 + a720_6: cpu@10200 { 188 + compatible = "arm,cortex-a720ae"; 189 + reg = <0x0 0x10200>; 190 + device_type = "cpu"; 191 + next-level-cache = <&L2_CA720_6>; 192 + }; 193 + 194 + a720_7: cpu@10300 { 195 + compatible = "arm,cortex-a720ae"; 196 + reg = <0x0 0x10300>; 197 + device_type = "cpu"; 198 + next-level-cache = <&L2_CA720_7>; 199 + }; 200 + 201 + a720_8: cpu@20000 { 202 + compatible = "arm,cortex-a720ae"; 203 + reg = <0x0 0x20000>; 204 + device_type = "cpu"; 205 + next-level-cache = <&L2_CA720_8>; 206 + }; 207 + 208 + a720_9: cpu@20100 { 209 + compatible = "arm,cortex-a720ae"; 210 + reg = <0x0 0x20100>; 211 + device_type = "cpu"; 212 + next-level-cache = <&L2_CA720_9>; 213 + }; 214 + 215 + a720_10: cpu@20200 { 216 + compatible = "arm,cortex-a720ae"; 217 + reg = <0x0 0x20200>; 218 + device_type = "cpu"; 219 + next-level-cache = <&L2_CA720_10>; 220 + }; 221 + 222 + a720_11: cpu@20300 { 223 + compatible = "arm,cortex-a720ae"; 224 + reg = <0x0 0x20300>; 225 + device_type = "cpu"; 226 + next-level-cache = <&L2_CA720_11>; 227 + }; 228 + 229 + a720_12: cpu@30000 { 230 + compatible = "arm,cortex-a720ae"; 231 + reg = <0x0 0x30000>; 232 + device_type = "cpu"; 233 + next-level-cache = <&L2_CA720_12>; 234 + }; 235 + 236 + a720_13: cpu@30100 { 237 + compatible = "arm,cortex-a720ae"; 238 + reg = <0x0 0x30100>; 239 + device_type = "cpu"; 240 + next-level-cache = <&L2_CA720_13>; 241 + }; 242 + 243 + a720_14: cpu@30200 { 244 + compatible = "arm,cortex-a720ae"; 245 + reg = <0x0 0x30200>; 246 + device_type = "cpu"; 247 + next-level-cache = <&L2_CA720_14>; 248 + }; 249 + 250 + a720_15: cpu@30300 { 251 + compatible = "arm,cortex-a720ae"; 252 + reg = <0x0 0x30300>; 253 + device_type = "cpu"; 254 + next-level-cache = <&L2_CA720_15>; 255 + }; 256 + 257 + a720_16: cpu@40000 { 258 + compatible = "arm,cortex-a720ae"; 259 + reg = <0x0 0x40000>; 260 + device_type = "cpu"; 261 + next-level-cache = <&L2_CA720_16>; 262 + }; 263 + 264 + a720_17: cpu@40100 { 265 + compatible = "arm,cortex-a720ae"; 266 + reg = <0x0 0x40100>; 267 + device_type = "cpu"; 268 + next-level-cache = <&L2_CA720_17>; 269 + }; 270 + 271 + a720_18: cpu@40200 { 272 + compatible = "arm,cortex-a720ae"; 273 + reg = <0x0 0x40200>; 274 + device_type = "cpu"; 275 + next-level-cache = <&L2_CA720_18>; 276 + }; 277 + 278 + a720_19: cpu@40300 { 279 + compatible = "arm,cortex-a720ae"; 280 + reg = <0x0 0x40300>; 281 + device_type = "cpu"; 282 + next-level-cache = <&L2_CA720_19>; 283 + }; 284 + 285 + a720_20: cpu@50000 { 286 + compatible = "arm,cortex-a720ae"; 287 + reg = <0x0 0x50000>; 288 + device_type = "cpu"; 289 + next-level-cache = <&L2_CA720_20>; 290 + }; 291 + 292 + a720_21: cpu@50100 { 293 + compatible = "arm,cortex-a720ae"; 294 + reg = <0x0 0x50100>; 295 + device_type = "cpu"; 296 + next-level-cache = <&L2_CA720_21>; 297 + }; 298 + 299 + a720_22: cpu@50200 { 300 + compatible = "arm,cortex-a720ae"; 301 + reg = <0x0 0x50200>; 302 + device_type = "cpu"; 303 + next-level-cache = <&L2_CA720_22>; 304 + }; 305 + 306 + a720_23: cpu@50300 { 307 + compatible = "arm,cortex-a720ae"; 308 + reg = <0x0 0x50300>; 309 + device_type = "cpu"; 310 + next-level-cache = <&L2_CA720_23>; 311 + }; 312 + 313 + a720_24: cpu@60000 { 314 + compatible = "arm,cortex-a720ae"; 315 + reg = <0x0 0x60000>; 316 + device_type = "cpu"; 317 + next-level-cache = <&L2_CA720_24>; 318 + }; 319 + 320 + a720_25: cpu@60100 { 321 + compatible = "arm,cortex-a720ae"; 322 + reg = <0x0 0x60100>; 323 + device_type = "cpu"; 324 + next-level-cache = <&L2_CA720_25>; 325 + }; 326 + 327 + a720_26: cpu@60200 { 328 + compatible = "arm,cortex-a720ae"; 329 + reg = <0x0 0x60200>; 330 + device_type = "cpu"; 331 + next-level-cache = <&L2_CA720_26>; 332 + }; 333 + 334 + a720_27: cpu@60300 { 335 + compatible = "arm,cortex-a720ae"; 336 + reg = <0x0 0x60300>; 337 + device_type = "cpu"; 338 + next-level-cache = <&L2_CA720_27>; 339 + }; 340 + 341 + a720_28: cpu@70000 { 342 + compatible = "arm,cortex-a720ae"; 343 + reg = <0x0 0x70000>; 344 + device_type = "cpu"; 345 + next-level-cache = <&L2_CA720_28>; 346 + }; 347 + 348 + a720_29: cpu@70100 { 349 + compatible = "arm,cortex-a720ae"; 350 + reg = <0x0 0x70100>; 351 + device_type = "cpu"; 352 + next-level-cache = <&L2_CA720_29>; 353 + }; 354 + 355 + a720_30: cpu@70200 { 356 + compatible = "arm,cortex-a720ae"; 357 + reg = <0x0 0x70200>; 358 + device_type = "cpu"; 359 + next-level-cache = <&L2_CA720_30>; 360 + }; 361 + 362 + a720_31: cpu@70300 { 363 + compatible = "arm,cortex-a720ae"; 364 + reg = <0x0 0x70300>; 365 + device_type = "cpu"; 366 + next-level-cache = <&L2_CA720_31>; 367 + }; 368 + 369 + L2_CA720_0: cache-controller-200 { 370 + compatible = "cache"; 371 + cache-unified; 372 + cache-level = <2>; 373 + next-level-cache = <&L3_CA720_0>; 374 + }; 375 + 376 + L2_CA720_1: cache-controller-201 { 377 + compatible = "cache"; 378 + cache-unified; 379 + cache-level = <2>; 380 + next-level-cache = <&L3_CA720_0>; 381 + }; 382 + 383 + L2_CA720_2: cache-controller-202 { 384 + compatible = "cache"; 385 + cache-unified; 386 + cache-level = <2>; 387 + next-level-cache = <&L3_CA720_0>; 388 + }; 389 + 390 + L2_CA720_3: cache-controller-203 { 391 + compatible = "cache"; 392 + cache-unified; 393 + cache-level = <2>; 394 + next-level-cache = <&L3_CA720_0>; 395 + }; 396 + 397 + L2_CA720_4: cache-controller-204 { 398 + compatible = "cache"; 399 + cache-unified; 400 + cache-level = <2>; 401 + next-level-cache = <&L3_CA720_1>; 402 + }; 403 + 404 + L2_CA720_5: cache-controller-205 { 405 + compatible = "cache"; 406 + cache-unified; 407 + cache-level = <2>; 408 + next-level-cache = <&L3_CA720_1>; 409 + }; 410 + 411 + L2_CA720_6: cache-controller-206 { 412 + compatible = "cache"; 413 + cache-unified; 414 + cache-level = <2>; 415 + next-level-cache = <&L3_CA720_1>; 416 + }; 417 + 418 + L2_CA720_7: cache-controller-207 { 419 + compatible = "cache"; 420 + cache-unified; 421 + cache-level = <2>; 422 + next-level-cache = <&L3_CA720_1>; 423 + }; 424 + 425 + L2_CA720_8: cache-controller-208 { 426 + compatible = "cache"; 427 + cache-unified; 428 + cache-level = <2>; 429 + next-level-cache = <&L3_CA720_2>; 430 + }; 431 + 432 + L2_CA720_9: cache-controller-209 { 433 + compatible = "cache"; 434 + cache-unified; 435 + cache-level = <2>; 436 + next-level-cache = <&L3_CA720_2>; 437 + }; 438 + 439 + L2_CA720_10: cache-controller-210 { 440 + compatible = "cache"; 441 + cache-unified; 442 + cache-level = <2>; 443 + next-level-cache = <&L3_CA720_2>; 444 + }; 445 + 446 + L2_CA720_11: cache-controller-211 { 447 + compatible = "cache"; 448 + cache-unified; 449 + cache-level = <2>; 450 + next-level-cache = <&L3_CA720_2>; 451 + }; 452 + 453 + L2_CA720_12: cache-controller-212 { 454 + compatible = "cache"; 455 + cache-unified; 456 + cache-level = <2>; 457 + next-level-cache = <&L3_CA720_3>; 458 + }; 459 + 460 + L2_CA720_13: cache-controller-213 { 461 + compatible = "cache"; 462 + cache-unified; 463 + cache-level = <2>; 464 + next-level-cache = <&L3_CA720_3>; 465 + }; 466 + 467 + L2_CA720_14: cache-controller-214 { 468 + compatible = "cache"; 469 + cache-unified; 470 + cache-level = <2>; 471 + next-level-cache = <&L3_CA720_3>; 472 + }; 473 + 474 + L2_CA720_15: cache-controller-215 { 475 + compatible = "cache"; 476 + cache-unified; 477 + cache-level = <2>; 478 + next-level-cache = <&L3_CA720_3>; 479 + }; 480 + 481 + L2_CA720_16: cache-controller-216 { 482 + compatible = "cache"; 483 + cache-unified; 484 + cache-level = <2>; 485 + next-level-cache = <&L3_CA720_4>; 486 + }; 487 + 488 + L2_CA720_17: cache-controller-217 { 489 + compatible = "cache"; 490 + cache-unified; 491 + cache-level = <2>; 492 + next-level-cache = <&L3_CA720_4>; 493 + }; 494 + 495 + L2_CA720_18: cache-controller-218 { 496 + compatible = "cache"; 497 + cache-unified; 498 + cache-level = <2>; 499 + next-level-cache = <&L3_CA720_4>; 500 + }; 501 + 502 + L2_CA720_19: cache-controller-219 { 503 + compatible = "cache"; 504 + cache-unified; 505 + cache-level = <2>; 506 + next-level-cache = <&L3_CA720_4>; 507 + }; 508 + 509 + L2_CA720_20: cache-controller-220 { 510 + compatible = "cache"; 511 + cache-unified; 512 + cache-level = <2>; 513 + next-level-cache = <&L3_CA720_5>; 514 + }; 515 + 516 + L2_CA720_21: cache-controller-221 { 517 + compatible = "cache"; 518 + cache-unified; 519 + cache-level = <2>; 520 + next-level-cache = <&L3_CA720_5>; 521 + }; 522 + 523 + L2_CA720_22: cache-controller-222 { 524 + compatible = "cache"; 525 + cache-unified; 526 + cache-level = <2>; 527 + next-level-cache = <&L3_CA720_5>; 528 + }; 529 + 530 + L2_CA720_23: cache-controller-223 { 531 + compatible = "cache"; 532 + cache-unified; 533 + cache-level = <2>; 534 + next-level-cache = <&L3_CA720_5>; 535 + }; 536 + 537 + L2_CA720_24: cache-controller-224 { 538 + compatible = "cache"; 539 + cache-unified; 540 + cache-level = <2>; 541 + next-level-cache = <&L3_CA720_6>; 542 + }; 543 + 544 + L2_CA720_25: cache-controller-225 { 545 + compatible = "cache"; 546 + cache-unified; 547 + cache-level = <2>; 548 + next-level-cache = <&L3_CA720_6>; 549 + }; 550 + 551 + L2_CA720_26: cache-controller-226 { 552 + compatible = "cache"; 553 + cache-unified; 554 + cache-level = <2>; 555 + next-level-cache = <&L3_CA720_6>; 556 + }; 557 + 558 + L2_CA720_27: cache-controller-227 { 559 + compatible = "cache"; 560 + cache-unified; 561 + cache-level = <2>; 562 + next-level-cache = <&L3_CA720_6>; 563 + }; 564 + 565 + L2_CA720_28: cache-controller-228 { 566 + compatible = "cache"; 567 + cache-unified; 568 + cache-level = <2>; 569 + next-level-cache = <&L3_CA720_7>; 570 + }; 571 + 572 + L2_CA720_29: cache-controller-229 { 573 + compatible = "cache"; 574 + cache-unified; 575 + cache-level = <2>; 576 + next-level-cache = <&L3_CA720_7>; 577 + }; 578 + 579 + L2_CA720_30: cache-controller-230 { 580 + compatible = "cache"; 581 + cache-unified; 582 + cache-level = <2>; 583 + next-level-cache = <&L3_CA720_7>; 584 + }; 585 + 586 + L2_CA720_31: cache-controller-231 { 587 + compatible = "cache"; 588 + cache-unified; 589 + cache-level = <2>; 590 + next-level-cache = <&L3_CA720_7>; 591 + }; 592 + 593 + L3_CA720_0: cache-controller-30 { 594 + compatible = "cache"; 595 + cache-unified; 596 + cache-level = <3>; 597 + }; 598 + 599 + L3_CA720_1: cache-controller-31 { 600 + compatible = "cache"; 601 + cache-unified; 602 + cache-level = <3>; 603 + }; 604 + 605 + L3_CA720_2: cache-controller-32 { 606 + compatible = "cache"; 607 + cache-unified; 608 + cache-level = <3>; 609 + }; 610 + 611 + L3_CA720_3: cache-controller-33 { 612 + compatible = "cache"; 613 + cache-unified; 614 + cache-level = <3>; 615 + }; 616 + 617 + L3_CA720_4: cache-controller-34 { 618 + compatible = "cache"; 619 + cache-unified; 620 + cache-level = <3>; 621 + }; 622 + 623 + L3_CA720_5: cache-controller-35 { 624 + compatible = "cache"; 625 + cache-unified; 626 + cache-level = <3>; 627 + }; 628 + 629 + L3_CA720_6: cache-controller-36 { 630 + compatible = "cache"; 631 + cache-unified; 632 + cache-level = <3>; 633 + }; 634 + 635 + L3_CA720_7: cache-controller-37 { 636 + compatible = "cache"; 637 + cache-unified; 638 + cache-level = <3>; 639 + }; 640 + }; 641 + 642 + /* 643 + * In the early phase, there is no clock control support, 644 + * so assume that the clocks are enabled by default. 645 + * Therefore, dummy clocks are used. 646 + */ 647 + dummy_clk_sgasyncd16: dummy-clk-sgasyncd16 { 648 + compatible = "fixed-clock"; 649 + #clock-cells = <0>; 650 + clock-frequency = <66666000>; 651 + }; 652 + 653 + dummy_clk_sgasyncd4: dummy-clk-sgasyncd4 { 654 + compatible = "fixed-clock"; 655 + #clock-cells = <0>; 656 + clock-frequency = <266660000>; 657 + }; 658 + 659 + extal_clk: extal-clk { 660 + compatible = "fixed-clock"; 661 + #clock-cells = <0>; 662 + /* clock-frequency must be set on board */ 663 + }; 664 + 665 + extalr_clk: extalr-clk { 666 + compatible = "fixed-clock"; 667 + #clock-cells = <0>; 668 + /* clock-frequency must be set on board */ 669 + }; 670 + 671 + firmware { 672 + scmi { 673 + compatible = "arm,scmi"; 674 + arm,poll-transport; 675 + mbox-names = "tx", "rx"; 676 + mboxes = <&mailbox 0>, <&mailbox 1>; 677 + shmem = <&cpu_scp_lpri0>, <&cpu_scp_hpri0>; 678 + #address-cells = <1>; 679 + #size-cells = <0>; 680 + 681 + scmi_devpd: protocol@11 { 682 + reg = <0x11>; 683 + #power-domain-cells = <1>; 684 + }; 685 + 686 + scmi_clk: protocol@14 { 687 + reg = <0x14>; 688 + #clock-cells = <1>; 689 + }; 690 + 691 + scmi_reset: protocol@16 { 692 + reg = <0x16>; 693 + #reset-cells = <1>; 694 + }; 695 + }; 696 + }; 697 + 698 + psci { 699 + compatible = "arm,psci-1.0", "arm,psci-0.2"; 700 + method = "smc"; 701 + }; 702 + 703 + /* External SCIF clock - to be overridden by boards that provide it */ 704 + scif_clk: scif-clk { 705 + compatible = "fixed-clock"; 706 + #clock-cells = <0>; 707 + clock-frequency = <0>; /* optional */ 708 + }; 709 + 710 + soc: soc { 711 + compatible = "simple-bus"; 712 + #address-cells = <2>; 713 + #size-cells = <2>; 714 + ranges; 715 + 716 + mailbox: mfis_mbox@18842000 { 717 + compatible = "renesas,mfis-mbox"; 718 + #mbox-cells = <1>; 719 + reg = <0 0x18842004 0 0x8>; 720 + interrupts = <GIC_SPI 4362 IRQ_TYPE_LEVEL_HIGH>; 721 + }; 722 + 723 + prr: chipid@189e0044 { 724 + compatible = "renesas,prr"; 725 + reg = <0 0x189e0044 0 4>; 726 + }; 727 + 728 + /* Application Processors manage View-1 of a GIC-720AE */ 729 + gic: interrupt-controller@39000000 { 730 + compatible = "arm,gic-v3"; 731 + #interrupt-cells = <3>; 732 + #address-cells = <0>; 733 + interrupt-controller; 734 + reg = <0 0x39000000 0 0x10000>, 735 + <0 0x39080000 0 0x800000>; 736 + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 737 + }; 738 + 739 + pfc: pinctrl@c0400000 { 740 + compatible = "renesas,pfc-r8a78000"; 741 + reg = <0 0xc1080000 0 0x104>, <0 0xc1080800 0 0x104>, 742 + <0 0xc1081000 0 0x104>, <0 0xc0800000 0 0x104>, 743 + <0 0xc0800800 0 0x104>, <0 0xc0400000 0 0x104>, 744 + <0 0xc0400800 0 0x104>, <0 0xc0401000 0 0x104>, 745 + <0 0xc0401800 0 0x104>, <0 0xc9b00000 0 0x104>, 746 + <0 0xc9b00800 0 0x104>; 747 + }; 748 + 749 + scif0: serial@c0700000 { 750 + compatible = "renesas,scif-r8a78000", 751 + "renesas,rcar-gen5-scif", "renesas,scif"; 752 + reg = <0 0xc0700000 0 0x40>; 753 + interrupts = <GIC_SPI 4074 IRQ_TYPE_LEVEL_HIGH>; 754 + clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; 755 + clock-names = "fck", "brg_int", "scif_clk"; 756 + status = "disabled"; 757 + }; 758 + 759 + scif1: serial@c0704000 { 760 + compatible = "renesas,scif-r8a78000", 761 + "renesas,rcar-gen5-scif", "renesas,scif"; 762 + reg = <0 0xc0704000 0 0x40>; 763 + interrupts = <GIC_SPI 4075 IRQ_TYPE_LEVEL_HIGH>; 764 + clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; 765 + clock-names = "fck", "brg_int", "scif_clk"; 766 + status = "okay"; 767 + }; 768 + 769 + scif3: serial@c0708000 { 770 + compatible = "renesas,scif-r8a78000", 771 + "renesas,rcar-gen5-scif", "renesas,scif"; 772 + reg = <0 0xc0708000 0 0x40>; 773 + interrupts = <GIC_SPI 4076 IRQ_TYPE_LEVEL_HIGH>; 774 + clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; 775 + clock-names = "fck", "brg_int", "scif_clk"; 776 + status = "disabled"; 777 + }; 778 + 779 + scif4: serial@c070c000 { 780 + compatible = "renesas,scif-r8a78000", 781 + "renesas,rcar-gen5-scif", "renesas,scif"; 782 + reg = <0 0xc070c000 0 0x40>; 783 + interrupts = <GIC_SPI 4077 IRQ_TYPE_LEVEL_HIGH>; 784 + clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; 785 + clock-names = "fck", "brg_int", "scif_clk"; 786 + status = "disabled"; 787 + }; 788 + 789 + mmc0: mmc@c0880000 { 790 + compatible = "renesas,rcar-gen5-sdhi"; 791 + reg = <0 0xc0880000 0 0x2000>; 792 + clock-names = "core"; 793 + max-frequency = <200000000>; 794 + status = "disabled"; 795 + }; 796 + 797 + ufs0: ufs@c0a80000 { 798 + compatible = "renesas,r8a78000-ufs"; 799 + reg = <0 0xc0a80000 0 0x1100>, <0 0xc0a00000 0 0x40000>; 800 + reg-names = "hcr", "phy"; 801 + interrupts = <GIC_SPI 4284 IRQ_TYPE_LEVEL_HIGH>; 802 + power-domains = <&scmi_devpd X5H_POWER_DOMAIN_ID_UFS0>; 803 + clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_UFS0>; 804 + resets = <&scmi_reset SCP_RESET_DOMAIN_ID_UFS0>; 805 + freq-table-hz = <38400000 38400000>; 806 + status = "disabled"; 807 + }; 808 + 809 + ufs1: ufs@c0a90000 { 810 + compatible = "renesas,r8a78000-ufs"; 811 + reg = <0 0xc0a90000 0 0x1100>, <0 0xc0a40000 0 0x40000>; 812 + reg-names = "hcr", "phy"; 813 + interrupts = <GIC_SPI 4285 IRQ_TYPE_LEVEL_HIGH>; 814 + power-domains = <&scmi_devpd X5H_POWER_DOMAIN_ID_UFS1>; 815 + clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_UFS1>; 816 + resets = <&scmi_reset SCP_RESET_DOMAIN_ID_UFS1>; 817 + freq-table-hz = <38400000 38400000>; 818 + status = "disabled"; 819 + }; 820 + 821 + scp: sram@c1000000 { 822 + compatible = "arm,rcar-sram-ns", "mmio-sram"; 823 + reg = <0x0 0xc1000000 0x0 0x80000>; 824 + #address-cells = <1>; 825 + #size-cells = <1>; 826 + ranges = <0 0x0 0xc1000000 0x80000>; 827 + 828 + cpu_scp_lpri0: scp-shmem@60000 { 829 + compatible = "arm,rcar-scp-shmem", "arm,scmi-shmem"; 830 + reg = <0x61200 0x0100>; 831 + }; 832 + 833 + cpu_scp_hpri0: scp-shmem@60300 { 834 + compatible = "arm,rcar-scp-shmem", "arm,scmi-shmem"; 835 + reg = <0x61300 0x100>; 836 + }; 837 + }; 838 + 839 + cpg: clock-controller@c64f0000 { 840 + compatible = "renesas,r8a78000-cpg-mssr"; 841 + reg = <0 0xc64f0000 0 0x4000>; 842 + clocks = <&extal_clk>, <&extalr_clk>; 843 + clock-names = "extal", "extalr"; 844 + #clock-cells = <2>; 845 + #power-domain-cells = <0>; 846 + #reset-cells = <1>; 847 + }; 848 + 849 + hscif0: serial@c0710000 { 850 + compatible = "renesas,hscif-r8a78000", 851 + "renesas,rcar-gen5-hscif", "renesas,hscif"; 852 + reg = <0 0xc0710000 0 0x60>; 853 + interrupts = <GIC_SPI 4078 IRQ_TYPE_LEVEL_HIGH>; 854 + clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; 855 + clock-names = "fck", "brg_int", "scif_clk"; 856 + status = "disabled"; 857 + }; 858 + 859 + hscif1: serial@c0714000 { 860 + compatible = "renesas,hscif-r8a78000", 861 + "renesas,rcar-gen5-hscif", "renesas,hscif"; 862 + reg = <0 0xc0714000 0 0x60>; 863 + interrupts = <GIC_SPI 4079 IRQ_TYPE_LEVEL_HIGH>; 864 + clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; 865 + clock-names = "fck", "brg_int", "scif_clk"; 866 + status = "disabled"; 867 + }; 868 + 869 + hscif2: serial@c0718000 { 870 + compatible = "renesas,hscif-r8a78000", 871 + "renesas,rcar-gen5-hscif", "renesas,hscif"; 872 + reg = <0 0xc0718000 0 0x60>; 873 + interrupts = <GIC_SPI 4080 IRQ_TYPE_LEVEL_HIGH>; 874 + clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; 875 + clock-names = "fck", "brg_int", "scif_clk"; 876 + status = "disabled"; 877 + }; 878 + 879 + hscif3: serial@c071c000 { 880 + compatible = "renesas,hscif-r8a78000", 881 + "renesas,rcar-gen5-hscif", "renesas,hscif"; 882 + reg = <0 0xc071c000 0 0x60>; 883 + interrupts = <GIC_SPI 4081 IRQ_TYPE_LEVEL_HIGH>; 884 + clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; 885 + clock-names = "fck", "brg_int", "scif_clk"; 886 + status = "disabled"; 887 + }; 888 + 889 + i2c0: i2c@c11d0000 { 890 + compatible = "renesas,i2c-r8a78000", 891 + "renesas,rcar-gen5-i2c"; 892 + reg = <0 0xc11d0000 0 0x40>; 893 + i2c-scl-internal-delay-ns = <110>; 894 + #address-cells = <1>; 895 + #size-cells = <0>; 896 + status = "disabled"; 897 + }; 898 + 899 + i2c1: i2c@c06c0000 { 900 + compatible = "renesas,i2c-r8a78000", 901 + "renesas,rcar-gen5-i2c"; 902 + reg = <0 0xc06c0000 0 0x40>; 903 + i2c-scl-internal-delay-ns = <110>; 904 + #address-cells = <1>; 905 + #size-cells = <0>; 906 + status = "disabled"; 907 + }; 908 + 909 + i2c2: i2c@c06c8000 { 910 + compatible = "renesas,i2c-r8a78000", 911 + "renesas,rcar-gen5-i2c"; 912 + reg = <0 0xc06c8000 0 0x40>; 913 + i2c-scl-internal-delay-ns = <110>; 914 + #address-cells = <1>; 915 + #size-cells = <0>; 916 + status = "disabled"; 917 + }; 918 + 919 + i2c3: i2c@c06d0000 { 920 + compatible = "renesas,i2c-r8a78000", 921 + "renesas,rcar-gen5-i2c"; 922 + reg = <0 0xc06d0000 0 0x40>; 923 + i2c-scl-internal-delay-ns = <110>; 924 + #address-cells = <1>; 925 + #size-cells = <0>; 926 + status = "disabled"; 927 + }; 928 + 929 + i2c4: i2c@c06d8000 { 930 + compatible = "renesas,i2c-r8a78000", 931 + "renesas,rcar-gen5-i2c"; 932 + reg = <0 0xc06d8000 0 0x40>; 933 + i2c-scl-internal-delay-ns = <110>; 934 + #address-cells = <1>; 935 + #size-cells = <0>; 936 + status = "disabled"; 937 + }; 938 + 939 + i2c5: i2c@c06e0000 { 940 + compatible = "renesas,i2c-r8a78000", 941 + "renesas,rcar-gen5-i2c"; 942 + reg = <0 0xc06e0000 0 0x40>; 943 + i2c-scl-internal-delay-ns = <110>; 944 + #address-cells = <1>; 945 + #size-cells = <0>; 946 + status = "disabled"; 947 + }; 948 + 949 + i2c6: i2c@c06e8000 { 950 + compatible = "renesas,i2c-r8a78000", 951 + "renesas,rcar-gen5-i2c"; 952 + reg = <0 0xc06e8000 0 0x40>; 953 + i2c-scl-internal-delay-ns = <110>; 954 + #address-cells = <1>; 955 + #size-cells = <0>; 956 + status = "disabled"; 957 + }; 958 + 959 + i2c7: i2c@c06f0000 { 960 + compatible = "renesas,i2c-r8a78000", 961 + "renesas,rcar-gen5-i2c"; 962 + reg = <0 0xc06f0000 0 0x40>; 963 + i2c-scl-internal-delay-ns = <110>; 964 + #address-cells = <1>; 965 + #size-cells = <0>; 966 + status = "disabled"; 967 + }; 968 + 969 + i2c8: i2c@c06f8000 { 970 + compatible = "renesas,i2c-r8a78000", 971 + "renesas,rcar-gen5-i2c"; 972 + reg = <0 0xc06f8000 0 0x40>; 973 + i2c-scl-internal-delay-ns = <110>; 974 + #address-cells = <1>; 975 + #size-cells = <0>; 976 + status = "disabled"; 977 + }; 978 + 979 + gpio0: gpio@c1080110 { 980 + compatible = "renesas,gpio-r8a78000", 981 + "renesas,rcar-gen5-gpio"; 982 + reg = <0 0xc1080110 0 0xc0>; 983 + #gpio-cells = <2>; 984 + gpio-controller; 985 + gpio-ranges = <&pfc 0 0 28>; 986 + }; 987 + 988 + gpio1: gpio@c1080910 { 989 + compatible = "renesas,gpio-r8a78000", 990 + "renesas,rcar-gen5-gpio"; 991 + reg = <0 0xc1080910 0 0xc0>; 992 + #gpio-cells = <2>; 993 + gpio-controller; 994 + gpio-ranges = <&pfc 0 32 22>; 995 + }; 996 + 997 + gpio2: gpio@c1081110 { 998 + compatible = "renesas,gpio-r8a78000", 999 + "renesas,rcar-gen5-gpio"; 1000 + reg = <0 0xc1081110 0 0xc0>; 1001 + #gpio-cells = <2>; 1002 + gpio-controller; 1003 + gpio-ranges = <&pfc 0 64 29>; 1004 + }; 1005 + 1006 + gpio3: gpio@c0800110 { 1007 + compatible = "renesas,gpio-r8a78000", 1008 + "renesas,rcar-gen5-gpio"; 1009 + reg = <0 0xc0800110 0 0xc0>; 1010 + #gpio-cells = <2>; 1011 + gpio-controller; 1012 + gpio-ranges = <&pfc 0 96 17>; 1013 + }; 1014 + 1015 + gpio4: gpio@c0800910 { 1016 + compatible = "renesas,gpio-r8a78000", 1017 + "renesas,rcar-gen5-gpio"; 1018 + reg = <0 0xc0800910 0 0xc0>; 1019 + #gpio-cells = <2>; 1020 + gpio-controller; 1021 + gpio-ranges = <&pfc 0 128 16>; 1022 + }; 1023 + 1024 + gpio5: gpio@c0400110 { 1025 + compatible = "renesas,gpio-r8a78000", 1026 + "renesas,rcar-gen5-gpio"; 1027 + reg = <0 0xc0400110 0 0xc0>; 1028 + #gpio-cells = <2>; 1029 + gpio-controller; 1030 + gpio-ranges = <&pfc 0 160 23>; 1031 + }; 1032 + 1033 + gpio6: gpio@c0400910 { 1034 + compatible = "renesas,gpio-r8a78000", 1035 + "renesas,rcar-gen5-gpio"; 1036 + reg = <0 0xc0400910 0 0xc0>; 1037 + #gpio-cells = <2>; 1038 + gpio-controller; 1039 + gpio-ranges = <&pfc 0 192 31>; 1040 + }; 1041 + 1042 + gpio7: gpio@c0401110 { 1043 + compatible = "renesas,gpio-r8a78000", 1044 + "renesas,rcar-gen5-gpio"; 1045 + reg = <0 0xc0401110 0 0xc0>; 1046 + #gpio-cells = <2>; 1047 + gpio-controller; 1048 + gpio-ranges = <&pfc 0 224 31>; 1049 + }; 1050 + 1051 + gpio8: gpio@c0401910 { 1052 + compatible = "renesas,gpio-r8a78000", 1053 + "renesas,rcar-gen5-gpio"; 1054 + reg = <0 0xc0401910 0 0xc0>; 1055 + #gpio-cells = <2>; 1056 + gpio-controller; 1057 + gpio-ranges = <&pfc 0 256 32>; 1058 + gpio-reserved-ranges = <16 10>; 1059 + }; 1060 + 1061 + gpio9: gpio@c9b00110 { 1062 + compatible = "renesas,gpio-r8a78000", 1063 + "renesas,rcar-gen5-gpio"; 1064 + reg = <0 0xc9b00110 0 0xc0>; 1065 + #gpio-cells = <2>; 1066 + gpio-controller; 1067 + gpio-ranges = <&pfc 0 288 17>; 1068 + }; 1069 + 1070 + gpio10: gpio@c9b00910 { 1071 + compatible = "renesas,gpio-r8a78000", 1072 + "renesas,rcar-gen5-gpio"; 1073 + reg = <0 0xc9b00910 0 0xc0>; 1074 + #gpio-cells = <2>; 1075 + gpio-controller; 1076 + gpio-ranges = <&pfc 0 320 14>; 1077 + }; 1078 + 1079 + mp_phy: mp_phy@c9a00000 { 1080 + compatible = "renesas,r8a78000-multi-protocol-phy"; 1081 + reg = <0 0xc9a00000 0 0x100000>; 1082 + #phy-cells = <2>; 1083 + clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY01>, 1084 + <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY11>, 1085 + <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY21>, 1086 + <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY31>, 1087 + <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY02>; 1088 + clock-names = "mpphy01", "mpphy11", "mpphy21", 1089 + "mpphy31", "mpphy02"; 1090 + power-domains = <&scmi_devpd X5H_POWER_DOMAIN_ID_MPP0>, 1091 + <&scmi_devpd X5H_POWER_DOMAIN_ID_MPP1>, 1092 + <&scmi_devpd X5H_POWER_DOMAIN_ID_MPP2>, 1093 + <&scmi_devpd X5H_POWER_DOMAIN_ID_MPP3>; 1094 + resets = <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY01>, 1095 + <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY11>, 1096 + <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY21>, 1097 + <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY31>, 1098 + <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY02>; 1099 + status = "disabled"; 1100 + }; 1101 + 1102 + rswitch3: ethernet@c9bc0000 { 1103 + compatible = "renesas,r8a78000-ether-switch3", 1104 + "renesas,etherswitch"; 1105 + reg = <0 0xc9bc0000 0 0x40000>, <0 0xc9b80000 0 0x240000>; 1106 + reg-names = "base", "secure_base"; 1107 + power-domains = <&scmi_devpd X5H_POWER_DOMAIN_ID_RSW>; 1108 + clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3>, 1109 + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSN>, 1110 + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3AES>, 1111 + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES0>, 1112 + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES1>, 1113 + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES2>, 1114 + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES3>, 1115 + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES4>, 1116 + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES5>, 1117 + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES6>, 1118 + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES7>, 1119 + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3MFWD>; 1120 + clock-names = "rsw3", "rsw3tsn", "rsw3aes", 1121 + "rsw3tsntes0", "rsw3tsntes1", "rsw3tsntes2", 1122 + "rsw3tsntes3", "rsw3tsntes4", "rsw3tsntes5", 1123 + "rsw3tsntes6", "rsw3tsntes7", "rsw3mfwd"; 1124 + status = "disabled"; 1125 + }; 1126 + 1127 + eth_pcs: phy@c9c50000 { 1128 + compatible = "renesas,r8a78000-ether-pcs"; 1129 + reg = <0 0xc9c50000 0 0x4000>; 1130 + #phy-cells = <1>; 1131 + clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS0>, 1132 + <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS1>, 1133 + <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS2>, 1134 + <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS3>, 1135 + <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS4>, 1136 + <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS5>, 1137 + <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS6>, 1138 + <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS7>; 1139 + clock-names = "xpcs0", "xpcs1", "xpcs2", "xpcs3", 1140 + "xpcs4", "xpcs5", "xpcs6", "xpcs7"; 1141 + resets = <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS0>, 1142 + <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS1>, 1143 + <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS2>, 1144 + <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS3>, 1145 + <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS4>, 1146 + <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS5>, 1147 + <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS6>, 1148 + <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS7>; 1149 + reset-names = "xpcs0", "xpcs1", "xpcs2", "xpcs3", 1150 + "xpcs4", "xpcs5", "xpcs6", "xpcs7"; 1151 + status = "disabled"; 1152 + }; 1153 + }; 1154 + 1155 + timer { 1156 + compatible = "arm,armv8-timer"; 1157 + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 1158 + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 1159 + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 1160 + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 1161 + <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 1162 + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 1163 + }; 1164 + };
+8
arch/arm/dts/socfpga-common-u-boot.dtsi
··· 5 5 * Copyright (c) 2019 Simon Goldschmidt 6 6 */ 7 7 /{ 8 + memory { 9 + bootph-all; 10 + }; 11 + 8 12 soc { 9 13 bootph-all; 10 14 }; 11 15 }; 12 16 13 17 &clkmgr { 18 + bootph-all; 19 + }; 20 + 21 + &L2 { 14 22 bootph-all; 15 23 }; 16 24
+26
arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi
··· 13 13 spi0 = "/soc/spi@ff705000"; 14 14 udc0 = &usb1; 15 15 }; 16 + 17 + leds { 18 + compatible = "gpio-leds"; 19 + 20 + led-0 { 21 + default-state = "off"; 22 + gpios = <&portb 20 GPIO_ACTIVE_HIGH>; 23 + }; 24 + 25 + led-1 { 26 + default-state = "off"; 27 + gpios = <&portb 25 GPIO_ACTIVE_HIGH>; 28 + label = "status_1"; 29 + }; 30 + 31 + led-2 { 32 + default-state = "off"; 33 + gpios = <&portb 26 GPIO_ACTIVE_HIGH>; 34 + label = "status_2"; 35 + }; 36 + 37 + led-3 { 38 + default-state = "off"; 39 + gpios = <&portc 7 GPIO_ACTIVE_HIGH>; 40 + }; 41 + }; 16 42 }; 17 43 18 44 &mmc {
+2 -2
arch/arm/include/asm/arch-imx9/imx91_pins.h
··· 329 329 MX91_PAD_ENET1_TD3__CAN2_TX = IOMUX_PAD(0x0250, 0x00A0, 0x02, 0x0000, 0x00, 0x00), 330 330 MX91_PAD_ENET1_TD3__HSIOMIX_OTG_ID2 = IOMUX_PAD(0x0250, 0x00A0, 0x03, 0x0000, 0x00, 0x00), 331 331 MX91_PAD_ENET1_TD3__FLEXIO2_FLEXIO2 = IOMUX_PAD(0x0250, 0x00A0, 0x04, 0x0000, 0x00, 0x00), 332 - MX91_PAD_ENET1_TD3__GPIO4_IO3 = IOMUX_PAD(0x0250, 0x00A0, 0x05, 0x0000, 0x00, 0x00), 332 + MX91_PAD_ENET1_TD3__GPIO4_IO2 = IOMUX_PAD(0x0250, 0x00A0, 0x05, 0x0000, 0x00, 0x00), 333 333 MX91_PAD_ENET1_TD3__LPI2C2_SCL = IOMUX_PAD(0x0250, 0x00A0, 0x06, 0x03E8, 0x00, 0x00), 334 334 335 335 MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 = IOMUX_PAD(0x0254, 0x00A4, 0x00, 0x0000, 0x00, 0x00), ··· 679 679 MX91_PAD_I2C2_SCL__LPUART2_DCB_B = IOMUX_PAD(0x0328, 0x0178, 0x02, 0x0000, 0x00, 0x00), 680 680 MX91_PAD_I2C2_SCL__TPM2_CH2 = IOMUX_PAD(0x0328, 0x0178, 0x03, 0x0000, 0x00, 0x00), 681 681 MX91_PAD_I2C2_SCL__SAI1_RX_SYNC = IOMUX_PAD(0x0328, 0x0178, 0x04, 0x0000, 0x00, 0x00), 682 - MX91_PAD_I2C2_SCL__GPIO1_IO3 = IOMUX_PAD(0x0328, 0x0178, 0x05, 0x0000, 0x00, 0x00), 682 + MX91_PAD_I2C2_SCL__GPIO1_IO2 = IOMUX_PAD(0x0328, 0x0178, 0x05, 0x0000, 0x00, 0x00), 683 683 MX91_PAD_I2C2_SCL__I3C1_PUR_B = IOMUX_PAD(0x0328, 0x0178, 0x06, 0x0000, 0x00, 0x00), 684 684 685 685 MX91_PAD_I2C2_SDA__LPI2C2_SDA = IOMUX_PAD(0x032C, 0x017C, 0x00, 0x03EC, 0x01, 0x00),
+10
arch/arm/mach-bcm283x/include/mach/gpio.h
··· 26 26 #define BCM2835_GPIO_FSEL_BANK(gpio) (gpio / 10) 27 27 #define BCM2835_GPIO_FSEL_SHIFT(gpio) ((gpio % 10) * 3) 28 28 29 + /* BCM2835 GPIO Pull-up/down register offsets */ 30 + #define BCM2835_GPPUD 37 31 + #define BCM2835_GPPUDCLK0 38 32 + 33 + /* BCM2711 GPIO Pull-up/down control */ 34 + #define BCM2711_GPPUD_CNTRL_REG0 57 35 + #define BCM2711_PUD_REG_OFFSET(gpio) ((gpio) / 16) 36 + #define BCM2711_PUD_REG_SHIFT(gpio) (((gpio) % 16) * 2) 37 + #define BCM2711_PUD_2711_MASK 0x3 38 + 29 39 struct bcm2835_gpio_regs { 30 40 u32 gpfsel[6]; 31 41 u32 reserved1;
+10 -1
arch/arm/mach-exynos/Kconfig
··· 2 2 3 3 config BOARD_COMMON 4 4 def_bool y 5 - depends on !TARGET_SMDKV310 && !TARGET_ARNDALE && !TARGET_E850_96 5 + depends on !TARGET_SMDKV310 && !TARGET_ARNDALE && !TARGET_EXYNOS_MOBILE && !TARGET_E850_96 6 6 7 7 config SPI_BOOTING 8 8 bool ··· 252 252 endchoice 253 253 endif 254 254 255 + config TARGET_EXYNOS_MOBILE 256 + bool "Samsung Exynos Generic Boards (for mobile devices)" 257 + select ARM64 258 + select BOARD_EARLY_INIT_F 259 + select CLK_EXYNOS 260 + select LINUX_KERNEL_IMAGE_HEADER 261 + select OF_CONTROL 262 + 255 263 config SYS_SOC 256 264 default "exynos" 257 265 ··· 277 285 source "board/samsung/espresso7420/Kconfig" 278 286 source "board/samsung/axy17lte/Kconfig" 279 287 source "board/samsung/e850-96/Kconfig" 288 + source "board/samsung/exynos-mobile/Kconfig" 280 289 281 290 endif
+12
arch/arm/mach-k3/r5/j722s/clk-data.c
··· 68 68 "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", 69 69 }; 70 70 71 + static const char * const main_emmcsd0_refclk_sel_out0_parents[] = { 72 + "postdiv4_16ff_main_0_hsdivout5_clk", 73 + "hsdiv4_16fft_main_2_hsdivout2_clk", 74 + }; 75 + 71 76 static const char * const main_emmcsd1_refclk_sel_out0_parents[] = { 72 77 "postdiv4_16ff_main_0_hsdivout5_clk", 73 78 "hsdiv4_16fft_main_2_hsdivout2_clk", ··· 102 107 "postdiv4_16ff_main_2_hsdivout6_clk", 103 108 "cpsw_3guss_am67_main_0_cpts_genf0", 104 109 "cpsw_3guss_am67_main_0_cpts_genf1", 110 + NULL, 111 + NULL, 105 112 NULL, 106 113 NULL, 107 114 NULL, ··· 205 212 CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0), 206 213 CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0), 207 214 CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0), 215 + CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0), 208 216 CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0), 209 217 CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0), 210 218 CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0), ··· 262 270 DEV_CLK(36, 10, "board_0_cp_gemac_cpts0_rft_clk_out"), 263 271 DEV_CLK(36, 11, "hsdiv4_16fft_main_1_hsdivout3_clk"), 264 272 DEV_CLK(36, 12, "postdiv4_16ff_main_2_hsdivout6_clk"), 273 + DEV_CLK(57, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), 274 + DEV_CLK(57, 2, "main_emmcsd0_refclk_sel_out0"), 275 + DEV_CLK(57, 3, "postdiv4_16ff_main_0_hsdivout5_clk"), 276 + DEV_CLK(57, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"), 265 277 DEV_CLK(36, 13, "cpsw_3guss_am67_main_0_cpts_genf0"), 266 278 DEV_CLK(36, 14, "cpsw_3guss_am67_main_0_cpts_genf1"), 267 279 DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"),
+26 -24
arch/arm/mach-k3/r5/j722s/dev-data.c
··· 23 23 24 24 static struct ti_lpsc soc_lpsc_list[] = { 25 25 [0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL), 26 - [1] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[4]), 27 - [2] = PSC_LPSC(13, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[4]), 28 - [3] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]), 29 - [4] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]), 30 - [5] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]), 31 - [6] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]), 32 - [7] = PSC_LPSC(42, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]), 33 - [8] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[6]), 34 - [9] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[8]), 35 - [10] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[6]), 36 - [11] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[10]), 37 - [12] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[11]), 26 + [1] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[5]), 27 + [2] = PSC_LPSC(13, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[5]), 28 + [3] = PSC_LPSC(20, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]), 29 + [4] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]), 30 + [5] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]), 31 + [6] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]), 32 + [7] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]), 33 + [8] = PSC_LPSC(42, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]), 34 + [9] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[7]), 35 + [10] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[9]), 36 + [11] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[7]), 37 + [12] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[11]), 38 + [13] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[12]), 38 39 }; 39 40 40 41 static struct ti_dev soc_dev_list[] = { ··· 43 44 PSC_DEV(61, &soc_lpsc_list[0]), 44 45 PSC_DEV(178, &soc_lpsc_list[1]), 45 46 PSC_DEV(179, &soc_lpsc_list[2]), 46 - PSC_DEV(58, &soc_lpsc_list[3]), 47 - PSC_DEV(161, &soc_lpsc_list[4]), 48 - PSC_DEV(75, &soc_lpsc_list[5]), 49 - PSC_DEV(36, &soc_lpsc_list[6]), 50 - PSC_DEV(102, &soc_lpsc_list[6]), 51 - PSC_DEV(146, &soc_lpsc_list[6]), 52 - PSC_DEV(13, &soc_lpsc_list[7]), 53 - PSC_DEV(166, &soc_lpsc_list[8]), 54 - PSC_DEV(135, &soc_lpsc_list[9]), 55 - PSC_DEV(170, &soc_lpsc_list[10]), 56 - PSC_DEV(177, &soc_lpsc_list[11]), 57 - PSC_DEV(55, &soc_lpsc_list[12]), 47 + PSC_DEV(57, &soc_lpsc_list[3]), 48 + PSC_DEV(58, &soc_lpsc_list[4]), 49 + PSC_DEV(161, &soc_lpsc_list[5]), 50 + PSC_DEV(75, &soc_lpsc_list[6]), 51 + PSC_DEV(36, &soc_lpsc_list[7]), 52 + PSC_DEV(102, &soc_lpsc_list[7]), 53 + PSC_DEV(146, &soc_lpsc_list[7]), 54 + PSC_DEV(13, &soc_lpsc_list[8]), 55 + PSC_DEV(166, &soc_lpsc_list[9]), 56 + PSC_DEV(135, &soc_lpsc_list[10]), 57 + PSC_DEV(170, &soc_lpsc_list[11]), 58 + PSC_DEV(177, &soc_lpsc_list[12]), 59 + PSC_DEV(55, &soc_lpsc_list[13]), 58 60 }; 59 61 60 62 const struct ti_k3_pd_platdata j722s_pd_platdata = {
+5
arch/arm/mach-renesas/Kconfig
··· 46 46 select RCAR_64 47 47 select PINCTRL_PFC 48 48 49 + config RCAR_GEN5 50 + bool "Renesas ARM SoCs R-Car Gen5 (64bit)" 51 + select RCAR_64 52 + select PINCTRL_PFC 53 + 49 54 config RZA1 50 55 prompt "Renesas ARM SoCs RZ/A1 (32bit)" 51 56 select CPU_V7A
+1
arch/arm/mach-renesas/Kconfig.64
··· 8 8 9 9 source "arch/arm/mach-renesas/Kconfig.rcar3" 10 10 source "arch/arm/mach-renesas/Kconfig.rcar4" 11 + source "arch/arm/mach-renesas/Kconfig.rcar5" 11 12 12 13 endif
+26
arch/arm/mach-renesas/Kconfig.rcar5
··· 1 + if RCAR_GEN5 2 + 3 + menu "Select Target SoC" 4 + 5 + config R8A78000 6 + bool "Renesas SoC R8A78000" 7 + select GICV3 8 + imply PINCTRL_PFC_R8A78000 9 + 10 + endmenu 11 + 12 + choice 13 + prompt "Renesas ARM64 SoCs board select" 14 + optional 15 + 16 + config TARGET_IRONHIDE 17 + bool "Ironhide board" 18 + imply R8A78000 19 + help 20 + Support for Renesas R-Car Gen5 Ironhide platform 21 + 22 + endchoice 23 + 24 + source "board/renesas/ironhide/Kconfig" 25 + 26 + endif
+1
arch/arm/mach-renesas/Makefile
··· 12 12 obj-$(CONFIG_RCAR_64) += lowlevel_init_gen3.o 13 13 obj-$(CONFIG_RCAR_GEN3) += cpu_info-rcar.o memmap-gen3.o 14 14 obj-$(CONFIG_RCAR_GEN4) += cpu_info-rcar.o memmap-gen3.o 15 + obj-$(CONFIG_RCAR_GEN5) += cpu_info-rcar.o memmap-gen3.o 15 16 obj-$(CONFIG_RZ_G2) += cpu_info-rzg.o 16 17 obj-$(CONFIG_RZG2L) += cpu_info-rzg2l.o memmap-rzg2l.o 17 18
+6 -2
arch/arm/mach-renesas/cpu_info-rcar.c
··· 15 15 16 16 static u32 renesas_get_prr(void) 17 17 { 18 - if (IS_ENABLED(CONFIG_RCAR_64)) 19 - return readl(0xFFF00044); 18 + if (IS_ENABLED(CONFIG_RCAR_64)) { 19 + if (IS_ENABLED(CONFIG_RCAR_GEN5)) 20 + return readl(0x189E0044); 21 + else 22 + return readl(0xFFF00044); 23 + } 20 24 21 25 return readl(0xFF000044); 22 26 }
+1
arch/arm/mach-renesas/cpu_info.c
··· 72 72 { RENESAS_CPU_TYPE_R8A779F0, "R8A779F0" }, 73 73 { RENESAS_CPU_TYPE_R8A779G0, "R8A779G0" }, 74 74 { RENESAS_CPU_TYPE_R8A779H0, "R8A779H0" }, 75 + { RMOBILE_CPU_TYPE_R8A78000, "R8A78000" }, 75 76 { 0x0, "CPU" }, 76 77 }; 77 78
+44
arch/arm/mach-renesas/include/mach/rcar-gen5-base.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0-only */ 2 + /* 3 + * Copyright (C) 2025 Renesas Electronics Corp. 4 + */ 5 + 6 + #ifndef __ASM_ARCH_RCAR_GEN5_BASE_H 7 + #define __ASM_ARCH_RCAR_GEN5_BASE_H 8 + 9 + /* 10 + * R-Car (R8A78000) I/O Addresses 11 + */ 12 + #define TMU_BASE 0x1C030000 13 + 14 + /* Arm Generic Timer */ 15 + #define CNTCR_BASE 0x1C000FFF /* Region 0 */ 16 + #define CNTFID0 (CNTCR_BASE + 0x020) 17 + #define CNTCR_EN BIT(0) 18 + 19 + /* Reset */ 20 + #define RST_BASE 0xC1320000 /* Domain0 */ 21 + #define RST_SWSRES1A (RST_BASE + 0x410) 22 + #define RST_WDTRSTCR (RST_BASE + 0x420) 23 + #define RST_RWDT_RSTMSK BIT(0) 24 + #define RST_WWDT_RSTMSK BIT(2) 25 + #define RST_RESKCPROT0 (RST_BASE + 0x4F0) 26 + #define RST_KCPROT_DIS 0xA5A5A501 27 + 28 + /* GICv4 */ 29 + /* Distributor Registers */ 30 + #define GICD_BASE 0x38000000 31 + #define GICR_BASE (GICR_LPI_BASE) 32 + 33 + /* ReDistributor Registers for Control and Physical LPIs */ 34 + #define GICR_LPI_BASE 0x38080000 35 + #define GICR_WAKER 0x0014 36 + #define GICR_PWRR 0x0024 37 + #define GICR_LPI_WAKER (GICR_LPI_BASE + GICR_WAKER) 38 + #define GICR_LPI_PWRR (GICR_LPI_BASE + GICR_PWRR) 39 + 40 + /* ReDistributor Registers for SGIs and PPIs */ 41 + #define GICR_SGI_BASE 0x38090000 42 + #define GICR_IGROUPR0 0x0080 43 + 44 + #endif /* __ASM_ARCH_RCAR_GEN5_BASE_H */
+3
arch/arm/mach-renesas/include/mach/renesas.h
··· 16 16 #include <asm/arch/rcar-gen3-base.h> 17 17 #elif defined(CONFIG_RCAR_GEN4) 18 18 #include <asm/arch/rcar-gen4-base.h> 19 + #elif defined(CONFIG_RCAR_GEN5) 20 + #include <asm/arch/rcar-gen5-base.h> 19 21 #elif defined(CONFIG_R7S72100) 20 22 #elif defined(CONFIG_RZG2L) 21 23 #include <asm/arch/rzg2l.h> ··· 42 44 #define RENESAS_CPU_TYPE_R8A779F0 0x5A 43 45 #define RENESAS_CPU_TYPE_R8A779G0 0x5C 44 46 #define RENESAS_CPU_TYPE_R8A779H0 0x5D 47 + #define RMOBILE_CPU_TYPE_R8A78000 0x60 45 48 #define RENESAS_CPU_TYPE_R9A07G044L 0x9A070440 46 49 47 50 #ifndef __ASSEMBLY__
+5
arch/arm/mach-renesas/psci-rcar64.c
··· 32 32 33 33 void __secure __noreturn psci_system_reset(void) 34 34 { 35 + #if defined(CONFIG_RCAR_GEN5) 36 + writel(RST_KCPROT_DIS, RST_RESKCPROT0); 37 + writel(0x1, RST_SWSRES1A); 38 + #else 35 39 writel(RST_SPRES, RST_SRESCR0); 40 + #endif 36 41 37 42 while (1) 38 43 ;
+48
arch/arm/mach-socfpga/config.mk
··· 1 + # SPDX-License-Identifier: GPL-2.0+ 2 + # 3 + # Brian Sune <briansune@gmail.com> 4 + 5 + ifeq ($(CONFIG_TARGET_SOCFPGA_CYCLONE5),y) 6 + archprepare: socfpga_g5_handoff_prepare 7 + else ifeq ($(CONFIG_TARGET_SOCFPGA_ARRIA5),y) 8 + archprepare: socfpga_g5_handoff_prepare 9 + endif 10 + 11 + socfpga_g5_handoff_prepare: 12 + @SOCFAMILY="$(SOCFAMILY)"; \ 13 + if [ -z "$$SOCFAMILY" ]; then \ 14 + exit 0; \ 15 + fi; \ 16 + echo "[INFO] SOC family detected: $$SOCFAMILY"; 17 + @set -- $$(awk -F'"' ' \ 18 + /^CONFIG_SYS_VENDOR=/ {v=$$2} \ 19 + /^CONFIG_SYS_BOARD=/ {b=$$2} \ 20 + END {print v, b}' .config); \ 21 + VENDOR=$$1; \ 22 + BOARD=$$2; \ 23 + if [ -z "$$VENDOR" ] || [ -z "$$BOARD" ]; then \ 24 + exit 0; \ 25 + fi; \ 26 + BOARD_DIR=$(src)/board/$$VENDOR/$$BOARD; \ 27 + if [ "$$HANDOFF_PATH" ]; then \ 28 + echo "[INFO] Using manually specified handoff folder: $$HANDOFF_PATH"; \ 29 + else \ 30 + HANDOFF_BASE=$$BOARD_DIR/hps_isw_handoff; \ 31 + if [ ! -d "$$HANDOFF_BASE" ]; then \ 32 + exit 0; \ 33 + fi; \ 34 + HANDOFF_PATH=$$(ls -d "$$HANDOFF_BASE"/*/ 2>/dev/null | head -n1); \ 35 + if [ -z "$$HANDOFF_PATH" ]; then \ 36 + exit 0; \ 37 + fi; \ 38 + echo "[INFO] Auto-detected handoff folder: $$HANDOFF_PATH"; \ 39 + fi; \ 40 + HIOF_FILE=$$HANDOFF_PATH/$$(basename $$HANDOFF_PATH).hiof; \ 41 + if [ ! -f "$$HIOF_FILE" ]; then \ 42 + echo "[WARN] No .hiof file found in $$HANDOFF_PATH, skipping BSP generation."; \ 43 + exit 0; \ 44 + fi; \ 45 + echo "[INFO] Found hiof file: $$HIOF_FILE"; \ 46 + echo "[INFO] Running BSP generator..."; \ 47 + python3 $(src)/tools/cv_bsp_generator/cv_bsp_generator.py -i "$$HANDOFF_PATH" -o "$$BOARD_DIR/qts" || echo "[WARN] BSP generator failed, continuing..."; \ 48 + echo "[DONE] SoCFPGA QTS handoff conversion complete."
+11 -2
arch/arm/mach-socfpga/misc.c
··· 222 222 } 223 223 224 224 U_BOOT_CMD(bridge, 3, 1, do_bridge, 225 - "SoCFPGA HPS FPGA bridge control", 225 + "GEN5 SoCFPGA HPS FPGA bridge control", 226 226 "enable [mask] - Enable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2) bridges\n" 227 227 "bridge disable [mask] - Disable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2) bridges\n" 228 228 "" ··· 261 261 if (ret) 262 262 hang(); 263 263 264 - else if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)) 264 + if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) && 265 + !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) && 266 + !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)) { 267 + ret = socfpga_get_base_addr("altr,sys-mgr", 268 + &socfpga_sysmgr_base); 269 + if (ret) 270 + hang(); 271 + } 272 + 273 + if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)) 265 274 ret = socfpga_get_base_addr("intel,n5x-clkmgr", 266 275 &socfpga_clkmgr_base); 267 276 else if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) &&
+33 -1
arch/arm/mach-socfpga/misc_gen5.c
··· 217 217 static struct socfpga_sdr_ctrl *sdr_ctrl = 218 218 (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS; 219 219 220 + void socfpga_sdram_apply_static_cfg(void) 221 + { 222 + const u32 applymask = 0x8; 223 + u32 val = readl(&sdr_ctrl->static_cfg) | applymask; 224 + 225 + /* 226 + * SDRAM staticcfg register specific: 227 + * When applying the register setting, the CPU must not access 228 + * SDRAM. Luckily for us, we can use i-cache here to help us 229 + * circumvent the SDRAM access issue. The idea is to make sure 230 + * that the code is in one full i-cache line by branching past 231 + * it and back. Once it is in the i-cache, we execute the core 232 + * of the code and apply the register settings. 233 + * 234 + * The code below uses 7 instructions, while the Cortex-A9 has 235 + * 32-byte cachelines, thus the limit is 8 instructions total. 236 + */ 237 + asm volatile(".align 5 \n" 238 + " b 2f \n" 239 + "1: str %0, [%1] \n" 240 + " dsb \n" 241 + " isb \n" 242 + " b 3f \n" 243 + "2: b 1b \n" 244 + "3: nop \n" 245 + : : "r"(val), "r"(&sdr_ctrl->static_cfg) : "memory", "cc"); 246 + } 247 + 220 248 void do_bridge_reset(int enable, unsigned int mask) 221 249 { 222 250 int i; ··· 234 262 writel(iswgrp_handoff[2], 235 263 socfpga_get_sysmgr_addr() + 236 264 SYSMGR_GEN5_FPGAINFGRP_MODULE); 237 - writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst); 265 + if (iswgrp_handoff[3]) { 266 + writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst); 267 + socfpga_sdram_apply_static_cfg(); 268 + } 238 269 writel(iswgrp_handoff[0], 239 270 socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST); 240 271 writel(iswgrp_handoff[1], &nic301_regs->remap); ··· 246 277 writel(0, socfpga_get_sysmgr_addr() + 247 278 SYSMGR_GEN5_FPGAINFGRP_MODULE); 248 279 writel(0, &sdr_ctrl->fpgaport_rst); 280 + socfpga_sdram_apply_static_cfg(); 249 281 writel(0x7, socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST); 250 282 writel(1, &nic301_regs->remap); 251 283 }
+2 -1
arch/sh/cpu/u-boot.lds
··· 72 72 73 73 __u_boot_list : { 74 74 KEEP(*(SORT(__u_boot_list*))); 75 + . = ALIGN(8); 75 76 } >ram 76 77 77 78 PROVIDE (__init_end = .); ··· 83 84 .bss : 84 85 { 85 86 *(.bss) 86 - . = ALIGN(4); 87 + . = ALIGN(8); 87 88 } >ram 88 89 PROVIDE (bss_end = .); 89 90 PROVIDE (__bss_end = .);
+2 -3
board/BuR/brppt1/MAINTAINERS
··· 1 1 BRPPT1 BOARD 2 - M: Wolfgang Wallner <wolfgang.wallner@br-automation.com> 2 + M: Wolfgang Wallner <wolfgang.wallner@at.abb.com> 3 3 S: Maintained 4 4 F: board/BuR/brppt1/ 5 5 F: board/BuR/common/ 6 6 F: include/configs/brppt1.h 7 7 F: configs/brppt1_mmc_defconfig 8 - F: configs/brppt1_nand_defconfig 9 - F: configs/brppt1_spi_defconfig 8 + F: arch/arm/dts/am335x-brppt1-mmc*
+2 -1
board/BuR/brppt2/MAINTAINERS
··· 1 1 BUR_PPT2 BOARD 2 - M: Wolfgang Wallner <wolfgang.wallner@br-automation.com> 2 + M: Wolfgang Wallner <wolfgang.wallner@at.abb.com> 3 3 S: Maintained 4 4 F: board/BuR/brppt2/ 5 5 F: board/BuR/common/ 6 6 F: include/configs/brppt2.h 7 7 F: configs/brppt2_defconfig 8 + F: arch/arm/dts/imx6dl-brppt2.dts
+2 -1
board/BuR/brsmarc1/MAINTAINERS
··· 1 1 BRSMARC1 BOARD 2 - M: Wolfgang Wallner <wolfgang.wallner@br-automation.com> 2 + M: Wolfgang Wallner <wolfgang.wallner@at.abb.com> 3 3 S: Maintained 4 4 F: board/BuR/brsmarc1/ 5 5 F: board/BuR/common/ 6 6 F: include/configs/brsmarc1.h 7 7 F: configs/brsmarc1_defconfig 8 + F: arch/arm/dts/am335x-brsmarc1.dts
+1 -1
board/BuR/brxre1/MAINTAINERS
··· 1 1 BRXRE1 BOARD 2 - M: Wolfgang Wallner <wolfgang.wallner@br-automation.com> 2 + M: Wolfgang Wallner <wolfgang.wallner@at.abb.com> 3 3 S: Maintained 4 4 F: board/BuR/brxre1/ 5 5 F: board/BuR/common/
+1 -1
board/BuR/zynq/MAINTAINERS
··· 1 1 ZYNQ BOARD 2 - M: Wolfgang Wallner <wolfgang.wallner@br-automation.com> 2 + M: Wolfgang Wallner <wolfgang.wallner@at.abb.com> 3 3 S: Maintained 4 4 F: board/BuR/zynq/ 5 5 F: board/BuR/common/
+1 -1
board/armltd/integrator/MAINTAINERS
··· 1 1 INTEGRATOR BOARD 2 - M: Linus Walleij <linus.walleij@linaro.org> 2 + M: Linus Walleij <linusw@kernel.org> 3 3 S: Maintained 4 4 F: board/armltd/integrator/ 5 5 F: include/configs/integratorcp.h
+3 -3
board/armltd/vexpress64/MAINTAINERS
··· 1 1 VEXPRESS64 PLATFORM 2 2 M: David Feng <fenghua@phytium.com.cn> 3 - M: Linus Walleij <linus.walleij@linaro.org> 3 + M: Linus Walleij <linusw@kernel.org> 4 4 M: Peter Hoyes <Peter.Hoyes@arm.com> 5 5 S: Maintained 6 6 F: board/armltd/vexpress64/ 7 7 F: include/configs/vexpress_aemv8.h 8 8 9 9 VEXPRESS_AEMV8A_SEMI BOARD 10 - M: Linus Walleij <linus.walleij@linaro.org> 10 + M: Linus Walleij <linusw@kernel.org> 11 11 S: Maintained 12 12 F: configs/vexpress_aemv8a_semi_defconfig 13 13 14 14 JUNO DEVELOPMENT PLATFORM BOARD 15 - M: Linus Walleij <linus.walleij@linaro.org> 15 + M: Linus Walleij <linusw@kernel.org> 16 16 S: Maintained 17 17 F: configs/vexpress_aemv8a_juno_defconfig 18 18
+1 -1
board/broadcom/bcmns/MAINTAINERS
··· 1 1 BCMNS BOARD 2 - M: Linus Walleij <linus.walleij@linaro.org> 2 + M: Linus Walleij <linusw@kernel.org> 3 3 S: Maintained 4 4 F: board/broadcom/bcmns/ 5 5 F: configs/bcmns_defconfig
+2 -1
board/raspberrypi/rpi/lowlevel_init.S
··· 16 16 17 17 /* The firmware provided ATAG/FDT address can be found in r2/x0 */ 18 18 #ifdef CONFIG_ARM64 19 - adr x8, fw_dtb_pointer 19 + adrp x8, fw_dtb_pointer 20 + add x8, x8, #:lo12:fw_dtb_pointer 20 21 str x0, [x8] 21 22 #else 22 23 ldr r8, =fw_dtb_pointer
+25 -8
board/raspberrypi/rpi/rpi.c
··· 3 3 * (C) Copyright 2012-2016 Stephen Warren 4 4 */ 5 5 6 + #define LOG_CATEGORY LOGC_BOARD 7 + 6 8 #include <config.h> 7 9 #include <dm.h> 8 10 #include <env.h> ··· 332 334 #ifdef CONFIG_OF_BOARD 333 335 int dram_init_banksize(void) 334 336 { 337 + phys_addr_t total_size = 0; 338 + int i; 335 339 int ret; 336 340 337 341 ret = fdtdec_setup_memory_banksize(); 338 342 if (ret) 339 343 return ret; 340 344 341 - return fdtdec_setup_mem_size_base(); 345 + ret = fdtdec_setup_mem_size_base(); 346 + if (ret) 347 + return ret; 348 + 349 + /* Update gd->ram_size to reflect total RAM across all banks */ 350 + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 351 + if (gd->bd->bi_dram[i].size == 0) 352 + break; 353 + total_size += gd->bd->bi_dram[i].size; 354 + } 355 + gd->ram_size = total_size; 356 + 357 + return 0; 342 358 } 343 359 #endif 344 360 ··· 354 370 } 355 371 356 372 /* 357 - * If the firmware provided a valid FDT at boot time, let's expose it in 358 - * ${fdt_addr} so it may be passed unmodified to the kernel. 373 + * Allow U-Boot to use its control FDT with extlinux if one is not provided. 374 + * This will then go through the usual fixups that U-Boot does, before being 375 + * handed off to Linux 359 376 */ 360 377 static void set_fdt_addr(void) 361 378 { 362 - if (fdt_magic(fw_dtb_pointer) != FDT_MAGIC) 363 - return; 364 - 365 - env_set_hex("fdt_addr", fw_dtb_pointer); 379 + env_set_hex("fdt_addr", (ulong)gd->fdt_blob); 366 380 } 367 381 368 382 /* ··· 608 622 { 609 623 int node; 610 624 611 - update_fdt_from_fw(blob, (void *)fw_dtb_pointer); 625 + if (blob == gd->fdt_blob) 626 + log_debug("Same FDT: nothing to do\n"); 627 + else 628 + update_fdt_from_fw(blob, (void *)gd->fdt_blob); 612 629 613 630 if (CONFIG_IS_ENABLED(FDT_SIMPLEFB)) { 614 631 node = fdt_node_offset_by_compatible(blob, -1, "simple-framebuffer");
+1 -1
board/renesas/MAINTAINERS
··· 6 6 N: r2dplus 7 7 N: r7s72100 8 8 N: r8a66597 9 - N: r8a77 9 + N: r8a7[78] 10 10 N: r9a0[0-9]g 11 11 N: rcar 12 12 N: renesas
+4
board/renesas/common/Makefile
··· 43 43 obj-y += gen4-common.o 44 44 endif 45 45 endif 46 + 47 + ifdef CONFIG_RCAR_GEN5 48 + obj-y += gen5-common.o 49 + endif 46 50 endif 47 51 48 52 endif
+75
board/renesas/common/gen5-common.c
··· 1 + // SPDX-License-Identifier: GPL-2.0-only 2 + /* 3 + * Copyright (C) 2025 Renesas Electronics Corp. 4 + */ 5 + 6 + #include <asm/arch/renesas.h> 7 + #include <asm/arch/sys_proto.h> 8 + #include <asm/global_data.h> 9 + #include <asm/io.h> 10 + #include <asm/mach-types.h> 11 + #include <asm/processor.h> 12 + #include <asm/system.h> 13 + #include <linux/errno.h> 14 + 15 + DECLARE_GLOBAL_DATA_PTR; 16 + 17 + static void init_generic_timer(void) 18 + { 19 + const u32 freq = CONFIG_SYS_CLK_FREQ; 20 + 21 + /* Update memory mapped and register based freqency */ 22 + asm volatile ("msr cntfrq_el0, %0" :: "r" (freq)); 23 + writel(freq, CNTFID0); 24 + 25 + /* Enable counter */ 26 + setbits_le32(CNTCR_BASE, CNTCR_EN); 27 + } 28 + 29 + static void init_gic_v3(void) 30 + { 31 + /* GIC v3 power on */ 32 + writel(BIT(1), GICR_LPI_PWRR); 33 + 34 + /* Wait till the WAKER_CA_BIT changes to 0 */ 35 + clrbits_le32(GICR_LPI_WAKER, BIT(1)); 36 + while (readl(GICR_LPI_WAKER) & BIT(2)) 37 + ; 38 + 39 + writel(0xffffffff, GICR_SGI_BASE + GICR_IGROUPR0); 40 + } 41 + 42 + void s_init(void) 43 + { 44 + if (current_el() == 3) 45 + init_generic_timer(); 46 + } 47 + 48 + int board_early_init_f(void) 49 + { 50 + return 0; 51 + } 52 + 53 + int board_init(void) 54 + { 55 + /* Allow WDT reset */ 56 + writel(RST_KCPROT_DIS, RST_RESKCPROT0); 57 + clrbits_le32(RST_WDTRSTCR, RST_WWDT_RSTMSK | RST_RWDT_RSTMSK); 58 + 59 + if (current_el() != 3) 60 + return 0; 61 + init_gic_v3(); 62 + 63 + return 0; 64 + } 65 + 66 + void __weak reset_cpu(void) 67 + { 68 + writel(RST_KCPROT_DIS, RST_RESKCPROT0); 69 + writel(0x1, RST_SWSRES1A); 70 + } 71 + 72 + int ft_board_setup(void *blob, struct bd_info *bd) 73 + { 74 + return 0; 75 + }
+15
board/renesas/ironhide/Kconfig
··· 1 + if TARGET_IRONHIDE 2 + 3 + config SYS_SOC 4 + default "renesas" 5 + 6 + config SYS_BOARD 7 + default "ironhide" 8 + 9 + config SYS_VENDOR 10 + default "renesas" 11 + 12 + config SYS_CONFIG_NAME 13 + default "ironhide" 14 + 15 + endif
+1 -1
board/samsung/e850-96/Makefile
··· 3 3 # Copyright (C) 2024, Linaro Limited 4 4 # Sam Protsenko <semen.protsenko@linaro.org> 5 5 6 - obj-y := e850-96.o fw.o acpm.o pmic.o 6 + obj-y := e850-96.o fw.o acpm.o pmic.o bootdev.o
+99
board/samsung/e850-96/bootdev.c
··· 1 + // SPDX-License-Identifier: GPL-2.0+ 2 + /* 3 + * Copyright (c) 2025 Linaro Ltd. 4 + * Author: Sam Protsenko <semen.protsenko@linaro.org> 5 + * 6 + * Routines for checking current boot device. 7 + */ 8 + 9 + #include <linux/arm-smccc.h> 10 + #include <vsprintf.h> 11 + #include "bootdev.h" 12 + 13 + /* Flag from BL2 bootloader in RAM */ 14 + #define BL2_TAG_ADDR 0x80000000 /* DRAM base */ 15 + #define BL2_TAG 0xabcdef 16 + 17 + /* Boot device info location in iRAM (only accessible from EL3) */ 18 + #define IRAM_BASE 0x02020000 19 + #define BOOTDEVICE_INFO_ADDR (IRAM_BASE + 0x64) 20 + 21 + /* SMC call for getting boot device information from EL3 monitor */ 22 + #define SMC_CMD_CHECK_SECOND_BOOT -233 23 + 24 + /* Boot device constants for the encoded boot device info value */ 25 + #define BD_NO_DEVICE 0x0 26 + #define BD_UFS 0x1 27 + #define BD_EMMC 0x2 28 + #define BD_ERROR 0x3 29 + #define BD_USB 0x4 30 + #define BD_SDMMC 0x5 31 + #define BD_UFS_CARD 0x6 32 + #define BD_SPI 0x7 33 + 34 + /* If BL2 bootloader wasn't executed, it means U-Boot is running via JTAG */ 35 + static bool bootdev_is_jtag_session(void) 36 + { 37 + u32 bl2_tag_val = *(u32 *)BL2_TAG_ADDR; 38 + 39 + return bl2_tag_val != BL2_TAG; 40 + } 41 + 42 + /* Obtain boot device information encoded in 32-bit value */ 43 + static u32 bootdev_get_info(void) 44 + { 45 + u32 info; 46 + 47 + /* 48 + * On regular boot U-Boot is executed by BL2 bootloader, and is running 49 + * in EL1 mode, so the boot device information has to be obtained via 50 + * SMC call from EL3 software (EL3 monitor), which can read that info 51 + * from the protected iRAM memory. If U-Boot is running via TRACE32 JTAG 52 + * (in EL3 mode), read the boot device info directly from iRAM, as EL3 53 + * software might not be available. 54 + */ 55 + if (bootdev_is_jtag_session()) { 56 + info = *(u32 *)BOOTDEVICE_INFO_ADDR; 57 + } else { 58 + struct arm_smccc_res res; 59 + 60 + arm_smccc_smc(SMC_CMD_CHECK_SECOND_BOOT, 0, 0, 0, 0, 0, 0, 0, 61 + &res); 62 + info = (u32)res.a2; 63 + } 64 + 65 + return info; 66 + } 67 + 68 + enum bootdev bootdev_get_current(void) 69 + { 70 + u32 info, magic, order, dev; 71 + 72 + info = bootdev_get_info(); 73 + magic = info >> 24; 74 + order = info & 0xf; 75 + dev = (info >> (4 * order)) & 0xf; 76 + 77 + if (magic != 0xcb) 78 + panic("Abnormal boot"); 79 + 80 + switch (dev) { 81 + case BD_UFS: 82 + return BOOTDEV_UFS; 83 + case BD_EMMC: 84 + return BOOTDEV_EMMC; 85 + case BD_USB: 86 + return BOOTDEV_USB; 87 + case BD_SDMMC: 88 + return BOOTDEV_SD; 89 + default: 90 + return BOOTDEV_ERROR; 91 + } 92 + 93 + return BOOTDEV_ERROR; 94 + } 95 + 96 + bool bootdev_is_usb(void) 97 + { 98 + return bootdev_get_current() == BOOTDEV_USB; 99 + }
+23
board/samsung/e850-96/bootdev.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0+ */ 2 + /* 3 + * Copyright (c) 2025 Linaro Ltd. 4 + * Sam Protsenko <semen.protsenko@linaro.org> 5 + */ 6 + 7 + #ifndef __E850_96_BOOTDEV_H 8 + #define __E850_96_BOOTDEV_H 9 + 10 + #include <stdbool.h> 11 + 12 + enum bootdev { 13 + BOOTDEV_ERROR, 14 + BOOTDEV_SD, 15 + BOOTDEV_EMMC, 16 + BOOTDEV_USB, 17 + BOOTDEV_UFS, 18 + }; 19 + 20 + enum bootdev bootdev_get_current(void); 21 + bool bootdev_is_usb(void); 22 + 23 + #endif /* __E850_96_BOOTDEV_H */
+57 -14
board/samsung/e850-96/e850-96.c
··· 11 11 #include <net.h> 12 12 #include <usb.h> 13 13 #include <asm/io.h> 14 + #include "bootdev.h" 14 15 #include "fw.h" 15 16 #include "pmic.h" 16 17 ··· 30 31 #define EMMC_IFNAME "mmc" 31 32 #define EMMC_DEV_NUM 0 32 33 #define EMMC_ESP_PART 1 34 + 35 + /* Firmware size */ 36 + #define LDFW_MAX_SIZE SZ_4M 37 + #define SP_MAX_SIZE SZ_1M 33 38 34 39 struct efi_fw_image fw_images[] = { 35 40 { ··· 77 82 .ipc_ch = EXYNOS850_IPC_AP_I3C, 78 83 }; 79 84 80 - int dram_init(void) 81 - { 82 - return fdtdec_setup_mem_size_base(); 83 - } 84 - 85 - int dram_init_banksize(void) 86 - { 87 - return fdtdec_setup_memory_banksize(); 88 - } 89 - 90 85 /* Read the unique SoC ID from OTP registers */ 91 86 static u64 get_chip_id(void) 92 87 { ··· 137 132 eth_env_set_enetaddr("ethaddr", mac_addr); 138 133 } 139 134 135 + static void load_firmware_usb(void) 136 + { 137 + int err; 138 + 139 + printf("Loading LDFW firmware (over USB)...\n"); 140 + err = load_image_usb(USB_DN_IMAGE_LDFW, LDFW_NWD_ADDR, LDFW_MAX_SIZE); 141 + if (err) { 142 + printf("ERROR: LDFW loading failed (%d)\n", err); 143 + return; 144 + } 145 + 146 + err = init_ldfw(LDFW_NWD_ADDR); 147 + if (err) { 148 + printf("ERROR: LDFW init failed (%d)\n", err); 149 + /* Do not return, still need to download SP */ 150 + } 151 + 152 + printf("Loading SP firmware (over USB)...\n"); 153 + err = load_image_usb(USB_DN_IMAGE_SP, LDFW_NWD_ADDR, SP_MAX_SIZE); 154 + if (err) 155 + printf("ERROR: SP loading failed (%d)\n", err); 156 + } 157 + 140 158 /* 141 159 * Call this in board_late_init() to avoid probing block devices before 142 160 * efi_init_early(). 143 161 */ 144 - void load_firmware(void) 162 + static void load_firmware_blk(void) 145 163 { 146 164 const char *ifname; 147 165 ulong dev, part; ··· 161 179 } 162 180 163 181 printf("Loading LDFW firmware (from %s %ld)...\n", ifname, dev); 164 - err = load_ldfw(ifname, dev, part, LDFW_NWD_ADDR); 182 + err = load_ldfw_from_blk(ifname, dev, part, LDFW_NWD_ADDR); 183 + if (err) { 184 + printf("ERROR: LDFW loading failed (%d)\n", err); 185 + return; 186 + } 187 + err = init_ldfw(LDFW_NWD_ADDR); 165 188 if (err) 166 - printf("ERROR: LDFW loading failed (%d)\n", err); 189 + printf("ERROR: LDFW init failed (%d)\n", err); 190 + } 191 + 192 + int dram_init(void) 193 + { 194 + return fdtdec_setup_mem_size_base(); 195 + } 196 + 197 + int dram_init_banksize(void) 198 + { 199 + return fdtdec_setup_memory_banksize(); 167 200 } 168 201 169 202 int board_late_init(void) 170 203 { 171 204 setup_serial(); 172 205 setup_ethaddr(); 173 - load_firmware(); 206 + 207 + if (bootdev_is_usb()) 208 + load_firmware_usb(); 209 + else 210 + load_firmware_blk(); 211 + 212 + if (bootdev_is_usb()) { 213 + env_set("bootcmd", "echo \"Entering DFU mode...\"; " 214 + "dfu 0 mmc 0"); 215 + env_set("bootdelay", "0"); 216 + } 174 217 175 218 return 0; 176 219 }
+57 -19
board/samsung/e850-96/fw.c
··· 11 11 #include <linux/arm-smccc.h> 12 12 #include "fw.h" 13 13 14 - #define LDFW_RAW_PART "ldfw" 15 - #define LDFW_FAT_PATH "/EFI/firmware/ldfw.bin" 14 + #define LDFW_RAW_PART "ldfw" 15 + #define LDFW_FAT_PATH "/EFI/firmware/ldfw.bin" 16 + #define LDFW_MAGIC 0x10adab1e 17 + 18 + /* SMC command for providing LDFW to EL3 monitor */ 19 + #define SMC_CMD_LOAD_LDFW -0x500 20 + /* SMC command for loading some binary over USB */ 21 + #define SMC_CMD_LOAD_IMAGE_BY_USB -0x512 16 22 17 - #define LDFW_MAGIC 0x10adab1e 18 - #define SMC_CMD_LOAD_LDFW -0x500 19 - #define SDM_HW_RESET_STATUS 0x1230 20 - #define SDM_SW_RESET_STATUS 0x1231 21 - #define SB_ERROR_PREFIX 0xfdaa0000 23 + /* Error codes for SMC_CMD_LOAD_LDFW */ 24 + #define SDM_HW_RESET_STATUS 0x1230 25 + #define SDM_SW_RESET_STATUS 0x1231 26 + #define SB_ERROR_PREFIX 0xfdaa0000 22 27 23 28 struct ldfw_header { 24 29 u32 magic; ··· 94 99 } 95 100 96 101 /** 97 - * load_ldfw - Load the loadable firmware (LDFW) 102 + * load_image_usb - Load some binary over USB during USB boot 103 + * @type: Image type 104 + * @addr: Memory address where the image should be downloaded to 105 + * @size: Image size 106 + * 107 + * Return: 0 on success or a negative value on error. 108 + */ 109 + int load_image_usb(enum usb_dn_image type, phys_addr_t addr, phys_size_t size) 110 + { 111 + struct arm_smccc_res res; 112 + 113 + arm_smccc_smc(SMC_CMD_LOAD_IMAGE_BY_USB, (u64)type, addr, size, 114 + 0, 0, 0, 0, &res); 115 + if (res.a0) 116 + return -EIO; 117 + 118 + return 0; 119 + } 120 + 121 + /** 122 + * load_ldfw_from_blk - Load the loadable firmware (LDFW) from block device 98 123 * @ifname: Interface name of the block device to load the firmware from 99 124 * @dev: Device number 100 125 * @part: Partition number ··· 102 127 * 103 128 * Return: 0 on success or a negative value on error. 104 129 */ 105 - int load_ldfw(const char *ifname, int dev, int part, phys_addr_t addr) 130 + int load_ldfw_from_blk(const char *ifname, int dev, int part, phys_addr_t addr) 131 + { 132 + void *buf = (void *)addr; 133 + int err; 134 + 135 + /* First try to read LDFW from EFI partition, then from the raw one */ 136 + err = read_fw_from_fat(ifname, dev, part, LDFW_FAT_PATH, buf); 137 + if (err) 138 + return read_fw_from_raw(ifname, dev, LDFW_RAW_PART, buf); 139 + 140 + return 0; 141 + } 142 + 143 + /** 144 + * init_ldfw - Provide the LDFW (loaded to RAM) to EL3 monitor to make use of it 145 + * @addr: Memory address where LDFW resides 146 + * 147 + * EL3 monitor will copy the LDFW from the provided Normal World memory @addr to 148 + * Secure World location, and start using it. 149 + * 150 + * Return: 0 on success or a negative value on error. 151 + */ 152 + int init_ldfw(phys_addr_t addr) 106 153 { 107 154 struct ldfw_header *hdr; 108 155 struct arm_smccc_res res; 109 - void *buf = (void *)addr; 110 156 u64 size = 0; 111 157 int err, i; 112 158 113 - /* First try to read LDFW from EFI partition, then from the raw one */ 114 - err = read_fw_from_fat(ifname, dev, part, LDFW_FAT_PATH, buf); 115 - if (err) { 116 - err = read_fw_from_raw(ifname, dev, LDFW_RAW_PART, buf); 117 - if (err) 118 - return err; 119 - } 120 - 121 159 /* Validate LDFW by magic number in its header */ 122 - hdr = buf; 160 + hdr = (struct ldfw_header *)addr; 123 161 if (hdr->magic != LDFW_MAGIC) { 124 162 debug("%s: Wrong LDFW magic; is LDFW flashed?\n", __func__); 125 163 return -EINVAL;
+9 -1
board/samsung/e850-96/fw.h
··· 9 9 10 10 #include <asm/types.h> 11 11 12 - int load_ldfw(const char *ifname, int dev, int part, phys_addr_t addr); 12 + /* Image types for downloading over USB */ 13 + enum usb_dn_image { 14 + USB_DN_IMAGE_LDFW = 1, /* Loadable Firmware */ 15 + USB_DN_IMAGE_SP = 2, /* Secure Payload (tzsw.img) */ 16 + }; 17 + 18 + int load_image_usb(enum usb_dn_image type, phys_addr_t addr, phys_size_t size); 19 + int load_ldfw_from_blk(const char *ifname, int dev, int part, phys_addr_t addr); 20 + int init_ldfw(phys_addr_t addr); 13 21 14 22 #endif /* __E850_96_FW_H */
+18
board/samsung/exynos-mobile/Kconfig
··· 1 + if TARGET_EXYNOS_MOBILE 2 + 3 + config ENV_SOURCE_FILE 4 + default "exynos-mobile" 5 + 6 + config LNX_KRNL_IMG_TEXT_OFFSET_BASE 7 + default TEXT_BASE 8 + 9 + config SYS_BOARD 10 + default "exynos-mobile" 11 + 12 + config SYS_CONFIG_NAME 13 + default "exynos-mobile" 14 + 15 + config SYS_VENDOR 16 + default "samsung" 17 + 18 + endif # TARGET_EXYNOS_MOBILE
+6
board/samsung/exynos-mobile/MAINTAINERS
··· 1 + Exynos Generic Boards (for mobile devices) 2 + M: Kaustabh Chakraborty <kauschluss@disroot.org> 3 + S: Maintained 4 + F: board/samsung/exynos-mobile/ 5 + F: configs/exynos-mobile_defconfig 6 + F: include/configs/exynos-mobile.h
+5
board/samsung/exynos-mobile/Makefile
··· 1 + # SPDX-License-Identifier: GPL-2.0 2 + # 3 + # Copyright (C) 2025 Kaustabh Chakraborty <kauschluss@disroot.org> 4 + 5 + obj-y := exynos-mobile.o
+7
board/samsung/exynos-mobile/debug-exynos7870.config
··· 1 + CONFIG_DEBUG_UART=y 2 + CONFIG_DEBUG_UART_BASE=0x13820000 3 + CONFIG_DEBUG_UART_CLOCK=133250000 4 + CONFIG_DEBUG_UART_S5P=y 5 + CONFIG_LOG=y 6 + CONFIG_LOG_CONSOLE=y 7 + CONFIG_LOG_MAX_LEVEL=8
+403
board/samsung/exynos-mobile/exynos-mobile.c
··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * Samsung Exynos Generic Board Source (for mobile devices) 4 + * 5 + * Copyright (c) 2025 Kaustabh Chakraborty <kauschluss@disroot.org> 6 + */ 7 + 8 + #include <asm/armv8/mmu.h> 9 + #include <blk.h> 10 + #include <bootflow.h> 11 + #include <ctype.h> 12 + #include <dm/ofnode.h> 13 + #include <env.h> 14 + #include <errno.h> 15 + #include <init.h> 16 + #include <limits.h> 17 + #include <linux/sizes.h> 18 + #include <lmb.h> 19 + #include <part.h> 20 + #include <stdbool.h> 21 + 22 + DECLARE_GLOBAL_DATA_PTR; 23 + 24 + #define lmb_alloc(size, addr) \ 25 + lmb_alloc_mem(LMB_MEM_ALLOC_ANY, SZ_2M, addr, size, LMB_NONE) 26 + 27 + struct exynos_board_info { 28 + const char *name; 29 + const char *chip; 30 + const u64 *const dram_bank_bases; 31 + 32 + char serial[64]; 33 + 34 + int (*const match)(struct exynos_board_info *); 35 + const char *match_model; 36 + const u8 match_max_rev; 37 + }; 38 + 39 + /* 40 + * The memory mapping includes all DRAM banks, along with the 41 + * peripheral block, and a sentinel at the end. This is filled in 42 + * dynamically. 43 + */ 44 + static struct mm_region exynos_mem_map[CONFIG_NR_DRAM_BANKS + 2] = { 45 + { 46 + /* Peripheral MMIO block */ 47 + .virt = 0x10000000UL, 48 + .phys = 0x10000000UL, 49 + .size = 0x10000000UL, 50 + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 51 + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN, 52 + }, 53 + }; 54 + 55 + struct mm_region *mem_map = exynos_mem_map; 56 + 57 + static const u64 exynos7870_common_dram_bank_bases[CONFIG_NR_DRAM_BANKS] = { 58 + 0x40000000, 0x80000000, 0x100000000, 59 + }; 60 + 61 + static const char *exynos_prev_bl_get_bootargs(void) 62 + { 63 + void *prev_bl_fdt_base = (void *)get_prev_bl_fdt_addr(); 64 + int chosen_node_offset, ret; 65 + const struct fdt_property *bootargs_prop; 66 + 67 + ret = fdt_check_header(prev_bl_fdt_base); 68 + if (ret < 0) { 69 + log_err("%s: FDT is invalid (FDT_ERR %d)\n", __func__, ret); 70 + return NULL; 71 + } 72 + 73 + ret = fdt_path_offset(prev_bl_fdt_base, "/chosen"); 74 + chosen_node_offset = ret; 75 + if (ret < 0) { 76 + log_err("%s: /chosen node not found (FDT_ERR %d)\n", __func__, 77 + ret); 78 + return NULL; 79 + } 80 + 81 + bootargs_prop = fdt_get_property(prev_bl_fdt_base, chosen_node_offset, 82 + "bootargs", &ret); 83 + if (!bootargs_prop) { 84 + log_err("%s: /chosen/bootargs property not found (FDT_ERR %d)\n", 85 + __func__, ret); 86 + return NULL; 87 + } 88 + 89 + return bootargs_prop->data; 90 + } 91 + 92 + static int exynos7870_fdt_match(struct exynos_board_info *board_info) 93 + { 94 + const char *prev_bl_bootargs; 95 + int val, ret; 96 + 97 + prev_bl_bootargs = exynos_prev_bl_get_bootargs(); 98 + if (!prev_bl_bootargs) 99 + return -1; 100 + 101 + /* 102 + * Read the cmdline property which stores the 103 + * bootloader/firmware version. An example value of the option 104 + * can be: "J600GDXU3ARH5". This can be used to verify the model 105 + * of the device. 106 + */ 107 + ret = cmdline_get_arg(prev_bl_bootargs, "androidboot.bootloader", &val); 108 + if (ret < 0) { 109 + log_err("%s: unable to find property for bootloader version (%d)\n", 110 + __func__, ret); 111 + return -1; 112 + } 113 + 114 + if (strncmp(prev_bl_bootargs + val, board_info->match_model, 115 + strlen(board_info->match_model))) 116 + return -1; 117 + 118 + /* 119 + * Read the cmdline property which stores the hardware revision. 120 + * This is required to allow selecting one of multiple dtbs 121 + * available of a single device, varying in hardware changes in 122 + * different revisions. 123 + */ 124 + ret = cmdline_get_arg(prev_bl_bootargs, "androidboot.revision", &val); 125 + if (ret < 0) 126 + ret = cmdline_get_arg(prev_bl_bootargs, "androidboot.hw_rev", &val); 127 + if (ret < 0) { 128 + log_err("%s: unable to find property for bootloader revision (%d)\n", 129 + __func__, ret); 130 + return -1; 131 + } 132 + 133 + if (strtoul(prev_bl_bootargs + val, NULL, 10) > board_info->match_max_rev) 134 + return -1; 135 + 136 + /* 137 + * Read the cmdline property which stores the serial number. 138 + * Store this in the board info struct. 139 + */ 140 + ret = cmdline_get_arg(prev_bl_bootargs, "androidboot.serialno", &val); 141 + if (ret > 0) 142 + strlcpy(board_info->serial, prev_bl_bootargs + val, ret); 143 + 144 + return 0; 145 + } 146 + 147 + /* 148 + * This array is used for matching the models and revisions with the 149 + * devicetree used by U-Boot. This allows a single U-Boot to work on 150 + * multiple devices. 151 + * 152 + * Entries are kept in lexicographical order of board SoCs, followed by 153 + * board names. 154 + */ 155 + static struct exynos_board_info exynos_board_info_match[] = { 156 + { 157 + /* Samsung Galaxy A2 Core */ 158 + .name = "a2corelte", 159 + .chip = "exynos7870", 160 + .dram_bank_bases = exynos7870_common_dram_bank_bases, 161 + .match = exynos7870_fdt_match, 162 + .match_model = "A260", 163 + .match_max_rev = U8_MAX, 164 + }, { 165 + /* Samsung Galaxy J6 */ 166 + .name = "j6lte", 167 + .chip = "exynos7870", 168 + .dram_bank_bases = exynos7870_common_dram_bank_bases, 169 + .match = exynos7870_fdt_match, 170 + .match_model = "J600", 171 + .match_max_rev = U8_MAX, 172 + }, { 173 + /* Samsung Galaxy J7 Prime */ 174 + .name = "on7xelte", 175 + .chip = "exynos7870", 176 + .dram_bank_bases = exynos7870_common_dram_bank_bases, 177 + .match = exynos7870_fdt_match, 178 + .match_model = "G610", 179 + .match_max_rev = U8_MAX, 180 + }, 181 + }; 182 + 183 + static void exynos_parse_dram_banks(const struct exynos_board_info *board_info, 184 + const void *fdt_base) 185 + { 186 + u64 mem_addr, mem_size = 0; 187 + u32 na, ns, i, j; 188 + int offset; 189 + 190 + if (fdt_check_header(fdt_base) < 0) 191 + return; 192 + 193 + /* #address-cells and #size-cells as defined in the fdt root. */ 194 + na = fdt_address_cells(fdt_base, 0); 195 + ns = fdt_size_cells(fdt_base, 0); 196 + 197 + fdt_for_each_subnode(offset, fdt_base, 0) { 198 + if (strncmp(fdt_get_name(fdt_base, offset, NULL), "memory", 6)) 199 + continue; 200 + 201 + for (i = 0; ; i++) { 202 + mem_addr = fdtdec_get_addr_size_fixed(fdt_base, offset, 203 + "reg", i, na, ns, 204 + &mem_size, false); 205 + if (mem_addr == FDT_ADDR_T_NONE) 206 + break; 207 + 208 + if (!mem_size) 209 + continue; 210 + 211 + for (j = 0; j < CONFIG_NR_DRAM_BANKS; j++) { 212 + if (board_info->dram_bank_bases[j] != mem_addr) 213 + continue; 214 + 215 + mem_map[j + 1].phys = mem_addr; 216 + mem_map[j + 1].virt = mem_addr; 217 + mem_map[j + 1].size = mem_size; 218 + mem_map[j + 1].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 219 + PTE_BLOCK_INNER_SHARE; 220 + break; 221 + } 222 + } 223 + } 224 + } 225 + 226 + static int exynos_fastboot_setup(void) 227 + { 228 + struct blk_desc *blk_dev; 229 + struct disk_partition info = {0}; 230 + char buf[128]; 231 + phys_addr_t addr; 232 + int offset, i, j; 233 + 234 + /* Allocate and define buffer address for fastboot interface. */ 235 + if (lmb_alloc(CONFIG_FASTBOOT_BUF_SIZE, &addr)) { 236 + log_err("%s: failed to allocate fastboot buffer\n", __func__); 237 + return -ENOMEM; 238 + } 239 + env_set_hex("fastboot_addr_r", addr); 240 + 241 + blk_dev = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV); 242 + if (!blk_dev) { 243 + log_err("%s: required mmc device not available\n", __func__); 244 + return -ENODEV; 245 + } 246 + 247 + strcpy(buf, "fastboot_partition_alias_"); 248 + offset = strlen(buf); 249 + 250 + for (i = 1; i < CONFIG_EFI_PARTITION_ENTRIES_NUMBERS; i++) { 251 + if (part_get_info(blk_dev, i, &info)) 252 + continue; 253 + 254 + /* 255 + * The partition name must be lowercase (stored in buf[]), 256 + * as is expected in all fastboot partitions ... 257 + */ 258 + strlcpy(buf + offset, info.name, sizeof(buf) - offset); 259 + for (j = offset; buf[j]; j++) 260 + buf[j] = tolower(buf[j]); 261 + if (!strcmp(buf + offset, info.name)) 262 + continue; 263 + /* 264 + * ... However, if that isn't the case, a fastboot 265 + * partition alias must be defined to establish it. 266 + */ 267 + env_set(buf, info.name); 268 + } 269 + 270 + return 0; 271 + } 272 + 273 + int board_fit_config_name_match(const char *name) 274 + { 275 + struct exynos_board_info *board_info; 276 + char buf[128]; 277 + unsigned int i; 278 + int ret; 279 + 280 + /* 281 + * Iterate over exynos_board_info_match[] to select the 282 + * appropriate board info struct. If not found, exit. 283 + */ 284 + for (i = 0; i < ARRAY_SIZE(exynos_board_info_match); i++) { 285 + board_info = exynos_board_info_match + i; 286 + snprintf(buf, sizeof(buf), "%s-%s", board_info->chip, 287 + board_info->name); 288 + 289 + if (!strcmp(name, buf)) 290 + break; 291 + } 292 + if (i == ARRAY_SIZE(exynos_board_info_match)) 293 + return -1; 294 + 295 + /* 296 + * Execute match logic for the target board. This is separated 297 + * as the process may be different for multiple boards. 298 + */ 299 + ret = board_info->match(board_info); 300 + if (ret) 301 + return ret; 302 + 303 + /* 304 + * Store the correct board info struct in gd->board_type to 305 + * allow other functions to access it. 306 + */ 307 + gd->board_type = (ulong)board_info; 308 + log_debug("%s: device detected: %s\n", __func__, name); 309 + 310 + return 0; 311 + } 312 + 313 + int timer_init(void) 314 + { 315 + ofnode timer_node; 316 + 317 + /* 318 + * In a lot of Exynos devices, the previous bootloader does not 319 + * set CNTFRQ_EL0 properly. However, the timer node in 320 + * devicetree has the correct frequency, use that instead. 321 + */ 322 + timer_node = ofnode_by_compatible(ofnode_null(), "arm,armv8-timer"); 323 + gd->arch.timer_rate_hz = ofnode_read_u32_default(timer_node, 324 + "clock-frequency", 0); 325 + 326 + return 0; 327 + } 328 + 329 + int board_early_init_f(void) 330 + { 331 + const struct exynos_board_info *board_info; 332 + 333 + if (!gd->board_type) 334 + return -ENODATA; 335 + board_info = (const struct exynos_board_info *)gd->board_type; 336 + 337 + exynos_parse_dram_banks(board_info, gd->fdt_blob); 338 + /* 339 + * Some devices have multiple variants based on the amount of 340 + * memory and internal storage. The lowest bank base has been 341 + * observed to have the same memory range in all board variants. 342 + * For variants with more memory, the previous bootloader should 343 + * overlay the devicetree with the required extra memory ranges. 344 + */ 345 + exynos_parse_dram_banks(board_info, (const void *)get_prev_bl_fdt_addr()); 346 + 347 + return 0; 348 + } 349 + 350 + int dram_init(void) 351 + { 352 + unsigned int i; 353 + 354 + /* Select the largest RAM bank for U-Boot. */ 355 + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 356 + if (gd->ram_size < mem_map[i + 1].size) { 357 + gd->ram_base = mem_map[i + 1].phys; 358 + gd->ram_size = mem_map[i + 1].size; 359 + } 360 + } 361 + 362 + return 0; 363 + } 364 + 365 + int dram_init_banksize(void) 366 + { 367 + unsigned int i; 368 + 369 + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 370 + gd->bd->bi_dram[i].start = mem_map[i + 1].phys; 371 + gd->bd->bi_dram[i].size = mem_map[i + 1].size; 372 + } 373 + 374 + return 0; 375 + } 376 + 377 + int board_init(void) 378 + { 379 + return 0; 380 + } 381 + 382 + int misc_init_r(void) 383 + { 384 + const struct exynos_board_info *board_info; 385 + char buf[128]; 386 + 387 + if (!gd->board_type) 388 + return -ENODATA; 389 + board_info = (const struct exynos_board_info *)gd->board_type; 390 + 391 + env_set("platform", board_info->chip); 392 + env_set("board", board_info->name); 393 + 394 + if (strlen(board_info->serial)) 395 + env_set("serial#", board_info->serial); 396 + 397 + /* EFI booting requires the path to correct dtb, specify it here. */ 398 + snprintf(buf, sizeof(buf), "exynos/%s-%s.dtb", board_info->chip, 399 + board_info->name); 400 + env_set("fdtfile", buf); 401 + 402 + return exynos_fastboot_setup(); 403 + }
+18
board/samsung/exynos-mobile/exynos-mobile.env
··· 1 + stdin=serial,button-kbd 2 + stdout=serial,vidconsole 3 + stderr=serial,vidconsole 4 + 5 + bootdelay=0 6 + bootcmd=bootefi bootmgr; pause; bootmenu 7 + 8 + fastbootcmd=echo "Fastboot Mode"; 9 + fastboot -l $fastboot_addr_r usb 0 10 + 11 + bootmenu_0=Continue Boot=boot 12 + bootmenu_1=Enter Fastboot Mode=run fastbootcmd 13 + bootmenu_2=UEFI Maintenance Menu=eficonfig 14 + bootmenu_3=Reboot=reset 15 + bootmenu_4=Power Off=poweroff 16 + 17 + button_cmd_0_name=Volume Down Key 18 + button_cmd_0=bootmenu
+9 -3
board/softing/vining_fpga/socfpga.c
··· 8 8 #include <env.h> 9 9 #include <init.h> 10 10 #include <net.h> 11 - #include <status_led.h> 11 + #include <led.h> 12 12 #include <asm/arch/reset_manager.h> 13 13 #include <asm/global_data.h> 14 14 #include <asm/io.h> ··· 24 24 int board_late_init(void) 25 25 { 26 26 const unsigned int usb_nrst_gpio = 35; 27 + struct udevice *dev; 27 28 int ret; 28 29 29 - status_led_set(1, CONFIG_LED_STATUS_ON); 30 - status_led_set(2, CONFIG_LED_STATUS_ON); 30 + ret = led_get_by_label("status_1", &dev); 31 + if (!ret) 32 + led_set_state(dev, LEDST_ON); 33 + 34 + ret = led_get_by_label("status_2", &dev); 35 + if (!ret) 36 + led_set_state(dev, LEDST_ON); 31 37 32 38 /* Address of boot parameters for ATAG (if ATAG is used) */ 33 39 gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
+1 -1
board/ti/am335x/board.c
··· 429 429 { 430 430 int sil_rev, mpu_vdd; 431 431 432 - if (!IS_ENABLED(CONFIG_DM_PMIC_TPS65910)) 432 + if (!IS_ENABLED(CONFIG_SPL_POWER_TPS65910)) 433 433 return; 434 434 435 435 /*
+7 -2
board/ti/am62x/evm.c
··· 82 82 }; 83 83 84 84 #if CONFIG_IS_ENABLED(TI_I2C_BOARD_DETECT) 85 + int do_board_detect(void) 86 + { 87 + return do_board_detect_am6(); 88 + } 89 + 85 90 int checkboard(void) 86 91 { 87 92 struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA; 88 93 89 - if (!do_board_detect_am6()) 94 + if (!do_board_detect()) 90 95 printf("Board: %s rev %s\n", ep->name, ep->version); 91 96 92 97 return 0; ··· 97 102 { 98 103 char *name = "am62x_skevm"; 99 104 100 - if (do_board_detect_am6()) 105 + if (do_board_detect()) 101 106 goto invalid_eeprom; 102 107 103 108 if (board_is_am62x_skevm())
+7 -2
board/ti/am64x/evm.c
··· 114 114 #endif 115 115 116 116 #ifdef CONFIG_TI_I2C_BOARD_DETECT 117 + int do_board_detect(void) 118 + { 119 + return do_board_detect_am6(); 120 + } 121 + 117 122 int checkboard(void) 118 123 { 119 124 struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA; 120 125 121 - if (!do_board_detect_am6()) 126 + if (!do_board_detect()) 122 127 printf("Board: %s rev %s\n", ep->name, ep->version); 123 128 124 129 return 0; ··· 135 140 { 136 141 char *name = "am64x_gpevm"; 137 142 138 - if (do_board_detect_am6()) 143 + if (do_board_detect()) 139 144 goto invalid_eeprom; 140 145 141 146 if (board_is_am64x_gpevm())
+7 -2
board/ti/am65x/evm.c
··· 72 72 #endif 73 73 74 74 #ifdef CONFIG_TI_I2C_BOARD_DETECT 75 + int do_board_detect(void) 76 + { 77 + return do_board_detect_am6(); 78 + } 79 + 75 80 int checkboard(void) 76 81 { 77 82 struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA; 78 83 79 - if (do_board_detect_am6()) 84 + if (do_board_detect()) 80 85 /* EEPROM not populated */ 81 86 printf("Board: %s rev %s\n", "AM6-COMPROCEVM", "E3"); 82 87 else ··· 89 94 { 90 95 char *name = "am65x"; 91 96 92 - if (do_board_detect_am6()) 97 + if (do_board_detect()) 93 98 goto invalid_eeprom; 94 99 95 100 if (board_is_am65x_base_board())
+1 -1
board/ti/common/board_detect.c
··· 825 825 return false; 826 826 } 827 827 828 - #if CONFIG_IS_ENABLED(TI_I2C_BOARD_DETECT) 828 + #if IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT) 829 829 int do_board_detect_am6(void) 830 830 { 831 831 int ret;
+1 -1
board/ti/omap3evm/MAINTAINERS
··· 1 1 EVM BOARD 2 - M: Derald D. Woods <woods.technical@gmail.com> 2 + M: Tom Rini <trini@konsulko.com> 3 3 S: Maintained 4 4 F: board/ti/omap3evm/ 5 5 F: include/configs/omap3_evm.h
+10 -5
boot/bootmeth_rauc.c
··· 17 17 #include <fs.h> 18 18 #include <malloc.h> 19 19 #include <mapmem.h> 20 + #include <part.h> 20 21 #include <string.h> 21 22 #include <linux/stringify.h> 22 23 #include <asm/cache.h> ··· 98 99 struct distro_rauc_priv *priv; 99 100 char *boot_order; 100 101 const char **boot_order_list; 102 + bool slot_found = false; 101 103 int ret; 102 104 int i; 103 105 ··· 119 121 if (desc) { 120 122 ret = fs_set_blk_dev_with_part(desc, slot->boot_part); 121 123 if (ret) 122 - return log_msg_ret("part", ret); 124 + continue; 123 125 fs_close(); 124 - ret = fs_set_blk_dev_with_part(desc, slot->root_part); 126 + ret = part_get_info(desc, slot->root_part, NULL); 125 127 if (ret) 126 - return log_msg_ret("part", ret); 127 - fs_close(); 128 + continue; 129 + slot_found = true; 128 130 } 129 131 } 130 132 str_free_list(boot_order_list); 131 133 132 - return 0; 134 + if (slot_found) 135 + return 0; 136 + 137 + return -1; 133 138 } 134 139 135 140 static int distro_rauc_read_bootflow(struct udevice *dev, struct bootflow *bflow)
+19
boot/fdt_support.c
··· 27 27 #include <fdtdec.h> 28 28 #include <version.h> 29 29 #include <video.h> 30 + #include <smbios.h> 30 31 31 32 DECLARE_GLOBAL_DATA_PTR; 32 33 ··· 333 334 int nodeoffset; 334 335 int err; 335 336 const char *str; /* used to set string properties */ 337 + ulong smbiosaddr; /* SMBIOS table address */ 336 338 337 339 err = fdt_check_header(fdt); 338 340 if (err < 0) { ··· 385 387 printf("WARNING: could not set u-boot,version %s.\n", 386 388 fdt_strerror(err)); 387 389 return err; 390 + } 391 + 392 + if (CONFIG_IS_ENABLED(GENERATE_SMBIOS_TABLE)) { 393 + /* Inject SMBIOS address when we have a valid address. 394 + * This is useful for systems using booti/bootm instead of bootefi. 395 + * Failure to set this property is non-fatal, we only generate a 396 + * warning. 397 + */ 398 + smbiosaddr = gd_smbios_start(); 399 + if (smbiosaddr) { 400 + err = fdt_setprop_u64(fdt, nodeoffset, "smbios3-entrypoint", 401 + smbiosaddr); 402 + if (err < 0) { 403 + printf("WARNING: could not set smbios3-entrypoint %s.\n", 404 + fdt_strerror(err)); 405 + } 406 + } 388 407 } 389 408 390 409 return fdt_fixup_stdout(fdt, nodeoffset);
+4
cmd/extension_board.c
··· 99 99 int i = 0; 100 100 101 101 extension_list = extension_get_list(); 102 + if (!extension_list) { 103 + printf("No extension device\n"); 104 + return CMD_RET_FAILURE; 105 + } 102 106 if (!alist_get_ptr(extension_list, 0)) { 103 107 printf("No extension registered - Please run \"extension scan\"\n"); 104 108 return CMD_RET_SUCCESS;
+2 -2
common/spl/Kconfig
··· 545 545 depends on SPL_DM_MMC || SPL_MMC 546 546 default y if ARCH_SUNXI || ARCH_DAVINCI || ARCH_UNIPHIER || \ 547 547 ARCH_MX6 || ARCH_MX7 || \ 548 - ARCH_ROCKCHIP || ARCH_MVEBU || ARCH_SOCFPGA || \ 548 + ARCH_ROCKCHIP || ARCH_MVEBU || TARGET_SOCFPGA_GEN5 || \ 549 549 ARCH_AT91 || ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || \ 550 550 OMAP54XX || AM33XX || AM43XX || \ 551 551 TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED ··· 589 589 default 0x8a if ARCH_MX6 || ARCH_MX7 590 590 default 0x100 if ARCH_UNIPHIER 591 591 default 0x0 if ARCH_MVEBU 592 - default 0x200 if ARCH_SOCFPGA || ARCH_AT91 592 + default 0x200 if TARGET_SOCFPGA_GEN5 || ARCH_AT91 593 593 default 0x300 if ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || \ 594 594 OMAP54XX || AM33XX || AM43XX || ARCH_K3 595 595 default 0x4000 if ARCH_ROCKCHIP
+1 -1
configs/apalis-tk1_defconfig
··· 3 3 CONFIG_ARCH_TEGRA=y 4 4 CONFIG_TEXT_BASE=0x80110000 5 5 CONFIG_SYS_MALLOC_F_LEN=0x2000 6 - CONFIG_NR_DRAM_BANKS=2 7 6 CONFIG_ENV_SOURCE_FILE="apalis-tk1" 7 + CONFIG_NR_DRAM_BANKS=2 8 8 CONFIG_ENV_SIZE=0x2000 9 9 CONFIG_ENV_OFFSET=0xFFFFDE00 10 10 CONFIG_DEFAULT_DEVICE_TREE="tegra124-apalis"
+1 -1
configs/apalis_t30_defconfig
··· 3 3 CONFIG_ARCH_TEGRA=y 4 4 CONFIG_TEXT_BASE=0x80110000 5 5 CONFIG_SYS_MALLOC_F_LEN=0x2000 6 - CONFIG_NR_DRAM_BANKS=2 7 6 CONFIG_ENV_SOURCE_FILE="apalis_t30" 7 + CONFIG_NR_DRAM_BANKS=2 8 8 CONFIG_ENV_SIZE=0x2000 9 9 CONFIG_ENV_OFFSET=0xFFFFDE00 10 10 CONFIG_DEFAULT_DEVICE_TREE="tegra30-apalis"
+1 -1
configs/brcp150_defconfig
··· 6 6 CONFIG_TEXT_BASE=0x4000000 7 7 CONFIG_SYS_MALLOC_F_LEN=0x1000 8 8 CONFIG_SPL_GPIO=y 9 - CONFIG_NR_DRAM_BANKS=1 10 9 CONFIG_ENV_SOURCE_FILE="env/brcp150" 10 + CONFIG_NR_DRAM_BANKS=1 11 11 CONFIG_SF_DEFAULT_SPEED=100000000 12 12 CONFIG_SF_DEFAULT_MODE=0x3 13 13 CONFIG_ENV_SIZE=0x10000
+1 -1
configs/brcp170_defconfig
··· 6 6 CONFIG_TEXT_BASE=0x4000000 7 7 CONFIG_SYS_MALLOC_F_LEN=0x1000 8 8 CONFIG_SPL_GPIO=y 9 - CONFIG_NR_DRAM_BANKS=1 10 9 CONFIG_ENV_SOURCE_FILE="env/brcp1" 10 + CONFIG_NR_DRAM_BANKS=1 11 11 CONFIG_SF_DEFAULT_SPEED=100000000 12 12 CONFIG_SF_DEFAULT_MODE=0x3 13 13 CONFIG_ENV_SIZE=0x10000
+1 -1
configs/brcp1_1r_defconfig
··· 6 6 CONFIG_TEXT_BASE=0x4000000 7 7 CONFIG_SYS_MALLOC_F_LEN=0x1000 8 8 CONFIG_SPL_GPIO=y 9 - CONFIG_NR_DRAM_BANKS=1 10 9 CONFIG_ENV_SOURCE_FILE="env/brcp1" 10 + CONFIG_NR_DRAM_BANKS=1 11 11 CONFIG_SF_DEFAULT_SPEED=100000000 12 12 CONFIG_SF_DEFAULT_MODE=0x3 13 13 CONFIG_ENV_SIZE=0x10000
+1 -1
configs/brcp1_1r_switch_defconfig
··· 6 6 CONFIG_TEXT_BASE=0x4000000 7 7 CONFIG_SYS_MALLOC_F_LEN=0x1000 8 8 CONFIG_SPL_GPIO=y 9 - CONFIG_NR_DRAM_BANKS=1 10 9 CONFIG_ENV_SOURCE_FILE="env/brcp1" 10 + CONFIG_NR_DRAM_BANKS=1 11 11 CONFIG_SF_DEFAULT_SPEED=100000000 12 12 CONFIG_SF_DEFAULT_MODE=0x3 13 13 CONFIG_ENV_SIZE=0x10000
+1 -1
configs/brcp1_2r_defconfig
··· 6 6 CONFIG_TEXT_BASE=0x4000000 7 7 CONFIG_SYS_MALLOC_F_LEN=0x1000 8 8 CONFIG_SPL_GPIO=y 9 - CONFIG_NR_DRAM_BANKS=1 10 9 CONFIG_ENV_SOURCE_FILE="env/brcp1" 10 + CONFIG_NR_DRAM_BANKS=1 11 11 CONFIG_SF_DEFAULT_SPEED=100000000 12 12 CONFIG_SF_DEFAULT_MODE=0x3 13 13 CONFIG_ENV_SIZE=0x10000
+1 -1
configs/brsmarc2_defconfig
··· 8 8 CONFIG_TEXT_BASE=0x4000000 9 9 CONFIG_SYS_MALLOC_F_LEN=0x1000 10 10 CONFIG_SPL_GPIO=y 11 - CONFIG_NR_DRAM_BANKS=1 12 11 CONFIG_ENV_SOURCE_FILE="env/brcp1" 12 + CONFIG_NR_DRAM_BANKS=1 13 13 CONFIG_SF_DEFAULT_SPEED=100000000 14 14 CONFIG_SF_DEFAULT_MODE=0x3 15 15 CONFIG_ENV_SIZE=0x10000
+1 -1
configs/cardhu_defconfig
··· 3 3 CONFIG_SYS_L2CACHE_OFF=y 4 4 CONFIG_ARCH_TEGRA=y 5 5 CONFIG_TEXT_BASE=0x80110000 6 - CONFIG_NR_DRAM_BANKS=2 7 6 CONFIG_ENV_SOURCE_FILE="cardhu" 7 + CONFIG_NR_DRAM_BANKS=2 8 8 CONFIG_SF_DEFAULT_SPEED=24000000 9 9 CONFIG_ENV_SIZE=0x2000 10 10 CONFIG_ENV_OFFSET=0xFFFFE000
+1 -1
configs/chagall_defconfig
··· 1 1 CONFIG_ARM=y 2 2 CONFIG_ARCH_TEGRA=y 3 3 CONFIG_TEXT_BASE=0x80110000 4 - CONFIG_NR_DRAM_BANKS=2 5 4 CONFIG_ENV_SOURCE_FILE="chagall" 5 + CONFIG_NR_DRAM_BANKS=2 6 6 CONFIG_ENV_SIZE=0x3000 7 7 CONFIG_ENV_OFFSET=0xFFFFD000 8 8 CONFIG_DEFAULT_DEVICE_TREE="tegra30-pegatron-chagall"
+1 -1
configs/colibri_imx7_defconfig
··· 22 22 CONFIG_OF_ENV_SETUP=y 23 23 CONFIG_BOOTCOMMAND="run ubiboot ; echo ; echo ubiboot failed ; run distro_bootcmd;" 24 24 CONFIG_USE_PREBOOT=y 25 - CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile ${soc}-colibri-${fdt_board}.dtb " 25 + CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile ${soc}-colibri${variant}-${fdt_board}.dtb " 26 26 CONFIG_SYS_PBSIZE=544 27 27 CONFIG_SYS_CONSOLE_IS_IN_ENV=y 28 28 # CONFIG_DISPLAY_BOARDINFO is not set
+1 -1
configs/colibri_imx7_emmc_defconfig
··· 19 19 CONFIG_DISTRO_DEFAULTS=y 20 20 CONFIG_BOOTDELAY=1 21 21 CONFIG_USE_PREBOOT=y 22 - CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile ${soc}-colibri-emmc-${fdt_board}.dtb" 22 + CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile ${soc}-colibri${variant}-${fdt_board}.dtb" 23 23 CONFIG_SYS_PBSIZE=544 24 24 CONFIG_SYS_CONSOLE_IS_IN_ENV=y 25 25 # CONFIG_DISPLAY_BOARDINFO is not set
+1 -1
configs/colibri_t20_defconfig
··· 3 3 CONFIG_ARCH_TEGRA=y 4 4 CONFIG_TEXT_BASE=0x00110000 5 5 CONFIG_SYS_MALLOC_F_LEN=0x2000 6 - CONFIG_NR_DRAM_BANKS=2 7 6 CONFIG_ENV_SOURCE_FILE="colibri_t20" 7 + CONFIG_NR_DRAM_BANKS=2 8 8 CONFIG_ENV_SIZE=0x10000 9 9 CONFIG_ENV_OFFSET=0x200000 10 10 CONFIG_DEFAULT_DEVICE_TREE="tegra20-colibri"
+1 -1
configs/colibri_t30_defconfig
··· 3 3 CONFIG_ARCH_TEGRA=y 4 4 CONFIG_TEXT_BASE=0x80110000 5 5 CONFIG_SYS_MALLOC_F_LEN=0x2000 6 - CONFIG_NR_DRAM_BANKS=2 7 6 CONFIG_ENV_SOURCE_FILE="colibri_t30" 7 + CONFIG_NR_DRAM_BANKS=2 8 8 CONFIG_ENV_SIZE=0x2000 9 9 CONFIG_ENV_OFFSET=0xFFFFDE00 10 10 CONFIG_DEFAULT_DEVICE_TREE="tegra30-colibri"
+1 -1
configs/endeavoru_defconfig
··· 1 1 CONFIG_ARM=y 2 2 CONFIG_ARCH_TEGRA=y 3 3 CONFIG_TEXT_BASE=0x80110000 4 - CONFIG_NR_DRAM_BANKS=2 5 4 CONFIG_ENV_SOURCE_FILE="endeavoru" 5 + CONFIG_NR_DRAM_BANKS=2 6 6 CONFIG_ENV_SIZE=0x3000 7 7 CONFIG_ENV_OFFSET=0xFFFFD000 8 8 CONFIG_DEFAULT_DEVICE_TREE="tegra30-htc-endeavoru"
+70
configs/exynos-mobile_defconfig
··· 1 + CONFIG_ARM=y 2 + CONFIG_SKIP_LOWLEVEL_INIT=y 3 + CONFIG_COUNTER_FREQUENCY=26000000 4 + CONFIG_POSITION_INDEPENDENT=y 5 + CONFIG_ARCH_EXYNOS=y 6 + CONFIG_SYS_MALLOC_LEN=0x2000000 7 + CONFIG_SYS_MALLOC_F_LEN=0x16000 8 + CONFIG_TARGET_EXYNOS_MOBILE=y 9 + CONFIG_NR_DRAM_BANKS=3 10 + CONFIG_DEFAULT_DEVICE_TREE="exynos/exynos7870-a2corelte" 11 + CONFIG_SYS_BOOTM_LEN=0x2000000 12 + CONFIG_SYS_LOAD_ADDR=0x80000000 13 + CONFIG_ARMV8_CNTFRQ_BROKEN=y 14 + # CONFIG_PSCI_RESET is not set 15 + CONFIG_BUTTON_CMD=y 16 + CONFIG_SAVE_PREV_BL_FDT_ADDR=y 17 + CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y 18 + CONFIG_SYS_PBSIZE=1024 19 + CONFIG_BOARD_TYPES=y 20 + # CONFIG_DISPLAY_CPUINFO is not set 21 + CONFIG_MISC_INIT_R=y 22 + CONFIG_HUSH_PARSER=y 23 + CONFIG_CMD_BOOTMENU=y 24 + CONFIG_CMD_POWEROFF=y 25 + CONFIG_CMD_FS_GENERIC=y 26 + CONFIG_EFI_PARTITION=y 27 + CONFIG_OF_UPSTREAM=y 28 + CONFIG_OF_LIST="exynos/exynos7870-a2corelte exynos/exynos7870-j6lte exynos/exynos7870-on7xelte" 29 + CONFIG_MULTI_DTB_FIT=y 30 + CONFIG_BUTTON=y 31 + CONFIG_BUTTON_REMAP_PHONE_KEYS=y 32 + CONFIG_CLK_EXYNOS7870=y 33 + CONFIG_USB_FUNCTION_FASTBOOT=y 34 + CONFIG_FASTBOOT_BUF_ADDR=0xdead0000 35 + CONFIG_FASTBOOT_FLASH=y 36 + CONFIG_FASTBOOT_FLASH_MMC_DEV=0 37 + CONFIG_SYS_I2C_S3C24X0=y 38 + CONFIG_BUTTON_KEYBOARD=y 39 + CONFIG_MISC=y 40 + CONFIG_MMC_BROKEN_CD=y 41 + CONFIG_MMC_IO_VOLTAGE=y 42 + CONFIG_MMC_UHS_SUPPORT=y 43 + CONFIG_MMC_HS400_SUPPORT=y 44 + CONFIG_MMC_DW=y 45 + CONFIG_PHY=y 46 + CONFIG_PHY_EXYNOS_USBDRD=y 47 + CONFIG_PINCTRL=y 48 + CONFIG_PINCTRL_EXYNOS78x0=y 49 + CONFIG_DM_PMIC=y 50 + CONFIG_PMIC_S2MPS11=y 51 + CONFIG_DM_REGULATOR=y 52 + CONFIG_DM_REGULATOR_FIXED=y 53 + CONFIG_DM_REGULATOR_S2MPS11=y 54 + CONFIG_SOC_SAMSUNG=y 55 + CONFIG_EXYNOS_PMU=y 56 + CONFIG_SYSRESET=y 57 + CONFIG_SYSRESET_CMD_POWEROFF=y 58 + CONFIG_SYSRESET_SYSCON=y 59 + CONFIG_USB=y 60 + CONFIG_DM_USB_GADGET=y 61 + CONFIG_USB_DWC3=y 62 + CONFIG_USB_DWC3_GENERIC=y 63 + CONFIG_USB_GADGET=y 64 + CONFIG_USB_GADGET_MANUFACTURER="Samsung" 65 + CONFIG_USB_GADGET_VENDOR_NUM=0x04e8 66 + CONFIG_USB_GADGET_PRODUCT_NUM=0x6602 67 + CONFIG_VIDEO=y 68 + CONFIG_VIDEO_SIMPLE=y 69 + CONFIG_FS_EXT4=y 70 + CONFIG_FS_FAT=y
+1 -1
configs/grouper_defconfig
··· 1 1 CONFIG_ARM=y 2 2 CONFIG_ARCH_TEGRA=y 3 3 CONFIG_TEXT_BASE=0x80110000 4 - CONFIG_NR_DRAM_BANKS=2 5 4 CONFIG_ENV_SOURCE_FILE="grouper" 5 + CONFIG_NR_DRAM_BANKS=2 6 6 CONFIG_ENV_SIZE=0x3000 7 7 CONFIG_ENV_OFFSET=0xFFFFD000 8 8 CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-nexus7-grouper-E1565"
+1 -1
configs/ideapad-yoga-11_defconfig
··· 1 1 CONFIG_ARM=y 2 2 CONFIG_ARCH_TEGRA=y 3 3 CONFIG_TEXT_BASE=0x80110000 4 - CONFIG_NR_DRAM_BANKS=2 5 4 CONFIG_ENV_SOURCE_FILE="ideapad-yoga-11" 5 + CONFIG_NR_DRAM_BANKS=2 6 6 CONFIG_ENV_SIZE=0x3000 7 7 CONFIG_ENV_OFFSET=0xFFFFD000 8 8 CONFIG_DEFAULT_DEVICE_TREE="tegra30-lenovo-ideapad-yoga-11"
+1 -1
configs/imx6dl_sielaff_defconfig
··· 5 5 CONFIG_SPL_GPIO=y 6 6 CONFIG_SPL_LIBCOMMON_SUPPORT=y 7 7 CONFIG_SPL_LIBGENERIC_SUPPORT=y 8 - CONFIG_NR_DRAM_BANKS=1 9 8 CONFIG_ENV_SOURCE_FILE="imx6dl-sielaff" 9 + CONFIG_NR_DRAM_BANKS=1 10 10 CONFIG_SF_DEFAULT_SPEED=20000000 11 11 CONFIG_ENV_SIZE=0x10000 12 12 CONFIG_ENV_OFFSET=0xF0000
+1 -1
configs/imx8mn_beacon_2g_defconfig
··· 5 5 CONFIG_SPL_GPIO=y 6 6 CONFIG_SPL_LIBCOMMON_SUPPORT=y 7 7 CONFIG_SPL_LIBGENERIC_SUPPORT=y 8 - CONFIG_NR_DRAM_BANKS=1 9 8 CONFIG_ENV_SOURCE_FILE="imx8mn_beacon" 9 + CONFIG_NR_DRAM_BANKS=1 10 10 CONFIG_SF_DEFAULT_SPEED=40000000 11 11 CONFIG_ENV_SIZE=0x2000 12 12 CONFIG_ENV_OFFSET=0xFFFFDE00
+1 -1
configs/imx8mn_beacon_defconfig
··· 5 5 CONFIG_SPL_GPIO=y 6 6 CONFIG_SPL_LIBCOMMON_SUPPORT=y 7 7 CONFIG_SPL_LIBGENERIC_SUPPORT=y 8 - CONFIG_NR_DRAM_BANKS=1 9 8 CONFIG_ENV_SOURCE_FILE="imx8mn_beacon" 9 + CONFIG_NR_DRAM_BANKS=1 10 10 CONFIG_SF_DEFAULT_SPEED=40000000 11 11 CONFIG_ENV_SIZE=0x2000 12 12 CONFIG_ENV_OFFSET=0xFFFFDE00
+1 -1
configs/imx8mn_beacon_fspi_defconfig
··· 5 5 CONFIG_SPL_GPIO=y 6 6 CONFIG_SPL_LIBCOMMON_SUPPORT=y 7 7 CONFIG_SPL_LIBGENERIC_SUPPORT=y 8 - CONFIG_NR_DRAM_BANKS=1 9 8 CONFIG_ENV_SOURCE_FILE="imx8mn_beacon" 9 + CONFIG_NR_DRAM_BANKS=1 10 10 CONFIG_SF_DEFAULT_SPEED=40000000 11 11 CONFIG_ENV_SIZE=0x2000 12 12 CONFIG_ENV_OFFSET=0xFFFFDE00
+1 -1
configs/imx943_evk_defconfig
··· 6 6 CONFIG_SPL_GPIO=y 7 7 CONFIG_SPL_LIBCOMMON_SUPPORT=y 8 8 CONFIG_SPL_LIBGENERIC_SUPPORT=y 9 - CONFIG_NR_DRAM_BANKS=2 10 9 CONFIG_ENV_SOURCE_FILE="imx94_evk" 10 + CONFIG_NR_DRAM_BANKS=2 11 11 CONFIG_ENV_SIZE=0x4000 12 12 CONFIG_ENV_OFFSET=0x700000 13 13 CONFIG_DM_GPIO=y
+1 -1
configs/imx95_15x15_evk_defconfig
··· 6 6 CONFIG_SPL_GPIO=y 7 7 CONFIG_SPL_LIBCOMMON_SUPPORT=y 8 8 CONFIG_SPL_LIBGENERIC_SUPPORT=y 9 - CONFIG_NR_DRAM_BANKS=3 10 9 CONFIG_ENV_SOURCE_FILE="imx95_evk" 10 + CONFIG_NR_DRAM_BANKS=3 11 11 CONFIG_SF_DEFAULT_SPEED=40000000 12 12 CONFIG_ENV_SIZE=0x4000 13 13 CONFIG_ENV_OFFSET=0x700000
+1 -1
configs/imxrt1050-evk_fspi_defconfig
··· 8 8 CONFIG_SPL_GPIO=y 9 9 CONFIG_SPL_LIBCOMMON_SUPPORT=y 10 10 CONFIG_SPL_LIBGENERIC_SUPPORT=y 11 - CONFIG_NR_DRAM_BANKS=1 12 11 CONFIG_ENV_SOURCE_FILE="imxrt1050-evk-nor" 12 + CONFIG_NR_DRAM_BANKS=1 13 13 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y 14 14 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20020000 15 15 CONFIG_ENV_OFFSET=0x80000
+1 -1
configs/mocha_defconfig
··· 2 2 CONFIG_ARCH_TEGRA=y 3 3 CONFIG_TEXT_BASE=0x80110000 4 4 CONFIG_SYS_MALLOC_LEN=0x2500000 5 - CONFIG_NR_DRAM_BANKS=2 6 5 CONFIG_ENV_SOURCE_FILE="mocha" 6 + CONFIG_NR_DRAM_BANKS=2 7 7 CONFIG_ENV_SIZE=0x3000 8 8 CONFIG_ENV_OFFSET=0xFFFFD000 9 9 CONFIG_DEFAULT_DEVICE_TREE="tegra124-xiaomi-mocha"
+1 -1
configs/mot_defconfig
··· 1 1 CONFIG_ARM=y 2 2 CONFIG_ARCH_TEGRA=y 3 3 CONFIG_TEXT_BASE=0x00110000 4 - CONFIG_NR_DRAM_BANKS=2 5 4 CONFIG_ENV_SOURCE_FILE="mot" 5 + CONFIG_NR_DRAM_BANKS=2 6 6 CONFIG_ENV_SIZE=0x3000 7 7 CONFIG_ENV_OFFSET=0xFFFFD000 8 8 CONFIG_DEFAULT_DEVICE_TREE="tegra20-motorola-olympus"
+1 -1
configs/n1_defconfig
··· 1 1 CONFIG_ARM=y 2 2 CONFIG_ARCH_TEGRA=y 3 3 CONFIG_TEXT_BASE=0x00110000 4 - CONFIG_NR_DRAM_BANKS=2 5 4 CONFIG_ENV_SOURCE_FILE="n1" 5 + CONFIG_NR_DRAM_BANKS=2 6 6 CONFIG_ENV_SIZE=0x3000 7 7 CONFIG_ENV_OFFSET=0xFFFFD000 8 8 CONFIG_DEFAULT_DEVICE_TREE="tegra20-samsung-n1"
+1 -1
configs/ouya_defconfig
··· 1 1 CONFIG_ARM=y 2 2 CONFIG_ARCH_TEGRA=y 3 3 CONFIG_TEXT_BASE=0x80110000 4 - CONFIG_NR_DRAM_BANKS=2 5 4 CONFIG_ENV_SOURCE_FILE="ouya" 5 + CONFIG_NR_DRAM_BANKS=2 6 6 CONFIG_ENV_SIZE=0x3000 7 7 CONFIG_ENV_OFFSET=0xFFFFD000 8 8 CONFIG_DEFAULT_DEVICE_TREE="tegra30-ouya"
+1 -1
configs/p2771-0000-000_defconfig
··· 4 4 CONFIG_SYS_L2CACHE_OFF=y 5 5 CONFIG_ARCH_TEGRA=y 6 6 CONFIG_TEXT_BASE=0x80080000 7 - CONFIG_NR_DRAM_BANKS=1026 8 7 CONFIG_ENV_SOURCE_FILE="p2771-0000" 8 + CONFIG_NR_DRAM_BANKS=1026 9 9 CONFIG_ENV_SIZE=0x2000 10 10 CONFIG_ENV_OFFSET=0xFFFFE000 11 11 CONFIG_DEFAULT_DEVICE_TREE="tegra186-p2771-0000-000"
+1 -1
configs/p3450-0000_defconfig
··· 5 5 CONFIG_ARCH_TEGRA=y 6 6 CONFIG_TEXT_BASE=0x80080000 7 7 CONFIG_SYS_MALLOC_LEN=0x2500000 8 - CONFIG_NR_DRAM_BANKS=2 9 8 CONFIG_ENV_SOURCE_FILE="p3450-0000" 9 + CONFIG_NR_DRAM_BANKS=2 10 10 CONFIG_SF_DEFAULT_SPEED=24000000 11 11 CONFIG_ENV_SIZE=0x2000 12 12 CONFIG_ENV_OFFSET=0xFFFFE000
+1 -1
configs/pg_wcom_expu1_defconfig
··· 4 4 CONFIG_TARGET_PG_WCOM_EXPU1=y 5 5 CONFIG_TEXT_BASE=0x60100000 6 6 CONFIG_SYS_MALLOC_LEN=0x1004000 7 - CONFIG_NR_DRAM_BANKS=1 8 7 CONFIG_ENV_SOURCE_FILE="pg-wcom-expu1" 8 + CONFIG_NR_DRAM_BANKS=1 9 9 CONFIG_ENV_SIZE=0x4000 10 10 CONFIG_ENV_SECT_SIZE=0x20000 11 11 CONFIG_DM_GPIO=y
+1 -1
configs/pg_wcom_expu1_update_defconfig
··· 4 4 CONFIG_TARGET_PG_WCOM_EXPU1=y 5 5 CONFIG_TEXT_BASE=0x60240000 6 6 CONFIG_SYS_MALLOC_LEN=0x1004000 7 - CONFIG_NR_DRAM_BANKS=1 8 7 CONFIG_ENV_SOURCE_FILE="pg-wcom-expu1" 8 + CONFIG_NR_DRAM_BANKS=1 9 9 CONFIG_ENV_SIZE=0x4000 10 10 CONFIG_ENV_SECT_SIZE=0x20000 11 11 CONFIG_DM_GPIO=y
+1 -1
configs/pg_wcom_seli8_defconfig
··· 4 4 CONFIG_TARGET_PG_WCOM_SELI8=y 5 5 CONFIG_TEXT_BASE=0x60100000 6 6 CONFIG_SYS_MALLOC_LEN=0x1004000 7 - CONFIG_NR_DRAM_BANKS=1 8 7 CONFIG_ENV_SOURCE_FILE="pg-wcom-seli8" 8 + CONFIG_NR_DRAM_BANKS=1 9 9 CONFIG_ENV_SIZE=0x4000 10 10 CONFIG_ENV_SECT_SIZE=0x20000 11 11 CONFIG_DM_GPIO=y
+1 -1
configs/pg_wcom_seli8_update_defconfig
··· 4 4 CONFIG_TARGET_PG_WCOM_SELI8=y 5 5 CONFIG_TEXT_BASE=0x60240000 6 6 CONFIG_SYS_MALLOC_LEN=0x1004000 7 - CONFIG_NR_DRAM_BANKS=1 8 7 CONFIG_ENV_SOURCE_FILE="pg-wcom-seli8" 8 + CONFIG_NR_DRAM_BANKS=1 9 9 CONFIG_ENV_SIZE=0x4000 10 10 CONFIG_ENV_SECT_SIZE=0x20000 11 11 CONFIG_DM_GPIO=y
+2 -2
configs/phycore_am64x_a53_defconfig
··· 122 122 CONFIG_DM_MAILBOX=y 123 123 CONFIG_K3_SEC_PROXY=y 124 124 CONFIG_SUPPORT_EMMC_BOOT=y 125 - CONFIG_MMC_HS400_SUPPORT=y 126 - CONFIG_SPL_MMC_HS400_SUPPORT=y 125 + CONFIG_MMC_HS200_SUPPORT=y 126 + CONFIG_SPL_MMC_HS200_SUPPORT=y 127 127 CONFIG_MMC_SDHCI=y 128 128 CONFIG_MMC_SDHCI_ADMA=y 129 129 CONFIG_SPL_MMC_SDHCI_ADMA=y
+1 -1
configs/picasso_defconfig
··· 1 1 CONFIG_ARM=y 2 2 CONFIG_ARCH_TEGRA=y 3 3 CONFIG_TEXT_BASE=0x00110000 4 - CONFIG_NR_DRAM_BANKS=2 5 4 CONFIG_ENV_SOURCE_FILE="picasso" 5 + CONFIG_NR_DRAM_BANKS=2 6 6 CONFIG_ENV_SIZE=0x3000 7 7 CONFIG_ENV_OFFSET=0xFFFFD000 8 8 CONFIG_DEFAULT_DEVICE_TREE="tegra20-acer-a500-picasso"
+1 -1
configs/qc750_defconfig
··· 1 1 CONFIG_ARM=y 2 2 CONFIG_ARCH_TEGRA=y 3 3 CONFIG_TEXT_BASE=0x80110000 4 - CONFIG_NR_DRAM_BANKS=2 5 4 CONFIG_ENV_SOURCE_FILE="qc750" 5 + CONFIG_NR_DRAM_BANKS=2 6 6 CONFIG_ENV_SIZE=0x3000 7 7 CONFIG_ENV_OFFSET=0xFFFFD000 8 8 CONFIG_DEFAULT_DEVICE_TREE="tegra30-wexler-qc750"
+1
configs/r8a779g3_sparrowhawk_defconfig
··· 6 6 CONFIG_ARM_SMCCC=y 7 7 CONFIG_ARMV8_PSCI=y 8 8 CONFIG_ENV_IS_IN_SPI_FLASH=y 9 + CONFIG_ENV_REDUNDANT=y 9 10 CONFIG_ENV_OFFSET=0x3f80000 10 11 CONFIG_ENV_OFFSET_REDUND=0x3fc0000 11 12 CONFIG_ENV_SECT_SIZE=0x40000
+43
configs/r8a78000_ironhide_defconfig
··· 1 + #include <configs/renesas_rcar5.config> 2 + 3 + CONFIG_ARM=y 4 + CONFIG_ARCH_RENESAS=y 5 + CONFIG_RCAR_GEN5=y 6 + CONFIG_TARGET_IRONHIDE=y 7 + 8 + # CONFIG_OF_UPSTREAM is not set 9 + CONFIG_ARMV8_PSCI=y 10 + CONFIG_ARM_SMCCC=y 11 + CONFIG_BAUDRATE=1843200 12 + CONFIG_BOOTCOMMAND="setexpr dloadaddr ${loadaddr} + 0x200000 && setexpr dloadaddr ${dloadaddr} \\\\& 0xffc00000 && setexpr kloadaddr ${dloadaddr} + 0x200000 && tftp ${dloadaddr} r8a78000-ironhide.dtb && tftp ${kloadaddr} Image && booti ${kloadaddr} - ${dloadaddr}" 13 + CONFIG_DEFAULT_DEVICE_TREE="r8a78000-ironhide" 14 + CONFIG_CLK_CCF=y 15 + CONFIG_CLK_COMPOSITE_CCF=y 16 + CONFIG_CLK_SCMI=y 17 + CONFIG_CMD_CLK=y 18 + CONFIG_CMD_MEMTEST=y 19 + CONFIG_CMD_SCMI=y 20 + CONFIG_CMD_UFS=y 21 + CONFIG_DM_MAILBOX=y 22 + CONFIG_DM_RESET=y 23 + CONFIG_ENV_IS_IN_MMC=y 24 + CONFIG_ENV_MMC_DEVICE_INDEX=0 25 + CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 26 + CONFIG_ENV_OFFSET=0xFFFE0000 27 + CONFIG_ENV_SIZE=0x20000 28 + CONFIG_FIRMWARE=y 29 + CONFIG_NR_DRAM_BANKS=16 30 + CONFIG_POWER_DOMAIN=y 31 + CONFIG_RCAR_MFIS_MBOX=y 32 + CONFIG_RESET_SCMI=y 33 + CONFIG_SCMI_AGENT_MAILBOX=y 34 + CONFIG_SCMI_FIRMWARE=y 35 + CONFIG_SCMI_POWER_DOMAIN=y 36 + CONFIG_SCSI=y 37 + CONFIG_SYS_ALT_MEMTEST=y 38 + CONFIG_SYS_BARGSIZE=2048 39 + CONFIG_SYS_BOOT_GET_CMDLINE=y 40 + CONFIG_SYS_CBSIZE=2048 41 + CONFIG_SYS_CLK_FREQ=1066666667 42 + CONFIG_UFS=y 43 + CONFIG_UFS_RENESAS_GEN5=y
-1
configs/renesas_rcar.config
··· 17 17 CONFIG_DM_REGULATOR_GPIO=y 18 18 CONFIG_DM_SPI=y 19 19 CONFIG_DM_SPI_FLASH=y 20 - CONFIG_ENV_OVERWRITE=y 21 20 CONFIG_ENV_VARS_UBOOT_CONFIG=y 22 21 CONFIG_FIT=y 23 22 CONFIG_HUSH_PARSER=y
+23
configs/renesas_rcar5.config
··· 1 + #include <configs/renesas_rcar64.config> 2 + 3 + CONFIG_ARCH_CPU_INIT=y 4 + CONFIG_SYS_LOAD_ADDR=0x9E600000 5 + CONFIG_SYS_RELOC_GD_ENV_ADDR=y 6 + CONFIG_USE_BOOTARGS=y 7 + CONFIG_USE_BOOTCOMMAND=y 8 + 9 + CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" 10 + CONFIG_CMD_MMC=y 11 + CONFIG_DM_ETH_PHY=y 12 + # CONFIG_MMC_HS200_SUPPORT is not set 13 + # CONFIG_MMC_IO_VOLTAGE is not set 14 + # CONFIG_MMC_UHS_SUPPORT is not set 15 + CONFIG_PHY_R8A78000_ETHERNET_PCS=y 16 + CONFIG_PHY_R8A78000_MP_PHY=y 17 + CONFIG_PHY_TI_DP83869=y 18 + # CONFIG_PSCI_RESET is not set 19 + CONFIG_RENESAS_ETHER_SWITCH=y 20 + CONFIG_RENESAS_SDHI=y 21 + CONFIG_SPI_FLASH_SPANSION=y 22 + # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set 23 + CONFIG_SYS_I2C_RCAR_I2C=y
+2
configs/socfpga_agilex5_defconfig
··· 70 70 # CONFIG_ISO_PARTITION is not set 71 71 # CONFIG_EFI_PARTITION is not set 72 72 CONFIG_OF_LIST="" 73 + CONFIG_ENV_IS_IN_FAT=y 73 74 CONFIG_ENV_IS_IN_UBI=y 75 + CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" 74 76 CONFIG_ENV_UBI_PART="root" 75 77 CONFIG_ENV_UBI_VOLUME="env" 76 78 CONFIG_ENV_RELOC_GD_ENV_ADDR=y
+5 -3
configs/socfpga_cyclone5_defconfig
··· 12 12 CONFIG_SPL_STACK=0x0 13 13 CONFIG_SPL_TEXT_BASE=0xFFFF0000 14 14 CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y 15 + CONFIG_SPL_FS_FAT=y 16 + # CONFIG_SPL_SPI is not set 15 17 CONFIG_TIMESTAMP=y 16 18 CONFIG_FIT=y 17 19 CONFIG_DISTRO_DEFAULTS=y 18 - # CONFIG_USE_BOOTCOMMAND is not set 20 + CONFIG_BOOTCOMMAND="run fatscript;bridge enable; run distro_bootcmd" 19 21 CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_socdk.dtb" 20 22 CONFIG_SYS_CONSOLE_IS_IN_ENV=y 21 23 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y ··· 27 29 CONFIG_SPL_NO_BSS_LIMIT=y 28 30 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set 29 31 CONFIG_SPL_HAVE_INIT_STACK=y 30 - CONFIG_SPL_SPI_LOAD=y 31 - CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 32 + # CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set 32 33 CONFIG_SYS_MAXARGS=32 33 34 CONFIG_CMD_ASKENV=y 34 35 CONFIG_CMD_GREPENV=y ··· 79 80 CONFIG_USB_GADGET_DOWNLOAD=y 80 81 # CONFIG_SPL_WDT is not set 81 82 CONFIG_SYS_TIMER_COUNTS_DOWN=y 83 + # CONFIG_TOOLS_MKEFICAPSULE is not set
+2 -11
configs/socfpga_vining_fpga_defconfig
··· 78 78 CONFIG_DWAPB_GPIO=y 79 79 CONFIG_DM_I2C=y 80 80 CONFIG_SYS_I2C_DW=y 81 - CONFIG_LED_STATUS=y 82 - CONFIG_LED_STATUS_GPIO=y 83 - CONFIG_LED_STATUS0=y 84 - CONFIG_LED_STATUS_BIT=48 85 - CONFIG_LED_STATUS1=y 86 - CONFIG_LED_STATUS_BIT1=53 87 - CONFIG_LED_STATUS2=y 88 - CONFIG_LED_STATUS_BIT2=54 89 - CONFIG_LED_STATUS3=y 90 - CONFIG_LED_STATUS_BIT3=65 91 - CONFIG_LED_STATUS_CMD=y 81 + CONFIG_LED=y 82 + CONFIG_LED_GPIO=y 92 83 CONFIG_MISC=y 93 84 CONFIG_I2C_EEPROM=y 94 85 CONFIG_SYS_I2C_EEPROM_ADDR=0x50
+1 -1
configs/star_defconfig
··· 1 1 CONFIG_ARM=y 2 2 CONFIG_ARCH_TEGRA=y 3 3 CONFIG_TEXT_BASE=0x00110000 4 - CONFIG_NR_DRAM_BANKS=2 5 4 CONFIG_ENV_SOURCE_FILE="star" 5 + CONFIG_NR_DRAM_BANKS=2 6 6 CONFIG_ENV_SIZE=0x3000 7 7 CONFIG_ENV_OFFSET=0xFFFFD000 8 8 CONFIG_DEFAULT_DEVICE_TREE="tegra20-lg-star"
+1 -1
configs/surface-2_defconfig
··· 2 2 CONFIG_ARCH_TEGRA=y 3 3 CONFIG_TEXT_BASE=0x80110000 4 4 CONFIG_SYS_MALLOC_LEN=0x2500000 5 - CONFIG_NR_DRAM_BANKS=2 6 5 CONFIG_ENV_SOURCE_FILE="surface-2" 6 + CONFIG_NR_DRAM_BANKS=2 7 7 CONFIG_ENV_SIZE=0x3000 8 8 CONFIG_ENV_OFFSET=0xFFFFD000 9 9 CONFIG_DEFAULT_DEVICE_TREE="tegra114-microsoft-surface-2-0b"
+1 -1
configs/surface-rt_defconfig
··· 1 1 CONFIG_ARM=y 2 2 CONFIG_ARCH_TEGRA=y 3 3 CONFIG_TEXT_BASE=0x80110000 4 - CONFIG_NR_DRAM_BANKS=2 5 4 CONFIG_ENV_SOURCE_FILE="surface-rt" 5 + CONFIG_NR_DRAM_BANKS=2 6 6 CONFIG_ENV_SIZE=0x3000 7 7 CONFIG_ENV_OFFSET=0xFFFFD000 8 8 CONFIG_DEFAULT_DEVICE_TREE="tegra30-microsoft-surface-rt"
+1 -1
configs/tegratab_defconfig
··· 2 2 CONFIG_ARCH_TEGRA=y 3 3 CONFIG_TEXT_BASE=0x80110000 4 4 CONFIG_SYS_MALLOC_LEN=0x2500000 5 - CONFIG_NR_DRAM_BANKS=2 6 5 CONFIG_ENV_SOURCE_FILE="tegratab" 6 + CONFIG_NR_DRAM_BANKS=2 7 7 CONFIG_ENV_SIZE=0x3000 8 8 CONFIG_ENV_OFFSET=0xFFFFD000 9 9 CONFIG_DEFAULT_DEVICE_TREE="tegra114-nvidia-tegratab"
+1 -1
configs/tf701t_defconfig
··· 2 2 CONFIG_ARCH_TEGRA=y 3 3 CONFIG_TEXT_BASE=0x80110000 4 4 CONFIG_SYS_MALLOC_LEN=0x2500000 5 - CONFIG_NR_DRAM_BANKS=2 6 5 CONFIG_ENV_SOURCE_FILE="transformer-t114" 6 + CONFIG_NR_DRAM_BANKS=2 7 7 CONFIG_ENV_SIZE=0x3000 8 8 CONFIG_ENV_OFFSET=0xFFFFD000 9 9 CONFIG_DEFAULT_DEVICE_TREE="tegra114-asus-tf701t"
+2
configs/toradex-smarc-imx95_defconfig
··· 17 17 CONFIG_SPL_MMC=y 18 18 CONFIG_SPL_SERIAL=y 19 19 CONFIG_SPL_DRIVERS_MISC=y 20 + CONFIG_SPL_STACK=0x204d6000 20 21 CONFIG_SPL_TEXT_BASE=0x20480000 21 22 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y 22 23 CONFIG_SPL_BSS_START_ADDR=0x204d6000 ··· 49 50 CONFIG_SPL_LOAD_IMX_CONTAINER=y 50 51 CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/scmi/container.cfg" 51 52 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set 53 + CONFIG_SPL_HAVE_INIT_STACK=y 52 54 CONFIG_SPL_SYS_MALLOC=y 53 55 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y 54 56 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x93200000
+1 -1
configs/transformer_t20_defconfig
··· 1 1 CONFIG_ARM=y 2 2 CONFIG_ARCH_TEGRA=y 3 3 CONFIG_TEXT_BASE=0x00110000 4 - CONFIG_NR_DRAM_BANKS=2 5 4 CONFIG_ENV_SOURCE_FILE="transformer-t20" 5 + CONFIG_NR_DRAM_BANKS=2 6 6 CONFIG_ENV_SIZE=0x3000 7 7 CONFIG_ENV_OFFSET=0xFFFFD000 8 8 CONFIG_DEFAULT_DEVICE_TREE="tegra20-asus-tf101"
+1 -1
configs/transformer_t30_defconfig
··· 1 1 CONFIG_ARM=y 2 2 CONFIG_ARCH_TEGRA=y 3 3 CONFIG_TEXT_BASE=0x80110000 4 - CONFIG_NR_DRAM_BANKS=2 5 4 CONFIG_ENV_SOURCE_FILE="transformer-t30" 5 + CONFIG_NR_DRAM_BANKS=2 6 6 CONFIG_ENV_SIZE=0x3000 7 7 CONFIG_ENV_OFFSET=0xFFFFD000 8 8 CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-tf201"
+2 -2
configs/xilinx_versal_mini_ospi_defconfig
··· 3 3 CONFIG_COUNTER_FREQUENCY=100000000 4 4 CONFIG_ARCH_VERSAL=y 5 5 CONFIG_TEXT_BASE=0xFFFC0000 6 - CONFIG_SYS_MALLOC_LEN=0x2000 6 + CONFIG_SYS_MALLOC_LEN=0x3000 7 7 CONFIG_SYS_MALLOC_F_LEN=0x500 8 8 CONFIG_NR_DRAM_BANKS=1 9 9 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y 10 - CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xFFFE1000 10 + CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xFFFE2000 11 11 CONFIG_SF_DEFAULT_SPEED=30000000 12 12 CONFIG_ENV_SIZE=0x80 13 13 # CONFIG_DM_GPIO is not set
+2 -2
configs/xilinx_versal_mini_qspi_defconfig
··· 3 3 CONFIG_COUNTER_FREQUENCY=100000000 4 4 CONFIG_ARCH_VERSAL=y 5 5 CONFIG_TEXT_BASE=0xFFFC0000 6 - CONFIG_SYS_MALLOC_LEN=0x2000 6 + CONFIG_SYS_MALLOC_LEN=0x3000 7 7 CONFIG_NR_DRAM_BANKS=1 8 8 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y 9 - CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xFFFE0000 9 + CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xFFFE2000 10 10 CONFIG_SF_DEFAULT_SPEED=30000000 11 11 CONFIG_ENV_SIZE=0x80 12 12 CONFIG_DEFAULT_DEVICE_TREE="versal-mini-qspi-single"
+45
doc/board/samsung/exynos-mobile.rst
··· 1 + .. SPDX-License-Identifier: GPL-2.0+ 2 + .. sectionauthor:: Kaustabh Chakraborty <kauschluss@disroot.org> 3 + 4 + Samsung Exynos Generic ARMv8 Boards (for mobile devices) 5 + ======================================================== 6 + 7 + Overview 8 + -------- 9 + This document describes how to build and run U-Boot for Samsung Exynos generic 10 + boards. Boards are expected to boot with a primary bootloader, such as S-BOOT or 11 + S-LK, which hands off control to U-Boot. Presently, only ARMv8 devices are 12 + supported. 13 + 14 + The U-Boot image is built with all device tree blobs packed in a single FIT 15 + image. During boot, it uses simple heuristics to detect the target board, and 16 + subsequently the appropriate FDT is selected. 17 + 18 + Installation 19 + ------------ 20 + Building 21 + ^^^^^^^^ 22 + If a cross-compiler is required, install it and set it up like so: 23 + 24 + .. prompt:: bash $ 25 + 26 + export CROSS_COMPILE=aarch64-linux-gnu- 27 + 28 + Then, run the following commands to build U-Boot: 29 + 30 + .. prompt:: bash $ 31 + 32 + make O=.output exynos-mobile_defconfig 33 + make O=.output -j$(nproc) 34 + 35 + If successful, the U-Boot binary will be present in ``.output/u-boot.bin``. 36 + 37 + Preparation and Flashing 38 + ^^^^^^^^^^^^^^^^^^^^^^^^ 39 + Since U-Boot supports multiple boards, and devices have different requirements, 40 + this step will vary depending on your target. 41 + 42 + .. toctree:: 43 + :maxdepth: 1 44 + 45 + exynos-mobile/exynos7870
+85
doc/board/samsung/exynos-mobile/exynos7870.rst
··· 1 + .. SPDX-License-Identifier: GPL-2.0+ 2 + .. sectionauthor:: Kaustabh Chakraborty <kauschluss@disroot.org> 3 + 4 + Samsung Exynos 7870 Boards 5 + ========================== 6 + 7 + Preparation 8 + ----------- 9 + Create the following device tree (named ``stub.dts``) 10 + 11 + .. code-block:: devicetree 12 + 13 + /dts-v1/; 14 + 15 + / { 16 + compatible = "samsung,exynos7870"; 17 + #address-cells = <2>; 18 + #size-cells = <1>; 19 + 20 + model_info-chip = <7870>; 21 + model_info-hw_rev = <0>; 22 + model_info-hw_rev_end = <255>; 23 + 24 + chosen { 25 + }; 26 + 27 + memory@80000000 { 28 + device_type = "memory"; 29 + reg = <0x0 0x80000000 0x0>; 30 + }; 31 + 32 + memory@100000000 { 33 + device_type = "memory"; 34 + reg = <0x1 0x00000000 0x0>; 35 + }; 36 + }; 37 + 38 + The chosen node and memory ranges are populated by S-BOOT. A certain device 39 + model may have multiple variants, with differing amounts of RAM and storage. The 40 + RAM capacity information is graciously provided by S-BOOT's device tree 41 + overlays. 42 + 43 + Compile it to a device tree blob, then pack it in the QCDT format [1]_ using 44 + ``dtbTool-exynos`` [2]_ by issuing the following commands: 45 + 46 + .. prompt:: bash $ 47 + 48 + dtc -I dts -O dtb -o stub.dtb stub.dts 49 + dtbTool-exynos -o stub-dt.img stub.dtb 50 + 51 + Finally, use ``mkbootimg`` by osm0sis [3]_ to generate the boot image: 52 + 53 + .. prompt:: bash $ 54 + 55 + mkbootimg -o u-boot.img \ 56 + --kernel .output/u-boot.bin \ 57 + --dt stub-dt.img 58 + 59 + Offsets are not provided to ``mkbootimg`` as S-BOOT ignores them. 60 + 61 + Flashing 62 + -------- 63 + If flashing for the first time, it must be done via Samsung's Download (Odin) 64 + mode. Heimdall [4]_ can be used for flashing, like so: 65 + 66 + .. prompt:: bash $ 67 + 68 + heimdall flash --BOOT u-boot.img 69 + 70 + However, if U-Boot is already installed, you may also use its fastboot interface 71 + for flashing. Boot into the boot menu by holding the volume down key. Enable 72 + fastboot mode from there, connect the device to your host, then run: 73 + 74 + .. prompt:: bash $ 75 + 76 + fastboot flash boot u-boot.img 77 + 78 + To flash an OS image in internal storage, fastboot is a reliable option. 79 + 80 + References 81 + ---------- 82 + .. [1] https://wiki.postmarketos.org/wiki/QCDT 83 + .. [2] https://github.com/dsankouski/dtbtool-exynos 84 + .. [3] https://github.com/osm0sis/mkbootimg 85 + .. [4] https://git.sr.ht/~grimler/Heimdall
+1
doc/board/samsung/index.rst
··· 8 8 9 9 axy17lte 10 10 e850-96 11 + exynos-mobile 11 12 n1
+60 -63
doc/board/toradex/verdin-am62p.rst
··· 125 125 Boot 126 126 ---- 127 127 128 - Output: 128 + Output:: 129 129 130 - .. code-block:: console 130 + U-Boot SPL 2025.04-00006-g51dc98d36470 (May 12 2025 - 15:46:57 +0100) 131 + SYSFW ABI: 4.0 (firmware rev 0x000b '11.0.7--v11.00.07 (Fancy Rat)') 132 + Changed A53 CPU frequency to 1250000000Hz (U grade) in DT 133 + SPL initial stack usage: 17080 bytes 134 + Trying to boot from MMC1 135 + Authentication passed 136 + Authentication passed 137 + Authentication passed 138 + Loading Environment from nowhere... OK 139 + init_env from device 9 not supported! 140 + Authentication passed 141 + Authentication passed 142 + Starting ATF on ARM64 core... 131 143 132 - U-Boot SPL 2025.04-00006-g51dc98d36470 (May 12 2025 - 15:46:57 +0100) 133 - SYSFW ABI: 4.0 (firmware rev 0x000b '11.0.7--v11.00.07 (Fancy Rat)') 134 - Changed A53 CPU frequency to 1250000000Hz (U grade) in DT 135 - SPL initial stack usage: 17080 bytes 136 - Trying to boot from MMC1 137 - Authentication passed 138 - Authentication passed 139 - Authentication passed 140 - Loading Environment from nowhere... OK 141 - init_env from device 9 not supported! 142 - Authentication passed 143 - Authentication passed 144 - Starting ATF on ARM64 core... 144 + NOTICE: BL31: v2.12.0(release):v2.12.0-1106-g4301798db096 145 + NOTICE: BL31: Built : 10:57:58, May 9 2025 146 + I/TC: 147 + I/TC: OP-TEE version: 4.6.0-18-g76d920d354df (gcc version 12.3.1 20230626 (Arm GNU Toolchain 12.3.Rel1 (Build arm-12.35))) #4 Tue May 6 19:48:13 UTC 2025 aarch64 148 + I/TC: WARNING: This OP-TEE configuration might be insecure! 149 + I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html 150 + I/TC: Primary CPU initializing 151 + I/TC: GIC redistributor base address not provided 152 + I/TC: Assuming default GIC group status and modifier 153 + I/TC: SYSFW ABI: 4.0 (firmware rev 0x000b '11.0.7--v11.00.07 (Fancy Rat)') 154 + I/TC: Activated SA2UL device 155 + I/TC: Enabled firewalls for SA2UL TRNG device 156 + I/TC: SA2UL TRNG initialized 157 + I/TC: SA2UL Drivers initialized 158 + I/TC: HUK Initialized 159 + I/TC: Primary CPU switching to normal world boot 145 160 146 - NOTICE: BL31: v2.12.0(release):v2.12.0-1106-g4301798db096 147 - NOTICE: BL31: Built : 10:57:58, May 9 2025 148 - I/TC: 149 - I/TC: OP-TEE version: 4.6.0-18-g76d920d354df (gcc version 12.3.1 20230626 (Arm GNU Toolchain 12.3.Rel1 (Build arm-12.35))) #4 Tue May 6 19:48:13 UTC 2025 aarch64 150 - I/TC: WARNING: This OP-TEE configuration might be insecure! 151 - I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html 152 - I/TC: Primary CPU initializing 153 - I/TC: GIC redistributor base address not provided 154 - I/TC: Assuming default GIC group status and modifier 155 - I/TC: SYSFW ABI: 4.0 (firmware rev 0x000b '11.0.7--v11.00.07 (Fancy Rat)') 156 - I/TC: Activated SA2UL device 157 - I/TC: Enabled firewalls for SA2UL TRNG device 158 - I/TC: SA2UL TRNG initialized 159 - I/TC: SA2UL Drivers initialized 160 - I/TC: HUK Initialized 161 - I/TC: Primary CPU switching to normal world boot 161 + U-Boot SPL 2025.04-00006-g51dc98d36470 (May 12 2025 - 15:47:54 +0100) 162 + SYSFW ABI: 4.0 (firmware rev 0x000b '11.0.7--v11.00.07 (Fancy Rat)') 163 + SPL initial stack usage: 1760 bytes 164 + HW CFG: 0x00 165 + Trying to boot from MMC1 166 + Authentication passed 167 + Authentication passed 162 168 163 - U-Boot SPL 2025.04-00006-g51dc98d36470 (May 12 2025 - 15:47:54 +0100) 164 - SYSFW ABI: 4.0 (firmware rev 0x000b '11.0.7--v11.00.07 (Fancy Rat)') 165 - SPL initial stack usage: 1760 bytes 166 - HW CFG: 0x00 167 - Trying to boot from MMC1 168 - Authentication passed 169 - Authentication passed 170 169 171 - 172 - U-Boot 2025.04-00006-g51dc98d36470 (May 12 2025 - 15:47:54 +0100) 173 - 174 - SoC: AM62PX SR1.0 HS-FS 175 - DRAM: 2 GiB 176 - Core: 147 devices, 31 uclasses, devicetree: separate 177 - MMC: mmc@fa10000: 0, mmc@fa00000: 1 178 - Loading Environment from MMC... Reading from MMC(0)... OK 179 - In: serial@2800000 180 - Out: serial@2800000 181 - Err: serial@2800000 182 - Model: Toradex 0099 Verdin AM62P Quad 2GB WB IT V1.0A 183 - Serial#: 15664919 184 - Carrier: Toradex Dahlia V1.1D, Serial# 11287149 185 - am65_cpsw_nuss ethernet@8000000: K3 CPSW: nuss_ver: 0x6BA01903 cpsw_ver: 0x6BA81903 ale_ver: 0x00290105 Ports:2 186 - Setting variant to wifi 187 - Net: 188 - Warning: ethernet@8000000port@1 MAC addresses don't match: 189 - Address in ROM is 58:a1:5f:b8:93:f9 190 - Address in environment is 00:14:2d:ef:07:17 191 - eth0: ethernet@8000000port@1 [PRIME]Could not get PHY for mdio@f00: addr 7 192 - am65_cpsw_nuss_port ethernet@8000000port@2: phy_connect() failed 170 + U-Boot 2025.04-00006-g51dc98d36470 (May 12 2025 - 15:47:54 +0100) 171 + 172 + SoC: AM62PX SR1.0 HS-FS 173 + DRAM: 2 GiB 174 + Core: 147 devices, 31 uclasses, devicetree: separate 175 + MMC: mmc@fa10000: 0, mmc@fa00000: 1 176 + Loading Environment from MMC... Reading from MMC(0)... OK 177 + In: serial@2800000 178 + Out: serial@2800000 179 + Err: serial@2800000 180 + Model: Toradex 0099 Verdin AM62P Quad 2GB WB IT V1.0A 181 + Serial#: 15664919 182 + Carrier: Toradex Dahlia V1.1D, Serial# 11287149 183 + am65_cpsw_nuss ethernet@8000000: K3 CPSW: nuss_ver: 0x6BA01903 cpsw_ver: 0x6BA81903 ale_ver: 0x00290105 Ports:2 184 + Setting variant to wifi 185 + Net: 186 + Warning: ethernet@8000000port@1 MAC addresses don't match: 187 + Address in ROM is 58:a1:5f:b8:93:f9 188 + Address in environment is 00:14:2d:ef:07:17 189 + eth0: ethernet@8000000port@1 [PRIME]Could not get PHY for mdio@f00: addr 7 190 + am65_cpsw_nuss_port ethernet@8000000port@2: phy_connect() failed 193 191 194 - Hit any key to stop autoboot: 0 195 - Verdin AM62P # 196 - 192 + Hit any key to stop autoboot: 0 193 + Verdin AM62P #
+9 -7
doc/develop/pytest/usage.rst
··· 315 315 316 316 The following environment variables are set when running hook scripts: 317 317 318 - - ``UBOOT_BOARD_TYPE`` the board type being tested. 319 - - ``UBOOT_BOARD_IDENTITY`` the board identity being tested, or ``na`` if none 318 + - ``U_BOOT_BOARD_TYPE`` the board type being tested. 319 + - ``U_BOOT_BOARD_TYPE_EXTRA`` the 2nd board type being tested, if applicable. 320 + - ``U_BOOT_BOARD_IDENTITY`` the board identity being tested, or ``na`` if none 320 321 was specified. 321 - - ``UBOOT_SOURCE_DIR`` the U-Boot source directory. 322 - - ``UBOOT_TEST_PY_DIR`` the full path to ``test/py/`` in the source directory. 323 - - ``UBOOT_BUILD_DIR`` the U-Boot build directory. 324 - - ``UBOOT_RESULT_DIR`` the test result directory. 325 - - ``UBOOT_PERSISTENT_DATA_DIR`` the test persistent data directory. 322 + - ``U_BOOT_SOURCE_DIR`` the U-Boot source directory. 323 + - ``U_BOOT_TEST_PY_DIR`` the full path to ``test/py/`` in the source directory. 324 + - ``U_BOOT_BUILD_DIR`` the U-Boot build directory. 325 + - ``U_BOOT_BUILD_DIR_EXTRA`` the 2nd U-Boot build directory, if applicable. 326 + - ``U_BOOT_RESULT_DIR`` the test result directory. 327 + - ``U_BOOT_PERSISTENT_DATA_DIR`` the test persistent data directory. 326 328 327 329 u-boot-test-console 328 330 '''''''''''''''''''
+1 -1
doc/develop/release_cycle.rst
··· 77 77 78 78 * U-Boot |next_ver|-rc3 was released on Mon 24 November 2025. 79 79 80 - .. * U-Boot |next_ver|-rc4 was released on Mon 08 December 2025. 80 + * U-Boot |next_ver|-rc4 was released on Mon 08 December 2025. 81 81 82 82 .. * U-Boot |next_ver|-rc5 was released on Tue 22 December 2025. 83 83
+1
doc/learn/index.rst
··· 6 6 .. toctree:: 7 7 :maxdepth: 1 8 8 9 + logo 9 10 talks
+20
doc/learn/logo.rst
··· 1 + .. SPDX-License-Identifier: GPL-2.0-or-later 2 + 3 + U-Boot logo 4 + =========== 5 + 6 + The project uses the logos below. 7 + 8 + Logo with text 9 + -------------- 10 + 11 + .. image:: ../../tools/logos/u-boot_logo_with_text.svg 12 + :width: 10em 13 + :alt: U-Boot logo with text 14 + 15 + Logo without text 16 + ----------------- 17 + 18 + .. image:: ../../tools/logos/u-boot_logo.svg 19 + :width: 10em 20 + :alt: U-Boot logo without text
+1 -1
doc/sphinx/requirements.txt
··· 24 24 sphinxcontrib-jsmath==1.0.1 25 25 sphinxcontrib-qthelp==2.0.0 26 26 sphinxcontrib-serializinghtml==2.0.0 27 - urllib3==2.5.0 27 + urllib3==2.6.0
+3 -3
drivers/clk/clk-uclass.c
··· 594 594 if (!clk_valid(clk)) 595 595 return 0; 596 596 ops = clk_dev_ops(clk->dev); 597 + clk_get_priv(clk, &clkp); 597 598 598 599 /* Try to find parents which can set rate */ 599 600 while (!ops->set_rate) { 600 601 struct clk *parent; 601 602 602 - if (!(clk->flags & CLK_SET_RATE_PARENT)) 603 + if (!(clkp->flags & CLK_SET_RATE_PARENT)) 603 604 return -ENOSYS; 604 605 605 606 parent = clk_get_parent(clk); ··· 608 609 609 610 clk = parent; 610 611 ops = clk_dev_ops(clk->dev); 612 + clk_get_priv(clk, &clkp); 611 613 } 612 614 613 - /* get private clock struct used for cache */ 614 - clk_get_priv(clk, &clkp); 615 615 /* Clean up cached rates for us and all child clocks */ 616 616 clk_clean_rate_cache(clkp); 617 617
+7
drivers/clk/exynos/Kconfig
··· 15 15 This enables common clock driver support for platforms based 16 16 on Samsung Exynos7420 SoC. 17 17 18 + config CLK_EXYNOS7870 19 + bool "Clock driver for Samsung's Exynos7870 SoC" 20 + select CLK_CCF 21 + help 22 + This enables common clock driver support for platforms based 23 + on Samsung Exynos7870 SoC. 24 + 18 25 config CLK_EXYNOS850 19 26 bool "Clock driver for Samsung's Exynos850 SoC" 20 27 select CLK_CCF
+1
drivers/clk/exynos/Makefile
··· 9 9 10 10 obj-$(CONFIG_$(PHASE_)CLK_CCF) += clk.o clk-pll.o 11 11 obj-$(CONFIG_CLK_EXYNOS7420) += clk-exynos7420.o 12 + obj-$(CONFIG_CLK_EXYNOS7870) += clk-exynos7870.o 12 13 obj-$(CONFIG_CLK_EXYNOS850) += clk-exynos850.o
+929
drivers/clk/exynos/clk-exynos7870.c
··· 1 + // SPDX-License-Identifier: GPL-2.0-only 2 + /* 3 + * Samsung Exynos7870 clock driver. 4 + * Copyright (C) 2015 Samsung Electronics Co., Ltd. 5 + * Author: Kaustabh Chakraborty <kauschluss@disroot.org> 6 + */ 7 + 8 + #include "linux/clk-provider.h" 9 + #include <dm.h> 10 + #include <asm/io.h> 11 + #include <dt-bindings/clock/samsung,exynos7870-cmu.h> 12 + #include "clk.h" 13 + 14 + enum exynos7870_cmu_id { 15 + CMU_MIF, 16 + CMU_FSYS, 17 + CMU_PERI, 18 + }; 19 + 20 + /* 21 + * Register offsets for CMU_MIF (0x10460000) 22 + */ 23 + #define PLL_LOCKTIME_MIF_MEM_PLL 0x0000 24 + #define PLL_LOCKTIME_MIF_MEDIA_PLL 0x0020 25 + #define PLL_LOCKTIME_MIF_BUS_PLL 0x0040 26 + #define PLL_CON0_MIF_MEM_PLL 0x0100 27 + #define PLL_CON0_MIF_MEDIA_PLL 0x0120 28 + #define PLL_CON0_MIF_BUS_PLL 0x0140 29 + #define CLK_CON_GAT_MIF_MUX_MEM_PLL 0x0200 30 + #define CLK_CON_GAT_MIF_MUX_MEM_PLL_CON 0x0200 31 + #define CLK_CON_GAT_MIF_MUX_MEDIA_PLL 0x0204 32 + #define CLK_CON_GAT_MIF_MUX_MEDIA_PLL_CON 0x0204 33 + #define CLK_CON_GAT_MIF_MUX_BUS_PLL 0x0208 34 + #define CLK_CON_GAT_MIF_MUX_BUS_PLL_CON 0x0208 35 + #define CLK_CON_GAT_MIF_MUX_BUSD 0x0220 36 + #define CLK_CON_MUX_MIF_BUSD 0x0220 37 + #define CLK_CON_GAT_MIF_MUX_CMU_ISP_VRA 0x0264 38 + #define CLK_CON_MUX_MIF_CMU_ISP_VRA 0x0264 39 + #define CLK_CON_GAT_MIF_MUX_CMU_ISP_CAM 0x0268 40 + #define CLK_CON_MUX_MIF_CMU_ISP_CAM 0x0268 41 + #define CLK_CON_GAT_MIF_MUX_CMU_ISP_ISP 0x026c 42 + #define CLK_CON_MUX_MIF_CMU_ISP_ISP 0x026c 43 + #define CLK_CON_GAT_MIF_MUX_CMU_DISPAUD_BUS 0x0270 44 + #define CLK_CON_MUX_MIF_CMU_DISPAUD_BUS 0x0270 45 + #define CLK_CON_GAT_MIF_MUX_CMU_DISPAUD_DECON_VCLK 0x0274 46 + #define CLK_CON_MUX_MIF_CMU_DISPAUD_DECON_VCLK 0x0274 47 + #define CLK_CON_GAT_MIF_MUX_CMU_DISPAUD_DECON_ECLK 0x0278 48 + #define CLK_CON_MUX_MIF_CMU_DISPAUD_DECON_ECLK 0x0278 49 + #define CLK_CON_GAT_MIF_MUX_CMU_MFCMSCL_MSCL 0x027c 50 + #define CLK_CON_MUX_MIF_CMU_MFCMSCL_MSCL 0x027c 51 + #define CLK_CON_GAT_MIF_MUX_CMU_MFCMSCL_MFC 0x0280 52 + #define CLK_CON_MUX_MIF_CMU_MFCMSCL_MFC 0x0280 53 + #define CLK_CON_GAT_MIF_MUX_CMU_FSYS_BUS 0x0284 54 + #define CLK_CON_MUX_MIF_CMU_FSYS_BUS 0x0284 55 + #define CLK_CON_GAT_MIF_MUX_CMU_FSYS_MMC0 0x0288 56 + #define CLK_CON_MUX_MIF_CMU_FSYS_MMC0 0x0288 57 + #define CLK_CON_GAT_MIF_MUX_CMU_FSYS_MMC1 0x028c 58 + #define CLK_CON_MUX_MIF_CMU_FSYS_MMC1 0x028c 59 + #define CLK_CON_GAT_MIF_MUX_CMU_FSYS_MMC2 0x0290 60 + #define CLK_CON_MUX_MIF_CMU_FSYS_MMC2 0x0290 61 + #define CLK_CON_GAT_MIF_MUX_CMU_FSYS_USB20DRD_REFCLK 0x029c 62 + #define CLK_CON_MUX_MIF_CMU_FSYS_USB20DRD_REFCLK 0x029c 63 + #define CLK_CON_GAT_MIF_MUX_CMU_PERI_BUS 0x02a0 64 + #define CLK_CON_MUX_MIF_CMU_PERI_BUS 0x02a0 65 + #define CLK_CON_GAT_MIF_MUX_CMU_PERI_UART1 0x02a4 66 + #define CLK_CON_MUX_MIF_CMU_PERI_UART1 0x02a4 67 + #define CLK_CON_GAT_MIF_MUX_CMU_PERI_UART2 0x02a8 68 + #define CLK_CON_MUX_MIF_CMU_PERI_UART2 0x02a8 69 + #define CLK_CON_GAT_MIF_MUX_CMU_PERI_UART0 0x02ac 70 + #define CLK_CON_MUX_MIF_CMU_PERI_UART0 0x02ac 71 + #define CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI2 0x02b0 72 + #define CLK_CON_MUX_MIF_CMU_PERI_SPI2 0x02b0 73 + #define CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI1 0x02b4 74 + #define CLK_CON_MUX_MIF_CMU_PERI_SPI1 0x02b4 75 + #define CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI0 0x02b8 76 + #define CLK_CON_MUX_MIF_CMU_PERI_SPI0 0x02b8 77 + #define CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI3 0x02bc 78 + #define CLK_CON_MUX_MIF_CMU_PERI_SPI3 0x02bc 79 + #define CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI4 0x02c0 80 + #define CLK_CON_MUX_MIF_CMU_PERI_SPI4 0x02c0 81 + #define CLK_CON_GAT_MIF_MUX_CMU_ISP_SENSOR0 0x02c4 82 + #define CLK_CON_MUX_MIF_CMU_ISP_SENSOR0 0x02c4 83 + #define CLK_CON_GAT_MIF_MUX_CMU_ISP_SENSOR1 0x02c8 84 + #define CLK_CON_MUX_MIF_CMU_ISP_SENSOR1 0x02c8 85 + #define CLK_CON_GAT_MIF_MUX_CMU_ISP_SENSOR2 0x02cc 86 + #define CLK_CON_MUX_MIF_CMU_ISP_SENSOR2 0x02cc 87 + #define CLK_CON_DIV_MIF_BUSD 0x0420 88 + #define CLK_CON_DIV_MIF_APB 0x0424 89 + #define CLK_CON_DIV_MIF_HSI2C 0x0430 90 + #define CLK_CON_DIV_MIF_CMU_G3D_SWITCH 0x0460 91 + #define CLK_CON_DIV_MIF_CMU_ISP_VRA 0x0464 92 + #define CLK_CON_DIV_MIF_CMU_ISP_CAM 0x0468 93 + #define CLK_CON_DIV_MIF_CMU_ISP_ISP 0x046c 94 + #define CLK_CON_DIV_MIF_CMU_DISPAUD_BUS 0x0470 95 + #define CLK_CON_DIV_MIF_CMU_DISPAUD_DECON_VCLK 0x0474 96 + #define CLK_CON_DIV_MIF_CMU_DISPAUD_DECON_ECLK 0x0478 97 + #define CLK_CON_DIV_MIF_CMU_MFCMSCL_MSCL 0x047c 98 + #define CLK_CON_DIV_MIF_CMU_MFCMSCL_MFC 0x0480 99 + #define CLK_CON_DIV_MIF_CMU_FSYS_BUS 0x0484 100 + #define CLK_CON_DIV_MIF_CMU_FSYS_MMC0 0x0488 101 + #define CLK_CON_DIV_MIF_CMU_FSYS_MMC1 0x048c 102 + #define CLK_CON_DIV_MIF_CMU_FSYS_MMC2 0x0490 103 + #define CLK_CON_DIV_MIF_CMU_FSYS_USB20DRD_REFCLK 0x049c 104 + #define CLK_CON_DIV_MIF_CMU_PERI_BUS 0x04a0 105 + #define CLK_CON_DIV_MIF_CMU_PERI_UART1 0x04a4 106 + #define CLK_CON_DIV_MIF_CMU_PERI_UART2 0x04a8 107 + #define CLK_CON_DIV_MIF_CMU_PERI_UART0 0x04ac 108 + #define CLK_CON_DIV_MIF_CMU_PERI_SPI2 0x04b0 109 + #define CLK_CON_DIV_MIF_CMU_PERI_SPI1 0x04b4 110 + #define CLK_CON_DIV_MIF_CMU_PERI_SPI0 0x04b8 111 + #define CLK_CON_DIV_MIF_CMU_PERI_SPI3 0x04bc 112 + #define CLK_CON_DIV_MIF_CMU_PERI_SPI4 0x04c0 113 + #define CLK_CON_DIV_MIF_CMU_ISP_SENSOR0 0x04c4 114 + #define CLK_CON_DIV_MIF_CMU_ISP_SENSOR1 0x04c8 115 + #define CLK_CON_DIV_MIF_CMU_ISP_SENSOR2 0x04cc 116 + #define CLK_CON_GAT_MIF_WRAP_ADC_IF_OSC_SYS 0x080c 117 + #define CLK_CON_GAT_MIF_HSI2C_AP_PCLKS 0x0828 118 + #define CLK_CON_GAT_MIF_HSI2C_CP_PCLKS 0x0828 119 + #define CLK_CON_GAT_MIF_WRAP_ADC_IF_PCLK_S0 0x0828 120 + #define CLK_CON_GAT_MIF_WRAP_ADC_IF_PCLK_S1 0x0828 121 + #define CLK_CON_GAT_MIF_CP_PCLK_HSI2C 0x0840 122 + #define CLK_CON_GAT_MIF_CP_PCLK_HSI2C_BAT_0 0x0840 123 + #define CLK_CON_GAT_MIF_CP_PCLK_HSI2C_BAT_1 0x0840 124 + #define CLK_CON_GAT_MIF_HSI2C_AP_PCLKM 0x0840 125 + #define CLK_CON_GAT_MIF_HSI2C_CP_PCLKM 0x0840 126 + #define CLK_CON_GAT_MIF_HSI2C_IPCLK 0x0840 127 + #define CLK_CON_GAT_MIF_HSI2C_ITCLK 0x0840 128 + #define CLK_CON_GAT_MIF_CMU_G3D_SWITCH 0x0860 129 + #define CLK_CON_GAT_MIF_CMU_ISP_VRA 0x0864 130 + #define CLK_CON_GAT_MIF_CMU_ISP_CAM 0x0868 131 + #define CLK_CON_GAT_MIF_CMU_ISP_ISP 0x086c 132 + #define CLK_CON_GAT_MIF_CMU_DISPAUD_BUS 0x0870 133 + #define CLK_CON_GAT_MIF_CMU_DISPAUD_DECON_VCLK 0x0874 134 + #define CLK_CON_GAT_MIF_CMU_DISPAUD_DECON_ECLK 0x0878 135 + #define CLK_CON_GAT_MIF_CMU_MFCMSCL_MSCL 0x087c 136 + #define CLK_CON_GAT_MIF_CMU_MFCMSCL_MFC 0x0880 137 + #define CLK_CON_GAT_MIF_CMU_FSYS_BUS 0x0884 138 + #define CLK_CON_GAT_MIF_CMU_FSYS_MMC0 0x0888 139 + #define CLK_CON_GAT_MIF_CMU_FSYS_MMC1 0x088c 140 + #define CLK_CON_GAT_MIF_CMU_FSYS_MMC2 0x0890 141 + #define CLK_CON_GAT_MIF_CMU_FSYS_USB20DRD_REFCLK 0x089c 142 + #define CLK_CON_GAT_MIF_CMU_PERI_BUS 0x08a0 143 + #define CLK_CON_GAT_MIF_CMU_PERI_UART1 0x08a4 144 + #define CLK_CON_GAT_MIF_CMU_PERI_UART2 0x08a8 145 + #define CLK_CON_GAT_MIF_CMU_PERI_UART0 0x08ac 146 + #define CLK_CON_GAT_MIF_CMU_PERI_SPI2 0x08b0 147 + #define CLK_CON_GAT_MIF_CMU_PERI_SPI1 0x08b4 148 + #define CLK_CON_GAT_MIF_CMU_PERI_SPI0 0x08b8 149 + #define CLK_CON_GAT_MIF_CMU_PERI_SPI3 0x08bc 150 + #define CLK_CON_GAT_MIF_CMU_PERI_SPI4 0x08c0 151 + #define CLK_CON_GAT_MIF_CMU_ISP_SENSOR0 0x08c4 152 + #define CLK_CON_GAT_MIF_CMU_ISP_SENSOR1 0x08c8 153 + #define CLK_CON_GAT_MIF_CMU_ISP_SENSOR2 0x08cc 154 + 155 + static const struct samsung_pll_clock mif_pll_clks[] = { 156 + PLL(pll_1417x, CLK_FOUT_MIF_BUS_PLL, "fout_mif_bus_pll", "oscclk", 157 + PLL_CON0_MIF_BUS_PLL), 158 + PLL(pll_1417x, CLK_FOUT_MIF_MEDIA_PLL, "fout_mif_media_pll", "oscclk", 159 + PLL_CON0_MIF_MEDIA_PLL), 160 + PLL(pll_1417x, CLK_FOUT_MIF_MEM_PLL, "fout_mif_mem_pll", "oscclk", 161 + PLL_CON0_MIF_MEM_PLL), 162 + }; 163 + 164 + static const struct samsung_gate_clock mif_pll_gate_clks[] = { 165 + GATE(CLK_GOUT_MIF_MUX_BUS_PLL_CON, 166 + "gout_mif_mux_bus_pll_con", "fout_mif_bus_pll", 167 + CLK_CON_GAT_MIF_MUX_BUS_PLL_CON, 12, 168 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 169 + GATE(CLK_GOUT_MIF_MUX_MEDIA_PLL_CON, 170 + "gout_mif_mux_media_pll_con", "fout_mif_media_pll", 171 + CLK_CON_GAT_MIF_MUX_MEDIA_PLL_CON, 12, 172 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 173 + GATE(CLK_GOUT_MIF_MUX_MEM_PLL_CON, 174 + "gout_mif_mux_mem_pll_con", "fout_mif_mem_pll", 175 + CLK_CON_GAT_MIF_MUX_MEM_PLL_CON, 12, 176 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 177 + GATE(CLK_GOUT_MIF_MUX_BUS_PLL, 178 + "gout_mif_mux_bus_pll", "gout_mif_mux_bus_pll_con", 179 + CLK_CON_GAT_MIF_MUX_BUS_PLL, 21, 180 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 181 + GATE(CLK_GOUT_MIF_MUX_MEM_PLL, 182 + "gout_mif_mux_mem_pll", "gout_mif_mux_mem_pll_con", 183 + CLK_CON_GAT_MIF_MUX_MEM_PLL, 21, 184 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 185 + GATE(CLK_GOUT_MIF_MUX_MEDIA_PLL, 186 + "gout_mif_mux_media_pll", "gout_mif_mux_media_pll_con", 187 + CLK_CON_GAT_MIF_MUX_MEDIA_PLL, 21, 188 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 189 + }; 190 + 191 + static const struct samsung_fixed_factor_clock mif_fixed_factor_clks[] = { 192 + FFACTOR(0, "ffac_mif_mux_bus_pll_div2", "gout_mif_mux_bus_pll_con", 193 + 1, 2, 0), 194 + FFACTOR(0, "ffac_mif_mux_media_pll_div2", "gout_mif_mux_media_pll_con", 195 + 1, 2, 0), 196 + FFACTOR(0, "ffac_mif_mux_mem_pll_div2", "gout_mif_mux_mem_pll_con", 197 + 1, 2, 0), 198 + }; 199 + 200 + /* List of parent clocks for muxes in CMU_MIF */ 201 + PNAME(mout_mif_busd_p) = { "ffac_mif_mux_bus_pll_div2", 202 + "ffac_mif_mux_media_pll_div2", 203 + "ffac_mif_mux_mem_pll_div2" }; 204 + PNAME(mout_mif_cmu_fsys_bus_p) = { "ffac_mif_mux_bus_pll_div2", 205 + "ffac_mif_mux_media_pll_div2" }; 206 + PNAME(mout_mif_cmu_fsys_mmc0_p) = { "ffac_mif_mux_bus_pll_div2", 207 + "ffac_mif_mux_media_pll_div2" }; 208 + PNAME(mout_mif_cmu_fsys_mmc1_p) = { "ffac_mif_mux_bus_pll_div2", 209 + "ffac_mif_mux_media_pll_div2" }; 210 + PNAME(mout_mif_cmu_fsys_mmc2_p) = { "ffac_mif_mux_bus_pll_div2", 211 + "ffac_mif_mux_media_pll_div2" }; 212 + PNAME(mout_mif_cmu_fsys_usb20drd_refclk_p) = { "ffac_mif_mux_bus_pll_div2", 213 + "ffac_mif_mux_media_pll_div2" }; 214 + PNAME(mout_mif_cmu_peri_bus_p) = { "ffac_mif_mux_bus_pll_div2", 215 + "ffac_mif_mux_media_pll_div2" }; 216 + PNAME(mout_mif_cmu_peri_spi0_p) = { "ffac_mif_mux_bus_pll_div2", 217 + "oscclk" }; 218 + PNAME(mout_mif_cmu_peri_spi1_p) = { "ffac_mif_mux_bus_pll_div2", 219 + "oscclk" }; 220 + PNAME(mout_mif_cmu_peri_spi2_p) = { "ffac_mif_mux_bus_pll_div2", 221 + "oscclk" }; 222 + PNAME(mout_mif_cmu_peri_spi3_p) = { "ffac_mif_mux_bus_pll_div2", 223 + "oscclk" }; 224 + PNAME(mout_mif_cmu_peri_spi4_p) = { "ffac_mif_mux_bus_pll_div2", 225 + "oscclk" }; 226 + PNAME(mout_mif_cmu_peri_uart2_p) = { "ffac_mif_mux_bus_pll_div2", 227 + "ffac_mif_mux_media_pll_div2" }; 228 + PNAME(mout_mif_cmu_peri_uart0_p) = { "ffac_mif_mux_bus_pll_div2", 229 + "ffac_mif_mux_media_pll_div2" }; 230 + PNAME(mout_mif_cmu_peri_uart1_p) = { "ffac_mif_mux_bus_pll_div2", 231 + "ffac_mif_mux_media_pll_div2" }; 232 + 233 + static const struct samsung_mux_clock mif_mux_clks[] = { 234 + MUX(CLK_MOUT_MIF_BUSD, 235 + "mout_mif_busd", mout_mif_busd_p, 236 + CLK_CON_MUX_MIF_BUSD, 12, 2), 237 + MUX(CLK_MOUT_MIF_CMU_FSYS_BUS, 238 + "mout_mif_cmu_fsys_bus", mout_mif_cmu_fsys_bus_p, 239 + CLK_CON_MUX_MIF_CMU_FSYS_BUS, 12, 1), 240 + MUX(CLK_MOUT_MIF_CMU_FSYS_MMC0, 241 + "mout_mif_cmu_fsys_mmc0", mout_mif_cmu_fsys_mmc0_p, 242 + CLK_CON_MUX_MIF_CMU_FSYS_MMC0, 12, 1), 243 + MUX(CLK_MOUT_MIF_CMU_FSYS_MMC1, 244 + "mout_mif_cmu_fsys_mmc1", mout_mif_cmu_fsys_mmc1_p, 245 + CLK_CON_MUX_MIF_CMU_FSYS_MMC1, 12, 1), 246 + MUX(CLK_MOUT_MIF_CMU_FSYS_MMC2, 247 + "mout_mif_cmu_fsys_mmc2", mout_mif_cmu_fsys_mmc2_p, 248 + CLK_CON_MUX_MIF_CMU_FSYS_MMC2, 12, 1), 249 + MUX(CLK_MOUT_MIF_CMU_FSYS_USB20DRD_REFCLK, 250 + "mout_mif_cmu_fsys_usb20drd_refclk", mout_mif_cmu_fsys_usb20drd_refclk_p, 251 + CLK_CON_MUX_MIF_CMU_FSYS_USB20DRD_REFCLK, 12, 1), 252 + MUX(CLK_MOUT_MIF_CMU_PERI_BUS, 253 + "mout_mif_cmu_peri_bus", mout_mif_cmu_peri_bus_p, 254 + CLK_CON_MUX_MIF_CMU_PERI_BUS, 12, 1), 255 + MUX(CLK_MOUT_MIF_CMU_PERI_SPI0, 256 + "mout_mif_cmu_peri_spi0", mout_mif_cmu_peri_spi0_p, 257 + CLK_CON_MUX_MIF_CMU_PERI_SPI0, 12, 1), 258 + MUX(CLK_MOUT_MIF_CMU_PERI_SPI1, 259 + "mout_mif_cmu_peri_spi1", mout_mif_cmu_peri_spi1_p, 260 + CLK_CON_MUX_MIF_CMU_PERI_SPI1, 12, 1), 261 + MUX(CLK_MOUT_MIF_CMU_PERI_SPI2, 262 + "mout_mif_cmu_peri_spi2", mout_mif_cmu_peri_spi2_p, 263 + CLK_CON_MUX_MIF_CMU_PERI_SPI2, 12, 1), 264 + MUX(CLK_MOUT_MIF_CMU_PERI_SPI3, 265 + "mout_mif_cmu_peri_spi3", mout_mif_cmu_peri_spi3_p, 266 + CLK_CON_MUX_MIF_CMU_PERI_SPI3, 12, 1), 267 + MUX(CLK_MOUT_MIF_CMU_PERI_SPI4, 268 + "mout_mif_cmu_peri_spi4", mout_mif_cmu_peri_spi4_p, 269 + CLK_CON_MUX_MIF_CMU_PERI_SPI4, 12, 1), 270 + MUX(CLK_MOUT_MIF_CMU_PERI_UART0, 271 + "mout_mif_cmu_peri_uart0", mout_mif_cmu_peri_uart0_p, 272 + CLK_CON_MUX_MIF_CMU_PERI_UART0, 12, 1), 273 + MUX(CLK_MOUT_MIF_CMU_PERI_UART1, 274 + "mout_mif_cmu_peri_uart1", mout_mif_cmu_peri_uart1_p, 275 + CLK_CON_MUX_MIF_CMU_PERI_UART1, 12, 1), 276 + MUX(CLK_MOUT_MIF_CMU_PERI_UART2, 277 + "mout_mif_cmu_peri_uart2", mout_mif_cmu_peri_uart2_p, 278 + CLK_CON_MUX_MIF_CMU_PERI_UART2, 12, 1), 279 + }; 280 + 281 + static const struct samsung_gate_clock mif_mux_gate_clks[] = { 282 + GATE(CLK_GOUT_MIF_MUX_BUSD, 283 + "gout_mif_mux_busd", "mout_mif_busd", 284 + CLK_CON_GAT_MIF_MUX_BUSD, 21, 285 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 286 + GATE(CLK_GOUT_MIF_MUX_CMU_FSYS_BUS, 287 + "gout_mif_mux_cmu_fsys_bus", "mout_mif_cmu_fsys_bus", 288 + CLK_CON_GAT_MIF_MUX_CMU_FSYS_BUS, 21, 289 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 290 + GATE(CLK_GOUT_MIF_MUX_CMU_FSYS_MMC0, 291 + "gout_mif_mux_cmu_fsys_mmc0", "mout_mif_cmu_fsys_mmc0", 292 + CLK_CON_GAT_MIF_MUX_CMU_FSYS_MMC0, 21, 293 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 294 + GATE(CLK_GOUT_MIF_MUX_CMU_FSYS_MMC1, 295 + "gout_mif_mux_cmu_fsys_mmc1", "mout_mif_cmu_fsys_mmc1", 296 + CLK_CON_GAT_MIF_MUX_CMU_FSYS_MMC1, 21, 297 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 298 + GATE(CLK_GOUT_MIF_MUX_CMU_FSYS_MMC2, 299 + "gout_mif_mux_cmu_fsys_mmc2", "mout_mif_cmu_fsys_mmc2", 300 + CLK_CON_GAT_MIF_MUX_CMU_FSYS_MMC2, 21, 301 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 302 + GATE(CLK_GOUT_MIF_MUX_CMU_FSYS_USB20DRD_REFCLK, 303 + "gout_mif_mux_cmu_fsys_usb20drd_refclk", "mout_mif_cmu_fsys_usb20drd_refclk", 304 + CLK_CON_GAT_MIF_MUX_CMU_FSYS_USB20DRD_REFCLK, 21, 305 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 306 + GATE(CLK_GOUT_MIF_MUX_CMU_PERI_BUS, 307 + "gout_mif_mux_cmu_peri_bus", "mout_mif_cmu_peri_bus", 308 + CLK_CON_GAT_MIF_MUX_CMU_PERI_BUS, 21, 309 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 310 + GATE(CLK_GOUT_MIF_MUX_CMU_PERI_SPI0, 311 + "gout_mif_mux_cmu_peri_spi0", "mout_mif_cmu_peri_spi0", 312 + CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI0, 21, 313 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 314 + GATE(CLK_GOUT_MIF_MUX_CMU_PERI_SPI1, 315 + "gout_mif_mux_cmu_peri_spi1", "mout_mif_cmu_peri_spi1", 316 + CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI1, 21, 317 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 318 + GATE(CLK_GOUT_MIF_MUX_CMU_PERI_SPI2, 319 + "gout_mif_mux_cmu_peri_spi2", "mout_mif_cmu_peri_spi2", 320 + CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI2, 21, 321 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 322 + GATE(CLK_GOUT_MIF_MUX_CMU_PERI_SPI3, 323 + "gout_mif_mux_cmu_peri_spi3", "mout_mif_cmu_peri_spi3", 324 + CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI3, 21, 325 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 326 + GATE(CLK_GOUT_MIF_MUX_CMU_PERI_SPI4, 327 + "gout_mif_mux_cmu_peri_spi4", "mout_mif_cmu_peri_spi4", 328 + CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI4, 21, 329 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 330 + GATE(CLK_GOUT_MIF_MUX_CMU_PERI_UART0, 331 + "gout_mif_mux_cmu_peri_uart0", "mout_mif_cmu_peri_uart0", 332 + CLK_CON_GAT_MIF_MUX_CMU_PERI_UART0, 21, 333 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 334 + GATE(CLK_GOUT_MIF_MUX_CMU_PERI_UART1, 335 + "gout_mif_mux_cmu_peri_uart1", "mout_mif_cmu_peri_uart1", 336 + CLK_CON_GAT_MIF_MUX_CMU_PERI_UART1, 21, 337 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 338 + GATE(CLK_GOUT_MIF_MUX_CMU_PERI_UART2, 339 + "gout_mif_mux_cmu_peri_uart2", "mout_mif_cmu_peri_uart2", 340 + CLK_CON_GAT_MIF_MUX_CMU_PERI_UART2, 21, 341 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 342 + }; 343 + 344 + static const struct samsung_div_clock mif_div_clks[] = { 345 + DIV(CLK_DOUT_MIF_HSI2C, 346 + "dout_mif_hsi2c", "ffac_mif_mux_media_pll_div2", 347 + CLK_CON_DIV_MIF_HSI2C, 0, 4), 348 + DIV(CLK_DOUT_MIF_BUSD, 349 + "dout_mif_busd", "gout_mif_mux_busd", 350 + CLK_CON_DIV_MIF_BUSD, 0, 4), 351 + DIV(CLK_DOUT_MIF_CMU_FSYS_BUS, 352 + "dout_mif_cmu_fsys_bus", "gout_mif_mux_cmu_fsys_bus", 353 + CLK_CON_DIV_MIF_CMU_FSYS_BUS, 0, 4), 354 + DIV(CLK_DOUT_MIF_CMU_FSYS_MMC0, 355 + "dout_mif_cmu_fsys_mmc0", "gout_mif_mux_cmu_fsys_mmc0", 356 + CLK_CON_DIV_MIF_CMU_FSYS_MMC0, 0, 10), 357 + DIV(CLK_DOUT_MIF_CMU_FSYS_MMC1, 358 + "dout_mif_cmu_fsys_mmc1", "gout_mif_mux_cmu_fsys_mmc1", 359 + CLK_CON_DIV_MIF_CMU_FSYS_MMC1, 0, 10), 360 + DIV(CLK_DOUT_MIF_CMU_FSYS_MMC2, 361 + "dout_mif_cmu_fsys_mmc2", "gout_mif_mux_cmu_fsys_mmc2", 362 + CLK_CON_DIV_MIF_CMU_FSYS_MMC2, 0, 10), 363 + DIV(CLK_DOUT_MIF_CMU_FSYS_USB20DRD_REFCLK, 364 + "dout_mif_cmu_fsys_usb20drd_refclk", "gout_mif_mux_cmu_fsys_usb20drd_refclk", 365 + CLK_CON_DIV_MIF_CMU_FSYS_USB20DRD_REFCLK, 0, 4), 366 + DIV(CLK_DOUT_MIF_CMU_PERI_BUS, 367 + "dout_mif_cmu_peri_bus", "gout_mif_mux_cmu_peri_bus", 368 + CLK_CON_DIV_MIF_CMU_PERI_BUS, 0, 4), 369 + DIV(CLK_DOUT_MIF_CMU_PERI_SPI0, 370 + "dout_mif_cmu_peri_spi0", "gout_mif_mux_cmu_peri_spi0", 371 + CLK_CON_DIV_MIF_CMU_PERI_SPI0, 0, 6), 372 + DIV(CLK_DOUT_MIF_CMU_PERI_SPI1, 373 + "dout_mif_cmu_peri_spi1", "gout_mif_mux_cmu_peri_spi1", 374 + CLK_CON_DIV_MIF_CMU_PERI_SPI1, 0, 6), 375 + DIV(CLK_DOUT_MIF_CMU_PERI_SPI2, 376 + "dout_mif_cmu_peri_spi2", "gout_mif_mux_cmu_peri_spi2", 377 + CLK_CON_DIV_MIF_CMU_PERI_SPI2, 0, 6), 378 + DIV(CLK_DOUT_MIF_CMU_PERI_SPI3, 379 + "dout_mif_cmu_peri_spi3", "gout_mif_mux_cmu_peri_spi3", 380 + CLK_CON_DIV_MIF_CMU_PERI_SPI3, 0, 6), 381 + DIV(CLK_DOUT_MIF_CMU_PERI_SPI4, 382 + "dout_mif_cmu_peri_spi4", "gout_mif_mux_cmu_peri_spi4", 383 + CLK_CON_DIV_MIF_CMU_PERI_SPI4, 0, 6), 384 + DIV(CLK_DOUT_MIF_CMU_PERI_UART0, 385 + "dout_mif_cmu_peri_uart0", "gout_mif_mux_cmu_peri_uart0", 386 + CLK_CON_DIV_MIF_CMU_PERI_UART0, 0, 4), 387 + DIV(CLK_DOUT_MIF_CMU_PERI_UART1, 388 + "dout_mif_cmu_peri_uart1", "gout_mif_mux_cmu_peri_uart1", 389 + CLK_CON_DIV_MIF_CMU_PERI_UART1, 0, 4), 390 + DIV(CLK_DOUT_MIF_CMU_PERI_UART2, 391 + "dout_mif_cmu_peri_uart2", "gout_mif_mux_cmu_peri_uart2", 392 + CLK_CON_DIV_MIF_CMU_PERI_UART2, 0, 4), 393 + DIV(CLK_DOUT_MIF_APB, 394 + "dout_mif_apb", "dout_mif_busd", 395 + CLK_CON_DIV_MIF_APB, 0, 2), 396 + }; 397 + 398 + static const struct samsung_gate_clock mif_gate_clks[] = { 399 + GATE(CLK_GOUT_MIF_WRAP_ADC_IF_OSC_SYS, 400 + "gout_mif_wrap_adc_if_osc_sys", "oscclk", 401 + CLK_CON_GAT_MIF_WRAP_ADC_IF_OSC_SYS, 3, 402 + CLK_SET_RATE_PARENT, 0), 403 + GATE(CLK_GOUT_MIF_HSI2C_AP_PCLKS, 404 + "gout_mif_hsi2c_ap_pclks", "dout_mif_apb", 405 + CLK_CON_GAT_MIF_HSI2C_AP_PCLKS, 14, 406 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 407 + GATE(CLK_GOUT_MIF_HSI2C_CP_PCLKS, 408 + "gout_mif_hsi2c_cp_pclks", "dout_mif_apb", 409 + CLK_CON_GAT_MIF_HSI2C_CP_PCLKS, 15, 410 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 411 + GATE(CLK_GOUT_MIF_WRAP_ADC_IF_PCLK_S0, 412 + "gout_mif_wrap_adc_if_pclk_s0", "dout_mif_apb", 413 + CLK_CON_GAT_MIF_WRAP_ADC_IF_PCLK_S0, 20, 414 + CLK_SET_RATE_PARENT, 0), 415 + GATE(CLK_GOUT_MIF_WRAP_ADC_IF_PCLK_S1, 416 + "gout_mif_wrap_adc_if_pclk_s1", "dout_mif_apb", 417 + CLK_CON_GAT_MIF_WRAP_ADC_IF_PCLK_S1, 21, 418 + CLK_SET_RATE_PARENT, 0), 419 + GATE(CLK_GOUT_MIF_CMU_FSYS_BUS, 420 + "gout_mif_cmu_fsys_bus", "dout_mif_cmu_fsys_bus", 421 + CLK_CON_GAT_MIF_CMU_FSYS_BUS, 0, 422 + CLK_SET_RATE_PARENT, 0), 423 + GATE(CLK_GOUT_MIF_CMU_FSYS_MMC0, 424 + "gout_mif_cmu_fsys_mmc0", "dout_mif_cmu_fsys_mmc0", 425 + CLK_CON_GAT_MIF_CMU_FSYS_MMC0, 0, 426 + CLK_SET_RATE_PARENT, 0), 427 + GATE(CLK_GOUT_MIF_CMU_FSYS_MMC1, 428 + "gout_mif_cmu_fsys_mmc1", "dout_mif_cmu_fsys_mmc1", 429 + CLK_CON_GAT_MIF_CMU_FSYS_MMC1, 0, 430 + CLK_SET_RATE_PARENT, 0), 431 + GATE(CLK_GOUT_MIF_CMU_FSYS_MMC2, 432 + "gout_mif_cmu_fsys_mmc2", "dout_mif_cmu_fsys_mmc2", 433 + CLK_CON_GAT_MIF_CMU_FSYS_MMC2, 0, 434 + CLK_SET_RATE_PARENT, 0), 435 + GATE(CLK_GOUT_MIF_CMU_FSYS_USB20DRD_REFCLK, 436 + "gout_mif_cmu_fsys_usb20drd_refclk", "dout_mif_cmu_fsys_usb20drd_refclk", 437 + CLK_CON_GAT_MIF_CMU_FSYS_USB20DRD_REFCLK, 0, 438 + CLK_SET_RATE_PARENT, 0), 439 + GATE(CLK_GOUT_MIF_CMU_PERI_BUS, 440 + "gout_mif_cmu_peri_bus", "dout_mif_cmu_peri_bus", 441 + CLK_CON_GAT_MIF_CMU_PERI_BUS, 0, 442 + CLK_SET_RATE_PARENT, 0), 443 + GATE(CLK_GOUT_MIF_CMU_PERI_SPI0, 444 + "gout_mif_cmu_peri_spi0", "dout_mif_cmu_peri_spi0", 445 + CLK_CON_GAT_MIF_CMU_PERI_SPI0, 0, 446 + CLK_SET_RATE_PARENT, 0), 447 + GATE(CLK_GOUT_MIF_CMU_PERI_SPI1, 448 + "gout_mif_cmu_peri_spi1", "dout_mif_cmu_peri_spi1", 449 + CLK_CON_GAT_MIF_CMU_PERI_SPI1, 0, 450 + CLK_SET_RATE_PARENT, 0), 451 + GATE(CLK_GOUT_MIF_CMU_PERI_SPI2, 452 + "gout_mif_cmu_peri_spi2", "dout_mif_cmu_peri_spi2", 453 + CLK_CON_GAT_MIF_CMU_PERI_SPI2, 0, 454 + CLK_SET_RATE_PARENT, 0), 455 + GATE(CLK_GOUT_MIF_CMU_PERI_SPI3, 456 + "gout_mif_cmu_peri_spi3", "dout_mif_cmu_peri_spi3", 457 + CLK_CON_GAT_MIF_CMU_PERI_SPI3, 0, 458 + CLK_SET_RATE_PARENT, 0), 459 + GATE(CLK_GOUT_MIF_CMU_PERI_SPI4, 460 + "gout_mif_cmu_peri_spi4", "dout_mif_cmu_peri_spi4", 461 + CLK_CON_GAT_MIF_CMU_PERI_SPI4, 0, 462 + CLK_SET_RATE_PARENT, 0), 463 + GATE(CLK_GOUT_MIF_CMU_PERI_UART0, 464 + "gout_mif_cmu_peri_uart0", "dout_mif_cmu_peri_uart0", 465 + CLK_CON_GAT_MIF_CMU_PERI_UART0, 0, 466 + CLK_SET_RATE_PARENT, 0), 467 + GATE(CLK_GOUT_MIF_CMU_PERI_UART1, 468 + "gout_mif_cmu_peri_uart1", "dout_mif_cmu_peri_uart1", 469 + CLK_CON_GAT_MIF_CMU_PERI_UART1, 0, 470 + CLK_SET_RATE_PARENT, 0), 471 + GATE(CLK_GOUT_MIF_CMU_PERI_UART2, 472 + "gout_mif_cmu_peri_uart2", "dout_mif_cmu_peri_uart2", 473 + CLK_CON_GAT_MIF_CMU_PERI_UART2, 0, 474 + CLK_SET_RATE_PARENT, 0), 475 + GATE(CLK_GOUT_MIF_CP_PCLK_HSI2C, 476 + "gout_mif_cp_pclk_hsi2c", "dout_mif_hsi2c", 477 + CLK_CON_GAT_MIF_CP_PCLK_HSI2C, 6, 478 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 479 + GATE(CLK_GOUT_MIF_CP_PCLK_HSI2C_BAT_0, 480 + "gout_mif_cp_pclk_hsi2c_bat_0", "dout_mif_hsi2c", 481 + CLK_CON_GAT_MIF_CP_PCLK_HSI2C_BAT_0, 4, 482 + CLK_SET_RATE_PARENT, 0), 483 + GATE(CLK_GOUT_MIF_CP_PCLK_HSI2C_BAT_1, 484 + "gout_mif_cp_pclk_hsi2c_bat_1", "dout_mif_hsi2c", 485 + CLK_CON_GAT_MIF_CP_PCLK_HSI2C_BAT_1, 5, 486 + CLK_SET_RATE_PARENT, 0), 487 + GATE(CLK_GOUT_MIF_HSI2C_AP_PCLKM, 488 + "gout_mif_hsi2c_ap_pclkm", "dout_mif_hsi2c", 489 + CLK_CON_GAT_MIF_HSI2C_AP_PCLKM, 0, 490 + CLK_SET_RATE_PARENT, 0), 491 + GATE(CLK_GOUT_MIF_HSI2C_CP_PCLKM, 492 + "gout_mif_hsi2c_cp_pclkm", "dout_mif_hsi2c", 493 + CLK_CON_GAT_MIF_HSI2C_CP_PCLKM, 1, 494 + CLK_SET_RATE_PARENT, 0), 495 + GATE(CLK_GOUT_MIF_HSI2C_IPCLK, 496 + "gout_mif_hsi2c_ipclk", "dout_mif_hsi2c", 497 + CLK_CON_GAT_MIF_HSI2C_IPCLK, 2, 498 + CLK_SET_RATE_PARENT, 0), 499 + GATE(CLK_GOUT_MIF_HSI2C_ITCLK, 500 + "gout_mif_hsi2c_itclk", "dout_mif_hsi2c", 501 + CLK_CON_GAT_MIF_HSI2C_ITCLK, 3, 502 + CLK_SET_RATE_PARENT, 0), 503 + }; 504 + 505 + static const struct samsung_clk_group mif_cmu_clks[] = { 506 + { S_CLK_PLL, mif_pll_clks, ARRAY_SIZE(mif_pll_clks) }, 507 + { S_CLK_GATE, mif_pll_gate_clks, ARRAY_SIZE(mif_pll_gate_clks) }, 508 + { S_CLK_FFACTOR, mif_fixed_factor_clks, ARRAY_SIZE(mif_fixed_factor_clks) }, 509 + { S_CLK_MUX, mif_mux_clks, ARRAY_SIZE(mif_mux_clks) }, 510 + { S_CLK_GATE, mif_mux_gate_clks, ARRAY_SIZE(mif_mux_gate_clks) }, 511 + { S_CLK_DIV, mif_div_clks, ARRAY_SIZE(mif_div_clks) }, 512 + { S_CLK_GATE, mif_gate_clks, ARRAY_SIZE(mif_gate_clks) }, 513 + }; 514 + 515 + static int exynos7870_cmu_mif_probe(struct udevice *dev) 516 + { 517 + return samsung_register_cmu(dev, CMU_MIF, mif_cmu_clks, 518 + exynos7870_cmu_mif); 519 + } 520 + 521 + static const struct udevice_id exynos7870_cmu_mif_ids[] = { 522 + { .compatible = "samsung,exynos7870-cmu-mif" }, 523 + { } 524 + }; 525 + 526 + SAMSUNG_CLK_OPS(exynos7870_cmu_mif, CMU_MIF); 527 + 528 + U_BOOT_DRIVER(exynos7870_cmu_mif) = { 529 + .name = "exynos7870-cmu-mif", 530 + .id = UCLASS_CLK, 531 + .of_match = exynos7870_cmu_mif_ids, 532 + .ops = &exynos7870_cmu_mif_clk_ops, 533 + .probe = exynos7870_cmu_mif_probe, 534 + .flags = DM_FLAG_PRE_RELOC, 535 + }; 536 + 537 + /* 538 + * Register offsets for CMU_FSYS (0x13730000) 539 + */ 540 + #define PLL_LOCKTIME_FSYS_USB_PLL 0x0000 541 + #define PLL_CON0_FSYS_USB_PLL 0x0100 542 + #define CLK_CON_GAT_FSYS_MUX_USB_PLL 0x0200 543 + #define CLK_CON_GAT_FSYS_MUX_USB_PLL_CON 0x0200 544 + #define CLK_CON_GAT_FSYS_MUX_USB20DRD_PHYCLOCK_USER 0x0230 545 + #define CLK_CON_GAT_FSYS_MUX_USB20DRD_PHYCLOCK_USER_CON 0x0230 546 + #define CLK_CON_GAT_FSYS_BUSP3_HCLK 0x0804 547 + #define CLK_CON_GAT_FSYS_MMC0_ACLK 0x0804 548 + #define CLK_CON_GAT_FSYS_MMC1_ACLK 0x0804 549 + #define CLK_CON_GAT_FSYS_MMC2_ACLK 0x0804 550 + #define CLK_CON_GAT_FSYS_PDMA0_ACLK_PDMA0 0x0804 551 + #define CLK_CON_GAT_FSYS_PPMU_ACLK 0x0804 552 + #define CLK_CON_GAT_FSYS_PPMU_PCLK 0x0804 553 + #define CLK_CON_GAT_FSYS_SROMC_HCLK 0x0804 554 + #define CLK_CON_GAT_FSYS_UPSIZER_BUS1_ACLK 0x0804 555 + #define CLK_CON_GAT_FSYS_USB20DRD_ACLK_HSDRD 0x0804 556 + #define CLK_CON_GAT_FSYS_USB20DRD_HCLK_USB20_CTRL 0x0804 557 + #define CLK_CON_GAT_FSYS_USB20DRD_HSDRD_REF_CLK 0x0828 558 + 559 + static const struct samsung_fixed_rate_clock fsys_fixed_rate_clks[] = { 560 + FRATE(0, "frat_fsys_usb20drd_phyclock", 60000000), 561 + }; 562 + 563 + static const struct samsung_pll_clock fsys_pll_clks[] = { 564 + PLL(pll_1417x, CLK_FOUT_FSYS_USB_PLL, "fout_fsys_usb_pll", "oscclk", 565 + PLL_CON0_FSYS_USB_PLL), 566 + }; 567 + 568 + static const struct samsung_gate_clock fsys_gate_clks[] = { 569 + GATE(CLK_GOUT_FSYS_BUSP3_HCLK, 570 + "gout_fsys_busp3_hclk", "bus", 571 + CLK_CON_GAT_FSYS_BUSP3_HCLK, 2, 572 + CLK_SET_RATE_PARENT, 0), 573 + GATE(CLK_GOUT_FSYS_UPSIZER_BUS1_ACLK, 574 + "gout_fsys_upsizer_bus1_aclk", "bus", 575 + CLK_CON_GAT_FSYS_UPSIZER_BUS1_ACLK, 12, 576 + CLK_SET_RATE_PARENT, 0), 577 + GATE(CLK_GOUT_FSYS_PPMU_ACLK, 578 + "gout_fsys_ppmu_aclk", "bus", 579 + CLK_CON_GAT_FSYS_PPMU_ACLK, 17, 580 + CLK_SET_RATE_PARENT, 0), 581 + GATE(CLK_GOUT_FSYS_PPMU_PCLK, 582 + "gout_fsys_ppmu_pclk", "bus", 583 + CLK_CON_GAT_FSYS_PPMU_PCLK, 18, 584 + CLK_SET_RATE_PARENT, 0), 585 + GATE(CLK_GOUT_FSYS_USB20DRD_HSDRD_REF_CLK, 586 + "gout_fsys_usb20drd_hsdrd_ref_clk", "usb20drd", 587 + CLK_CON_GAT_FSYS_USB20DRD_HSDRD_REF_CLK, 0, 588 + CLK_SET_RATE_PARENT, 0), 589 + GATE(CLK_GOUT_FSYS_MUX_USB20DRD_PHYCLOCK_USER_CON, 590 + "gout_fsys_mux_usb20drd_phyclock_user_con", "frat_fsys_usb20drd_phyclock", 591 + CLK_CON_GAT_FSYS_MUX_USB20DRD_PHYCLOCK_USER_CON, 12, 592 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 593 + GATE(CLK_GOUT_FSYS_MUX_USB_PLL_CON, 594 + "gout_fsys_mux_usb_pll_con", "fout_fsys_usb_pll", 595 + CLK_CON_GAT_FSYS_MUX_USB_PLL_CON, 12, 596 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 597 + GATE(CLK_GOUT_FSYS_MMC0_ACLK, 598 + "gout_fsys_mmc0_aclk", "gout_fsys_busp3_hclk", 599 + CLK_CON_GAT_FSYS_MMC0_ACLK, 8, 600 + CLK_SET_RATE_PARENT, 0), 601 + GATE(CLK_GOUT_FSYS_MMC1_ACLK, 602 + "gout_fsys_mmc1_aclk", "gout_fsys_busp3_hclk", 603 + CLK_CON_GAT_FSYS_MMC1_ACLK, 9, 604 + CLK_SET_RATE_PARENT, 0), 605 + GATE(CLK_GOUT_FSYS_MMC2_ACLK, 606 + "gout_fsys_mmc2_aclk", "gout_fsys_busp3_hclk", 607 + CLK_CON_GAT_FSYS_MMC2_ACLK, 10, 608 + CLK_SET_RATE_PARENT, 0), 609 + GATE(CLK_GOUT_FSYS_USB20DRD_ACLK_HSDRD, 610 + "gout_fsys_usb20drd_aclk_hsdrd", "gout_fsys_busp3_hclk", 611 + CLK_CON_GAT_FSYS_USB20DRD_ACLK_HSDRD, 20, 612 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 613 + GATE(CLK_GOUT_FSYS_SROMC_HCLK, 614 + "gout_fsys_sromc_hclk", "gout_fsys_busp3_hclk", 615 + CLK_CON_GAT_FSYS_SROMC_HCLK, 6, 616 + CLK_SET_RATE_PARENT, 0), 617 + GATE(CLK_GOUT_FSYS_USB20DRD_HCLK_USB20_CTRL, 618 + "gout_fsys_usb20drd_hclk_usb20_ctrl", "gout_fsys_busp3_hclk", 619 + CLK_CON_GAT_FSYS_USB20DRD_HCLK_USB20_CTRL, 21, 620 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 621 + GATE(CLK_GOUT_FSYS_MUX_USB_PLL, 622 + "gout_fsys_mux_usb_pll", "gout_fsys_mux_usb_pll_con", 623 + CLK_CON_GAT_FSYS_MUX_USB_PLL, 21, 624 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 625 + GATE(CLK_GOUT_FSYS_MUX_USB20DRD_PHYCLOCK_USER, 626 + "gout_fsys_mux_usb20drd_phyclock_user", "gout_fsys_mux_usb20drd_phyclock_user_con", 627 + CLK_CON_GAT_FSYS_MUX_USB20DRD_PHYCLOCK_USER, 21, 628 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), 629 + GATE(CLK_GOUT_FSYS_PDMA0_ACLK_PDMA0, 630 + "gout_fsys_pdma0_aclk_pdma0", "gout_fsys_upsizer_bus1_aclk", 631 + CLK_CON_GAT_FSYS_PDMA0_ACLK_PDMA0, 7, 632 + CLK_SET_RATE_PARENT, 0), 633 + }; 634 + 635 + static const struct samsung_clk_group fsys_cmu_clks[] = { 636 + { S_CLK_FRATE, fsys_fixed_rate_clks, ARRAY_SIZE(fsys_fixed_rate_clks) }, 637 + { S_CLK_PLL, fsys_pll_clks, ARRAY_SIZE(fsys_pll_clks) }, 638 + { S_CLK_GATE, fsys_gate_clks, ARRAY_SIZE(fsys_gate_clks) }, 639 + }; 640 + 641 + static int exynos7870_cmu_fsys_probe(struct udevice *dev) 642 + { 643 + return samsung_register_cmu(dev, CMU_FSYS, fsys_cmu_clks, 644 + exynos7870_cmu_fsys); 645 + } 646 + 647 + static const struct udevice_id exynos7870_cmu_fsys_ids[] = { 648 + { .compatible = "samsung,exynos7870-cmu-fsys" }, 649 + { } 650 + }; 651 + 652 + SAMSUNG_CLK_OPS(exynos7870_cmu_fsys, CMU_FSYS); 653 + 654 + U_BOOT_DRIVER(exynos7870_cmu_fsys) = { 655 + .name = "exynos7870-cmu-fsys", 656 + .id = UCLASS_CLK, 657 + .of_match = exynos7870_cmu_fsys_ids, 658 + .ops = &exynos7870_cmu_fsys_clk_ops, 659 + .probe = exynos7870_cmu_fsys_probe, 660 + .flags = DM_FLAG_PRE_RELOC, 661 + }; 662 + 663 + /* 664 + * Register offsets for CMU_PERI (0x101f0000) 665 + */ 666 + #define CLK_CON_GAT_PERI_PWM_MOTOR_OSCCLK 0x0800 667 + #define CLK_CON_GAT_PERI_TMU_CLK 0x0800 668 + #define CLK_CON_GAT_PERI_TMU_CPUCL0_CLK 0x0800 669 + #define CLK_CON_GAT_PERI_TMU_CPUCL1_CLK 0x0800 670 + #define CLK_CON_GAT_PERI_BUSP1_PERIC0_HCLK 0x0810 671 + #define CLK_CON_GAT_PERI_GPIO2_PCLK 0x0810 672 + #define CLK_CON_GAT_PERI_GPIO5_PCLK 0x0810 673 + #define CLK_CON_GAT_PERI_GPIO6_PCLK 0x0810 674 + #define CLK_CON_GAT_PERI_GPIO7_PCLK 0x0810 675 + #define CLK_CON_GAT_PERI_HSI2C1_IPCLK 0x0810 676 + #define CLK_CON_GAT_PERI_HSI2C2_IPCLK 0x0810 677 + #define CLK_CON_GAT_PERI_HSI2C3_IPCLK 0x0810 678 + #define CLK_CON_GAT_PERI_HSI2C4_IPCLK 0x0810 679 + #define CLK_CON_GAT_PERI_HSI2C5_IPCLK 0x0810 680 + #define CLK_CON_GAT_PERI_HSI2C6_IPCLK 0x0810 681 + #define CLK_CON_GAT_PERI_I2C0_PCLK 0x0810 682 + #define CLK_CON_GAT_PERI_I2C1_PCLK 0x0810 683 + #define CLK_CON_GAT_PERI_I2C2_PCLK 0x0810 684 + #define CLK_CON_GAT_PERI_I2C3_PCLK 0x0810 685 + #define CLK_CON_GAT_PERI_I2C4_PCLK 0x0810 686 + #define CLK_CON_GAT_PERI_I2C5_PCLK 0x0810 687 + #define CLK_CON_GAT_PERI_I2C6_PCLK 0x0810 688 + #define CLK_CON_GAT_PERI_I2C7_PCLK 0x0810 689 + #define CLK_CON_GAT_PERI_I2C8_PCLK 0x0810 690 + #define CLK_CON_GAT_PERI_MCT_PCLK 0x0810 691 + #define CLK_CON_GAT_PERI_PWM_MOTOR_PCLK_S0 0x0810 692 + #define CLK_CON_GAT_PERI_SFRIF_TMU_CPUCL0_PCLK 0x0814 693 + #define CLK_CON_GAT_PERI_SFRIF_TMU_CPUCL1_PCLK 0x0814 694 + #define CLK_CON_GAT_PERI_SFRIF_TMU_PCLK 0x0814 695 + #define CLK_CON_GAT_PERI_SPI0_PCLK 0x0814 696 + #define CLK_CON_GAT_PERI_SPI1_PCLK 0x0814 697 + #define CLK_CON_GAT_PERI_SPI2_PCLK 0x0814 698 + #define CLK_CON_GAT_PERI_SPI3_PCLK 0x0814 699 + #define CLK_CON_GAT_PERI_SPI4_PCLK 0x0814 700 + #define CLK_CON_GAT_PERI_UART0_PCLK 0x0814 701 + #define CLK_CON_GAT_PERI_UART1_PCLK 0x0814 702 + #define CLK_CON_GAT_PERI_UART2_PCLK 0x0814 703 + #define CLK_CON_GAT_PERI_WDT_CPUCL0_PCLK 0x0814 704 + #define CLK_CON_GAT_PERI_WDT_CPUCL1_PCLK 0x0814 705 + #define CLK_CON_GAT_PERI_UART1_EXT_UCLK 0x0830 706 + #define CLK_CON_GAT_PERI_UART2_EXT_UCLK 0x0834 707 + #define CLK_CON_GAT_PERI_UART0_EXT_UCLK 0x0838 708 + #define CLK_CON_GAT_PERI_SPI2_SPI_EXT_CLK 0x083c 709 + #define CLK_CON_GAT_PERI_SPI1_SPI_EXT_CLK 0x0840 710 + #define CLK_CON_GAT_PERI_SPI0_SPI_EXT_CLK 0x0844 711 + #define CLK_CON_GAT_PERI_SPI3_SPI_EXT_CLK 0x0848 712 + #define CLK_CON_GAT_PERI_SPI4_SPI_EXT_CLK 0x084c 713 + 714 + static const struct samsung_gate_clock peri_gate_clks[] = { 715 + GATE(CLK_GOUT_PERI_PWM_MOTOR_OSCCLK, 716 + "gout_peri_pwm_motor_oscclk", "oscclk", 717 + CLK_CON_GAT_PERI_PWM_MOTOR_OSCCLK, 2, 718 + CLK_SET_RATE_PARENT, 0), 719 + GATE(CLK_GOUT_PERI_TMU_CLK, 720 + "gout_peri_tmu_clk", "oscclk", 721 + CLK_CON_GAT_PERI_TMU_CLK, 6, 722 + CLK_SET_RATE_PARENT, 0), 723 + GATE(CLK_GOUT_PERI_TMU_CPUCL0_CLK, 724 + "gout_peri_tmu_cpucl0_clk", "oscclk", 725 + CLK_CON_GAT_PERI_TMU_CPUCL0_CLK, 4, 726 + CLK_SET_RATE_PARENT, 0), 727 + GATE(CLK_GOUT_PERI_TMU_CPUCL1_CLK, 728 + "gout_peri_tmu_cpucl1_clk", "oscclk", 729 + CLK_CON_GAT_PERI_TMU_CPUCL1_CLK, 5, 730 + CLK_SET_RATE_PARENT, 0), 731 + GATE(CLK_GOUT_PERI_BUSP1_PERIC0_HCLK, 732 + "gout_peri_busp1_peric0_hclk", "bus", 733 + CLK_CON_GAT_PERI_BUSP1_PERIC0_HCLK, 3, 734 + CLK_SET_RATE_PARENT, 0), 735 + GATE(CLK_GOUT_PERI_GPIO2_PCLK, 736 + "gout_peri_gpio2_pclk", "bus", 737 + CLK_CON_GAT_PERI_GPIO2_PCLK, 7, 738 + CLK_SET_RATE_PARENT, 0), 739 + GATE(CLK_GOUT_PERI_GPIO5_PCLK, 740 + "gout_peri_gpio5_pclk", "bus", 741 + CLK_CON_GAT_PERI_GPIO5_PCLK, 8, 742 + CLK_SET_RATE_PARENT, 0), 743 + GATE(CLK_GOUT_PERI_GPIO6_PCLK, 744 + "gout_peri_gpio6_pclk", "bus", 745 + CLK_CON_GAT_PERI_GPIO6_PCLK, 9, 746 + CLK_SET_RATE_PARENT, 0), 747 + GATE(CLK_GOUT_PERI_GPIO7_PCLK, 748 + "gout_peri_gpio7_pclk", "bus", 749 + CLK_CON_GAT_PERI_GPIO7_PCLK, 10, 750 + CLK_SET_RATE_PARENT, 0), 751 + GATE(CLK_GOUT_PERI_HSI2C5_IPCLK, 752 + "gout_peri_hsi2c5_ipclk", "bus", 753 + CLK_CON_GAT_PERI_HSI2C5_IPCLK, 15, 754 + CLK_SET_RATE_PARENT, 0), 755 + GATE(CLK_GOUT_PERI_HSI2C6_IPCLK, 756 + "gout_peri_hsi2c6_ipclk", "bus", 757 + CLK_CON_GAT_PERI_HSI2C6_IPCLK, 16, 758 + CLK_SET_RATE_PARENT, 0), 759 + GATE(CLK_GOUT_PERI_MCT_PCLK, 760 + "gout_peri_mct_pclk", "bus", 761 + CLK_CON_GAT_PERI_MCT_PCLK, 26, 762 + CLK_SET_RATE_PARENT, 0), 763 + GATE(CLK_GOUT_PERI_PWM_MOTOR_PCLK_S0, 764 + "gout_peri_pwm_motor_pclk_s0", "bus", 765 + CLK_CON_GAT_PERI_PWM_MOTOR_PCLK_S0, 29, 766 + CLK_SET_RATE_PARENT, 0), 767 + GATE(CLK_GOUT_PERI_SFRIF_TMU_CPUCL0_PCLK, 768 + "gout_peri_sfrif_tmu_cpucl0_pclk", "bus", 769 + CLK_CON_GAT_PERI_SFRIF_TMU_CPUCL0_PCLK, 1, 770 + CLK_SET_RATE_PARENT, 0), 771 + GATE(CLK_GOUT_PERI_SFRIF_TMU_CPUCL1_PCLK, 772 + "gout_peri_sfrif_tmu_cpucl1_pclk", "bus", 773 + CLK_CON_GAT_PERI_SFRIF_TMU_CPUCL1_PCLK, 2, 774 + CLK_SET_RATE_PARENT, 0), 775 + GATE(CLK_GOUT_PERI_SFRIF_TMU_PCLK, 776 + "gout_peri_sfrif_tmu_pclk", "bus", 777 + CLK_CON_GAT_PERI_SFRIF_TMU_PCLK, 3, 778 + CLK_SET_RATE_PARENT, 0), 779 + GATE(CLK_GOUT_PERI_SPI0_PCLK, 780 + "gout_peri_spi0_pclk", "bus", 781 + CLK_CON_GAT_PERI_SPI0_PCLK, 6, 782 + CLK_SET_RATE_PARENT, 0), 783 + GATE(CLK_GOUT_PERI_SPI1_PCLK, 784 + "gout_peri_spi1_pclk", "bus", 785 + CLK_CON_GAT_PERI_SPI1_PCLK, 5, 786 + CLK_SET_RATE_PARENT, 0), 787 + GATE(CLK_GOUT_PERI_SPI2_PCLK, 788 + "gout_peri_spi2_pclk", "bus", 789 + CLK_CON_GAT_PERI_SPI2_PCLK, 4, 790 + CLK_SET_RATE_PARENT, 0), 791 + GATE(CLK_GOUT_PERI_SPI3_PCLK, 792 + "gout_peri_spi3_pclk", "bus", 793 + CLK_CON_GAT_PERI_SPI3_PCLK, 7, 794 + CLK_SET_RATE_PARENT, 0), 795 + GATE(CLK_GOUT_PERI_SPI4_PCLK, 796 + "gout_peri_spi4_pclk", "bus", 797 + CLK_CON_GAT_PERI_SPI4_PCLK, 8, 798 + CLK_SET_RATE_PARENT, 0), 799 + GATE(CLK_GOUT_PERI_WDT_CPUCL0_PCLK, 800 + "gout_peri_wdt_cpucl0_pclk", "bus", 801 + CLK_CON_GAT_PERI_WDT_CPUCL0_PCLK, 13, 802 + CLK_SET_RATE_PARENT, 0), 803 + GATE(CLK_GOUT_PERI_WDT_CPUCL1_PCLK, 804 + "gout_peri_wdt_cpucl1_pclk", "bus", 805 + CLK_CON_GAT_PERI_WDT_CPUCL1_PCLK, 14, 806 + CLK_SET_RATE_PARENT, 0), 807 + GATE(CLK_GOUT_PERI_SPI0_SPI_EXT_CLK, 808 + "gout_peri_spi0_spi_ext_clk", "spi0", 809 + CLK_CON_GAT_PERI_SPI0_SPI_EXT_CLK, 0, 810 + CLK_SET_RATE_PARENT, 0), 811 + GATE(CLK_GOUT_PERI_SPI1_SPI_EXT_CLK, 812 + "gout_peri_spi1_spi_ext_clk", "spi1", 813 + CLK_CON_GAT_PERI_SPI1_SPI_EXT_CLK, 0, 814 + CLK_SET_RATE_PARENT, 0), 815 + GATE(CLK_GOUT_PERI_SPI2_SPI_EXT_CLK, 816 + "gout_peri_spi2_spi_ext_clk", "spi2", 817 + CLK_CON_GAT_PERI_SPI2_SPI_EXT_CLK, 0, 818 + CLK_SET_RATE_PARENT, 0), 819 + GATE(CLK_GOUT_PERI_SPI3_SPI_EXT_CLK, 820 + "gout_peri_spi3_spi_ext_clk", "spi3", 821 + CLK_CON_GAT_PERI_SPI3_SPI_EXT_CLK, 0, 822 + CLK_SET_RATE_PARENT, 0), 823 + GATE(CLK_GOUT_PERI_SPI4_SPI_EXT_CLK, 824 + "gout_peri_spi4_spi_ext_clk", "spi4", 825 + CLK_CON_GAT_PERI_SPI4_SPI_EXT_CLK, 0, 826 + CLK_SET_RATE_PARENT, 0), 827 + GATE(CLK_GOUT_PERI_UART0_EXT_UCLK, 828 + "gout_peri_uart0_ext_uclk", "uart0", 829 + CLK_CON_GAT_PERI_UART0_EXT_UCLK, 0, 830 + CLK_SET_RATE_PARENT, 0), 831 + GATE(CLK_GOUT_PERI_UART1_EXT_UCLK, 832 + "gout_peri_uart1_ext_uclk", "uart1", 833 + CLK_CON_GAT_PERI_UART1_EXT_UCLK, 0, 834 + CLK_SET_RATE_PARENT, 0), 835 + GATE(CLK_GOUT_PERI_UART2_EXT_UCLK, 836 + "gout_peri_uart2_ext_uclk", "uart2", 837 + CLK_CON_GAT_PERI_UART2_EXT_UCLK, 0, 838 + CLK_SET_RATE_PARENT, 0), 839 + GATE(CLK_GOUT_PERI_HSI2C1_IPCLK, 840 + "gout_peri_hsi2c1_ipclk", "gout_peri_busp1_peric0_hclk", 841 + CLK_CON_GAT_PERI_HSI2C1_IPCLK, 11, 842 + CLK_SET_RATE_PARENT, 0), 843 + GATE(CLK_GOUT_PERI_HSI2C2_IPCLK, 844 + "gout_peri_hsi2c2_ipclk", "gout_peri_busp1_peric0_hclk", 845 + CLK_CON_GAT_PERI_HSI2C2_IPCLK, 12, 846 + CLK_SET_RATE_PARENT, 0), 847 + GATE(CLK_GOUT_PERI_HSI2C3_IPCLK, 848 + "gout_peri_hsi2c3_ipclk", "gout_peri_busp1_peric0_hclk", 849 + CLK_CON_GAT_PERI_HSI2C3_IPCLK, 13, 850 + CLK_SET_RATE_PARENT, 0), 851 + GATE(CLK_GOUT_PERI_HSI2C4_IPCLK, 852 + "gout_peri_hsi2c4_ipclk", "gout_peri_busp1_peric0_hclk", 853 + CLK_CON_GAT_PERI_HSI2C4_IPCLK, 14, 854 + CLK_SET_RATE_PARENT, 0), 855 + GATE(CLK_GOUT_PERI_I2C0_PCLK, 856 + "gout_peri_i2c0_pclk", "gout_peri_busp1_peric0_hclk", 857 + CLK_CON_GAT_PERI_I2C0_PCLK, 21, 858 + CLK_SET_RATE_PARENT, 0), 859 + GATE(CLK_GOUT_PERI_I2C1_PCLK, 860 + "gout_peri_i2c1_pclk", "gout_peri_busp1_peric0_hclk", 861 + CLK_CON_GAT_PERI_I2C1_PCLK, 23, 862 + CLK_SET_RATE_PARENT, 0), 863 + GATE(CLK_GOUT_PERI_I2C2_PCLK, 864 + "gout_peri_i2c2_pclk", "gout_peri_busp1_peric0_hclk", 865 + CLK_CON_GAT_PERI_I2C2_PCLK, 22, 866 + CLK_SET_RATE_PARENT, 0), 867 + GATE(CLK_GOUT_PERI_I2C3_PCLK, 868 + "gout_peri_i2c3_pclk", "gout_peri_busp1_peric0_hclk", 869 + CLK_CON_GAT_PERI_I2C3_PCLK, 20, 870 + CLK_SET_RATE_PARENT, 0), 871 + GATE(CLK_GOUT_PERI_I2C4_PCLK, 872 + "gout_peri_i2c4_pclk", "gout_peri_busp1_peric0_hclk", 873 + CLK_CON_GAT_PERI_I2C4_PCLK, 17, 874 + CLK_SET_RATE_PARENT, 0), 875 + GATE(CLK_GOUT_PERI_I2C5_PCLK, 876 + "gout_peri_i2c5_pclk", "gout_peri_busp1_peric0_hclk", 877 + CLK_CON_GAT_PERI_I2C5_PCLK, 18, 878 + CLK_SET_RATE_PARENT, 0), 879 + GATE(CLK_GOUT_PERI_I2C6_PCLK, 880 + "gout_peri_i2c6_pclk", "gout_peri_busp1_peric0_hclk", 881 + CLK_CON_GAT_PERI_I2C6_PCLK, 19, 882 + CLK_SET_RATE_PARENT, 0), 883 + GATE(CLK_GOUT_PERI_I2C7_PCLK, 884 + "gout_peri_i2c7_pclk", "gout_peri_busp1_peric0_hclk", 885 + CLK_CON_GAT_PERI_I2C7_PCLK, 24, 886 + CLK_SET_RATE_PARENT, 0), 887 + GATE(CLK_GOUT_PERI_I2C8_PCLK, 888 + "gout_peri_i2c8_pclk", "gout_peri_busp1_peric0_hclk", 889 + CLK_CON_GAT_PERI_I2C8_PCLK, 25, 890 + CLK_SET_RATE_PARENT, 0), 891 + GATE(CLK_GOUT_PERI_UART0_PCLK, 892 + "gout_peri_uart0_pclk", "gout_peri_busp1_peric0_hclk", 893 + CLK_CON_GAT_PERI_UART0_PCLK, 10, 894 + CLK_SET_RATE_PARENT, 0), 895 + GATE(CLK_GOUT_PERI_UART1_PCLK, 896 + "gout_peri_uart1_pclk", "gout_peri_busp1_peric0_hclk", 897 + CLK_CON_GAT_PERI_UART1_PCLK, 11, 898 + CLK_SET_RATE_PARENT, 0), 899 + GATE(CLK_GOUT_PERI_UART2_PCLK, 900 + "gout_peri_uart2_pclk", "gout_peri_busp1_peric0_hclk", 901 + CLK_CON_GAT_PERI_UART2_PCLK, 12, 902 + CLK_SET_RATE_PARENT, 0), 903 + }; 904 + 905 + static const struct samsung_clk_group peri_cmu_clks[] = { 906 + { S_CLK_GATE, peri_gate_clks, ARRAY_SIZE(peri_gate_clks) }, 907 + }; 908 + 909 + static int exynos7870_cmu_peri_probe(struct udevice *dev) 910 + { 911 + return samsung_register_cmu(dev, CMU_PERI, peri_cmu_clks, 912 + exynos7870_cmu_peri); 913 + } 914 + 915 + static const struct udevice_id exynos7870_cmu_peri_ids[] = { 916 + { .compatible = "samsung,exynos7870-cmu-peri" }, 917 + { } 918 + }; 919 + 920 + SAMSUNG_CLK_OPS(exynos7870_cmu_peri, CMU_PERI); 921 + 922 + U_BOOT_DRIVER(exynos7870_cmu_peri) = { 923 + .name = "exynos7870-cmu-peri", 924 + .id = UCLASS_CLK, 925 + .of_match = exynos7870_cmu_peri_ids, 926 + .ops = &exynos7870_cmu_peri_clk_ops, 927 + .probe = exynos7870_cmu_peri_probe, 928 + .flags = DM_FLAG_PRE_RELOC, 929 + };
+3 -1
drivers/clk/exynos/clk-pll.c
··· 117 117 118 118 switch (pll_clk->type) { 119 119 case pll_0822x: 120 + case pll_1417x: 120 121 drv_name = UBOOT_DM_CLK_SAMSUNG_PLL0822X; 121 122 break; 122 123 case pll_0831x: ··· 136 137 return clk; 137 138 } 138 139 139 - void samsung_clk_register_pll(void __iomem *base, unsigned int cmu_id, 140 + void samsung_clk_register_pll(struct udevice *dev, void __iomem *base, 141 + unsigned int cmu_id, 140 142 const struct samsung_pll_clock *clk_list, 141 143 unsigned int nr_clk) 142 144 {
+3 -1
drivers/clk/exynos/clk-pll.h
··· 20 20 enum samsung_pll_type { 21 21 pll_0822x, 22 22 pll_0831x, 23 + pll_1417x, 23 24 }; 24 25 25 - void samsung_clk_register_pll(void __iomem *base, unsigned int cmu_id, 26 + void samsung_clk_register_pll(struct udevice *dev, void __iomem *base, 27 + unsigned int cmu_id, 26 28 const struct samsung_pll_clock *clk_list, 27 29 unsigned int nr_clk); 28 30
+80 -19
drivers/clk/exynos/clk.c
··· 10 10 #include <dm.h> 11 11 #include "clk.h" 12 12 13 - static void samsung_clk_register_mux(void __iomem *base, unsigned int cmu_id, 13 + int samsung_clk_request(struct clk *clk) 14 + { 15 + struct clk *c; 16 + int ret; 17 + 18 + ret = clk_get_by_id(clk->id, &c); 19 + if (ret) 20 + return ret; 21 + 22 + clk->dev = c->dev; 23 + return 0; 24 + } 25 + 26 + static void 27 + samsung_clk_register_fixed_rate(struct udevice *dev, void __iomem *base, 28 + unsigned int cmu_id, 29 + const struct samsung_fixed_rate_clock *clk_list, 30 + unsigned int nr_clk) 31 + { 32 + unsigned int cnt; 33 + 34 + for (cnt = 0; cnt < nr_clk; cnt++) { 35 + struct clk *clk; 36 + const struct samsung_fixed_rate_clock *m; 37 + unsigned long clk_id; 38 + 39 + m = &clk_list[cnt]; 40 + clk = clk_register_fixed_rate(NULL, m->name, m->fixed_rate); 41 + clk_id = SAMSUNG_TO_CLK_ID(cmu_id, m->id); 42 + clk_dm(clk_id, clk); 43 + } 44 + } 45 + 46 + static void 47 + samsung_clk_register_fixed_factor(struct udevice *dev, void __iomem *base, 48 + unsigned int cmu_id, 49 + const struct samsung_fixed_factor_clock *clk_list, 50 + unsigned int nr_clk) 51 + { 52 + unsigned int cnt; 53 + 54 + for (cnt = 0; cnt < nr_clk; cnt++) { 55 + struct clk *clk; 56 + const struct samsung_fixed_factor_clock *m; 57 + unsigned long clk_id; 58 + 59 + m = &clk_list[cnt]; 60 + clk = clk_register_fixed_factor(dev, m->name, m->parent_name, 61 + m->flags, m->mult, m->div); 62 + clk_id = SAMSUNG_TO_CLK_ID(cmu_id, m->id); 63 + clk_dm(clk_id, clk); 64 + } 65 + } 66 + 67 + static void samsung_clk_register_mux(struct udevice *dev, void __iomem *base, 68 + unsigned int cmu_id, 14 69 const struct samsung_mux_clock *clk_list, 15 70 unsigned int nr_clk) 16 71 { ··· 22 77 unsigned long clk_id; 23 78 24 79 m = &clk_list[cnt]; 25 - clk = clk_register_mux(NULL, m->name, m->parent_names, 26 - m->num_parents, m->flags, base + m->offset, m->shift, 27 - m->width, m->mux_flags); 80 + clk = clk_register_mux(dev, m->name, m->parent_names, 81 + m->num_parents, m->flags, 82 + base + m->offset, m->shift, m->width, 83 + m->mux_flags); 28 84 clk_id = SAMSUNG_TO_CLK_ID(cmu_id, m->id); 29 85 clk_dm(clk_id, clk); 30 86 } 31 87 } 32 88 33 - static void samsung_clk_register_div(void __iomem *base, unsigned int cmu_id, 89 + static void samsung_clk_register_div(struct udevice *dev, void __iomem *base, 90 + unsigned int cmu_id, 34 91 const struct samsung_div_clock *clk_list, 35 92 unsigned int nr_clk) 36 93 { ··· 42 99 unsigned long clk_id; 43 100 44 101 d = &clk_list[cnt]; 45 - clk = clk_register_divider(NULL, d->name, d->parent_name, 46 - d->flags, base + d->offset, d->shift, 47 - d->width, d->div_flags); 102 + clk = clk_register_divider(dev, d->name, d->parent_name, 103 + d->flags, base + d->offset, d->shift, 104 + d->width, d->div_flags); 48 105 clk_id = SAMSUNG_TO_CLK_ID(cmu_id, d->id); 49 106 clk_dm(clk_id, clk); 50 107 } 51 108 } 52 109 53 - static void samsung_clk_register_gate(void __iomem *base, unsigned int cmu_id, 110 + static void samsung_clk_register_gate(struct udevice *dev, void __iomem *base, 111 + unsigned int cmu_id, 54 112 const struct samsung_gate_clock *clk_list, 55 113 unsigned int nr_clk) 56 114 { ··· 62 120 unsigned long clk_id; 63 121 64 122 g = &clk_list[cnt]; 65 - clk = clk_register_gate(NULL, g->name, g->parent_name, 66 - g->flags, base + g->offset, g->bit_idx, 67 - g->gate_flags, NULL); 123 + clk = clk_register_gate(dev, g->name, g->parent_name, 124 + g->flags, base + g->offset, g->bit_idx, 125 + g->gate_flags, NULL); 68 126 clk_id = SAMSUNG_TO_CLK_ID(cmu_id, g->id); 69 127 clk_dm(clk_id, clk); 70 128 } 71 129 } 72 130 73 - typedef void (*samsung_clk_register_fn)(void __iomem *base, unsigned int cmu_id, 74 - const void *clk_list, 131 + typedef void (*samsung_clk_register_fn)(struct udevice *dev, void __iomem *base, 132 + unsigned int cmu_id, const void *clk_list, 75 133 unsigned int nr_clk); 76 134 77 135 static const samsung_clk_register_fn samsung_clk_register_fns[] = { 136 + [S_CLK_FRATE] = (samsung_clk_register_fn)samsung_clk_register_fixed_rate, 137 + [S_CLK_FFACTOR] = (samsung_clk_register_fn)samsung_clk_register_fixed_factor, 78 138 [S_CLK_MUX] = (samsung_clk_register_fn)samsung_clk_register_mux, 79 139 [S_CLK_DIV] = (samsung_clk_register_fn)samsung_clk_register_div, 80 140 [S_CLK_GATE] = (samsung_clk_register_fn)samsung_clk_register_gate, ··· 91 151 * Having the array of clock groups @clk_groups makes it possible to keep a 92 152 * correct clocks registration order. 93 153 */ 94 - static void samsung_cmu_register_clocks(void __iomem *base, unsigned int cmu_id, 95 - const struct samsung_clk_group *clk_groups, 96 - unsigned int nr_groups) 154 + static void samsung_cmu_register_clocks(struct udevice *dev, void __iomem *base, 155 + unsigned int cmu_id, 156 + const struct samsung_clk_group *clk_groups, 157 + unsigned int nr_groups) 97 158 { 98 159 unsigned int i; 99 160 100 161 for (i = 0; i < nr_groups; i++) { 101 162 const struct samsung_clk_group *g = &clk_groups[i]; 102 163 103 - samsung_clk_register_fns[g->type](base, cmu_id, 164 + samsung_clk_register_fns[g->type](dev, base, cmu_id, 104 165 g->clk_list, g->nr_clk); 105 166 } 106 167 } ··· 124 185 if (!base) 125 186 return -EINVAL; 126 187 127 - samsung_cmu_register_clocks(base, cmu_id, clk_groups, nr_groups); 188 + samsung_cmu_register_clocks(dev, base, cmu_id, clk_groups, nr_groups); 128 189 129 190 return 0; 130 191 }
+53
drivers/clk/exynos/clk.h
··· 9 9 #ifndef __EXYNOS_CLK_H 10 10 #define __EXYNOS_CLK_H 11 11 12 + #include <clk.h> 12 13 #include <errno.h> 13 14 #include <linux/clk-provider.h> 14 15 #include "clk-pll.h" 16 + 17 + int samsung_clk_request(struct clk *clk); 15 18 16 19 #define _SAMSUNG_CLK_OPS(_name, _cmu) \ 17 20 static int _name##_of_xlate(struct clk *clk, \ ··· 37 40 .enable = ccf_clk_enable, \ 38 41 .disable = ccf_clk_disable, \ 39 42 .of_xlate = _name##_of_xlate, \ 43 + .request = samsung_clk_request, \ 40 44 } 41 45 42 46 /** ··· 57 61 * Keeps a range of 256 available clocks for every CMU. 58 62 */ 59 63 #define SAMSUNG_TO_CLK_ID(_cmu, _id) (((_cmu) << 8) | ((_id) & 0xff)) 64 + 65 + /** 66 + * struct samsung_fixed_rate_clock - information about fixed-rate clock 67 + * @id: platform specific id of the clock 68 + * @name: name of this fixed-rate clock 69 + * @fixed_rate: fixed clock rate of this clock 70 + */ 71 + struct samsung_fixed_rate_clock { 72 + unsigned int id; 73 + const char *name; 74 + unsigned long fixed_rate; 75 + }; 76 + 77 + #define FRATE(_id, cname, frate) \ 78 + { \ 79 + .id = _id, \ 80 + .name = cname, \ 81 + .fixed_rate = frate, \ 82 + } 83 + 84 + /** 85 + * struct samsung_fixed_factor_clock - information about fixed-factor clock 86 + * @id: platform specific id of the clock 87 + * @name: name of this fixed-factor clock 88 + * @parent_name: parent clock name 89 + * @mult: fixed multiplication factor 90 + * @div: fixed division factor 91 + * @flags: optional fixed-factor clock flags 92 + */ 93 + struct samsung_fixed_factor_clock { 94 + unsigned int id; 95 + const char *name; 96 + const char *parent_name; 97 + unsigned long mult; 98 + unsigned long div; 99 + unsigned long flags; 100 + }; 101 + 102 + #define FFACTOR(_id, cname, pname, m, d, f) \ 103 + { \ 104 + .id = _id, \ 105 + .name = cname, \ 106 + .parent_name = pname, \ 107 + .mult = m, \ 108 + .div = d, \ 109 + .flags = f, \ 110 + } 60 111 61 112 /** 62 113 * struct samsung_mux_clock - information about mux clock ··· 206 257 } 207 258 208 259 enum samsung_clock_type { 260 + S_CLK_FRATE, 261 + S_CLK_FFACTOR, 209 262 S_CLK_MUX, 210 263 S_CLK_DIV, 211 264 S_CLK_GATE,
+4
drivers/clk/renesas/Makefile
··· 26 26 obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o 27 27 obj-$(CONFIG_CLK_RZG2L) += rzg2l-cpg.o 28 28 obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o 29 + 30 + # Temporary stub clock used for SCP compatibility. 31 + # This is going to be removed once SCP solidifies. 32 + obj-$(CONFIG_R8A78000) += compound-clock.o
+92
drivers/clk/renesas/compound-clock.c
··· 1 + // SPDX-License-Identifier: GPL-2.0+ 2 + /* 3 + * Copyright (C) 2025 Marek Vasut <marek.vasut+renesas@mailbox.org> 4 + */ 5 + 6 + #define LOG_CATEGORY UCLASS_CLK 7 + 8 + #include <clk-uclass.h> 9 + #include <dm.h> 10 + #include <dm/device-internal.h> 11 + #include <linux/clk-provider.h> 12 + #include <log.h> 13 + 14 + struct clk_compound_rate { 15 + struct clk clk; /* This clock */ 16 + struct clk mdlc; /* MDLC parent module clock */ 17 + struct clk per; /* Peripheral parent clock */ 18 + }; 19 + 20 + static struct clk_compound_rate *to_clk_compound_rate(struct clk *clk) 21 + { 22 + return (struct clk_compound_rate *)dev_get_plat(clk->dev); 23 + } 24 + 25 + static int clk_compound_rate_enable(struct clk *clk) 26 + { 27 + struct clk_compound_rate *cc = to_clk_compound_rate(clk); 28 + 29 + return clk_enable(&cc->mdlc); 30 + } 31 + 32 + static int clk_compound_rate_disable(struct clk *clk) 33 + { 34 + struct clk_compound_rate *cc = to_clk_compound_rate(clk); 35 + 36 + return clk_disable(&cc->mdlc); 37 + } 38 + 39 + static ulong clk_compound_rate_get_rate(struct clk *clk) 40 + { 41 + struct clk_compound_rate *cc = to_clk_compound_rate(clk); 42 + 43 + return clk_get_rate(&cc->per); 44 + } 45 + 46 + static ulong clk_compound_rate_set_rate(struct clk *clk, ulong rate) 47 + { 48 + return 0; /* Set rate is not forwarded to SCP */ 49 + } 50 + 51 + const struct clk_ops clk_compound_rate_ops = { 52 + .enable = clk_compound_rate_enable, 53 + .disable = clk_compound_rate_disable, 54 + .get_rate = clk_compound_rate_get_rate, 55 + .set_rate = clk_compound_rate_set_rate, 56 + }; 57 + 58 + static int clk_compound_rate_of_to_plat(struct udevice *dev) 59 + { 60 + struct clk_compound_rate *cc = (struct clk_compound_rate *)dev_get_plat(dev); 61 + struct clk *clk = &cc->clk; 62 + int ret; 63 + 64 + clk->dev = dev; 65 + clk->id = CLK_ID(dev, 0); 66 + clk->enable_count = 0; 67 + 68 + ret = clk_get_by_index(dev, 0, &cc->mdlc); 69 + if (ret) 70 + return ret; 71 + 72 + ret = clk_get_by_index(dev, 1, &cc->per); 73 + if (ret) 74 + return ret; 75 + 76 + return 0; 77 + } 78 + 79 + static const struct udevice_id clk_compound_rate_match[] = { 80 + { .compatible = "renesas,compound-clock", }, 81 + { /* sentinel */ } 82 + }; 83 + 84 + U_BOOT_DRIVER(renesas_compound_clock) = { 85 + .name = "compound-clock", 86 + .id = UCLASS_CLK, 87 + .of_match = clk_compound_rate_match, 88 + .of_to_plat = clk_compound_rate_of_to_plat, 89 + .plat_auto = sizeof(struct clk_compound_rate), 90 + .ops = &clk_compound_rate_ops, 91 + .flags = DM_FLAG_PRE_RELOC, 92 + };
+8
drivers/gpio/Kconfig
··· 154 154 help 155 155 Support for the Designware APB GPIO driver. 156 156 157 + config SPL_DWAPB_GPIO 158 + bool "DWAPB GPIO driver in SPL" 159 + depends on SPL_DM_GPIO 160 + help 161 + Support for the Designware APB GPIO driver in SPL. 162 + 163 + If unsure, say N. 164 + 157 165 config AT91_GPIO 158 166 bool "AT91 PIO GPIO driver" 159 167 depends on ARCH_AT91
+1 -1
drivers/gpio/Makefile
··· 4 4 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 5 6 6 ifndef CONFIG_XPL_BUILD 7 - obj-$(CONFIG_DWAPB_GPIO) += dwapb_gpio.o 8 7 obj-$(CONFIG_AXP_GPIO) += axp_gpio.o 9 8 obj-$(CONFIG_DM_74X164) += 74x164_gpio.o 10 9 endif 11 10 obj-$(CONFIG_$(PHASE_)DM_GPIO) += gpio-uclass.o 12 11 12 + obj-$(CONFIG_$(PHASE_)DWAPB_GPIO) += dwapb_gpio.o 13 13 obj-$(CONFIG_$(PHASE_)DM_PCA953X) += pca953x_gpio.o 14 14 15 15 obj-$(CONFIG_ADI_GPIO) += gpio-adi-adsp.o
+2 -3
drivers/gpio/s5p_gpio.c
··· 319 319 base = dev_read_addr_ptr(parent); 320 320 for (node = fdt_first_subnode(blob, dev_of_offset(parent)), bank = base; 321 321 node > 0; 322 - node = fdt_next_subnode(blob, node), bank++) { 322 + node = fdt_next_subnode(blob, node)) { 323 323 struct exynos_gpio_plat *plat; 324 324 struct udevice *dev; 325 325 fdt_addr_t reg; ··· 341 341 if (reg != FDT_ADDR_T_NONE) 342 342 bank = (struct s5p_gpio_bank *)((ulong)base + reg); 343 343 344 - plat->bank = bank; 345 - 346 344 debug("dev at %p: %s\n", bank, plat->bank_name); 345 + plat->bank = bank++; 347 346 } 348 347 349 348 return 0;
+10
drivers/mailbox/Kconfig
··· 66 66 Select this driver if your platform has support for this hardware 67 67 block. 68 68 69 + config RCAR_MFIS_MBOX 70 + bool "Renesas MFIS Multifunctional Interface mailbox driver" 71 + depends on DM_MAILBOX && ARCH_RENESAS 72 + help 73 + This enables support for the Renesas MFIS mailbox module, which 74 + provides an interface between the different CPU Cores, such as AP 75 + System Core domain and the Realtime Core domain, SCP Core domain 76 + and AP System Core domain or Realtime Core domain and AP System 77 + Core domain or Realtime Core domain. 78 + 69 79 config ZYNQMP_IPI 70 80 bool "Xilinx ZynqMP IPI controller support" 71 81 depends on DM_MAILBOX && (ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2)
+1
drivers/mailbox/Makefile
··· 12 12 obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o 13 13 obj-$(CONFIG_TEGRA_HSP) += tegra-hsp.o 14 14 obj-$(CONFIG_K3_SEC_PROXY) += k3-sec-proxy.o 15 + obj-$(CONFIG_RCAR_MFIS_MBOX) += renesas-mfis.o 15 16 obj-$(CONFIG_ZYNQMP_IPI) += zynqmp-ipi.o
+59
drivers/mailbox/renesas-mfis.c
··· 1 + // SPDX-License-Identifier: GPL-2.0-only 2 + /* 3 + * Copyright (c) 2020-2025, Renesas Electronics Corporation. 4 + */ 5 + 6 + #include <asm/io.h> 7 + #include <dm.h> 8 + #include <linux/delay.h> 9 + #include <mailbox-uclass.h> 10 + 11 + #define COM 0x0 12 + #define IIR BIT(0) 13 + 14 + struct mfis_priv { 15 + void __iomem *tx_base; 16 + }; 17 + 18 + static int mfis_send(struct mbox_chan *chan, const void *data) 19 + { 20 + struct mfis_priv *mfis = dev_get_priv(chan->dev); 21 + 22 + writel(IIR, mfis->tx_base + COM); 23 + 24 + /* Give the remote side some time. */ 25 + mdelay(1); 26 + 27 + writel(0, mfis->tx_base + COM); 28 + 29 + return 0; 30 + } 31 + 32 + struct mbox_ops mfis_mbox_ops = { 33 + .send = mfis_send, 34 + }; 35 + 36 + static int mfis_mbox_probe(struct udevice *dev) 37 + { 38 + struct mfis_priv *mbox = dev_get_priv(dev); 39 + 40 + mbox->tx_base = dev_read_addr_index_ptr(dev, 0); 41 + if (!mbox->tx_base) 42 + return -ENODEV; 43 + 44 + return 0; 45 + } 46 + 47 + static const struct udevice_id mfis_mbox_of_match[] = { 48 + { .compatible = "renesas,mfis-mbox", }, 49 + {}, 50 + }; 51 + 52 + U_BOOT_DRIVER(renesas_mfis) = { 53 + .name = "renesas-mfis", 54 + .id = UCLASS_MAILBOX, 55 + .of_match = mfis_mbox_of_match, 56 + .probe = mfis_mbox_probe, 57 + .priv_auto = sizeof(struct mfis_priv), 58 + .ops = &mfis_mbox_ops, 59 + };
+29 -15
drivers/mmc/socfpga_dw_mmc.c
··· 58 58 u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) | 59 59 ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT); 60 60 61 - ret = clk_get_by_name(priv->dev, "ciu", &priv->mmc_clk_ciu); 62 - if (ret) { 63 - debug("%s: Failed to get SDMMC clock from dts\n", __func__); 64 - return ret; 65 - } 61 + if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) && 62 + !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M)) { 63 + /* Disable SDMMC clock. */ 64 + clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN, 65 + CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); 66 + } else { 67 + ret = clk_get_by_name(priv->dev, "ciu", &priv->mmc_clk_ciu); 68 + if (ret) { 69 + debug("%s: Failed to get SDMMC clock from dts\n", __func__); 70 + return ret; 71 + } 66 72 67 - /* Disable SDMMC clock. */ 68 - ret = clk_disable(&priv->mmc_clk_ciu); 69 - if (ret) { 70 - printf("%s: Failed to disable SDMMC clock\n", __func__); 71 - return ret; 73 + /* Disable SDMMC clock. */ 74 + ret = clk_disable(&priv->mmc_clk_ciu); 75 + if (ret) { 76 + printf("%s: Failed to disable SDMMC clock\n", __func__); 77 + return ret; 78 + } 72 79 } 73 80 74 81 debug("%s: drvsel %d smplsel %d\n", __func__, ··· 88 95 readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC)); 89 96 #endif 90 97 91 - /* Enable SDMMC clock */ 92 - ret = clk_enable(&priv->mmc_clk_ciu); 93 - if (ret) { 94 - printf("%s: Failed to enable SDMMC clock\n", __func__); 95 - return ret; 98 + if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) && 99 + !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M)) { 100 + /* Enable SDMMC clock */ 101 + setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN, 102 + CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); 103 + } else { 104 + /* Enable SDMMC clock */ 105 + ret = clk_enable(&priv->mmc_clk_ciu); 106 + if (ret) { 107 + printf("%s: Failed to enable SDMMC clock\n", __func__); 108 + return ret; 109 + } 96 110 } 97 111 98 112 return 0;
+1
drivers/mtd/nand/raw/Kconfig
··· 212 212 config NAND_DENALI 213 213 bool 214 214 select SYS_NAND_SELF_INIT 215 + select SYS_NAND_ONFI_DETECTION if TARGET_SOCFPGA_SOC64 215 216 imply CMD_NAND 216 217 217 218 config NAND_DENALI_DT
+7 -4
drivers/mtd/nand/raw/atmel/pmecc.c
··· 142 142 int nstrengths; 143 143 int el_offset; 144 144 bool correct_erased_chunks; 145 + bool clk_ctrl; 145 146 }; 146 147 147 148 struct atmel_pmecc_user_conf_cache { ··· 819 820 static struct atmel_pmecc * 820 821 atmel_pmecc_create(struct udevice *dev, 821 822 const struct atmel_pmecc_caps *caps, 822 - int pmecc_res_idx, int errloc_res_idx, 823 - int timing_res_idx) 823 + int pmecc_res_idx, int errloc_res_idx) 824 824 { 825 825 struct atmel_pmecc *pmecc; 826 826 struct resource res; ··· 838 838 ofnode_read_resource(dev->node_, 1, &res); 839 839 pmecc->regs.errloc = (void *)res.start; 840 840 841 - pmecc->regs.timing = 0; 841 + /* pmecc data setup time */ 842 + if (caps->clk_ctrl) 843 + writel(PMECC_CLK_133MHZ, pmecc->regs.base + ATMEL_PMECC_CLK); 842 844 843 845 /* Disable all interrupts before registering the PMECC handler. */ 844 846 writel(0xffffffff, pmecc->regs.base + ATMEL_PMECC_IDR); ··· 884 886 .strengths = atmel_pmecc_strengths, 885 887 .nstrengths = 5, 886 888 .el_offset = 0x8c, 889 + .clk_ctrl = true, 887 890 }; 888 891 889 892 static struct atmel_pmecc_caps sama5d4_caps = { ··· 946 949 return -EINVAL; 947 950 } 948 951 949 - pmecc = atmel_pmecc_create(dev, caps, 0, 1, 2); 952 + pmecc = atmel_pmecc_create(dev, caps, 0, 1); 950 953 if (IS_ERR(pmecc)) 951 954 return PTR_ERR(pmecc); 952 955
-1
drivers/mtd/nand/raw/atmel/pmecc.h
··· 65 65 struct { 66 66 void __iomem *base; 67 67 void __iomem *errloc; 68 - void __iomem *timing; 69 68 } regs; 70 69 71 70 /* Mutex used for pmecc enable/disable */
+40 -20
drivers/net/dwc_eth_xgmac.c
··· 140 140 XGMAC_TIMEOUT_100MS, true); 141 141 } 142 142 143 + static u32 xgmac_set_clause(struct xgmac_priv *xgmac, int mdio_addr, int mdio_devad, 144 + int mdio_reg, bool is_c45) 145 + { 146 + u32 hw_addr; 147 + u32 val; 148 + 149 + if (is_c45) { 150 + val = readl(&xgmac->mac_regs->mdio_clause_22_port); 151 + val &= ~BIT(mdio_addr); 152 + writel(val, &xgmac->mac_regs->mdio_clause_22_port); 153 + hw_addr = (mdio_addr << XGMAC_MAC_MDIO_ADDRESS_PA_SHIFT) | 154 + (mdio_reg & XGMAC_MAC_MDIO_REG_ADDR_C45P_MASK); 155 + hw_addr |= mdio_devad << XGMAC_MAC_MDIO_ADDRESS_DA_SHIFT; 156 + } else { 157 + /* Set clause 22 format */ 158 + val = BIT(mdio_addr); 159 + writel(val, &xgmac->mac_regs->mdio_clause_22_port); 160 + hw_addr = (mdio_addr << XGMAC_MAC_MDIO_ADDRESS_PA_SHIFT) | 161 + (mdio_reg & XGMAC_MAC_MDIO_REG_ADDR_C22P_MASK); 162 + } 163 + 164 + return hw_addr; 165 + } 166 + 143 167 static int xgmac_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad, 144 168 int mdio_reg) 145 169 { 170 + bool is_c45 = (mdio_devad != MDIO_DEVAD_NONE); 146 171 struct xgmac_priv *xgmac = bus->priv; 147 172 u32 val; 148 173 u32 hw_addr; ··· 159 184 return ret; 160 185 } 161 186 162 - /* Set clause 22 format */ 163 - val = BIT(mdio_addr); 164 - writel(val, &xgmac->mac_regs->mdio_clause_22_port); 165 - 166 - hw_addr = (mdio_addr << XGMAC_MAC_MDIO_ADDRESS_PA_SHIFT) | 167 - (mdio_reg & XGMAC_MAC_MDIO_REG_ADDR_C22P_MASK); 187 + hw_addr = xgmac_set_clause(xgmac, mdio_addr, mdio_devad, mdio_reg, is_c45); 168 188 169 189 val = xgmac->config->config_mac_mdio << 170 190 XGMAC_MAC_MDIO_ADDRESS_CR_SHIFT; 171 191 172 - val |= XGMAC_MAC_MDIO_ADDRESS_SADDR | 173 - XGMAC_MDIO_SINGLE_CMD_ADDR_CMD_READ | 174 - XGMAC_MAC_MDIO_ADDRESS_SBUSY; 192 + if (!is_c45) 193 + val |= XGMAC_MAC_MDIO_ADDRESS_SADDR; 194 + 195 + val |= XGMAC_MDIO_SINGLE_CMD_ADDR_CMD_READ | 196 + XGMAC_MAC_MDIO_ADDRESS_SBUSY; 175 197 176 198 ret = xgmac_mdio_wait_idle(xgmac); 177 199 if (ret) { ··· 203 225 static int xgmac_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad, 204 226 int mdio_reg, u16 mdio_val) 205 227 { 228 + bool is_c45 = (mdio_devad != MDIO_DEVAD_NONE); 206 229 struct xgmac_priv *xgmac = bus->priv; 207 230 u32 val; 208 231 u32 hw_addr; ··· 219 242 return ret; 220 243 } 221 244 222 - /* Set clause 22 format */ 223 - val = BIT(mdio_addr); 224 - writel(val, &xgmac->mac_regs->mdio_clause_22_port); 225 - 226 - hw_addr = (mdio_addr << XGMAC_MAC_MDIO_ADDRESS_PA_SHIFT) | 227 - (mdio_reg & XGMAC_MAC_MDIO_REG_ADDR_C22P_MASK); 228 - 229 - hw_addr |= (mdio_reg >> XGMAC_MAC_MDIO_ADDRESS_PA_SHIFT) << 230 - XGMAC_MAC_MDIO_ADDRESS_DA_SHIFT; 245 + hw_addr = xgmac_set_clause(xgmac, mdio_addr, mdio_devad, mdio_reg, is_c45); 231 246 232 247 val = (xgmac->config->config_mac_mdio << 233 248 XGMAC_MAC_MDIO_ADDRESS_CR_SHIFT); 234 249 235 - val |= XGMAC_MAC_MDIO_ADDRESS_SADDR | 236 - mdio_val | XGMAC_MDIO_SINGLE_CMD_ADDR_CMD_WRITE | 250 + if (!is_c45) { 251 + hw_addr |= (mdio_reg >> XGMAC_MAC_MDIO_ADDRESS_PA_SHIFT) << 252 + XGMAC_MAC_MDIO_ADDRESS_DA_SHIFT; 253 + val |= XGMAC_MAC_MDIO_ADDRESS_SADDR; 254 + } 255 + 256 + val |= mdio_val | XGMAC_MDIO_SINGLE_CMD_ADDR_CMD_WRITE | 237 257 XGMAC_MAC_MDIO_ADDRESS_SBUSY; 238 258 239 259 ret = xgmac_mdio_wait_idle(xgmac);
+1
drivers/net/dwc_eth_xgmac.h
··· 109 109 #define XGMAC_MAC_MDIO_ADDRESS_SBUSY BIT(22) 110 110 #define XGMAC_MAC_MDIO_REG_ADDR_C22P_MASK GENMASK(4, 0) 111 111 #define XGMAC_MAC_MDIO_DATA_GD_MASK GENMASK(15, 0) 112 + #define XGMAC_MAC_MDIO_REG_ADDR_C45P_MASK GENMASK(15, 0) 112 113 113 114 /* MTL Registers */ 114 115
+2 -2
drivers/net/phy/broadcom.c
··· 176 176 { 177 177 int ret; 178 178 179 - ret = bcm54xx_config_clock_delay(phydev); 179 + ret = bcm5461_config(phydev); 180 180 if (ret < 0) 181 181 return ret; 182 182 183 - ret = bcm5461_config(phydev); 183 + ret = bcm54xx_config_clock_delay(phydev); 184 184 if (ret < 0) 185 185 return ret; 186 186
+3 -2
drivers/net/phy/dp83869.c
··· 5 5 */ 6 6 7 7 #include <phy.h> 8 + #include <linux/bitfield.h> 8 9 #include <linux/compat.h> 9 10 #include <malloc.h> 10 11 ··· 64 65 #define DP83869_RGMII_RX_CLK_DELAY_EN BIT(0) 65 66 66 67 /* STRAP_STS1 bits */ 67 - #define DP83869_STRAP_OP_MODE_MASK GENMASK(2, 0) 68 + #define DP83869_STRAP_OP_MODE_MASK GENMASK(11, 9) 68 69 #define DP83869_STRAP_STS1_RESERVED BIT(11) 69 70 #define DP83869_STRAP_MIRROR_ENABLED BIT(12) 70 71 ··· 168 169 if (val < 0) 169 170 return val; 170 171 171 - dp83869->mode = val & DP83869_STRAP_OP_MODE_MASK; 172 + dp83869->mode = FIELD_GET(DP83869_STRAP_OP_MODE_MASK, val); 172 173 173 174 return 0; 174 175 }
+4
drivers/net/ti/am65-cpsw-nuss.c
··· 819 819 ofnode_for_each_subnode(node, ports_np) { 820 820 const char *node_name; 821 821 822 + /* Ignore disabled ports */ 823 + if (!ofnode_is_enabled(node)) 824 + continue; 825 + 822 826 node_name = ofnode_get_name(node); 823 827 824 828 ret = device_bind_driver_to_node(dev, "am65_cpsw_nuss_port", node_name, node,
+102 -3
drivers/pinctrl/broadcom/pinctrl-bcm283x.c
··· 21 21 #include <asm/system.h> 22 22 #include <asm/io.h> 23 23 #include <asm/gpio.h> 24 + #include <dt-bindings/pinctrl/bcm2835.h> 25 + #include <linux/delay.h> 24 26 25 27 struct bcm283x_pinctrl_priv { 26 28 u32 *base_reg; ··· 54 56 } 55 57 56 58 /* 57 - * bcm283x_pinctrl_set_state: configure pin functions. 59 + * bcm2835_gpio_set_pull: Set GPIO pull-up/down resistor for BCM2835 60 + * @dev: the pinctrl device 61 + * @gpio: the GPIO pin number 62 + * @pull: pull setting (BCM2835_PUD_OFF, BCM2835_PUD_DOWN, BCM2835_PUD_UP) 63 + */ 64 + static void bcm2835_gpio_set_pull(struct udevice *dev, unsigned int gpio, int pull) 65 + { 66 + struct bcm283x_pinctrl_priv *priv = dev_get_priv(dev); 67 + u32 bank = BCM2835_GPPUDCLK0 + BCM2835_GPIO_COMMON_BANK(gpio); 68 + u32 bit = BCM2835_GPIO_COMMON_SHIFT(gpio); 69 + 70 + /* Set required control signal */ 71 + writel(pull & 0x3, &priv->base_reg[BCM2835_GPPUD]); 72 + udelay(1); 73 + 74 + /* Clock the control signal into the GPIO pads */ 75 + writel(1 << bit, &priv->base_reg[bank]); 76 + udelay(1); 77 + 78 + /* Remove the control signal and clock */ 79 + writel(0, &priv->base_reg[BCM2835_GPPUD]); 80 + writel(0, &priv->base_reg[bank]); 81 + } 82 + 83 + /* 84 + * bcm2711_gpio_set_pull: Set GPIO pull-up/down resistor for BCM2711 85 + * @dev: the pinctrl device 86 + * @gpio: the GPIO pin number 87 + * @pull: pull setting (BCM2835_PUD_OFF, BCM2835_PUD_DOWN, BCM2835_PUD_UP) 88 + */ 89 + static void bcm2711_gpio_set_pull(struct udevice *dev, unsigned int gpio, int pull) 90 + { 91 + struct bcm283x_pinctrl_priv *priv = dev_get_priv(dev); 92 + u32 reg_offset; 93 + u32 bit_shift; 94 + u32 pull_bits; 95 + 96 + /* Findout which GPIO_PUP_PDN_CNTRL register to use */ 97 + reg_offset = BCM2711_GPPUD_CNTRL_REG0 + BCM2711_PUD_REG_OFFSET(gpio); 98 + 99 + /* Findout the bit position */ 100 + bit_shift = BCM2711_PUD_REG_SHIFT(gpio); 101 + 102 + /* Update the 2-bit field for this GPIO */ 103 + pull_bits = pull & BCM2711_PUD_2711_MASK; 104 + clrsetbits_le32(&priv->base_reg[reg_offset], 105 + BCM2711_PUD_2711_MASK << bit_shift, 106 + pull_bits << bit_shift); 107 + } 108 + 109 + static void bcm283x_gpio_set_pull(struct udevice *dev, unsigned int gpio, int pull) 110 + { 111 + if (device_is_compatible(dev, "brcm,bcm2835-gpio")) 112 + bcm2835_gpio_set_pull(dev, gpio, pull); 113 + else 114 + bcm2711_gpio_set_pull(dev, gpio, pull); 115 + } 116 + 117 + /* 118 + * bcm283x_pinctrl_set_state: configure pin functions and pull states. 58 119 * @dev: the pinctrl device to be configured. 59 120 * @config: the state to be configured. 60 121 * @return: 0 in success ··· 62 123 int bcm283x_pinctrl_set_state(struct udevice *dev, struct udevice *config) 63 124 { 64 125 u32 pin_arr[MAX_PINS_PER_BANK]; 126 + u32 pull_arr[MAX_PINS_PER_BANK]; 65 127 int function; 66 - int i, len, pin_count = 0; 128 + int i, len, pin_count = 0, pull_len = 0, pull_count = 0; 129 + int pull_value; 67 130 68 131 if (!dev_read_prop(config, "brcm,pins", &len) || !len || 69 132 len & 0x3 || dev_read_u32_array(config, "brcm,pins", pin_arr, ··· 82 145 return -EINVAL; 83 146 } 84 147 85 - for (i = 0; i < pin_count; i++) 148 + /* Check if brcm,pull property exists */ 149 + if (dev_read_prop(config, "brcm,pull", &pull_len) && pull_len > 0) { 150 + if (pull_len & 0x3) { 151 + debug("Invalid pull array length for pinconfig %s (%d)\n", 152 + config->name, pull_len); 153 + return -EINVAL; 154 + } 155 + 156 + pull_count = pull_len / sizeof(u32); 157 + 158 + if (pull_count != 1 && pull_count != pin_count) { 159 + debug("Pull array count (%d) must be 1 or match pin count (%d) for pinconfig %s\n", 160 + pull_count, pin_count, config->name); 161 + return -EINVAL; 162 + } 163 + 164 + if (dev_read_u32_array(config, "brcm,pull", pull_arr, pull_count)) { 165 + debug("Failed reading pull array for pinconfig %s\n", config->name); 166 + return -EINVAL; 167 + } 168 + 169 + /* Validate pull values */ 170 + for (i = 0; i < pull_count; i++) { 171 + if (pull_arr[i] > 2) { 172 + debug("Invalid pull value %d for pin %d in pinconfig %s\n", 173 + pull_arr[i], pin_arr[i], config->name); 174 + return -EINVAL; 175 + } 176 + } 177 + } 178 + 179 + for (i = 0; i < pin_count; i++) { 86 180 bcm2835_gpio_set_func_id(dev, pin_arr[i], function); 181 + if (pull_count > 0) { 182 + pull_value = (pull_count == 1) ? pull_arr[0] : pull_arr[i]; 183 + bcm283x_gpio_set_pull(dev, pin_arr[i], pull_value); 184 + } 185 + } 87 186 88 187 return 0; 89 188 }
+11
drivers/pinctrl/exynos/pinctrl-exynos.c
··· 7 7 8 8 #include <log.h> 9 9 #include <dm.h> 10 + #include <dm/lists.h> 10 11 #include <errno.h> 11 12 #include <asm/io.h> 12 13 #include "pinctrl-exynos.h" ··· 178 179 179 180 return 0; 180 181 } 182 + 183 + int exynos_pinctrl_bind(struct udevice *dev) 184 + { 185 + /* 186 + * Attempt to bind the Exynos GPIO driver. The GPIOs and 187 + * pin controller descriptors are found in the same OF node. 188 + */ 189 + return device_bind_driver_to_node(dev, "gpio_exynos", "gpio-banks", 190 + dev_ofnode(dev), NULL); 191 + }
+1
drivers/pinctrl/exynos/pinctrl-exynos.h
··· 97 97 int exynos_pinctrl_set_state(struct udevice *dev, 98 98 struct udevice *config); 99 99 int exynos_pinctrl_probe(struct udevice *dev); 100 + int exynos_pinctrl_bind(struct udevice *dev); 100 101 101 102 #endif /* __PINCTRL_EXYNOS_H_ */
+1
drivers/pinctrl/exynos/pinctrl-exynos7420.c
··· 114 114 .priv_auto = sizeof(struct exynos_pinctrl_priv), 115 115 .ops = &exynos7420_pinctrl_ops, 116 116 .probe = exynos_pinctrl_probe, 117 + .bind = exynos_pinctrl_bind, 117 118 };
+60
drivers/pinctrl/exynos/pinctrl-exynos78x0.c
··· 45 45 EXYNOS_PIN_BANK(4, 0x040, "gpz2"), 46 46 }; 47 47 48 + /* pin banks of exynos78x0 pin-controller 3 (ESE) */ 49 + static const struct samsung_pin_bank_data exynos78x0_pin_banks3[] = { 50 + EXYNOS_PIN_BANK(5, 0x000, "gpc7"), 51 + }; 52 + 48 53 /* pin banks of exynos78x0 pin-controller 4 (FSYS) */ 49 54 static const struct samsung_pin_bank_data exynos78x0_pin_banks4[] = { 50 55 EXYNOS_PIN_BANK(3, 0x000, "gpr0"), ··· 52 57 EXYNOS_PIN_BANK(2, 0x040, "gpr2"), 53 58 EXYNOS_PIN_BANK(4, 0x060, "gpr3"), 54 59 EXYNOS_PIN_BANK(6, 0x080, "gpr4"), 60 + }; 61 + 62 + /* pin banks of exynos78x0 pin-controller 5 (NFC) */ 63 + static const struct samsung_pin_bank_data exynos78x0_pin_banks5[] = { 64 + EXYNOS_PIN_BANK(4, 0x000, "gpc2"), 55 65 }; 56 66 57 67 /* pin banks of exynos78x0 pin-controller 6 (TOP) */ ··· 75 85 EXYNOS_PIN_BANK(2, 0x200, "gpf2"), 76 86 EXYNOS_PIN_BANK(4, 0x220, "gpf3"), 77 87 EXYNOS_PIN_BANK(5, 0x240, "gpf4"), 88 + }; 89 + 90 + /* pin banks of exynos7870 pin-controller 7 (TOUCH) */ 91 + static const struct samsung_pin_bank_data exynos78x0_pin_banks7[] = { 92 + EXYNOS_PIN_BANK(3, 0x000, "gpc3"), 78 93 }; 79 94 80 95 const struct samsung_pin_ctrl exynos78x0_pin_ctrl[] = { ··· 102 117 {/* list terminator */} 103 118 }; 104 119 120 + /* 121 + * In Exynos7870, the CCORE block is named as MIF instead. As the 122 + * pinctrl blocks are sorted in lexical order of their names, the 123 + * order isn't the same as Exynos7880. 124 + */ 125 + const struct samsung_pin_ctrl exynos7870_pin_ctrl[] = { 126 + { 127 + /* pin-controller instance 0 Alive data */ 128 + .pin_banks = exynos78x0_pin_banks0, 129 + .nr_banks = ARRAY_SIZE(exynos78x0_pin_banks0), 130 + }, { 131 + /* pin-controller instance 1 DISPAUD data */ 132 + .pin_banks = exynos78x0_pin_banks2, 133 + .nr_banks = ARRAY_SIZE(exynos78x0_pin_banks2), 134 + }, { 135 + /* pin-controller instance 2 ESE data */ 136 + .pin_banks = exynos78x0_pin_banks3, 137 + .nr_banks = ARRAY_SIZE(exynos78x0_pin_banks3), 138 + }, { 139 + /* pin-controller instance 3 FSYS data */ 140 + .pin_banks = exynos78x0_pin_banks4, 141 + .nr_banks = ARRAY_SIZE(exynos78x0_pin_banks4), 142 + }, { 143 + /* pin-controller instance 4 MIF data */ 144 + .pin_banks = exynos78x0_pin_banks1, 145 + .nr_banks = ARRAY_SIZE(exynos78x0_pin_banks1), 146 + }, { 147 + /* pin-controller instance 5 NFC data */ 148 + .pin_banks = exynos78x0_pin_banks5, 149 + .nr_banks = ARRAY_SIZE(exynos78x0_pin_banks5), 150 + }, { 151 + /* pin-controller instance 6 TOP data */ 152 + .pin_banks = exynos78x0_pin_banks6, 153 + .nr_banks = ARRAY_SIZE(exynos78x0_pin_banks6), 154 + }, { 155 + /* pin-controller instance 7 TOUCH data */ 156 + .pin_banks = exynos78x0_pin_banks7, 157 + .nr_banks = ARRAY_SIZE(exynos78x0_pin_banks7), 158 + }, 159 + {/* list terminator */} 160 + }; 161 + 105 162 static const struct udevice_id exynos78x0_pinctrl_ids[] = { 106 163 { .compatible = "samsung,exynos78x0-pinctrl", 107 164 .data = (ulong)exynos78x0_pin_ctrl }, 165 + { .compatible = "samsung,exynos7870-pinctrl", 166 + .data = (ulong)exynos7870_pin_ctrl }, 108 167 { } 109 168 }; 110 169 ··· 115 174 .priv_auto = sizeof(struct exynos_pinctrl_priv), 116 175 .ops = &exynos78x0_pinctrl_ops, 117 176 .probe = exynos_pinctrl_probe, 177 + .bind = exynos_pinctrl_bind, 118 178 };
+1
drivers/pinctrl/exynos/pinctrl-exynos850.c
··· 122 122 .priv_auto = sizeof(struct exynos_pinctrl_priv), 123 123 .ops = &exynos850_pinctrl_ops, 124 124 .probe = exynos_pinctrl_probe, 125 + .bind = exynos_pinctrl_bind, 125 126 };
+1 -1
drivers/power/domain/ti-power-domain.c
··· 227 227 228 228 pd_write(pdctl, pd, PSC_PDCTL); 229 229 230 - return 0; 230 + return ti_pd_wait(pd); 231 231 } 232 232 233 233 static int ti_pd_put(struct ti_pd *pd)
+1
drivers/serial/serial_s5p.c
··· 258 258 static const struct udevice_id s5p_serial_ids[] = { 259 259 { .compatible = "samsung,exynos4210-uart", .data = PORT_S5P }, 260 260 { .compatible = "samsung,exynos850-uart", .data = PORT_S5P }, 261 + { .compatible = "samsung,exynos8895-uart", .data = PORT_S5P }, 261 262 { .compatible = "apple,s5l-uart", .data = PORT_S5L }, 262 263 { } 263 264 };
+3
drivers/soc/samsung/exynos-pmu.c
··· 86 86 87 87 static const struct udevice_id exynos_pmu_ids[] = { 88 88 { 89 + .compatible = "samsung,exynos7-pmu", 90 + }, 91 + { 89 92 .compatible = "samsung,exynos850-pmu", 90 93 .data = (ulong)&exynos850_pmu_data 91 94 },
+15
drivers/spi/Kconfig
··· 180 180 This option is used to enable Versal OSPI DMA operations which 181 181 are used for ospi flash read using cadence qspi controller. 182 182 183 + config CADENCE_XSPI 184 + bool "Cadence XSPI driver (Experimental feature)" 185 + help 186 + Important: this feature is experimental so far and tested only 187 + on simulated environment. 188 + 189 + Enable the Cadence eXpanded Serial Periheral Interface (xSPI) flash 190 + driver. This driver can be used to access the SPI NOR flash on 191 + platforms embedding this Cadence IP core up to 8 bit wide bus. 192 + xSPI flash controller IP offers three work mode, Auto Command (ACMD) 193 + work mode, Software Triggered Instruction Generator (STIG) work mode 194 + and Direct work mode. This flash controller able to coomunicate 195 + with Flash Memory Devices supporting JESD216 and JESD251 stadards 196 + by using the Auto Command work mode. 197 + 183 198 config CF_SPI 184 199 bool "ColdFire SPI driver" 185 200 depends on M68K
+1
drivers/spi/Makefile
··· 8 8 obj-y += spi-uclass.o 9 9 obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o 10 10 obj-$(CONFIG_CADENCE_OSPI_VERSAL) += cadence_ospi_versal.o 11 + obj-$(CONFIG_CADENCE_XSPI) += cadence_xspi.o 11 12 obj-$(CONFIG_SANDBOX) += spi-emul-uclass.o 12 13 obj-$(CONFIG_SOFT_SPI) += soft_spi.o 13 14 obj-$(CONFIG_SPI_ASPEED_SMC) += spi-aspeed-smc.o
+449
drivers/spi/cadence_xspi.c
··· 1 + // SPDX-License-Identifier: GPL-2.0+ 2 + /* 3 + * Copyright (C) 2025 4 + * Altera Corporation <www.altera.com> 5 + */ 6 + 7 + #include <clk.h> 8 + #include <dm.h> 9 + #include <fdtdec.h> 10 + #include <log.h> 11 + #include <malloc.h> 12 + #include <reset.h> 13 + #include <spi.h> 14 + #include <spi-mem.h> 15 + #include <dm/device_compat.h> 16 + #include <linux/bitops.h> 17 + #include <linux/err.h> 18 + #include <linux/errno.h> 19 + #include <linux/io.h> 20 + #include <linux/iopoll.h> 21 + #include <linux/ioport.h> 22 + #include <linux/sizes.h> 23 + #include <linux/time.h> 24 + #include "cadence_xspi.h" 25 + 26 + static int cdns_xspi_wait_for_controller_idle(struct cdns_xspi_plat *cdns_xspi) 27 + { 28 + u32 ctrl_stat; 29 + 30 + return readl_relaxed_poll_timeout(cdns_xspi->iobase + 31 + CDNS_XSPI_CTRL_STATUS_REG, 32 + ctrl_stat, 33 + !(ctrl_stat & 34 + CDNS_XSPI_CTRL_BUSY), 35 + 1000); 36 + } 37 + 38 + static int cdns_xspi_wait_for_sdma_complete(struct cdns_xspi_plat *cdns_xspi) 39 + { 40 + u32 irq_status; 41 + int ret = 0; 42 + 43 + ret = readl_relaxed_poll_timeout(cdns_xspi->iobase + 44 + CDNS_XSPI_INTR_STATUS_REG, 45 + irq_status, 46 + (irq_status & 47 + CDNS_XSPI_SDMA_TRIGGER), 48 + 1000); 49 + 50 + if (!ret) { 51 + /* 52 + * SDMA return an interrupt, need to clear 53 + * the interrupt after read, wrtting 1 to clear the bit. 54 + */ 55 + setbits_le32(cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG, 56 + CDNS_XSPI_SDMA_TRIGGER); 57 + } 58 + 59 + /* Check if SDMA ERROR happened */ 60 + if (irq_status & CDNS_XSPI_SDMA_ERROR) { 61 + /* 62 + * Need to clear the SDMA_ERROR interrupt 63 + * after read, wrtting 1 to clear the bit. 64 + */ 65 + dev_err(cdns_xspi->dev, 66 + "Slave DMA transaction error\n"); 67 + 68 + cdns_xspi->sdma_error = true; 69 + setbits_le32(cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG, 70 + CDNS_XSPI_SDMA_ERROR); 71 + 72 + ret = -EIO; 73 + } 74 + 75 + return ret; 76 + } 77 + 78 + static int cdns_xspi_wait_for_cmd_complete(struct cdns_xspi_plat *cdns_xspi) 79 + { 80 + u32 irq_status; 81 + int ret = 0; 82 + 83 + ret = readl_relaxed_poll_timeout(cdns_xspi->iobase + 84 + CDNS_XSPI_INTR_STATUS_REG, 85 + irq_status, 86 + (irq_status & 87 + CDNS_XSPI_STIG_DONE), 88 + 100000); 89 + 90 + irq_status = readl(cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG); 91 + 92 + if (!ret) { 93 + /* 94 + * Need to clear the interrupt after read, 95 + * wrtting 1 to the clear the bit. 96 + */ 97 + writel(irq_status & CDNS_XSPI_STIG_DONE, 98 + cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG); 99 + } 100 + 101 + return ret; 102 + } 103 + 104 + static void cdns_xspi_trigger_command(struct cdns_xspi_plat *cdns_xspi, 105 + u32 cmd_regs[6]) 106 + { 107 + writel(cmd_regs[5], cdns_xspi->iobase + CDNS_XSPI_CMD_REG_5); 108 + writel(cmd_regs[4], cdns_xspi->iobase + CDNS_XSPI_CMD_REG_4); 109 + writel(cmd_regs[3], cdns_xspi->iobase + CDNS_XSPI_CMD_REG_3); 110 + writel(cmd_regs[2], cdns_xspi->iobase + CDNS_XSPI_CMD_REG_2); 111 + writel(cmd_regs[1], cdns_xspi->iobase + CDNS_XSPI_CMD_REG_1); 112 + writel(cmd_regs[0], cdns_xspi->iobase + CDNS_XSPI_CMD_REG_0); 113 + } 114 + 115 + static int cdns_xspi_check_command_status(struct cdns_xspi_plat *cdns_xspi) 116 + { 117 + int ret = 0; 118 + u32 cmd_status = readl(cdns_xspi->iobase + CDNS_XSPI_CMD_STATUS_REG); 119 + 120 + /* Check if the command has completed */ 121 + if (cmd_status & CDNS_XSPI_CMD_STATUS_COMPLETED) { 122 + /*Check for failure status and report each type of error */ 123 + if ((cmd_status & CDNS_XSPI_CMD_STATUS_FAILED) != 0) { 124 + if (cmd_status & CDNS_XSPI_CMD_STATUS_DQS_ERROR) 125 + dev_err(cdns_xspi->dev, 126 + "Incorrect DQS pulses detected\n"); 127 + 128 + if (cmd_status & CDNS_XSPI_CMD_STATUS_CRC_ERROR) 129 + dev_err(cdns_xspi->dev, 130 + "CRC error received\n"); 131 + 132 + if (cmd_status & CDNS_XSPI_CMD_STATUS_BUS_ERROR) 133 + dev_err(cdns_xspi->dev, 134 + "Error resp on system DMA interface\n"); 135 + 136 + if (cmd_status & CDNS_XSPI_CMD_STATUS_INV_SEQ_ERROR) 137 + dev_err(cdns_xspi->dev, 138 + "Invalid command sequence detected\n"); 139 + 140 + ret = -EPROTO; 141 + } 142 + } else { 143 + /* Command did not complete at all -- fatal error */ 144 + dev_err(cdns_xspi->dev, "Fatal err - command not completed\n"); 145 + ret = -EPROTO; 146 + } 147 + 148 + return ret; 149 + } 150 + 151 + static void cdns_xspi_set_interrupts(struct cdns_xspi_plat *cdns_xspi, 152 + bool enabled) 153 + { 154 + u32 intr_enable; 155 + 156 + intr_enable = readl(cdns_xspi->iobase + CDNS_XSPI_INTR_ENABLE_REG); 157 + if (enabled) 158 + intr_enable |= CDNS_XSPI_INTR_MASK; 159 + else 160 + intr_enable &= ~CDNS_XSPI_INTR_MASK; 161 + writel(intr_enable, cdns_xspi->iobase + CDNS_XSPI_INTR_ENABLE_REG); 162 + } 163 + 164 + static int cdns_xspi_controller_init(struct cdns_xspi_plat *cdns_xspi) 165 + { 166 + u32 ctrl_ver; 167 + u32 ctrl_features; 168 + u16 hw_magic_num; 169 + 170 + ctrl_ver = readl(cdns_xspi->iobase + CDNS_XSPI_CTRL_VERSION_REG); 171 + hw_magic_num = FIELD_GET(CDNS_XSPI_MAGIC_NUM, ctrl_ver); 172 + if (hw_magic_num != CDNS_XSPI_MAGIC_NUM_VALUE) { 173 + dev_err(cdns_xspi->dev, 174 + "Incorrect XSPI magic number: %x, expected: %x\n", 175 + hw_magic_num, CDNS_XSPI_MAGIC_NUM_VALUE); 176 + return -ENXIO; 177 + } 178 + 179 + ctrl_features = readl(cdns_xspi->iobase + CDNS_XSPI_CTRL_FEATURES_REG); 180 + cdns_xspi->hw_num_banks = FIELD_GET(CDNS_XSPI_NUM_BANKS, ctrl_features); 181 + cdns_xspi->set_interrupts_handler(cdns_xspi, false); 182 + 183 + return 0; 184 + } 185 + 186 + static void cdns_xspi_sdma_handle(struct cdns_xspi_plat *cdns_xspi) 187 + { 188 + u32 sdma_size, sdma_trd_info; 189 + u8 sdma_dir; 190 + u8 *in_buf; 191 + u8 *out_buf; 192 + 193 + sdma_size = readl(cdns_xspi->iobase + CDNS_XSPI_SDMA_SIZE_REG); 194 + sdma_trd_info = readl(cdns_xspi->iobase + CDNS_XSPI_SDMA_TRD_INFO_REG); 195 + sdma_dir = FIELD_GET(CDNS_XSPI_SDMA_DIR, sdma_trd_info); 196 + 197 + in_buf = (u8 *)cdns_xspi->in_buffer; 198 + out_buf = (u8 *)cdns_xspi->out_buffer; 199 + 200 + switch (sdma_dir) { 201 + case CDNS_XSPI_SDMA_DIR_READ: 202 + if (in_buf) 203 + memcpy_fromio(in_buf, cdns_xspi->sdmabase, sdma_size); 204 + break; 205 + 206 + case CDNS_XSPI_SDMA_DIR_WRITE: 207 + if (in_buf) 208 + memcpy_toio(cdns_xspi->sdmabase, out_buf, sdma_size); 209 + break; 210 + 211 + default: 212 + /* Handle unexpected direction */ 213 + dev_warn(cdns_xspi->dev, 214 + "Unknown SDMA direction: %u\n", sdma_dir); 215 + break; 216 + } 217 + } 218 + 219 + static int cdns_xspi_send_stig_command(struct cdns_xspi_plat *cdns_xspi, 220 + const struct spi_mem_op *op, 221 + bool data_phase) 222 + { 223 + u32 cmd_regs[6] = {0}; 224 + int ret = 0; 225 + int dummybytes = op->dummy.nbytes; 226 + 227 + ret = cdns_xspi_wait_for_controller_idle(cdns_xspi); 228 + if (ret < 0) 229 + return ret; 230 + 231 + writel(FIELD_PREP(CDNS_XSPI_CTRL_WORK_MODE, CDNS_XSPI_WORK_MODE_STIG), 232 + cdns_xspi->iobase + CDNS_XSPI_CTRL_CONFIG_REG); 233 + 234 + cdns_xspi->set_interrupts_handler(cdns_xspi, true); 235 + cdns_xspi->sdma_error = false; 236 + 237 + cmd_regs[1] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_1(op, data_phase); 238 + cmd_regs[2] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_2(op); 239 + if (dummybytes != 0) { 240 + cmd_regs[3] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_3(op, 1); 241 + dummybytes--; 242 + } else { 243 + cmd_regs[3] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_3(op, 0); 244 + } 245 + cmd_regs[4] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_4(op, 246 + cdns_xspi->cur_cs); 247 + 248 + cdns_xspi_trigger_command(cdns_xspi, cmd_regs); 249 + 250 + if (data_phase) { 251 + cmd_regs[0] = CDNS_XSPI_STIG_DONE_FLAG; 252 + cmd_regs[1] = CDNS_XSPI_CMD_FLD_DSEQ_CMD_1; 253 + cmd_regs[2] = CDNS_XSPI_CMD_FLD_DSEQ_CMD_2(op); 254 + cmd_regs[3] = CDNS_XSPI_CMD_FLD_DSEQ_CMD_3(op, dummybytes); 255 + cmd_regs[4] = CDNS_XSPI_CMD_FLD_DSEQ_CMD_4(op, 256 + cdns_xspi->cur_cs); 257 + 258 + cdns_xspi->in_buffer = op->data.buf.in; 259 + cdns_xspi->out_buffer = op->data.buf.out; 260 + 261 + cdns_xspi_trigger_command(cdns_xspi, cmd_regs); 262 + 263 + cdns_xspi_wait_for_sdma_complete(cdns_xspi); 264 + 265 + if (cdns_xspi->sdma_error) { 266 + cdns_xspi->set_interrupts_handler(cdns_xspi, false); 267 + return -EIO; 268 + } 269 + cdns_xspi_sdma_handle(cdns_xspi); 270 + } 271 + 272 + cdns_xspi_wait_for_cmd_complete(cdns_xspi); 273 + ret = cdns_xspi_check_command_status(cdns_xspi); 274 + if (ret) 275 + return ret; 276 + 277 + return 0; 278 + } 279 + 280 + static int cdns_xspi_mem_op(struct udevice *bus, 281 + const struct spi_mem_op *op, 282 + unsigned int cs) 283 + { 284 + struct cdns_xspi_plat *plat = dev_get_plat(bus); 285 + enum spi_mem_data_dir dir = op->data.dir; 286 + 287 + if (plat->cur_cs != cs) 288 + plat->cur_cs = cs; 289 + 290 + return cdns_xspi_send_stig_command(plat, op, 291 + (dir != SPI_MEM_NO_DATA)); 292 + } 293 + 294 + static int cdns_xspi_mem_op_execute(struct spi_slave *spi, 295 + const struct spi_mem_op *op) 296 + { 297 + struct udevice *bus = spi->dev->parent; 298 + unsigned int cs = 0; 299 + int ret = 0; 300 + 301 + cs = spi_chip_select(spi->dev); 302 + 303 + if (cs < 0) { 304 + /* 305 + * spi_chip_select will return error number when not 306 + * able to get chip select. 307 + */ 308 + pr_err("%s: Unable to get chip select, ret=%d", 309 + spi->dev->name, cs); 310 + return cs; 311 + } 312 + 313 + ret = cdns_xspi_mem_op(bus, op, cs); 314 + 315 + return ret; 316 + } 317 + 318 + static int cdns_xspi_adjust_mem_op_size(struct spi_slave *spi, 319 + struct spi_mem_op *op) 320 + { 321 + struct udevice *bus = spi->dev->parent; 322 + struct cdns_xspi_plat *plat = dev_get_plat(bus); 323 + 324 + op->data.nbytes = clamp_val(op->data.nbytes, 0, plat->sdmasize); 325 + 326 + return 0; 327 + } 328 + 329 + static const struct spi_controller_mem_ops cadence_xspi_mem_ops = { 330 + .exec_op = cdns_xspi_mem_op_execute, 331 + .adjust_op_size = cdns_xspi_adjust_mem_op_size, 332 + }; 333 + 334 + static void cdns_xspi_print_phy_config(struct cdns_xspi_plat *cdns_xspi) 335 + { 336 + struct device *dev = cdns_xspi->dev; 337 + 338 + dev_info(dev, "PHY configuration\n"); 339 + dev_info(dev, " * xspi_dll_phy_ctrl: %08x\n", 340 + readl(cdns_xspi->iobase + CDNS_XSPI_DLL_PHY_CTRL)); 341 + dev_info(dev, " * phy_dq_timing: %08x\n", 342 + readl(cdns_xspi->auxbase + CDNS_XSPI_CCP_PHY_DQ_TIMING)); 343 + dev_info(dev, " * phy_dqs_timing: %08x\n", 344 + readl(cdns_xspi->auxbase + CDNS_XSPI_CCP_PHY_DQS_TIMING)); 345 + dev_info(dev, " * phy_gate_loopback_ctrl: %08x\n", 346 + readl(cdns_xspi->auxbase + CDNS_XSPI_CCP_PHY_GATE_LPBCK_CTRL)); 347 + dev_info(dev, " * phy_dll_slave_ctrl: %08x\n", 348 + readl(cdns_xspi->auxbase + CDNS_XSPI_CCP_PHY_DLL_SLAVE_CTRL)); 349 + } 350 + 351 + static int cdns_xspi_probe(struct udevice *bus) 352 + { 353 + struct cdns_xspi_plat *cdns_xspi = dev_get_plat(bus); 354 + struct resource res; 355 + int ret = 0; 356 + 357 + cdns_xspi->sdma_handler = &cdns_xspi_sdma_handle; 358 + cdns_xspi->set_interrupts_handler = &cdns_xspi_set_interrupts; 359 + cdns_xspi->cur_cs = 0; 360 + 361 + ret = dev_read_resource_byname(bus, "io", &res); 362 + if (ret) 363 + return ret; 364 + 365 + cdns_xspi->iobase = devm_ioremap(bus, res.start, resource_size(&res)); 366 + 367 + if (IS_ERR(cdns_xspi->iobase)) { 368 + dev_err(bus, "Failed to remap controller base address\n"); 369 + return PTR_ERR(cdns_xspi->iobase); 370 + } 371 + 372 + ret = dev_read_resource_byname(bus, "sdma", &res); 373 + if (ret) 374 + return ret; 375 + 376 + cdns_xspi->sdmabase = devm_ioremap(bus, res.start, resource_size(&res)); 377 + 378 + if (IS_ERR(cdns_xspi->sdmabase)) { 379 + dev_err(bus, "Failed to remap SDMA address\n"); 380 + return PTR_ERR(cdns_xspi->sdmabase); 381 + } 382 + cdns_xspi->sdmasize = resource_size(&res); 383 + 384 + ret = dev_read_resource_byname(bus, "aux", &res); 385 + if (ret) 386 + return ret; 387 + 388 + cdns_xspi->auxbase = devm_ioremap(bus, res.start, resource_size(&res)); 389 + 390 + if (IS_ERR(cdns_xspi->auxbase)) { 391 + dev_err(bus, "Failed to remap AUX address\n"); 392 + return PTR_ERR(cdns_xspi->auxbase); 393 + } 394 + 395 + cdns_xspi_print_phy_config(cdns_xspi); 396 + 397 + ret = cdns_xspi_controller_init(cdns_xspi); 398 + 399 + if (ret) { 400 + dev_err(bus, "Failed to initialize controller\n"); 401 + return ret; 402 + } 403 + 404 + return 0; 405 + } 406 + 407 + static int cdns_xspi_remove(struct udevice *dev) 408 + { 409 + struct cdns_xspi_plat *plat = dev_get_plat(dev); 410 + int ret = 0; 411 + 412 + if (plat->resets) 413 + ret = reset_release_bulk(plat->resets); 414 + 415 + return ret; 416 + } 417 + 418 + static int cadence_spi_set_speed(struct udevice *bus, uint hz) 419 + { 420 + return 0; 421 + } 422 + 423 + static int cadence_spi_set_mode(struct udevice *bus, uint mode) 424 + { 425 + return 0; 426 + } 427 + 428 + static const struct dm_spi_ops cdns_xspi_ops = { 429 + .set_speed = cadence_spi_set_speed, 430 + .set_mode = cadence_spi_set_mode, 431 + .mem_ops = &cadence_xspi_mem_ops, 432 + }; 433 + 434 + static const struct udevice_id cdns_xspi_of_match[] = { 435 + { 436 + .compatible = "cdns,xspi-nor", 437 + }, 438 + {/* end of table */} 439 + }; 440 + 441 + U_BOOT_DRIVER(cadence_xspi) = { 442 + .name = CDNS_XSPI_NAME, 443 + .id = UCLASS_SPI, 444 + .of_match = cdns_xspi_of_match, 445 + .ops = &cdns_xspi_ops, 446 + .probe = cdns_xspi_probe, 447 + .remove = cdns_xspi_remove, 448 + .flags = DM_FLAG_OS_PREPARE, 449 + };
+226
drivers/spi/cadence_xspi.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0+ */ 2 + /* 3 + * Copyright (C) 2025 4 + * Altera Corporation <www.altera.com> 5 + */ 6 + 7 + #ifndef __CADENCE_XSPI_H__ 8 + #define __CADENCE_XSPI_H__ 9 + 10 + #include <spi-mem.h> 11 + #include <reset.h> 12 + #include <linux/mtd/spi-nor.h> 13 + #include <linux/bitfield.h> 14 + #include <linux/log2.h> 15 + 16 + #define CDNS_XSPI_MAGIC_NUM_VALUE 0x6522 17 + #define CDNS_XSPI_MAX_BANKS 8 18 + #define CDNS_XSPI_NAME "cadence_xspi" 19 + 20 + /* 21 + * Note: below are additional auxiliary registers to 22 + * configure XSPI controller pin-strap settings 23 + */ 24 + 25 + /* PHY DQ timing register */ 26 + #define CDNS_XSPI_CCP_PHY_DQ_TIMING 0x0000 27 + 28 + /* PHY DQS timing register */ 29 + #define CDNS_XSPI_CCP_PHY_DQS_TIMING 0x0004 30 + 31 + /* PHY gate loopback control register */ 32 + #define CDNS_XSPI_CCP_PHY_GATE_LPBCK_CTRL 0x0008 33 + 34 + /* PHY DLL slave control register */ 35 + #define CDNS_XSPI_CCP_PHY_DLL_SLAVE_CTRL 0x0010 36 + 37 + /* DLL PHY control register */ 38 + #define CDNS_XSPI_DLL_PHY_CTRL 0x1034 39 + 40 + /* Command registers */ 41 + #define CDNS_XSPI_CMD_REG_0 0x0000 42 + #define CDNS_XSPI_CMD_REG_1 0x0004 43 + #define CDNS_XSPI_CMD_REG_2 0x0008 44 + #define CDNS_XSPI_CMD_REG_3 0x000C 45 + #define CDNS_XSPI_CMD_REG_4 0x0010 46 + #define CDNS_XSPI_CMD_REG_5 0x0014 47 + 48 + /* Command status registers */ 49 + #define CDNS_XSPI_CMD_STATUS_REG 0x0044 50 + 51 + /* Controller status register */ 52 + #define CDNS_XSPI_CTRL_STATUS_REG 0x0100 53 + #define CDNS_XSPI_INIT_COMPLETED BIT(16) 54 + #define CDNS_XSPI_INIT_LEGACY BIT(9) 55 + #define CDNS_XSPI_INIT_FAIL BIT(8) 56 + #define CDNS_XSPI_CTRL_BUSY BIT(7) 57 + 58 + /* Controller interrupt status register */ 59 + #define CDNS_XSPI_INTR_STATUS_REG 0x0110 60 + #define CDNS_XSPI_STIG_DONE BIT(23) 61 + #define CDNS_XSPI_SDMA_ERROR BIT(22) 62 + #define CDNS_XSPI_SDMA_TRIGGER BIT(21) 63 + #define CDNS_XSPI_CMD_IGNRD_EN BIT(20) 64 + #define CDNS_XSPI_DDMA_TERR_EN BIT(18) 65 + #define CDNS_XSPI_CDMA_TREE_EN BIT(17) 66 + #define CDNS_XSPI_CTRL_IDLE_EN BIT(16) 67 + 68 + #define CDNS_XSPI_TRD_COMP_INTR_STATUS 0x0120 69 + #define CDNS_XSPI_TRD_ERR_INTR_STATUS 0x0130 70 + #define CDNS_XSPI_TRD_ERR_INTR_EN 0x0134 71 + 72 + /* Controller interrupt enable register */ 73 + #define CDNS_XSPI_INTR_ENABLE_REG 0x0114 74 + #define CDNS_XSPI_INTR_EN BIT(31) 75 + #define CDNS_XSPI_STIG_DONE_EN BIT(23) 76 + #define CDNS_XSPI_SDMA_ERROR_EN BIT(22) 77 + #define CDNS_XSPI_SDMA_TRIGGER_EN BIT(21) 78 + 79 + #define CDNS_XSPI_INTR_MASK (CDNS_XSPI_INTR_EN | \ 80 + CDNS_XSPI_STIG_DONE_EN | \ 81 + CDNS_XSPI_SDMA_ERROR_EN | \ 82 + CDNS_XSPI_SDMA_TRIGGER_EN) 83 + 84 + /* Controller config register */ 85 + #define CDNS_XSPI_CTRL_CONFIG_REG 0x0230 86 + #define CDNS_XSPI_CTRL_WORK_MODE GENMASK(6, 5) 87 + 88 + #define CDNS_XSPI_WORK_MODE_DIRECT 0 89 + #define CDNS_XSPI_WORK_MODE_STIG 1 90 + #define CDNS_XSPI_WORK_MODE_ACMD 3 91 + 92 + /* SDMA trigger transaction registers */ 93 + #define CDNS_XSPI_SDMA_SIZE_REG 0x0240 94 + #define CDNS_XSPI_SDMA_TRD_INFO_REG 0x0244 95 + #define CDNS_XSPI_SDMA_DIR BIT(8) 96 + 97 + /* Controller features register */ 98 + #define CDNS_XSPI_CTRL_FEATURES_REG 0x0F04 99 + #define CDNS_XSPI_NUM_BANKS GENMASK(25, 24) 100 + #define CDNS_XSPI_DMA_DATA_WIDTH BIT(21) 101 + #define CDNS_XSPI_NUM_THREADS GENMASK(3, 0) 102 + 103 + /* Controller version register */ 104 + #define CDNS_XSPI_CTRL_VERSION_REG 0x0F00 105 + #define CDNS_XSPI_MAGIC_NUM GENMASK(31, 16) 106 + #define CDNS_XSPI_CTRL_REV GENMASK(7, 0) 107 + 108 + /* STIG Profile 1.0 instruction fields (split into registers) */ 109 + #define CDNS_XSPI_CMD_INSTR_TYPE GENMASK(6, 0) 110 + #define CDNS_XSPI_CMD_P1_R1_ADDR0 GENMASK(31, 24) 111 + #define CDNS_XSPI_CMD_P1_R2_ADDR1 GENMASK(7, 0) 112 + #define CDNS_XSPI_CMD_P1_R2_ADDR2 GENMASK(15, 8) 113 + #define CDNS_XSPI_CMD_P1_R2_ADDR3 GENMASK(23, 16) 114 + #define CDNS_XSPI_CMD_P1_R2_ADDR4 GENMASK(31, 24) 115 + #define CDNS_XSPI_CMD_P1_R3_ADDR5 GENMASK(7, 0) 116 + #define CDNS_XSPI_CMD_P1_R3_CMD GENMASK(23, 16) 117 + #define CDNS_XSPI_CMD_P1_R3_NUM_ADDR_BYTES GENMASK(30, 28) 118 + #define CDNS_XSPI_CMD_P1_R4_ADDR_IOS GENMASK(1, 0) 119 + #define CDNS_XSPI_CMD_P1_R4_CMD_IOS GENMASK(9, 8) 120 + #define CDNS_XSPI_CMD_P1_R4_BANK GENMASK(14, 12) 121 + 122 + /* STIG data sequence instruction fields (split into registers) */ 123 + #define CDNS_XSPI_CMD_DSEQ_R2_DCNT_L GENMASK(31, 16) 124 + #define CDNS_XSPI_CMD_DSEQ_R3_DCNT_H GENMASK(15, 0) 125 + #define CDNS_XSPI_CMD_DSEQ_R3_NUM_OF_DUMMY GENMASK(25, 20) 126 + #define CDNS_XSPI_CMD_DSEQ_R4_BANK GENMASK(14, 12) 127 + #define CDNS_XSPI_CMD_DSEQ_R4_DATA_IOS GENMASK(9, 8) 128 + #define CDNS_XSPI_CMD_DSEQ_R4_DIR BIT(4) 129 + 130 + /* STIG command status fields */ 131 + #define CDNS_XSPI_CMD_STATUS_COMPLETED BIT(15) 132 + #define CDNS_XSPI_CMD_STATUS_FAILED BIT(14) 133 + #define CDNS_XSPI_CMD_STATUS_DQS_ERROR BIT(3) 134 + #define CDNS_XSPI_CMD_STATUS_CRC_ERROR BIT(2) 135 + #define CDNS_XSPI_CMD_STATUS_BUS_ERROR BIT(1) 136 + #define CDNS_XSPI_CMD_STATUS_INV_SEQ_ERROR BIT(0) 137 + 138 + #define CDNS_XSPI_STIG_DONE_FLAG BIT(0) 139 + #define CDNS_XSPI_TRD_STATUS 0x0104 140 + 141 + #define MODE_NO_OF_BYTES GENMASK(25, 24) 142 + #define MODEBYTES_COUNT 1 143 + 144 + /* Helper macros for filling command registers */ 145 + #define CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_1(op, data_phase) ( \ 146 + FIELD_PREP(CDNS_XSPI_CMD_INSTR_TYPE, (data_phase) ? \ 147 + CDNS_XSPI_STIG_INSTR_TYPE_1 : CDNS_XSPI_STIG_INSTR_TYPE_0) | \ 148 + FIELD_PREP(CDNS_XSPI_CMD_P1_R1_ADDR0, (op)->addr.val & 0xff)) 149 + 150 + #define CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_2(op) ( \ 151 + FIELD_PREP(CDNS_XSPI_CMD_P1_R2_ADDR1, ((op)->addr.val >> 8) & 0xFF) | \ 152 + FIELD_PREP(CDNS_XSPI_CMD_P1_R2_ADDR2, ((op)->addr.val >> 16) & 0xFF) | \ 153 + FIELD_PREP(CDNS_XSPI_CMD_P1_R2_ADDR3, ((op)->addr.val >> 24) & 0xFF) | \ 154 + FIELD_PREP(CDNS_XSPI_CMD_P1_R2_ADDR4, ((op)->addr.val >> 32) & 0xFF)) 155 + 156 + #define CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_3(op, modebytes) ( \ 157 + FIELD_PREP(CDNS_XSPI_CMD_P1_R3_ADDR5, ((op)->addr.val >> 40) & 0xFF) | \ 158 + FIELD_PREP(CDNS_XSPI_CMD_P1_R3_CMD, (op)->cmd.opcode) | \ 159 + FIELD_PREP(MODE_NO_OF_BYTES, modebytes) | \ 160 + FIELD_PREP(CDNS_XSPI_CMD_P1_R3_NUM_ADDR_BYTES, (op)->addr.nbytes)) 161 + 162 + #define CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_4(op, chipsel) ( \ 163 + FIELD_PREP(CDNS_XSPI_CMD_P1_R4_ADDR_IOS, ilog2((op)->addr.buswidth)) | \ 164 + FIELD_PREP(CDNS_XSPI_CMD_P1_R4_CMD_IOS, ilog2((op)->cmd.buswidth)) | \ 165 + FIELD_PREP(CDNS_XSPI_CMD_P1_R4_BANK, chipsel)) 166 + 167 + #define CDNS_XSPI_CMD_FLD_DSEQ_CMD_1 \ 168 + FIELD_PREP(CDNS_XSPI_CMD_INSTR_TYPE, CDNS_XSPI_STIG_INSTR_TYPE_DATA_SEQ) 169 + 170 + #define CDNS_XSPI_CMD_FLD_DSEQ_CMD_2(op) \ 171 + FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R2_DCNT_L, (op)->data.nbytes & 0xFFFF) 172 + 173 + #define CDNS_XSPI_CMD_FLD_DSEQ_CMD_3(op, dummybytes) ( \ 174 + FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R3_DCNT_H, \ 175 + ((op)->data.nbytes >> 16) & 0xffff) | \ 176 + FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R3_NUM_OF_DUMMY, \ 177 + (op)->dummy.buswidth != 0 ? \ 178 + (((dummybytes) * 8) / (op)->dummy.buswidth) : \ 179 + 0)) 180 + 181 + #define CDNS_XSPI_CMD_FLD_DSEQ_CMD_4(op, chipsel) ( \ 182 + FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R4_BANK, chipsel) | \ 183 + FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R4_DATA_IOS, \ 184 + ilog2((op)->data.buswidth)) | \ 185 + FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R4_DIR, \ 186 + ((op)->data.dir == SPI_MEM_DATA_IN) ? \ 187 + CDNS_XSPI_STIG_CMD_DIR_READ : CDNS_XSPI_STIG_CMD_DIR_WRITE)) 188 + 189 + enum cdns_xspi_stig_instr_type { 190 + CDNS_XSPI_STIG_INSTR_TYPE_0, 191 + CDNS_XSPI_STIG_INSTR_TYPE_1, 192 + CDNS_XSPI_STIG_INSTR_TYPE_DATA_SEQ = 127, 193 + }; 194 + 195 + enum cdns_xspi_sdma_dir { 196 + CDNS_XSPI_SDMA_DIR_READ, 197 + CDNS_XSPI_SDMA_DIR_WRITE, 198 + }; 199 + 200 + enum cdns_xspi_stig_cmd_dir { 201 + CDNS_XSPI_STIG_CMD_DIR_READ, 202 + CDNS_XSPI_STIG_CMD_DIR_WRITE, 203 + }; 204 + 205 + struct cdns_xspi_plat { 206 + struct device *dev; 207 + struct reset_ctl_bulk *resets; 208 + 209 + void __iomem *iobase; 210 + void __iomem *auxbase; 211 + void __iomem *sdmabase; 212 + 213 + int cur_cs; 214 + unsigned int sdmasize; 215 + bool sdma_error; 216 + 217 + void *in_buffer; 218 + const void *out_buffer; 219 + 220 + u8 hw_num_banks; 221 + 222 + void (*sdma_handler)(struct cdns_xspi_plat *cdns_xspi); 223 + void (*set_interrupts_handler)(struct cdns_xspi_plat *cdns_xspi, bool enabled); 224 + }; 225 + 226 + #endif /* __CADENCE_XSPI_H__ */
+1
drivers/usb/host/Kconfig
··· 271 271 272 272 config USB_EHCI_PCI 273 273 bool "Support for PCI-based EHCI USB controller" 274 + depends on PCI 274 275 default y if X86 275 276 help 276 277 Enables support for the PCI-based EHCI controller.
+1 -1
drivers/usb/host/xhci.c
··· 1249 1249 1250 1250 reg = xhci_readl(&hccr->cr_hcsparams1); 1251 1251 ctrl->hub_desc.bNbrPorts = HCS_MAX_PORTS(reg); 1252 - printf("Register %x NbrPorts %d\n", reg, ctrl->hub_desc.bNbrPorts); 1252 + debug("Register %x NbrPorts %d\n", reg, ctrl->hub_desc.bNbrPorts); 1253 1253 1254 1254 /* Port Indicators */ 1255 1255 reg = xhci_readl(&hccr->cr_hccparams);
+14
include/configs/exynos-mobile.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * Samsung Exynos Generic Board Configuration (for mobile devices) 4 + * 5 + * Copyright (C) 2025 Kaustabh Chakraborty <kauschluss@disroot.org> 6 + */ 7 + 8 + #ifndef __CONFIG_EXYNOS_MOBILE_H 9 + #define __CONFIG_EXYNOS_MOBILE_H 10 + 11 + #define CPU_RELEASE_ADDR secondary_boot_addr 12 + #define CFG_SYS_BAUDRATE_TABLE {9600, 115200} 13 + 14 + #endif /* __CONFIG_EXYNOS_MOBILE_H */
+11
include/configs/ironhide.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0-only */ 2 + /* 3 + * Copyright (C) 2025 Renesas Electronics Corp. 4 + */ 5 + 6 + #ifndef __IRONHIDE_H 7 + #define __IRONHIDE_H 8 + 9 + #include "rcar-gen5-common.h" 10 + 11 + #endif /* __IRONHIDE_H */
+24
include/configs/rcar-gen5-common.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0-only */ 2 + /* 3 + * Copyright (C) 2025 Renesas Electronics Corporation 4 + */ 5 + 6 + #ifndef __RCAR_GEN5_COMMON_H 7 + #define __RCAR_GEN5_COMMON_H 8 + 9 + #include <asm/arch/renesas.h> 10 + 11 + /* Console */ 12 + #define CFG_SYS_BAUDRATE_TABLE { 38400, 115200, 921600, 1843200, 3250000 } 13 + 14 + /* Memory */ 15 + #define DRAM_RSV_SIZE 0x08000000 16 + #define CFG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE) 17 + #define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE) 18 + #define CFG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE) 19 + 20 + /* Environment setting */ 21 + #define CFG_EXTRA_ENV_SETTINGS \ 22 + "bootm_size=0x10000000\0" 23 + 24 + #endif /* __RCAR_GEN5_COMMON_H */
-1
include/configs/s5p4418_nanopi2.h
··· 139 139 #endif 140 140 141 141 #define CFG_EXTRA_ENV_SETTINGS \ 142 - "fdt_high=0xffffffff\0" \ 143 142 "initrd_high=0xffffffff\0" \ 144 143 "rootdev=" __stringify(CONFIG_ROOT_DEV) "\0" \ 145 144 "rootpart=" __stringify(CONFIG_ROOT_PART) "\0" \
-1
include/configs/socfpga_vining_fpga.h
··· 40 40 "hostname=vining_fpga\0" \ 41 41 "kernel_addr_r=0x10000000\0" \ 42 42 "fdt_addr_r=0x20000000\0" \ 43 - "fdt_high=0xffffffff\0" \ 44 43 "initrd_high=0xffffffff\0" \ 45 44 "dfu_alt_info=qspi0 sf 0:0;qspi1 sf 0:1\0" \ 46 45 "mtdparts_0_16m=ff705000.spi.0:" /* 16MiB+128MiB SF config */ \
+46
include/dt-bindings/clock/r8a78000-clock-scmi.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (C) 2025 Renesas Electronics Corp. 4 + * 5 + * IDs match SCP 4.27 6 + */ 7 + 8 + #ifndef __DT_BINDINGS_R8A78000_SCMI_CLOCK_H__ 9 + #define __DT_BINDINGS_R8A78000_SCMI_CLOCK_H__ 10 + 11 + /* 12 + * These definition indices match the Clock ID defined by SCP FW 4.27. 13 + */ 14 + 15 + #define SCP_CLOCK_ID_MDLC_UFS0 202 16 + #define SCP_CLOCK_ID_MDLC_UFS1 203 17 + #define SCP_CLOCK_ID_MDLC_SDHI0 204 18 + 19 + #define SCP_CLOCK_ID_MDLC_XPCS0 316 20 + #define SCP_CLOCK_ID_MDLC_XPCS1 317 21 + #define SCP_CLOCK_ID_MDLC_XPCS2 318 22 + #define SCP_CLOCK_ID_MDLC_XPCS3 319 23 + #define SCP_CLOCK_ID_MDLC_XPCS4 320 24 + #define SCP_CLOCK_ID_MDLC_XPCS5 321 25 + #define SCP_CLOCK_ID_MDLC_XPCS6 322 26 + #define SCP_CLOCK_ID_MDLC_XPCS7 323 27 + #define SCP_CLOCK_ID_MDLC_RSW3 324 28 + #define SCP_CLOCK_ID_MDLC_RSW3TSN 325 29 + #define SCP_CLOCK_ID_MDLC_RSW3AES 326 30 + #define SCP_CLOCK_ID_MDLC_RSW3TSNTES0 327 31 + #define SCP_CLOCK_ID_MDLC_RSW3TSNTES1 328 32 + #define SCP_CLOCK_ID_MDLC_RSW3TSNTES2 329 33 + #define SCP_CLOCK_ID_MDLC_RSW3TSNTES3 330 34 + #define SCP_CLOCK_ID_MDLC_RSW3TSNTES4 331 35 + #define SCP_CLOCK_ID_MDLC_RSW3TSNTES5 332 36 + #define SCP_CLOCK_ID_MDLC_RSW3TSNTES6 333 37 + #define SCP_CLOCK_ID_MDLC_RSW3TSNTES7 334 38 + #define SCP_CLOCK_ID_MDLC_RSW3MFWD 335 39 + 40 + #define SCP_CLOCK_ID_MDLC_MPPHY01 344 41 + #define SCP_CLOCK_ID_MDLC_MPPHY11 345 42 + #define SCP_CLOCK_ID_MDLC_MPPHY21 346 43 + #define SCP_CLOCK_ID_MDLC_MPPHY31 347 44 + #define SCP_CLOCK_ID_MDLC_MPPHY02 348 45 + 46 + #endif /* __DT_BINDINGS_R8A78000_SCMI_CLOCK_H__ */
+25
include/dt-bindings/power/r8a78000-power-scmi.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (C) 2025 Renesas Electronics Corp. 4 + * 5 + * IDs match SCP 4.27 6 + */ 7 + 8 + #ifndef __DT_BINDINGS_R8A78000_SCMI_POWER_H__ 9 + #define __DT_BINDINGS_R8A78000_SCMI_POWER_H__ 10 + 11 + /* 12 + * These power domain indices match the Power Domain ID defined by SCP FW 4.27. 13 + */ 14 + 15 + #define X5H_POWER_DOMAIN_ID_UFS0 12 16 + #define X5H_POWER_DOMAIN_ID_UFS1 13 17 + 18 + #define X5H_POWER_DOMAIN_ID_RSW 15 19 + 20 + #define X5H_POWER_DOMAIN_ID_MPP0 17 21 + #define X5H_POWER_DOMAIN_ID_MPP1 18 22 + #define X5H_POWER_DOMAIN_ID_MPP2 19 23 + #define X5H_POWER_DOMAIN_ID_MPP3 20 24 + 25 + #endif /* __DT_BINDINGS_R8A78000_SCMI_POWER_H__ */
+33
include/dt-bindings/reset/r8a78000-reset-scmi.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (C) 2025 Renesas Electronics Corp. 4 + * 5 + * IDs match SCP 4.27 6 + */ 7 + 8 + #ifndef __DT_BINDINGS_R8A78000_SCMI_RESET_H__ 9 + #define __DT_BINDINGS_R8A78000_SCMI_RESET_H__ 10 + 11 + /* 12 + * These definition indices match the Reset ID defined by SCP FW 4.27. 13 + */ 14 + 15 + #define SCP_RESET_DOMAIN_ID_UFS0 202 16 + #define SCP_RESET_DOMAIN_ID_UFS1 203 17 + 18 + #define SCP_RESET_DOMAIN_ID_XPCS0 316 19 + #define SCP_RESET_DOMAIN_ID_XPCS1 317 20 + #define SCP_RESET_DOMAIN_ID_XPCS2 318 21 + #define SCP_RESET_DOMAIN_ID_XPCS3 319 22 + #define SCP_RESET_DOMAIN_ID_XPCS4 320 23 + #define SCP_RESET_DOMAIN_ID_XPCS5 321 24 + #define SCP_RESET_DOMAIN_ID_XPCS6 322 25 + #define SCP_RESET_DOMAIN_ID_XPCS7 323 26 + 27 + #define SCP_RESET_DOMAIN_ID_MPPHY01 344 28 + #define SCP_RESET_DOMAIN_ID_MPPHY11 345 29 + #define SCP_RESET_DOMAIN_ID_MPPHY21 346 30 + #define SCP_RESET_DOMAIN_ID_MPPHY31 347 31 + #define SCP_RESET_DOMAIN_ID_MPPHY02 348 32 + 33 + #endif /* __DT_BINDINGS_R8A78000_SCMI_RESET_H__ */
+1 -1
include/env/adi/adi_boot.env
··· 39 39 /* Boot modes are selectable and should be defined in the board env before including */ 40 40 #if defined(USE_NFS) 41 41 // rootpath is set by CONFIG_ROOTPATH 42 - nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}${rootpath},tcp,nfsvers=3 ${adi_bootargs} 42 + nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath},tcp,nfsvers=3 ${adi_bootargs} 43 43 nfsboot=run init_ethernet; 44 44 tftp ${loadaddr} ${tftp_dir_prefix}${imagefile}; 45 45 run nfsargs;
+7 -27
lib/efi_loader/efi_capsule.c
··· 857 857 struct efi_device_path *file_dp; 858 858 efi_status_t ret; 859 859 860 - size = 0; 861 - ret = efi_get_variable_int(boot_var, &efi_global_variable_guid, 862 - NULL, &size, NULL, NULL); 863 - if (ret == EFI_BUFFER_TOO_SMALL) { 864 - buf = malloc(size); 865 - if (!buf) 866 - return EFI_OUT_OF_RESOURCES; 867 - ret = efi_get_variable_int(boot_var, &efi_global_variable_guid, 868 - NULL, &size, buf, NULL); 869 - } 870 - if (ret != EFI_SUCCESS) 871 - return ret; 860 + buf = efi_get_var(boot_var, &efi_global_variable_guid, &size); 861 + if (!buf) 862 + return EFI_NOT_FOUND; 872 863 873 864 efi_deserialize_load_option(&lo, buf, &size); 874 865 ··· 960 951 961 952 skip: 962 953 /* find active boot device in BootOrder */ 963 - size = 0; 964 - ret = efi_get_variable_int(u"BootOrder", &efi_global_variable_guid, 965 - NULL, &size, NULL, NULL); 966 - if (ret == EFI_BUFFER_TOO_SMALL) { 967 - boot_order = malloc(size); 968 - if (!boot_order) { 969 - ret = EFI_OUT_OF_RESOURCES; 970 - goto out; 971 - } 972 - 973 - ret = efi_get_variable_int(u"BootOrder", 974 - &efi_global_variable_guid, 975 - NULL, &size, boot_order, NULL); 954 + boot_order = efi_get_var(u"BootOrder", &efi_global_variable_guid, &size); 955 + if (!boot_order) { 956 + ret = EFI_NOT_FOUND; 957 + goto out; 976 958 } 977 - if (ret != EFI_SUCCESS) 978 - goto out; 979 959 980 960 /* check in higher order */ 981 961 num = size / sizeof(u16);
+9
test/cmd/fdt.c
··· 1274 1274 char fdt[8192]; 1275 1275 struct udevice *dev; 1276 1276 ulong addr; 1277 + ulong smbiosaddr = gd_smbios_start(); 1277 1278 1278 1279 ut_assertok(make_test_fdt(uts, fdt, sizeof(fdt), &addr)); 1279 1280 fdt_shrink_to_minimum(fdt, 4096); /* Resize with 4096 extra bytes */ ··· 1292 1293 ut_assert(0 < console_record_readline(uts->actual_str, 1293 1294 sizeof(uts->actual_str))); 1294 1295 ut_asserteq_str("chosen {", uts->actual_str); 1296 + if (CONFIG_IS_ENABLED(GENERATE_SMBIOS_TABLE)) 1297 + ut_assert_nextline("\tsmbios3-entrypoint = <0x%08x 0x%08x>;", 1298 + upper_32_bits(smbiosaddr), 1299 + lower_32_bits(smbiosaddr)); 1295 1300 ut_assert_nextlinen("\tu-boot,version = "); /* Ignore the version string */ 1296 1301 if (env_bootargs) 1297 1302 ut_assert_nextline("\tbootargs = \"%s\";", env_bootargs); ··· 1316 1321 lower_32_bits(0x1234 + 0x5678 - 1)); 1317 1322 ut_assert_nextline("\tlinux,initrd-start = <0x%08x 0x%08x>;", 1318 1323 upper_32_bits(0x1234), lower_32_bits(0x1234)); 1324 + if (CONFIG_IS_ENABLED(GENERATE_SMBIOS_TABLE)) 1325 + ut_assert_nextline("\tsmbios3-entrypoint = <0x%08x 0x%08x>;", 1326 + upper_32_bits(smbiosaddr), 1327 + lower_32_bits(smbiosaddr)); 1319 1328 ut_assert_nextlinen("\tu-boot,version = "); /* Ignore the version string */ 1320 1329 if (env_bootargs) 1321 1330 ut_assert_nextline("\tbootargs = \"%s\";", env_bootargs);
+48
test/dm/fdtdec.c
··· 7 7 #include <asm/global_data.h> 8 8 #include <dm/of_extra.h> 9 9 #include <dm/test.h> 10 + #include <fdt_support.h> 11 + #include <mapmem.h> 12 + #include <smbios.h> 10 13 #include <test/ut.h> 11 14 12 15 DECLARE_GLOBAL_DATA_PTR; ··· 129 132 } 130 133 DM_TEST(dm_test_fdtdec_add_reserved_memory, 131 134 UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_FLAT_TREE); 135 + 136 + static int dm_test_fdt_chosen_smbios(struct unit_test_state *uts) 137 + { 138 + void *blob; 139 + ulong val; 140 + struct smbios3_entry *entry; 141 + int chosen, blob_sz; 142 + const fdt64_t *prop; 143 + 144 + if (!CONFIG_IS_ENABLED(GENERATE_SMBIOS_TABLE)) { 145 + return -EAGAIN; 146 + } 147 + 148 + blob_sz = fdt_totalsize(gd->fdt_blob) + 4096; 149 + blob = memalign(8, blob_sz); 150 + ut_assertnonnull(blob); 151 + 152 + /* Make a writable copy of the fdt blob */ 153 + ut_assertok(fdt_open_into(gd->fdt_blob, blob, blob_sz)); 154 + 155 + /* Mock SMBIOS table */ 156 + entry = map_sysmem(gd->arch.smbios_start, sizeof(struct smbios3_entry)); 157 + memcpy(entry->anchor, "_SM3_", 5); 158 + entry->length = sizeof(struct smbios3_entry); 159 + unmap_sysmem(entry); 160 + 161 + /* Force fdt_chosen to run */ 162 + ut_assertok(fdt_chosen(blob)); 163 + 164 + chosen = fdt_path_offset(blob, "/chosen"); 165 + ut_assert(chosen >= 0); 166 + 167 + /* Verify the property exists */ 168 + prop = fdt_getprop(blob, chosen, "smbios3-entrypoint", NULL); 169 + ut_assertnonnull(prop); 170 + 171 + /* Verify the property matches smbios_start */ 172 + val = fdt64_to_cpu(*prop); 173 + ut_asserteq_64(gd->arch.smbios_start, val); 174 + 175 + free(blob); 176 + 177 + return 0; 178 + } 179 + DM_TEST(dm_test_fdt_chosen_smbios, UTF_SCAN_PDATA | UTF_SCAN_FDT);
+1 -1
test/lib/strlcat.c
··· 1 - // SPDX-License-Identifier: GPL-2.1+ 1 + // SPDX-License-Identifier: GPL-2.0+ 2 2 /* 3 3 * Copyright (C) 2021 Sean Anderson <seanga2@gmail.com> 4 4 * Copyright (C) 2011-2021 Free Software Foundation, Inc.
+3 -2
tools/binman/control.py
··· 9 9 import glob 10 10 try: 11 11 import importlib.resources as importlib_resources 12 - except ImportError: # pragma: no cover 13 - # for Python 3.6 12 + # for Python 3.6, 3.7 and 3.8 13 + importlib_resources.files 14 + except (ImportError, AttributeError): # pragma: no cover 14 15 import importlib_resources 15 16 import os 16 17 import re
+100
tools/cv_bsp_generator/cv_bsp_generator.py
··· 1 + #! /usr/bin/env python 2 + # SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 3 + """ 4 + Bsp preloader header file generator 5 + 6 + Process the handoff files from Quartus and convert them to headers 7 + usable by U-Boot. Includes the qts filter.sh capability to generate 8 + correct format for headers to be used for mainline Uboot on FPGA, 9 + namely Cyclone V & Arria V. 10 + 11 + Copyright (C) 2022 Intel Corporation <www.intel.com> 12 + 13 + Author: Lee, Kah Jing <kah.jing.lee@intel.com> 14 + """ 15 + import glob 16 + import optparse 17 + import os 18 + import shutil 19 + import emif 20 + import hps 21 + import iocsr 22 + import renderer 23 + import model 24 + import collections 25 + import sys 26 + 27 + def printUsage(): 28 + """ usage string """ 29 + print ("Usage:\n\t%s\n" % ("sys.argv[0], --input_dir=<path to iswinfo directory> --output_dir=<path store output files>")) 30 + exit(1) 31 + 32 + def verifyInputDir(dir): 33 + """ check if the input directory exists """ 34 + if not os.path.isdir(dir): 35 + print ("There is no such directory '%s'!\n" % (dir)) 36 + exit(1) 37 + 38 + def verifyOutputDir(dir): 39 + """ check if the output directory exists """ 40 + if not os.path.isdir(dir): 41 + os.makedirs(dir) 42 + 43 + if __name__ == '__main__': 44 + # Do some rudimentary command line processing until it is proven we need something 45 + # heavier, such as argparse (preferred, but 2.7+ only) or optparse 46 + 47 + inputDir = '.' 48 + outputDir = '.' 49 + 50 + progVersion = '%prog 1.0' 51 + progDesc = 'Generate board-specific files for the preloader' 52 + optParser = optparse.OptionParser(version=progVersion, description=progDesc) 53 + optParser.add_option('-i', '--input-dir', action='store', type='string', dest='inputDir', default='.', 54 + help='input-dir is usually the iswinfo directory') 55 + optParser.add_option('-o', '--output-dir', action='store', type='string', dest='outputDir', default='.', 56 + help='output-dir is usually the directory containing the preloader source') 57 + 58 + (options, args) = optParser.parse_args() 59 + 60 + for arg in args: 61 + print ("***WARNING: I don't understand '%s', so I am ignoring it\n" % (arg)) 62 + 63 + inputDir = options.inputDir 64 + verifyInputDir(inputDir) 65 + outputDir = options.outputDir 66 + 67 + verifyOutputDir(outputDir) 68 + 69 + emif = emif.EMIFGrokker(inputDir, outputDir, 'emif.xml') 70 + hps = hps.HPSGrokker(inputDir, outputDir) 71 + 72 + pllConfigH = outputDir + "/" + "pll_config.h" 73 + print ("Generating file: " + pllConfigH) 74 + hpsModel = model.hps.create(inputDir + "/" + "hps.xml") 75 + emifModel = model.emif.create(inputDir +"/" + "emif.xml") 76 + 77 + content=str(renderer.pll_config_h(hpsModel, emifModel)) 78 + f = open(pllConfigH, "w") 79 + f.write(content) 80 + f.close() 81 + 82 + # For all the .hiof files, make a iocsr_config.[h|c] 83 + # Only support single hiof file currently 84 + hiof_list = glob.glob(inputDir + os.sep + "*.hiof") 85 + if len(hiof_list) < 1: 86 + print ("***Error: No .hiof files found in input!") 87 + 88 + elif len(hiof_list) > 1: 89 + print ("***Error: We don't handle more than one .hiof file yet") 90 + print (" Only the last .hiof file in the list will be converted") 91 + print (" hiof files found:") 92 + for f in hiof_list: 93 + print (" " + f) 94 + 95 + for hiof_file_path in hiof_list: 96 + hiof_file = os.path.basename(hiof_file_path) 97 + # Avoid IOCSRGrokker having to parse hps.xml to determine 98 + # device family for output file name, instead we'll just 99 + # get it from HPSGrokker 100 + iocsr = iocsr.IOCSRGrokker(hps.getDeviceFamily(), inputDir, outputDir, hiof_file)
+243
tools/cv_bsp_generator/doc.py
··· 1 + # SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 + """ 3 + Generic document construction classes. 4 + 5 + These classes are templates for creating documents that are not bound 6 + to a specific usage or data model. 7 + 8 + Copyright (C) 2022 Intel Corporation <www.intel.com> 9 + 10 + Author: Lee, Kah Jing <kah.jing.lee@intel.com> 11 + """ 12 + 13 + class document(object): 14 + """ 15 + An abstract document class which does not dictate 16 + how a document should be constructed or manipulated. 17 + 18 + It's sole purpose is to describe the entire document 19 + in smaller units 20 + """ 21 + 22 + class entry(object): 23 + """ 24 + An entry is the smallest unit 25 + """ 26 + 27 + def __init__(self, parent): 28 + """ entry initialization """ 29 + if parent != None: 30 + parent.add(self) 31 + 32 + class block(entry): 33 + """ 34 + A block is the smallest collection unit 35 + consists of entries and blocks. 36 + """ 37 + 38 + def __init__(self, parent): 39 + """ block initialization """ 40 + super(document.block, self).__init__(parent) 41 + self.entries = [] 42 + 43 + def add(self, entry): 44 + """ add entry to block """ 45 + self.entries.append(entry) 46 + 47 + 48 + def __init__(self): 49 + """ document initialization """ 50 + self.entries = [] 51 + 52 + def add(self, entry): 53 + """ add entry to entry list """ 54 + self.entries.append(entry) 55 + 56 + 57 + class text(document): 58 + """ 59 + A simple text document implementation 60 + """ 61 + 62 + class string(document.entry): 63 + """ 64 + The smallest unit of a text file is a string 65 + """ 66 + 67 + def __init__(self, parent, stringString=None): 68 + """ string initialization """ 69 + super(text.string, self).__init__(parent) 70 + self.stringString = stringString 71 + 72 + def __str__(self): 73 + """ convert None to empty string """ 74 + if (self.stringString != None): 75 + return self.stringString 76 + else: 77 + return "" 78 + 79 + 80 + class line(string): 81 + """ 82 + A line is a string with EOL character 83 + """ 84 + 85 + def __str__(self): 86 + """ convert string with newline """ 87 + return super(text.line, self).__str__() + "\n" 88 + 89 + class block(document.block): 90 + """ 91 + A block of text which can be made up of 92 + strings or lines 93 + """ 94 + 95 + def __str__(self): 96 + """ concatenate strings or lines """ 97 + blockString = "" 98 + 99 + for entry in self.entries: 100 + blockString += str(entry) 101 + 102 + return blockString 103 + 104 + 105 + def __str__(self): 106 + """ concatenate strings or lines """ 107 + textString = "" 108 + 109 + for entry in self.entries: 110 + textString += str(entry) 111 + 112 + return textString 113 + 114 + 115 + class c_source(text): 116 + """ 117 + A simple C header document implementation 118 + """ 119 + 120 + class define(text.string): 121 + """ 122 + C header define 123 + """ 124 + 125 + def __init__(self, parent, id, token=None): 126 + """ c header constructor initialization """ 127 + super(c_source.define, self).__init__(parent, id) 128 + self.token = token 129 + 130 + def __str__(self): 131 + """ c header to strings """ 132 + defineString = "#define" + " " + super(c_source.define, self).__str__() 133 + 134 + if self.token != None: 135 + defineString += " " + self.token 136 + 137 + defineString += "\n" 138 + 139 + return defineString 140 + 141 + class comment_string(text.string): 142 + """ 143 + C header comment 144 + """ 145 + 146 + def __str__(self): 147 + """ c comment """ 148 + return "/*" + " " + super(c_source.comment_string, self).__str__() + " " + "*/" 149 + 150 + class comment_line(comment_string): 151 + """ 152 + C header comment with newline 153 + """ 154 + 155 + def __str__(self): 156 + """ c comment with newline """ 157 + return super(c_source.comment_line, self).__str__() + "\n" 158 + 159 + class block(text.block): 160 + """ 161 + A simple C block string implementation 162 + """ 163 + 164 + def __init__(self, parent, prologue=None, epilogue=None): 165 + """ ifdef block string implementation """ 166 + super(c_source.block, self).__init__(parent) 167 + 168 + self.prologue = None 169 + self.epilogue = None 170 + 171 + if prologue != None: 172 + self.prologue = prologue 173 + 174 + if epilogue != None: 175 + self.epilogue = epilogue 176 + 177 + def __str__(self): 178 + """ convert ifdef to string """ 179 + blockString = "" 180 + 181 + if self.prologue != None: 182 + blockString += str(self.prologue) 183 + 184 + blockString += super(c_source.block, self).__str__() 185 + 186 + if self.epilogue != None: 187 + blockString += str(self.epilogue) 188 + 189 + return blockString 190 + 191 + class comment_block(block): 192 + """ 193 + A simple C header block comment implementation 194 + """ 195 + 196 + def __init__(self, parent, comments): 197 + """ block comment initialization """ 198 + super(c_source.comment_block, self).__init__(parent, "/*\n", " */\n") 199 + for comment in comments.split("\n"): 200 + self.add(comment) 201 + 202 + def add(self, entry): 203 + """ add line to block comment """ 204 + super(c_source.block, self).add(" * " + entry + "\n") 205 + 206 + class ifndef_block(block): 207 + """ 208 + A simple C header ifndef implementation 209 + """ 210 + 211 + def __init__(self, parent, id): 212 + """ ifndef block initialization """ 213 + prologue = text.line(None, "#ifndef" + " " + id) 214 + epilogue = text.block(None) 215 + text.string(epilogue, "#endif") 216 + text.string(epilogue, " ") 217 + c_source.comment_line(epilogue, id) 218 + super(c_source.ifndef_block, self).__init__(parent, prologue, epilogue) 219 + 220 + 221 + class generated_c_source(c_source): 222 + """ 223 + Caller to generate c format files using the helper classes 224 + """ 225 + 226 + def __init__(self, filename): 227 + """ Generate c header file with license, copyright, comment, 228 + ifdef block 229 + """ 230 + super(generated_c_source, self).__init__() 231 + 232 + self.entries.append(c_source.comment_line(None, "SPDX-License-Identifier: BSD-3-Clause")) 233 + self.entries.append(c_source.comment_block(None, "Copyright (C) 2022 Intel Corporation <www.intel.com>")) 234 + self.entries.append(c_source.comment_block(None, "Altera SoCFPGA Clock and PLL configuration")) 235 + self.entries.append(text.line(None)) 236 + 237 + self.body = c_source.ifndef_block(None, filename) 238 + self.body.add(c_source.define(None, filename)) 239 + self.entries.append(self.body) 240 + 241 + def add(self, entry): 242 + """ add content to be written into c header file """ 243 + self.body.add(entry)
+424
tools/cv_bsp_generator/emif.py
··· 1 + # SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 + """ 3 + SDRAM header file generator 4 + 5 + Process the handoff files from Quartus and convert them to headers 6 + usable by U-Boot. 7 + 8 + Copyright (C) 2022 Intel Corporation <www.intel.com> 9 + 10 + Author: Lee, Kah Jing <kah.jing.lee@intel.com> 11 + """ 12 + 13 + import os 14 + import re 15 + import xml.dom.minidom 16 + import streamer 17 + import xmlgrok 18 + 19 + class EMIFGrokker(object): 20 + """ parse an emif.xml input and translate to various 21 + outputs 22 + """ 23 + SCRIPT_DIR = os.path.dirname(os.path.realpath(__file__)) 24 + TEMPLATE_DIR = os.path.dirname(SCRIPT_DIR) + '/src' 25 + SDRAM_FILE_HEADER = '/*\n' + ' * Altera SoCFPGA SDRAM configuration\n' + ' *\n' + ' */\n\n' 26 + SDRAM_SENTINEL = '__SOCFPGA_SDRAM_CONFIG_H__' 27 + SDRAM_MATCH = r'#define (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE|CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL|CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER|CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN|CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN|CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN|CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT|CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN|CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC|CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI|CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD|CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP|CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR|CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR|CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP|CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS|CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC|CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD|CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD|CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT|CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT|CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES|CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES|CFG_HPS_SDR_CTRLCFG_DRAMODT_READ|CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE|CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS|CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS|CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS|CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS|CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH|CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH|CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN|CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK|CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL|CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA|CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH|CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH|CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP|CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP|CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP|CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP|CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR|CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN|CFG_HPS_SDR_CTRLCFG_FPGAPORTRST|CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE|CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC|CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY|CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0|CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32|CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0|CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14|CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46|CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0|CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0|CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32|CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0|CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4|CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36|CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0|CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32|CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64|RW_MGR_ACTIVATE_0_AND_1|RW_MGR_ACTIVATE_0_AND_1_WAIT1|RW_MGR_ACTIVATE_0_AND_1_WAIT2|RW_MGR_ACTIVATE_1|RW_MGR_CLEAR_DQS_ENABLE|RW_MGR_EMR_OCD_ENABLE|RW_MGR_EMR|RW_MGR_EMR2|RW_MGR_EMR3|RW_MGR_GUARANTEED_READ|RW_MGR_GUARANTEED_READ_CONT|RW_MGR_GUARANTEED_WRITE|RW_MGR_GUARANTEED_WRITE_WAIT0|RW_MGR_GUARANTEED_WRITE_WAIT1|RW_MGR_GUARANTEED_WRITE_WAIT2|RW_MGR_GUARANTEED_WRITE_WAIT3|RW_MGR_IDLE|RW_MGR_IDLE_LOOP1|RW_MGR_IDLE_LOOP2|RW_MGR_INIT_RESET_0_CKE_0|RW_MGR_INIT_RESET_1_CKE_0|RW_MGR_INIT_CKE_0|RW_MGR_LFSR_WR_RD_BANK_0|RW_MGR_LFSR_WR_RD_BANK_0_DATA|RW_MGR_LFSR_WR_RD_BANK_0_DQS|RW_MGR_LFSR_WR_RD_BANK_0_NOP|RW_MGR_LFSR_WR_RD_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_BANK_0_WL_1|RW_MGR_LFSR_WR_RD_DM_BANK_0|RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA|RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS|RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP|RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1|RW_MGR_MR_CALIB|RW_MGR_MR_USER|RW_MGR_MR_DLL_RESET|RW_MGR_MRS0_DLL_RESET|RW_MGR_MRS0_DLL_RESET_MIRR|RW_MGR_MRS0_USER|RW_MGR_MRS0_USER_MIRR|RW_MGR_MRS1|RW_MGR_MRS1_MIRR|RW_MGR_MRS2|RW_MGR_MRS2_MIRR|RW_MGR_MRS3|RW_MGR_MRS3_MIRR|RW_MGR_NOP|RW_MGR_PRECHARGE_ALL|RW_MGR_READ_B2B|RW_MGR_READ_B2B_WAIT1|RW_MGR_READ_B2B_WAIT2|RW_MGR_REFRESH|RW_MGR_REFRESH_ALL|RW_MGR_RETURN|RW_MGR_SGLE_READ|RW_MGR_ZQCL|RW_MGR_TRUE_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_ADDRESS_MIRRORING|RW_MGR_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_DATA_WIDTH|RW_MGR_MEM_DQ_PER_READ_DQS|RW_MGR_MEM_DQ_PER_WRITE_DQS|RW_MGR_MEM_IF_READ_DQS_WIDTH|RW_MGR_MEM_IF_WRITE_DQS_WIDTH|RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM|RW_MGR_MEM_NUMBER_OF_RANKS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS|IO_DELAY_PER_DCHAIN_TAP|IO_DELAY_PER_DQS_EN_DCHAIN_TAP|IO_DELAY_PER_OPA_TAP|IO_DLL_CHAIN_LENGTH|IO_DQDQS_OUT_PHASE_MAX|IO_DQS_EN_DELAY_MAX|IO_DQS_EN_DELAY_OFFSET|IO_DQS_EN_PHASE_MAX|IO_DQS_IN_DELAY_MAX|IO_DQS_IN_RESERVE|IO_DQS_OUT_RESERVE|IO_IO_IN_DELAY_MAX|IO_IO_OUT1_DELAY_MAX|IO_IO_OUT2_DELAY_MAX|IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS|AFI_RATE_RATIO|AFI_CLK_FREQ|CALIB_LFIFO_OFFSET|CALIB_VFIFO_OFFSET|ENABLE_SUPER_QUICK_CALIBRATION|MAX_LATENCY_COUNT_WIDTH|READ_VALID_FIFO_SIZE|REG_FILE_INIT_SEQ_SIGNATURE|TINIT_CNTR0_VAL|TINIT_CNTR1_VAL|TINIT_CNTR2_VAL|TRESET_CNTR0_VAL|TRESET_CNTR1_VAL|TRESET_CNTR2_VAL|CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR|CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC|CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP)\s+' 28 + 29 + SDRAM_CONFIG_H_FILENAME = "sdram_config.h" 30 + 31 + sdramHTemplate = "" 32 + seqAutoTemplate = "" 33 + seqDefinesTemplate = "" 34 + seqAutoAcTemplate = "" 35 + seqAutoInstTemplate = "" 36 + seqAutoTemplateList = [] 37 + seqDefinesTemplateList = [] 38 + seqAutoAcTemplateList = [] 39 + seqAutoInstTemplateList = [] 40 + 41 + def __init__(self, inputDir, outputDir, emifFileName='emif.xml', hpsFileName='hps.xml'): 42 + """ EMIFGrokker initialization """ 43 + self.inputDir = inputDir 44 + self.outputDir = outputDir 45 + 46 + sdramDir = self.outputDir 47 + if not os.path.isdir(sdramDir): 48 + os.makedirs(sdramDir) 49 + 50 + self.emifFileName = inputDir + os.sep + emifFileName 51 + self.hpsFileName = inputDir + os.sep + hpsFileName 52 + self.emifDom = xml.dom.minidom.parse(self.emifFileName) 53 + self.hpsDom = xml.dom.minidom.parse(self.hpsFileName) 54 + self.sequencerDefinesStream = None 55 + self.seqAutoFileName = inputDir + os.sep + "sequencer_auto.h" 56 + self.seqDefinesFileName = inputDir + os.sep + "sequencer_defines.h" 57 + self.seqAutoACFileName = inputDir + os.sep + "sequencer_auto_ac_init.c" 58 + self.seqAutoInstFileName = inputDir + os.sep + "sequencer_auto_inst_init.c" 59 + 60 + self.createFilesFromEMIF() 61 + 62 + def openSeqFiles(self): 63 + """ files to retrieve values to written to sdram_config.h """ 64 + self.seq_auto_fd = open(self.seqAutoFileName, "r") 65 + self.seq_defines_fd = open(self.seqDefinesFileName, "r") 66 + self.seq_auto_ac_fd = open(self.seqAutoACFileName, "r") 67 + self.seq_auto_inst_fd = open(self.seqAutoInstFileName, "r") 68 + 69 + def closeSeqFiles(self): 70 + """ close files """ 71 + self.seq_auto_fd.close() 72 + self.seq_defines_fd.close() 73 + self.seq_auto_ac_fd.close() 74 + self.seq_auto_inst_fd.close() 75 + 76 + def processSeqAuto(self): 77 + """ process sequencer files to retrieve variable. Regex match is from 78 + qts-filter.sh 79 + """ 80 + # replace underscore & bracket in sequencer_auto.h define 81 + for line in self.seq_auto_fd.readlines(): 82 + if re.match(".*__RW_MGR_", line) and not re.match(".*ac_", line) and not re.match(".*CONTENT_", line): 83 + line = re.sub("__RW_MGR", "RW_MGR", line) 84 + if re.match(self.SDRAM_MATCH, line): 85 + self.seqAutoTemplateList.append(re.sub(r' (\w+)(\s+)(\d+)', r' \1\t\3', line)) 86 + self.seqAutoTemplateList.sort() 87 + self.seqAutoTemplate = ''.join([item for item in self.seqAutoTemplateList]) 88 + 89 + # replace underscore & bracket in sequencer_defines.h define 90 + for line in self.seq_defines_fd.readlines(): 91 + if re.match("^#define (\w+_)", line): 92 + line = re.sub("__", "", line) 93 + if re.match(self.SDRAM_MATCH, line): 94 + self.seqDefinesTemplateList.append(re.sub(r' (\w+)(\s+)(\d+)', r' \1\t\3', line)) 95 + self.seqDefinesTemplateList.sort() 96 + self.seqDefinesTemplate = ''.join([item for item in self.seqDefinesTemplateList]) 97 + 98 + arrayMatchStart = 0 99 + # replace const variable declaration in sequencer_auto_ac_init.c 100 + for line in self.seq_auto_ac_fd.readlines(): 101 + if re.match("^const.*\[", line) or arrayMatchStart: 102 + if arrayMatchStart == 0: 103 + line = line.strip() + " " 104 + arrayMatchStart = 1 105 + if re.match("};", line): 106 + arrayMatchStart = 0 107 + self.seqAutoAcTemplateList.append("};") 108 + continue 109 + line = re.sub("alt_u32", "u32", line) 110 + self.seqAutoAcTemplateList.append(re.sub("\[.*\]", "[]", line)) 111 + self.seqAutoAcTemplate = ''.join([item for item in self.seqAutoAcTemplateList]) 112 + 113 + arrayMatchStart = 0 114 + # replace const variable declaration in sequencer_auto_inst_init.c 115 + for line in self.seq_auto_inst_fd.readlines(): 116 + if re.match("^const.*\[", line) or arrayMatchStart: 117 + if arrayMatchStart == 0: 118 + line = line.strip() + " " 119 + arrayMatchStart = 1 120 + if re.match("};", line): 121 + arrayMatchStart = 0 122 + self.seqAutoInstTemplateList.append("};") 123 + continue 124 + line = re.sub("alt_u32", "u32", line) 125 + self.seqAutoInstTemplateList.append(re.sub("\[.*\]", "[]", line)) 126 + self.seqAutoInstTemplate = ''.join([item for item in self.seqAutoInstTemplateList]) 127 + 128 + def handleSettingNode(self, settingNode): 129 + """ create define string from variable name and value """ 130 + if settingNode.hasAttribute('name') and settingNode.hasAttribute('value'): 131 + name = settingNode.getAttribute('name') 132 + value = settingNode.getAttribute('value') 133 + self.sequencerDefinesStream.write("#define " + name + ' ' + '(' + value + ')' + '\n') 134 + 135 + def updateTemplate(self, name, value): 136 + """ update sdram template """ 137 + pattern = "${" + name + "}" 138 + self.sdramHTemplate = self.sdramHTemplate.replace(pattern, value) 139 + 140 + def handleEMIFControllerNode(self, node): 141 + """ retrieve values from emif.xml for controller node """ 142 + derivedNoDmPins = 0 143 + derivedCtrlWidth = 0 144 + derivedEccEn = 0 145 + derivedEccCorrEn = 0 146 + 147 + self.mem_if_rd_to_wr_turnaround_oct = 0 148 + 149 + node = xmlgrok.firstElementChild(node) 150 + while node != None: 151 + name = node.getAttribute('name') 152 + value = node.getAttribute('value') 153 + 154 + if value == "true": 155 + value = "1" 156 + elif value == "false": 157 + value = "0" 158 + 159 + self.updateTemplate(name, value) 160 + 161 + if name == "MEM_IF_DM_PINS_EN": 162 + if value == "1": 163 + derivedNoDmPins = 0 164 + else: 165 + derivedNoDmPins = 1 166 + 167 + if name == "MEM_DQ_WIDTH": 168 + if value == "8": 169 + derivedCtrlWidth = 0 170 + derivedEccEn = 0 171 + derivedEccCorrEn = 0 172 + elif value == "16": 173 + derivedCtrlWidth = 1 174 + derivedEccEn = 0 175 + derivedEccCorrEn = 0 176 + elif value == "24": 177 + derivedCtrlWidth = 1 178 + derivedEccEn = 1 179 + derivedEccCorrEn = 1 180 + elif value == "32": 181 + derivedCtrlWidth = 2 182 + derivedEccEn = 0 183 + derivedEccCorrEn = 0 184 + elif value == "40": 185 + derivedCtrlWidth = 2 186 + derivedEccEn = 1 187 + derivedEccCorrEn = 1 188 + 189 + if name == "MEM_IF_RD_TO_WR_TURNAROUND_OCT": 190 + self.mem_if_rd_to_wr_turnaround_oct = int(value) 191 + 192 + node = xmlgrok.nextElementSibling(node) 193 + 194 + self.updateTemplate("DERIVED_NODMPINS", str(derivedNoDmPins)) 195 + self.updateTemplate("DERIVED_CTRLWIDTH", str(derivedCtrlWidth)) 196 + self.updateTemplate("DERIVED_ECCEN", str(derivedEccEn)) 197 + self.updateTemplate("DERIVED_ECCCORREN", str(derivedEccCorrEn)) 198 + 199 + def handleEMIFPllNode(self, node): 200 + """ retrieve values for pll node """ 201 + node = xmlgrok.firstElementChild(node) 202 + while node != None: 203 + name = node.getAttribute('name') 204 + value = node.getAttribute('value') 205 + 206 + self.updateTemplate(name, value) 207 + 208 + node = xmlgrok.nextElementSibling(node) 209 + 210 + def handleEMIFSequencerNode(self, node): 211 + """ retrieve values for sequencer node """ 212 + derivedMemtype = 0 213 + derivedSelfrfshexit = 0 214 + 215 + self.afi_rate_ratio = 0 216 + 217 + node = xmlgrok.firstElementChild(node) 218 + while node != None: 219 + name = node.getAttribute('name') 220 + value = node.getAttribute('value') 221 + 222 + self.updateTemplate(name, value) 223 + 224 + if value.isdigit(): 225 + intValue = int(value) 226 + else: 227 + intValue = 0 228 + 229 + if name == "DDR2" and intValue != 0: 230 + derivedMemtype = 1 231 + derivedSelfrfshexit = 200 232 + elif name == "DDR3" and intValue != 0: 233 + derivedMemtype = 2 234 + derivedSelfrfshexit = 512 235 + elif name == "LPDDR1" and intValue != 0: 236 + derivedMemtype = 3 237 + derivedSelfrfshexit = 200 238 + elif name == "LPDDR2" and intValue != 0: 239 + derivedMemtype = 4 240 + derivedSelfrfshexit = 200 241 + elif name == "AFI_RATE_RATIO" and intValue != 0: 242 + self.afi_rate_ratio = intValue 243 + 244 + node = xmlgrok.nextElementSibling(node) 245 + 246 + self.updateTemplate("DERIVED_MEMTYPE", str(derivedMemtype)) 247 + self.updateTemplate("DERIVED_SELFRFSHEXIT", str(derivedSelfrfshexit)) 248 + 249 + 250 + def handleHpsFpgaInterfaces(self, node): 251 + """ retrieve values for fpga interface """ 252 + node = xmlgrok.firstElementChild(node) 253 + 254 + while node != None: 255 + name = node.getAttribute('name') 256 + value = node.getAttribute('value') 257 + 258 + self.updateTemplate(name, value) 259 + 260 + node = xmlgrok.nextElementSibling(node) 261 + 262 + 263 + def createFilesFromEMIF(self): 264 + """ create sdram_config.h with the template and value read from xml. 265 + Different sequencer files are written to individual section, with 266 + comment at the start. 267 + """ 268 + self.sdramHTemplate ="""\ 269 + #define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A 270 + #define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 271 + #define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 272 + #define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 273 + #define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER ${ADDR_ORDER} 274 + #define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN ${USE_HPS_DQS_TRACKING} 275 + #define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN ${DERIVED_ECCCORREN} 276 + #define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN ${DERIVED_ECCEN} 277 + #define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL ${MEM_BURST_LENGTH} 278 + #define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE ${DERIVED_MEMTYPE} 279 + #define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS ${DERIVED_NODMPINS} 280 + #define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 281 + #define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 282 + #define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH ${DERIVED_CTRLWIDTH} 283 + #define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS ${MEM_IF_BANKADDR_WIDTH} 284 + #define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS ${MEM_IF_COL_ADDR_WIDTH} 285 + #define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS ${DEVICE_DEPTH} 286 + #define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS ${MEM_IF_ROW_ADDR_WIDTH} 287 + #define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 288 + #define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH ${MEM_DQ_WIDTH} 289 + #define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 290 + #define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ ${CFG_READ_ODT_CHIP} 291 + #define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE ${CFG_WRITE_ODT_CHIP} 292 + #define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 293 + #define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL ${MEM_TCL} 294 + #define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL ${MEM_WTCL_INT} 295 + #define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW ${MEM_TFAW} 296 + #define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC ${MEM_TRFC} 297 + #define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD ${MEM_TRRD} 298 + #define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD ${MEM_TRCD} 299 + #define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI ${MEM_TREFI} 300 + #define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP ${MEM_TRP} 301 + #define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR ${MEM_TWR} 302 + #define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR ${MEM_TWTR} 303 + #define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 304 + #define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD ${MEM_TMRD_CK} 305 + #define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS ${MEM_TRAS} 306 + #define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC ${MEM_TRC} 307 + #define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP ${MEM_TRTP} 308 + #define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 309 + #define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT ${DERIVED_SELFRFSHEXIT} 310 + #define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR ${DERIVED_CLK_RD_TO_WR} 311 + #define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC ${DERIVED_CLK_RD_TO_WR} 312 + #define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP ${DERIVED_CLK_RD_TO_WR} 313 + #define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 314 + #define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 315 + #define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST ${F2SDRAM_RESET_PORT_USED} 316 + #define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 317 + #define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 318 + #define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 319 + #define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 320 + #define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 321 + #define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 322 + #define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 323 + #define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 324 + #define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0 325 + #define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 326 + #define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 327 + #define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 328 + #define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 329 + #define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441 330 + #define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78 331 + #define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 332 + #define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0 333 + #define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 334 + #define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 335 + #define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 336 + #define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 337 + #define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 338 + #define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 339 + """ 340 + 341 + # Get a list of all nodes with the emif element name 342 + emifNodeList = self.emifDom.getElementsByTagName('emif') 343 + if len(emifNodeList) > 1: 344 + print ("*** WARNING:" + "Multiple emif Elements found in %s!" % self.emifFileName) 345 + # For each of the emif element nodes, go through the child list 346 + # Note that currently there is only one emif Element 347 + # but this code will handle more than one emif node 348 + # In the future, multiple emif nodes may need additional code 349 + # to combine settings from the multiple emif Elements 350 + for emifNode in emifNodeList: 351 + # Currently, there are only 3 children of the emif Element: 352 + # sequencer, controller, and pll 353 + # but this is left open-ended for future additions to the 354 + # specification for the emif.xml 355 + childNode = xmlgrok.firstElementChild(emifNode) 356 + while childNode != None: 357 + 358 + if childNode.nodeName == 'controller': 359 + self.handleEMIFControllerNode(childNode) 360 + elif childNode.nodeName == 'sequencer': 361 + self.handleEMIFSequencerNode(childNode) 362 + elif childNode.nodeName == 'pll': 363 + self.handleEMIFPllNode(childNode) 364 + 365 + childNode = xmlgrok.nextElementSibling(childNode) 366 + 367 + data_rate_ratio = 2 368 + dwidth_ratio = self.afi_rate_ratio * data_rate_ratio 369 + if dwidth_ratio == 0: 370 + derivedClkRdToWr = 0 371 + else: 372 + derivedClkRdToWr = (self.mem_if_rd_to_wr_turnaround_oct / (dwidth_ratio / 2)) 373 + 374 + if (self.mem_if_rd_to_wr_turnaround_oct % (dwidth_ratio / 2)) > 0: 375 + derivedClkRdToWr += 1 376 + 377 + self.updateTemplate("DERIVED_CLK_RD_TO_WR", str(int(derivedClkRdToWr))) 378 + 379 + # MPFE information are stored in hps.xml despite we generate 380 + # them into sdram_config, so let's load hps.xml 381 + hpsNodeList = self.hpsDom.getElementsByTagName('hps') 382 + 383 + for hpsNode in hpsNodeList: 384 + 385 + childNode = xmlgrok.firstElementChild(hpsNode) 386 + 387 + while childNode != None: 388 + # MPFE info is part of fpga_interfaces 389 + if childNode.nodeName == 'fpga_interfaces': 390 + self.handleHpsFpgaInterfaces(childNode) 391 + 392 + childNode = xmlgrok.nextElementSibling(childNode) 393 + 394 + self.sequencerDefinesStream = streamer.Streamer(self.outputDir + os.sep + EMIFGrokker.SDRAM_CONFIG_H_FILENAME, 'w') 395 + self.sequencerDefinesStream.open() 396 + self.sequencerDefinesStream.writeLicenseHeader() 397 + self.sequencerDefinesStream.write(EMIFGrokker.SDRAM_FILE_HEADER) 398 + ret = self.sequencerDefinesStream.writeSentinelStart(EMIFGrokker.SDRAM_SENTINEL) 399 + if ret == -1: 400 + print("Empty header written. Exiting.") 401 + self.sequencerDefinesStream.write("/* SDRAM configuration */\n") 402 + self.sequencerDefinesStream.write(self.sdramHTemplate) 403 + self.openSeqFiles() 404 + self.processSeqAuto() 405 + 406 + self.sequencerDefinesStream.write("\n") 407 + self.sequencerDefinesStream.write("/* Sequencer auto configuration */\n") 408 + self.sequencerDefinesStream.write(self.seqAutoTemplate) 409 + self.sequencerDefinesStream.write("\n") 410 + self.sequencerDefinesStream.write("/* Sequencer defines configuration */\n") 411 + self.sequencerDefinesStream.write(self.seqDefinesTemplate) 412 + self.sequencerDefinesStream.write("\n") 413 + self.sequencerDefinesStream.write("/* Sequencer ac_rom_init configuration */\n") 414 + self.sequencerDefinesStream.write(self.seqAutoAcTemplate) 415 + self.sequencerDefinesStream.write("\n\n") 416 + self.sequencerDefinesStream.write("/* Sequencer inst_rom_init configuration */\n") 417 + self.sequencerDefinesStream.write(self.seqAutoInstTemplate) 418 + self.sequencerDefinesStream.write("\n") 419 + 420 + ret = self.sequencerDefinesStream.writeSentinelEnd(EMIFGrokker.SDRAM_SENTINEL) 421 + if ret == -1: 422 + print("Empty header written. Exiting.") 423 + self.sequencerDefinesStream.close() 424 + self.closeSeqFiles()
+571
tools/cv_bsp_generator/hps.py
··· 1 + # SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 + """ 3 + Pinmux header file generator 4 + 5 + Process the hps.xml from Quartus and convert them to headers 6 + usable by U-Boot. 7 + 8 + Copyright (C) 2022 Intel Corporation <www.intel.com> 9 + 10 + Author: Lee, Kah Jing <kah.jing.lee@intel.com> 11 + """ 12 + import os 13 + import re 14 + import streamer 15 + import xmlgrok 16 + import xml.dom.minidom 17 + import collections 18 + import io 19 + from io import StringIO 20 + 21 + class CompatStringIO(io.StringIO): 22 + def write(self, s): 23 + if hasattr(s, 'decode'): 24 + # Use unicode for python2 to keep compatible 25 + return int(super(CompatStringIO, self).write(s.decode('utf-8'))) 26 + else: 27 + return super(CompatStringIO, self).write(s) 28 + def getvalue(self): 29 + return str(super(CompatStringIO, self).getvalue()) 30 + 31 + class HPSGrokker(object): 32 + 33 + SCRIPT_DIR = os.path.dirname(os.path.realpath(__file__)) 34 + TEMPLATE_DIR = os.path.dirname(SCRIPT_DIR) + '/src' 35 + 36 + MAKEFILE_FILENAME = "Makefile" 37 + makefileTemplate = "" 38 + RESET_CONFIG_H_FILENAME = "reset_config.h" 39 + resetConfigHTemplate = "" 40 + 41 + # If no device family is specified, assume Cyclone V. 42 + derivedDeviceFamily = "cyclone5" 43 + 44 + # Assume FPGA DMA 0-7 are not in use by default 45 + # Note: there appears to be a weird mismatch between sopcinfo 46 + # value vs hps.xml value of DMA_Enable of string_list hw.tcl 47 + # type, where sopcinfo uses comma as separator e.g. 48 + # "No,No,No,..." while hps.xml uses space as separator. 49 + dmaEnable = "No No No No No No No No" 50 + 51 + def __init__(self, inputDir, outputDir, hpsFileName='hps.xml'): 52 + """ HPSGrokker initialization """ 53 + self.inputDir = inputDir 54 + self.outputDir = outputDir 55 + self.hpsInFileName = inputDir + os.sep + hpsFileName 56 + self.dom = xml.dom.minidom.parse(self.hpsInFileName) 57 + self.peripheralStream = None 58 + self.pinmuxConfigBuffer = None 59 + self.pinmuxHeaderBuffer = None 60 + self.pinmuxHeaderFile = None 61 + self.pinmuxArraySize = 0 62 + self.config_hps_ = "CFG_HPS_" 63 + self.clockStream = None 64 + self.pinmux_regs = self.get_default_pinmux_regs() 65 + self.pinmux_configs = self.get_default_pinmux_configs() 66 + self.pinmux_config_h = None 67 + 68 + self.createFilesFromHPS() 69 + 70 + def get_default_pinmux_regs(self): 71 + """ Set default pinmux values """ 72 + p = collections.OrderedDict() 73 + 74 + p['EMACIO0'] = 0 75 + p['EMACIO1'] = 0 76 + p['EMACIO2'] = 0 77 + p['EMACIO3'] = 0 78 + p['EMACIO4'] = 0 79 + p['EMACIO5'] = 0 80 + p['EMACIO6'] = 0 81 + p['EMACIO7'] = 0 82 + p['EMACIO8'] = 0 83 + p['EMACIO9'] = 0 84 + p['EMACIO10'] = 0 85 + p['EMACIO11'] = 0 86 + p['EMACIO12'] = 0 87 + p['EMACIO13'] = 0 88 + p['EMACIO14'] = 0 89 + p['EMACIO15'] = 0 90 + p['EMACIO16'] = 0 91 + p['EMACIO17'] = 0 92 + p['EMACIO18'] = 0 93 + p['EMACIO19'] = 0 94 + p['FLASHIO0'] = 0 95 + p['FLASHIO1'] = 0 96 + p['FLASHIO2'] = 0 97 + p['FLASHIO3'] = 0 98 + p['FLASHIO4'] = 0 99 + p['FLASHIO5'] = 0 100 + p['FLASHIO6'] = 0 101 + p['FLASHIO7'] = 0 102 + p['FLASHIO8'] = 0 103 + p['FLASHIO9'] = 0 104 + p['FLASHIO10'] = 0 105 + p['FLASHIO11'] = 0 106 + p['GENERALIO0'] = 0 107 + p['GENERALIO1'] = 0 108 + p['GENERALIO2'] = 0 109 + p['GENERALIO3'] = 0 110 + p['GENERALIO4'] = 0 111 + p['GENERALIO5'] = 0 112 + p['GENERALIO6'] = 0 113 + p['GENERALIO7'] = 0 114 + p['GENERALIO8'] = 0 115 + p['GENERALIO9'] = 0 116 + p['GENERALIO10'] = 0 117 + p['GENERALIO11'] = 0 118 + p['GENERALIO12'] = 0 119 + p['GENERALIO13'] = 0 120 + p['GENERALIO14'] = 0 121 + p['GENERALIO15'] = 0 122 + p['GENERALIO16'] = 0 123 + p['GENERALIO17'] = 0 124 + p['GENERALIO18'] = 0 125 + p['GENERALIO19'] = 0 126 + p['GENERALIO20'] = 0 127 + p['GENERALIO21'] = 0 128 + p['GENERALIO22'] = 0 129 + p['GENERALIO23'] = 0 130 + p['GENERALIO24'] = 0 131 + p['GENERALIO25'] = 0 132 + p['GENERALIO26'] = 0 133 + p['GENERALIO27'] = 0 134 + p['GENERALIO28'] = 0 135 + p['GENERALIO29'] = 0 136 + p['GENERALIO30'] = 0 137 + p['GENERALIO31'] = 0 138 + p['MIXED1IO0'] = 0 139 + p['MIXED1IO1'] = 0 140 + p['MIXED1IO2'] = 0 141 + p['MIXED1IO3'] = 0 142 + p['MIXED1IO4'] = 0 143 + p['MIXED1IO5'] = 0 144 + p['MIXED1IO6'] = 0 145 + p['MIXED1IO7'] = 0 146 + p['MIXED1IO8'] = 0 147 + p['MIXED1IO9'] = 0 148 + p['MIXED1IO10'] = 0 149 + p['MIXED1IO11'] = 0 150 + p['MIXED1IO12'] = 0 151 + p['MIXED1IO13'] = 0 152 + p['MIXED1IO14'] = 0 153 + p['MIXED1IO15'] = 0 154 + p['MIXED1IO16'] = 0 155 + p['MIXED1IO17'] = 0 156 + p['MIXED1IO18'] = 0 157 + p['MIXED1IO19'] = 0 158 + p['MIXED1IO20'] = 0 159 + p['MIXED1IO21'] = 0 160 + p['MIXED2IO0'] = 0 161 + p['MIXED2IO1'] = 0 162 + p['MIXED2IO2'] = 0 163 + p['MIXED2IO3'] = 0 164 + p['MIXED2IO4'] = 0 165 + p['MIXED2IO5'] = 0 166 + p['MIXED2IO6'] = 0 167 + p['MIXED2IO7'] = 0 168 + p['GPLINMUX48'] = 0 169 + p['GPLINMUX49'] = 0 170 + p['GPLINMUX50'] = 0 171 + p['GPLINMUX51'] = 0 172 + p['GPLINMUX52'] = 0 173 + p['GPLINMUX53'] = 0 174 + p['GPLINMUX54'] = 0 175 + p['GPLINMUX55'] = 0 176 + p['GPLINMUX56'] = 0 177 + p['GPLINMUX57'] = 0 178 + p['GPLINMUX58'] = 0 179 + p['GPLINMUX59'] = 0 180 + p['GPLINMUX60'] = 0 181 + p['GPLINMUX61'] = 0 182 + p['GPLINMUX62'] = 0 183 + p['GPLINMUX63'] = 0 184 + p['GPLINMUX64'] = 0 185 + p['GPLINMUX65'] = 0 186 + p['GPLINMUX66'] = 0 187 + p['GPLINMUX67'] = 0 188 + p['GPLINMUX68'] = 0 189 + p['GPLINMUX69'] = 0 190 + p['GPLINMUX70'] = 0 191 + p['GPLMUX0'] = 1 192 + p['GPLMUX1'] = 1 193 + p['GPLMUX2'] = 1 194 + p['GPLMUX3'] = 1 195 + p['GPLMUX4'] = 1 196 + p['GPLMUX5'] = 1 197 + p['GPLMUX6'] = 1 198 + p['GPLMUX7'] = 1 199 + p['GPLMUX8'] = 1 200 + p['GPLMUX9'] = 1 201 + p['GPLMUX10'] = 1 202 + p['GPLMUX11'] = 1 203 + p['GPLMUX12'] = 1 204 + p['GPLMUX13'] = 1 205 + p['GPLMUX14'] = 1 206 + p['GPLMUX15'] = 1 207 + p['GPLMUX16'] = 1 208 + p['GPLMUX17'] = 1 209 + p['GPLMUX18'] = 1 210 + p['GPLMUX19'] = 1 211 + p['GPLMUX20'] = 1 212 + p['GPLMUX21'] = 1 213 + p['GPLMUX22'] = 1 214 + p['GPLMUX23'] = 1 215 + p['GPLMUX24'] = 1 216 + p['GPLMUX25'] = 1 217 + p['GPLMUX26'] = 1 218 + p['GPLMUX27'] = 1 219 + p['GPLMUX28'] = 1 220 + p['GPLMUX29'] = 1 221 + p['GPLMUX30'] = 1 222 + p['GPLMUX31'] = 1 223 + p['GPLMUX32'] = 1 224 + p['GPLMUX33'] = 1 225 + p['GPLMUX34'] = 1 226 + p['GPLMUX35'] = 1 227 + p['GPLMUX36'] = 1 228 + p['GPLMUX37'] = 1 229 + p['GPLMUX38'] = 1 230 + p['GPLMUX39'] = 1 231 + p['GPLMUX40'] = 1 232 + p['GPLMUX41'] = 1 233 + p['GPLMUX42'] = 1 234 + p['GPLMUX43'] = 1 235 + p['GPLMUX44'] = 1 236 + p['GPLMUX45'] = 1 237 + p['GPLMUX46'] = 1 238 + p['GPLMUX47'] = 1 239 + p['GPLMUX48'] = 1 240 + p['GPLMUX49'] = 1 241 + p['GPLMUX50'] = 1 242 + p['GPLMUX51'] = 1 243 + p['GPLMUX52'] = 1 244 + p['GPLMUX53'] = 1 245 + p['GPLMUX54'] = 1 246 + p['GPLMUX55'] = 1 247 + p['GPLMUX56'] = 1 248 + p['GPLMUX57'] = 1 249 + p['GPLMUX58'] = 1 250 + p['GPLMUX59'] = 1 251 + p['GPLMUX60'] = 1 252 + p['GPLMUX61'] = 1 253 + p['GPLMUX62'] = 1 254 + p['GPLMUX63'] = 1 255 + p['GPLMUX64'] = 1 256 + p['GPLMUX65'] = 1 257 + p['GPLMUX66'] = 1 258 + p['GPLMUX67'] = 1 259 + p['GPLMUX68'] = 1 260 + p['GPLMUX69'] = 1 261 + p['GPLMUX70'] = 1 262 + p['NANDUSEFPGA'] = 0 263 + p['UART0USEFPGA'] = 0 264 + p['RGMII1USEFPGA'] = 0 265 + p['SPIS0USEFPGA'] = 0 266 + p['CAN0USEFPGA'] = 0 267 + p['I2C0USEFPGA'] = 0 268 + p['SDMMCUSEFPGA'] = 0 269 + p['QSPIUSEFPGA'] = 0 270 + p['SPIS1USEFPGA'] = 0 271 + p['RGMII0USEFPGA'] = 0 272 + p['UART1USEFPGA'] = 0 273 + p['CAN1USEFPGA'] = 0 274 + p['USB1USEFPGA'] = 0 275 + p['I2C3USEFPGA'] = 0 276 + p['I2C2USEFPGA'] = 0 277 + p['I2C1USEFPGA'] = 0 278 + p['SPIM1USEFPGA'] = 0 279 + p['USB0USEFPGA'] = 0 280 + p['SPIM0USEFPGA'] = 0 281 + 282 + return p 283 + 284 + 285 + def get_default_pinmux_configs(self): 286 + """ Get default pinmux values """ 287 + p = collections.OrderedDict() 288 + 289 + p['rgmii0'] = { 'name': 'CFG_HPS_EMAC0', 'used': 0 } 290 + p['rgmii1'] = { 'name': 'CFG_HPS_EMAC1', 'used': 0 } 291 + p['usb0'] = { 'name': 'CFG_HPS_USB0', 'used': 0 } 292 + p['usb1'] = { 'name': 'CFG_HPS_USB1', 'used': 0 } 293 + p['nand'] = { 'name': 'CFG_HPS_NAND', 'used': 0 } 294 + p['sdmmc'] = { 'name': 'CFG_HPS_SDMMC', 'used': 0 } 295 + p['CFG_HPS_SDMMC_BUSWIDTH'] = { 'name': 'CFG_HPS_SDMMC_BUSWIDTH', 'used': 0 } 296 + p['qspi'] = { 'name': 'CFG_HPS_QSPI', 'used': 0 } 297 + p['CFG_HPS_QSPI_CS3'] = { 'name': 'CFG_HPS_QSPI_CS3', 'used': 0 } 298 + p['CFG_HPS_QSPI_CS2'] = { 'name': 'CFG_HPS_QSPI_CS2', 'used': 0 } 299 + p['CFG_HPS_QSPI_CS1'] = { 'name': 'CFG_HPS_QSPI_CS1', 'used': 0 } 300 + p['CFG_HPS_QSPI_CS0'] = { 'name': 'CFG_HPS_QSPI_CS0', 'used': 0 } 301 + p['uart0'] = { 'name': 'CFG_HPS_UART0', 'used': 0 } 302 + p['CFG_HPS_UART0_TX'] = { 'name': 'CFG_HPS_UART0_TX', 'used': 0 } 303 + p['CFG_HPS_UART0_CTS'] = { 'name': 'CFG_HPS_UART0_CTS', 'used': 0 } 304 + p['CFG_HPS_UART0_RTS'] = { 'name': 'CFG_HPS_UART0_RTS', 'used': 0 } 305 + p['CFG_HPS_UART0_RX'] = { 'name': 'CFG_HPS_UART0_RX', 'used': 0 } 306 + p['uart1'] = { 'name': 'CFG_HPS_UART1', 'used': 0 } 307 + p['CFG_HPS_UART1_TX'] = { 'name': 'CFG_HPS_UART1_TX', 'used': 0 } 308 + p['CFG_HPS_UART1_CTS'] = { 'name': 'CFG_HPS_UART1_CTS', 'used': 0 } 309 + p['CFG_HPS_UART1_RTS'] = { 'name': 'CFG_HPS_UART1_RTS', 'used': 0 } 310 + p['CFG_HPS_UART1_RX'] = { 'name': 'CFG_HPS_UART1_RX', 'used': 0 } 311 + p['trace'] = { 'name': 'CFG_HPS_TRACE', 'used': 0 } 312 + p['i2c0'] = { 'name': 'CFG_HPS_I2C0', 'used': 0 } 313 + p['i2c1'] = { 'name': 'CFG_HPS_I2C1', 'used': 0 } 314 + p['i2c2'] = { 'name': 'CFG_HPS_I2C2', 'used': 0 } 315 + p['i2c3'] = { 'name': 'CFG_HPS_I2C3', 'used': 0 } 316 + p['spim0'] = { 'name': 'CFG_HPS_SPIM0', 'used': 0 } 317 + p['spim1'] = { 'name': 'CFG_HPS_SPIM1', 'used': 0 } 318 + p['spis0'] = { 'name': 'CFG_HPS_SPIS0', 'used': 0 } 319 + p['spis1'] = { 'name': 'CFG_HPS_SPIS1', 'used': 0 } 320 + p['can0'] = { 'name': 'CFG_HPS_CAN0', 'used': 0 } 321 + p['can1'] = { 'name': 'CFG_HPS_CAN1', 'used': 0 } 322 + 323 + p['can1'] = { 'name': 'CFG_HPS_CAN1', 'used': 0 } 324 + p['can1'] = { 'name': 'CFG_HPS_CAN1', 'used': 0 } 325 + p['can1'] = { 'name': 'CFG_HPS_CAN1', 'used': 0 } 326 + p['can1'] = { 'name': 'CFG_HPS_CAN1', 'used': 0 } 327 + 328 + return p 329 + 330 + def updateTemplate(self, name, value): 331 + """ Update Makefile & reset_config.h """ 332 + pattern = "${" + name + "}" 333 + self.makefileTemplate = self.makefileTemplate.replace(pattern, value) 334 + self.resetConfigHTemplate = self.resetConfigHTemplate.replace(pattern, value) 335 + 336 + def romanToInteger(self, roman): 337 + """ 338 + Convert roman numerals to integer 339 + Since we only support I,V,X, the 340 + supported range is 1-39 341 + """ 342 + table = { 'I':1 , 'V':5, 'X':10 } 343 + 344 + literals = list(roman) 345 + 346 + value = 0 347 + i = 0 348 + 349 + while(i < (len(literals) - 1)): 350 + current = table[literals[i]] 351 + next = table[literals[i + 1]] 352 + if (current < next): 353 + value += (next - current) 354 + i += 2 355 + else: 356 + value += current 357 + i += 1 358 + 359 + if (i < (len(literals))): 360 + value += table[literals[i]] 361 + 362 + return value 363 + 364 + def getDeviceFamily(self): 365 + """ Get device family """ 366 + return self.derivedDeviceFamily 367 + 368 + def getDeviceFamilyName(self, deviceFamily): 369 + """ Get device family name """ 370 + p = re.compile('^(\w+)\s+(\w+)$') 371 + m = p.match(deviceFamily) 372 + return m.group(1).lower() + str(self.romanToInteger(m.group(2))) 373 + 374 + def handleHPSSystemNode(self, systemNode): 375 + """ handleHPSPeripheralsNode(peripheralsNode) 376 + peripheralsNode is a peripherals element node in hps.xml 377 + peripheralsNode is a list of peripheralNodes 378 + """ 379 + configNode = xmlgrok.firstElementChild(systemNode) 380 + while configNode != None: 381 + 382 + name = configNode.getAttribute('name') 383 + value = configNode.getAttribute('value') 384 + 385 + self.updateTemplate(name, value) 386 + 387 + if name == "DEVICE_FAMILY": 388 + self.derivedDeviceFamily = self.getDeviceFamilyName(value) 389 + 390 + if name == "DMA_Enable": 391 + self.dmaEnable = value 392 + 393 + configNode = xmlgrok.nextElementSibling(configNode) 394 + 395 + def handleHPSPeripheralNode(self, peripheralNode): 396 + """ This node of the hps.xml may contain a name, value pair 397 + We need to: 398 + emit a #define for the peripheral for is 'used' state 399 + emit a #define for that pair, if it is marked 'used' 400 + """ 401 + peripheralNode = xmlgrok.firstElementChild(peripheralNode) 402 + 403 + while peripheralNode != None: 404 + if peripheralNode.hasAttribute('name') and peripheralNode.hasAttribute('used'): 405 + newLine = "\n" 406 + name = peripheralNode.getAttribute('name') 407 + used = peripheralNode.getAttribute('used') 408 + 409 + if used == 'true' or used == True: 410 + used = 1 411 + elif used == 'false' or used == False: 412 + used = 0 413 + 414 + configs = collections.OrderedDict() 415 + 416 + configNode = xmlgrok.firstElementChild(peripheralNode) 417 + while configNode != None: 418 + config_define_name = configNode.getAttribute('name') 419 + config_define_value = configNode.getAttribute('value') 420 + configs[config_define_name] = config_define_value 421 + configNode = xmlgrok.nextElementSibling(configNode) 422 + if configNode == None: 423 + newLine += newLine 424 + self.pinmuxConfigBuffer.write("#define " + str(config_define_name) + ' ' + '(' + str(config_define_value) + ')' + newLine) 425 + 426 + entry = self.pinmux_configs[name] 427 + define_name = entry['name'] 428 + 429 + if (len(configs) > 0): 430 + self.pinmux_configs[name] = { 'name': define_name, 'used': used, 'configs': configs } 431 + else: 432 + self.pinmux_configs[name] = { 'name': define_name, 'used': used } 433 + 434 + # skip the parent peripheral node 435 + # since only need to define child config node(s) 436 + peripheralNode = xmlgrok.nextElementSibling(peripheralNode) 437 + 438 + def handleHPSPinmuxNode(self, pinmuxNode): 439 + """ For a pinmuxNode, we may emit a #define for the name, value pair 440 + """ 441 + if pinmuxNode.hasAttribute('name') and pinmuxNode.hasAttribute('value'): 442 + self.pinmuxArraySize += 1 443 + name = pinmuxNode.getAttribute('name') 444 + value = pinmuxNode.getAttribute('value') 445 + 446 + def handleHPSPinmuxesNode(self, pinmuxesNode): 447 + """ PinmuxesNode is a list of pinmuxNodes 448 + """ 449 + self.pinmuxHeaderBuffer.write(str("const u8 sys_mgr_init_table[] = {\n")) 450 + 451 + pinmuxNode = xmlgrok.firstElementChild(pinmuxesNode) 452 + while pinmuxNode != None: 453 + if pinmuxNode.hasAttribute('name') and pinmuxNode.hasAttribute('value'): 454 + self.pinmuxArraySize += 1 455 + name = pinmuxNode.getAttribute('name') 456 + value = pinmuxNode.getAttribute('value') 457 + self.pinmux_regs[name] = value 458 + pinmuxNode = xmlgrok.nextElementSibling(pinmuxNode) 459 + 460 + reg_count = 0 461 + pinmux_regs_count = len(self.pinmux_regs) 462 + for reg, value in self.pinmux_regs.items(): 463 + reg_count += 1 464 + if reg_count < pinmux_regs_count: 465 + self.pinmuxHeaderBuffer.write(str("\t" + str(value) + ', /* ' + reg + ' */\n' )) 466 + else: 467 + self.pinmuxHeaderBuffer.write(str("\t" + str(value) + ' /* ' + reg + ' */\n' )) 468 + 469 + # Write the close of the pin MUX array in the header 470 + self.pinmuxHeaderBuffer.write(str("};" )) 471 + 472 + def handleHPSClockNode(self, clockNode): 473 + """ A clockNode may emit a #define for the name, frequency pair 474 + """ 475 + if clockNode.hasAttribute('name') and clockNode.hasAttribute('frequency'): 476 + name = clockNode.getAttribute('name') 477 + frequency = clockNode.getAttribute('frequency') 478 + self.clockStream.write("#define " + name + ' ' + '(' + frequency + ')' + '\n') 479 + 480 + def handleHPSClocksNode(self, clocksNode): 481 + """ A list of clockNodes is call clocksNode 482 + """ 483 + self.clockStream = streamer.Streamer(self.outputDir + os.sep + clocksNode.nodeName + '.h', 'w') 484 + self.clockStream.open() 485 + clockNode = xmlgrok.firstElementChild(clocksNode) 486 + while clockNode != None: 487 + self.handleHPSClockNode(clockNode) 488 + clockNode = xmlgrok.nextElementSibling(clockNode) 489 + 490 + self.clockStream.close() 491 + 492 + def handleHpsFpgaInterfaces(self, node): 493 + """ Update FPGA Interface registers """ 494 + node = xmlgrok.firstElementChild(node) 495 + 496 + while node != None: 497 + name = node.getAttribute('name') 498 + used = node.getAttribute('used') 499 + 500 + if used == 'true': 501 + reset = 0 502 + else: 503 + reset = 1 504 + 505 + if name == 'F2H_AXI_SLAVE': 506 + self.updateTemplate("DERIVED_RESET_ASSERT_FPGA2HPS", str(reset)) 507 + elif name == 'H2F_AXI_MASTER': 508 + self.updateTemplate("DERIVED_RESET_ASSERT_HPS2FPGA", str(reset)) 509 + elif name == 'LWH2F_AXI_MASTER': 510 + self.updateTemplate("DERIVED_RESET_ASSERT_LWHPS2FPGA", str(reset)) 511 + 512 + node = xmlgrok.nextElementSibling(node) 513 + 514 + def createFilesFromHPS(self): 515 + """ Parse xml and create pinmux_config.h """ 516 + # Unfortunately we can't determine the file name before 517 + # parsing the XML, so let's build up the source file 518 + # content in string buffer 519 + self.pinmuxHeaderBuffer = CompatStringIO() 520 + self.pinmuxConfigBuffer = CompatStringIO() 521 + 522 + # Get a list of all nodes with the hps element name 523 + hpsNodeList = self.dom.getElementsByTagName('hps') 524 + if len(hpsNodeList) > 1: 525 + print ("*** WARNING:" + "Multiple hps Elements found in %s!" % self.hpsInFileName) 526 + # For each of the hps element nodes, go through the child list 527 + # Note that currently there is only one hps Element 528 + # but this code will handle more than one hps node 529 + # In the future, multiple hps nodes may need additional code 530 + # to combine settings from the multiple hps Elements 531 + for hpsNode in hpsNodeList: 532 + # Currently, there are only 3 children of the hps Element: 533 + # peripherals, pin_muxes, and clocks 534 + # but this is left open-ended for future additions to the 535 + # specification for the hps.xml 536 + childNode = xmlgrok.firstElementChild(hpsNode) 537 + while childNode != None: 538 + if childNode.nodeName == 'pin_muxes': 539 + self.handleHPSPinmuxesNode(childNode) 540 + elif childNode.nodeName == 'system': 541 + self.handleHPSSystemNode(childNode) 542 + elif childNode.nodeName == 'fpga_interfaces': 543 + self.handleHpsFpgaInterfaces(childNode) 544 + elif childNode.nodeName == 'peripherals': 545 + self.handleHPSPeripheralNode(childNode) 546 + else: 547 + print ("***Error:Found unexpected HPS child node:%s" % childNode.nodeName) 548 + childNode = xmlgrok.nextElementSibling(childNode) 549 + 550 + self.updateTemplate("DERIVED_DEVICE_FAMILY", self.derivedDeviceFamily) 551 + 552 + # Now we write string buffers into files once we know the device family 553 + self.pinmux_config_h = 'pinmux_config.h' 554 + self.pinmux_config_src = 'pinmux_config_' + self.derivedDeviceFamily + '.c' 555 + 556 + # Create pinmux_config .h 557 + headerDefine = "__SOCFPGA_PINMUX_CONFIG_H__" 558 + self.pinmuxHeaderFile = streamer.Streamer(self.outputDir + os.sep + self.pinmux_config_h, 'w') 559 + self.pinmuxHeaderFile.open() 560 + self.pinmuxHeaderFile.writeLicenseHeader() 561 + self.pinmuxHeaderFile.write('/*\n * Altera SoCFPGA PinMux configuration\n */\n\n') 562 + 563 + self.pinmuxHeaderFile.write("#ifndef " + headerDefine + "\n") 564 + self.pinmuxHeaderFile.write("#define " + headerDefine + "\n\n") 565 + self.pinmuxHeaderFile.write(self.pinmuxHeaderBuffer.getvalue()) 566 + self.pinmuxHeaderFile.write("\n#endif /* " + headerDefine + " */\n") 567 + self.pinmuxHeaderFile.close() 568 + 569 + # Free up string buffers 570 + self.pinmuxHeaderBuffer.close() 571 + self.pinmuxConfigBuffer.close()
+203
tools/cv_bsp_generator/iocsr.py
··· 1 + # SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 + """ 3 + IOCSR header file generator 4 + 5 + Process the hiof file from Quartus and generate iocsr header 6 + usable by U-Boot. 7 + 8 + Copyright (C) 2022 Intel Corporation <www.intel.com> 9 + 10 + Author: Lee, Kah Jing <kah.jing.lee@intel.com> 11 + """ 12 + import os 13 + import struct 14 + import streamer 15 + 16 + class IOCSRGrokker(object): 17 + """ Decode the .hiof file and produce some C source code 18 + """ 19 + IOCSR_ROOT_FILENAME = 'iocsr_config' 20 + IOCSR_SENTINEL = '__SOCFPGA_IOCSR_CONFIG_H__' 21 + IOCSR_FILE_EXTENSION_MAX_LEN = 6 22 + PTAG_HPS_IOCSR_INFO = 39 23 + PTAG_HPS_IOCSR = 40 24 + PTAG_DEVICE_NAME = 2 25 + PTAG_TERMINATION = 8 26 + 27 + def __init__(self, deviceFamily, inputDir, outputDir, hiofSrcFileName): 28 + """ IOCSRGrokker Initialization """ 29 + self.deviceFamily = deviceFamily 30 + self.inputDir = inputDir 31 + self.outputDir = outputDir 32 + self.hiofInFileName = hiofSrcFileName 33 + self.iocsrFileName = self.IOCSR_ROOT_FILENAME 34 + self.headerOut = None 35 + self.sourceOut = None 36 + self.createFilesFromHIOF() 37 + 38 + @staticmethod 39 + def byteArrayToStr(bytes): 40 + """ Convert a list of bytes into a string 41 + """ 42 + # We don't like nulls 43 + bytes = bytes.replace('\x00', '') 44 + s = '' 45 + for b in bytes: 46 + s += b 47 + return s 48 + 49 + @staticmethod 50 + def getLengthData(bytes): 51 + """ 52 + @param: bytes is a chunk of bytes that we need to decode 53 + There will be a ptag that we may care about. 54 + If we care about it, we will get the length of the chunk 55 + that the ptag cares about. 56 + @rtype: a pair, length of chunk and the chunk itself 57 + @return: length of the ptag chunk we care about 58 + @return: data chunk that ptag indicates we need to decode 59 + """ 60 + blockSize = len(bytes) 61 + i = 0 62 + bitlength = 0 63 + length = 0 64 + data = [] 65 + 66 + while i < blockSize: 67 + byte = struct.unpack('B', bytes[i:i+1])[0] 68 + i += 1 69 + 70 + if byte == 1: 71 + bitlength = struct.unpack('I', bytes[i:i+4])[0] 72 + i += 4 73 + elif byte == 2: 74 + length = struct.unpack('I', bytes[i:i+4])[0] 75 + i += 4 76 + 77 + elif byte == 5: 78 + j = 0 79 + while i < blockSize: 80 + data.append(struct.unpack('I', bytes[i:i+4])[0]) 81 + i += 4 82 + j += 1 83 + 84 + else: 85 + i += 4 86 + 87 + return (bitlength, data) 88 + 89 + 90 + def verifyRead(self, tagWeRead, tagWeExpected): 91 + """ verify the hiof value with tag expected """ 92 + if tagWeRead != tagWeExpected: 93 + print ("***Error: Expected ptag of %02d, but got %02d" % (tagWeExpected, tagWeRead)) 94 + 95 + def createFilesFromHIOF(self): 96 + """ read the hiof file to create iocsr_config.h """ 97 + self.hiofStream = streamer.Streamer(self.inputDir + os.sep + self.hiofInFileName, 'rb') 98 + self.iocsrHeaderStream = streamer.Streamer(self.outputDir + os.sep + self.iocsrFileName + '.h', 'w') 99 + self.hiofStream.open() 100 + self.iocsrHeaderStream.open() 101 + self.iocsrHeaderStream.writeLicenseHeader() 102 + self.iocsrHeaderStream.write('/*\n * Altera SoCFPGA IOCSR configuration\n */\n\n') 103 + ret = self.iocsrHeaderStream.writeSentinelStart(IOCSRGrokker.IOCSR_SENTINEL) 104 + if ret == -1: 105 + print("Empty header written. Exiting.") 106 + 107 + # Read the file extension (typically .hiof) 108 + # and the file version 109 + self.fileExtension = self.hiofStream.readBytesAsString(IOCSRGrokker.IOCSR_FILE_EXTENSION_MAX_LEN) 110 + self.fileVersion = self.hiofStream.readUnsignedInt() 111 + 112 + # Now read the ptags 113 + # Device name is first 114 + self.programmerTag = self.hiofStream.readUnsignedShort() 115 + self.verifyRead(self.programmerTag, self.PTAG_DEVICE_NAME) 116 + self.deviceNameLength = self.hiofStream.readUnsignedInt() 117 + self.deviceName = self.hiofStream.readBytesAsString(self.deviceNameLength) 118 + 119 + # Basic information of the HIOF files 120 + # This is not used by the preloader generator, but we read it and ignore the 121 + # contents. 122 + programmerTag = self.hiofStream.readUnsignedShort() 123 + self.verifyRead(programmerTag, self.PTAG_HPS_IOCSR_INFO) 124 + basicHPSIOCSRInfoLength = self.hiofStream.readUnsignedInt() 125 + self.hiofStream.read(basicHPSIOCSRInfoLength) 126 + 127 + # Actual content of IOCSR information 128 + self.programmerTag1 = self.hiofStream.readUnsignedShort() 129 + self.verifyRead(self.programmerTag1, self.PTAG_HPS_IOCSR) 130 + self.HPSIOCSRLength1 = self.hiofStream.readUnsignedInt() 131 + self.HPSIOCSRBytes1 = self.hiofStream.read(self.HPSIOCSRLength1) 132 + self.HPSIOCSRDataLength1, self.HPSIOCSRData1 = IOCSRGrokker.getLengthData(self.HPSIOCSRBytes1) 133 + 134 + # Actual content of IOCSR information 135 + self.programmerTag2 = self.hiofStream.readUnsignedShort() 136 + self.verifyRead(self.programmerTag2, self.PTAG_HPS_IOCSR) 137 + self.HPSIOCSRLength2 = self.hiofStream.readUnsignedInt() 138 + self.HPSIOCSRBytes2 = self.hiofStream.read(self.HPSIOCSRLength2) 139 + self.HPSIOCSRDataLength2, self.HPSIOCSRData2 = IOCSRGrokker.getLengthData(self.HPSIOCSRBytes2) 140 + 141 + # Actual content of IOCSR information 142 + self.programmerTag3 = self.hiofStream.readUnsignedShort() 143 + self.verifyRead(self.programmerTag3, self.PTAG_HPS_IOCSR) 144 + self.HPSIOCSRLength3 = self.hiofStream.readUnsignedInt() 145 + self.HPSIOCSRBytes3 = self.hiofStream.read(self.HPSIOCSRLength3) 146 + self.HPSIOCSRDataLength3, self.HPSIOCSRData3 = IOCSRGrokker.getLengthData(self.HPSIOCSRBytes3) 147 + 148 + # Actual content of IOCSR information 149 + self.programmerTag4 = self.hiofStream.readUnsignedShort() 150 + self.verifyRead(self.programmerTag4, self.PTAG_HPS_IOCSR) 151 + self.HPSIOCSRLength4 = self.hiofStream.readUnsignedInt() 152 + self.HPSIOCSRBytes4 = self.hiofStream.read(self.HPSIOCSRLength4) 153 + self.HPSIOCSRDataLength4, self.HPSIOCSRData4 = IOCSRGrokker.getLengthData(self.HPSIOCSRBytes4) 154 + 155 + # Now we should see the end of the hiof input 156 + programmerTag = self.hiofStream.readUnsignedShort() 157 + if 8 != programmerTag: 158 + print ("I didn't find the end of the .hiof file when I expected to!") 159 + 160 + self.iocsrHeaderStream.write('#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH\t' +\ 161 + str(self.HPSIOCSRDataLength1) + '\n') 162 + self.iocsrHeaderStream.write('#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH\t' +\ 163 + str(self.HPSIOCSRDataLength2) + '\n') 164 + self.iocsrHeaderStream.write('#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH\t' +\ 165 + str(self.HPSIOCSRDataLength3) + '\n') 166 + self.iocsrHeaderStream.write('#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH\t' +\ 167 + str(self.HPSIOCSRDataLength4) + '\n') 168 + 169 + self.iocsrHeaderStream.write("\n") 170 + 171 + self.iocsrHeaderStream.write('const unsigned long iocsr_scan_chain0_table[] = {\n') 172 + for value in self.HPSIOCSRData1: 173 + hv = '0x%08X' % (value) 174 + self.iocsrHeaderStream.write('\t' + hv + ',\n') 175 + self.iocsrHeaderStream.write('};\n') 176 + self.iocsrHeaderStream.write('\n') 177 + 178 + self.iocsrHeaderStream.write('const unsigned long iocsr_scan_chain1_table[] = {\n') 179 + for value in self.HPSIOCSRData2: 180 + hv = '0x%08X' % (value) 181 + self.iocsrHeaderStream.write('\t' + hv + ',\n') 182 + self.iocsrHeaderStream.write('};\n') 183 + self.iocsrHeaderStream.write('\n') 184 + 185 + self.iocsrHeaderStream.write('const unsigned long iocsr_scan_chain2_table[] = {\n') 186 + for value in self.HPSIOCSRData3: 187 + hv = '0x%08X' % (value) 188 + self.iocsrHeaderStream.write('\t' + hv + ',\n') 189 + self.iocsrHeaderStream.write('};\n') 190 + self.iocsrHeaderStream.write('\n') 191 + 192 + self.iocsrHeaderStream.write('const unsigned long iocsr_scan_chain3_table[] = {\n') 193 + for value in self.HPSIOCSRData4: 194 + hv = '0x%08X' % (value) 195 + self.iocsrHeaderStream.write('\t' + hv + ',\n') 196 + self.iocsrHeaderStream.write('};\n') 197 + self.iocsrHeaderStream.write('\n\n') 198 + 199 + ret = self.iocsrHeaderStream.writeSentinelEnd(IOCSRGrokker.IOCSR_SENTINEL) 200 + if ret == -1: 201 + print("Empty header written. Exiting.") 202 + 203 + self.iocsrHeaderStream.close()
+114
tools/cv_bsp_generator/model.py
··· 1 + # SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 + """ 3 + Data models for XML files required for generating a preloader. 4 + 5 + These classes encapsulate the complexities of XML DOM in order to 6 + make retrieving data from XML files easier and more reliable. 7 + By shielding data model deserialization from data consumers, 8 + it'd be easier to switch to other formats such as JSON if required. 9 + 10 + There are some assumptions about how these XML files are structured 11 + such as the hierarchy of elements and ordering of attributes, these 12 + are relatively safe assumptions for as long as the XML files are 13 + always generated by HPS megawizard (isw.tcl) and are not hand-edited. 14 + 15 + Copyright (C) 2022 Intel Corporation <www.intel.com> 16 + 17 + Author: Lee, Kah Jing <kah.jing.lee@intel.com> 18 + """ 19 + import xml.dom.minidom 20 + 21 + def getSingletonElementByTagName(parent, tagName): 22 + """ 23 + Find tag by name and ensure that there is exactly one match 24 + """ 25 + nodes = parent.getElementsByTagName(tagName) 26 + 27 + if len(nodes) == 0: 28 + raise Exception("Can't find element: " + tagName) 29 + elif len(nodes) > 1: 30 + raise Exception("Unexpected multiple matches for singleton element: " + tagName) 31 + else: 32 + return nodes[0] 33 + 34 + class hps(object): 35 + """ 36 + Data model for hps.xml 37 + """ 38 + @staticmethod 39 + def create(file): 40 + """ hps model """ 41 + return hps(file) 42 + 43 + def __init__(self, file): 44 + """ hps model initialization """ 45 + self.dom = xml.dom.minidom.parse(file) 46 + 47 + try: 48 + # Look for <hps> node 49 + self.hpsNode = getSingletonElementByTagName(self.dom, "hps") 50 + # Look for <hps><system> node 51 + self.hpsSystemNode = getSingletonElementByTagName(self.hpsNode, "system") 52 + except Exception: 53 + raise Exception("Can't initialize from file: " + file) 54 + 55 + def getSystemConfig(self, param): 56 + """ parse system configuration tag """ 57 + hpsSystemConfigNode = None 58 + 59 + # Look for <hps><system><config ...> nodes 60 + for node in self.hpsSystemNode.getElementsByTagName("config"): 61 + # assume name is the first attribute as in <config name="..." ...> 62 + nameAttrNode = node.attributes.item(0) 63 + if nameAttrNode.nodeName == "name" and nameAttrNode.nodeValue == param: 64 + # assume value is the second attribute as in <config name="..." value="..."> 65 + valueAttrNode = node.attributes.item(1) 66 + if valueAttrNode.nodeName == "value": 67 + hpsSystemConfigNode = valueAttrNode 68 + break 69 + 70 + if hpsSystemConfigNode == None: 71 + raise ValueError("Can't find <hps><system><config> node: " + param) 72 + 73 + return hpsSystemConfigNode.nodeValue 74 + 75 + class emif(object): 76 + """ 77 + Data model for emif.xml. 78 + """ 79 + @staticmethod 80 + def create(file): 81 + """ emif model """ 82 + return emif(file) 83 + 84 + def __init__(self, file): 85 + """ emif model initialization """ 86 + self.dom = xml.dom.minidom.parse(file) 87 + 88 + try: 89 + # Look for <emif> node 90 + self.emifNode = getSingletonElementByTagName(self.dom, "emif") 91 + # Look for <emif><pll> node 92 + self.emifPllNode = getSingletonElementByTagName(self.emifNode, "pll") 93 + except Exception: 94 + raise Exception("Can't initialize from file: " + file) 95 + 96 + def getPllDefine(self, param): 97 + """ parse pll define tag """ 98 + emifPllDefineNode = None 99 + 100 + # Look for <emif><pll><define ...> nodes 101 + for node in self.emifPllNode.getElementsByTagName("define"): 102 + nameAttrNode = node.attributes.item(0) 103 + # assume name is the first attribute as in <define name="..." ...> 104 + if nameAttrNode.nodeName == "name" and nameAttrNode.nodeValue == param: 105 + # assume value is the second attribute as in <config name="..." value="..."> 106 + valueAttrNode = node.attributes.item(1) 107 + if valueAttrNode.nodeName == "value": 108 + emifPllDefineNode = valueAttrNode 109 + break 110 + 111 + if emifPllDefineNode == None: 112 + raise Exception("Can't find EMIF PLL define node: " + param) 113 + 114 + return emifPllDefineNode.nodeValue
+196
tools/cv_bsp_generator/renderer.py
··· 1 + # SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 + """ 3 + Document renderer class for preloader source files 4 + 5 + Each document renderer takes care of a full construction of 6 + a specific file format using the required data model. 7 + 8 + Copyright (C) 2022 Intel Corporation <www.intel.com> 9 + 10 + Author: Lee, Kah Jing <kah.jing.lee@intel.com> 11 + """ 12 + import collections 13 + import doc 14 + 15 + class pll_config_h: 16 + """ 17 + pll_config.h renderer. 18 + """ 19 + 20 + def __init__(self, hpsModel, emifModel): 21 + """ renderer initialization """ 22 + self.hpsModel = hpsModel 23 + self.emifModel = emifModel 24 + self.doc = doc.generated_c_source("__SOCFPGA_PLL_CONFIG_H__") 25 + 26 + def createContent(self): 27 + """ add the content based on settings parsed. eventually it will be 28 + written to pll_config.h file 29 + """ 30 + doc.c_source.line(self.doc) 31 + id = "CFG_HPS_DBCTRL_STAYOSC1" 32 + valueString = self.hpsModel.getSystemConfig("dbctrl_stayosc1") 33 + # Unfortunately hps.xml never tells us the data type of values 34 + # attributes. Here we workaround this type of problem, often 35 + # this is case-by-case, i.e. having to know which parameter that 36 + # we're dealing with, hence this ugly parameter-specific 37 + # if-statement needs here to workaround the data type inconsistency 38 + if valueString.lower() == "true": 39 + value = "1" 40 + else: 41 + value = "0" 42 + doc.c_source.define(self.doc, id, value ) 43 + doc.c_source.line(self.doc) 44 + self.addMainPllSettings() 45 + doc.c_source.line(self.doc) 46 + self.addPeriphPllSettings() 47 + doc.c_source.line(self.doc) 48 + self.addSdramPllSettings() 49 + doc.c_source.line(self.doc) 50 + self.addClockFreq() 51 + doc.c_source.line(self.doc) 52 + self.addAlteraSettings() 53 + doc.c_source.line(self.doc) 54 + 55 + def addMainPllSettings(self): 56 + """ add pll settings to the file """ 57 + paramMap = collections.OrderedDict() 58 + paramMap["VCO_DENOM"] = "main_pll_n" 59 + paramMap["VCO_NUMER"] = "main_pll_m" 60 + 61 + for key in paramMap.keys(): 62 + id = "CFG_HPS_MAINPLLGRP_" + key 63 + value = self.hpsModel.getSystemConfig(paramMap[key]) 64 + doc.c_source.define(self.doc, id, value ) 65 + 66 + # main_pll_c0, main_pll_c1, main_pll_c2 are fixed counters, 67 + doc.c_source.define(self.doc, "CFG_HPS_MAINPLLGRP_MPUCLK_CNT", "0") 68 + doc.c_source.define(self.doc, "CFG_HPS_MAINPLLGRP_MAINCLK_CNT", "0") 69 + doc.c_source.define(self.doc, "CFG_HPS_MAINPLLGRP_DBGATCLK_CNT", "0") 70 + 71 + paramMap = collections.OrderedDict() 72 + 73 + paramMap["MAINQSPICLK_CNT"] = "main_pll_c3" 74 + paramMap["MAINNANDSDMMCCLK_CNT"] = "main_pll_c4" 75 + paramMap["CFGS2FUSER0CLK_CNT"] = "main_pll_c5" 76 + paramMap["MAINDIV_L3MPCLK"] = "l3_mp_clk_div" 77 + paramMap["MAINDIV_L3SPCLK"] = "l3_sp_clk_div" 78 + paramMap["MAINDIV_L4MPCLK"] = "l4_mp_clk_div" 79 + paramMap["MAINDIV_L4SPCLK"] = "l4_sp_clk_div" 80 + paramMap["DBGDIV_DBGATCLK"] = "dbg_at_clk_div" 81 + paramMap["DBGDIV_DBGCLK"] = "dbg_clk_div" 82 + paramMap["TRACEDIV_TRACECLK"] = "dbg_trace_clk_div" 83 + paramMap["L4SRC_L4MP"] = "l4_mp_clk_source" 84 + paramMap["L4SRC_L4SP"] = "l4_sp_clk_source" 85 + 86 + for key in paramMap.keys(): 87 + id = "CFG_HPS_MAINPLLGRP_" + key 88 + value = self.hpsModel.getSystemConfig(paramMap[key]) 89 + doc.c_source.define(self.doc, id, value ) 90 + 91 + def addPeriphPllSettings(self): 92 + """ add peripheral pll settings to the file """ 93 + paramMap = collections.OrderedDict() 94 + paramMap["VCO_DENOM"] = "periph_pll_n" 95 + paramMap["VCO_NUMER"] = "periph_pll_m" 96 + paramMap["VCO_PSRC"] = "periph_pll_source" 97 + paramMap["EMAC0CLK_CNT"] = "periph_pll_c0" 98 + paramMap["EMAC1CLK_CNT"] = "periph_pll_c1" 99 + paramMap["PERQSPICLK_CNT"] = "periph_pll_c2" 100 + paramMap["PERNANDSDMMCCLK_CNT"] = "periph_pll_c3" 101 + paramMap["PERBASECLK_CNT"] = "periph_pll_c4" 102 + paramMap["S2FUSER1CLK_CNT"] = "periph_pll_c5" 103 + paramMap["DIV_USBCLK"] = "usb_mp_clk_div" 104 + paramMap["DIV_SPIMCLK"] = "spi_m_clk_div" 105 + paramMap["DIV_CAN0CLK"] = "can0_clk_div" 106 + paramMap["DIV_CAN1CLK"] = "can1_clk_div" 107 + paramMap["GPIODIV_GPIODBCLK"] = "gpio_db_clk_div" 108 + paramMap["SRC_SDMMC"] = "sdmmc_clk_source" 109 + paramMap["SRC_NAND"] = "nand_clk_source" 110 + paramMap["SRC_QSPI"] = "qspi_clk_source" 111 + 112 + for key in paramMap.keys(): 113 + id = "CFG_HPS_PERPLLGRP_" + key 114 + value = self.hpsModel.getSystemConfig(paramMap[key]) 115 + doc.c_source.define(self.doc, id, value ) 116 + 117 + def addSdramPllSettings(self): 118 + """ add sdram pll settings to the file """ 119 + value = self.emifModel.getPllDefine("PLL_MEM_CLK_DIV") 120 + doc.c_source.define(self.doc, "CFG_HPS_SDRPLLGRP_VCO_DENOM", value ) 121 + value = self.emifModel.getPllDefine("PLL_MEM_CLK_MULT") 122 + doc.c_source.define(self.doc, "CFG_HPS_SDRPLLGRP_VCO_NUMER", value ) 123 + doc.c_source.define(self.doc, "CFG_HPS_SDRPLLGRP_VCO_SSRC", "0") 124 + doc.c_source.define(self.doc, "CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT", "1") 125 + value = self.emifModel.getPllDefine("PLL_MEM_CLK_PHASE_DEG") 126 + doc.c_source.define(self.doc, "CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE", value ) 127 + doc.c_source.define(self.doc, "CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT", "0") 128 + doc.c_source.define(self.doc, "CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE", "0") 129 + doc.c_source.define(self.doc, "CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT", "1") 130 + value = self.emifModel.getPllDefine("PLL_WRITE_CLK_PHASE_DEG") 131 + doc.c_source.define(self.doc, "CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE", value ) 132 + 133 + try: 134 + value = self.hpsModel.getSystemConfig("sdram_pll_c5") 135 + except ValueError: 136 + value = "5" 137 + doc.c_source.define(self.doc, "CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT", value ) 138 + doc.c_source.define(self.doc, "CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE", "0") 139 + 140 + def addClockFreq(self): 141 + """ add clock frequency settings to the file """ 142 + paramMap = collections.OrderedDict() 143 + paramMap["OSC1"] = "eosc1_clk_hz" 144 + paramMap["OSC2"] = "eosc2_clk_hz" 145 + paramMap["F2S_SDR_REF"] = "F2SCLK_SDRAMCLK_FREQ" 146 + paramMap["F2S_PER_REF"] = "F2SCLK_PERIPHCLK_FREQ" 147 + paramMap["MAINVCO"] = "main_pll_vco_hz" 148 + paramMap["PERVCO"] = "periph_pll_vco_hz" 149 + 150 + for key in paramMap.keys(): 151 + id = "CFG_HPS_CLK_" + key + "_HZ" 152 + value = self.hpsModel.getSystemConfig(paramMap[key]) 153 + doc.c_source.define(self.doc, id, value ) 154 + 155 + eosc1 = int(self.hpsModel.getSystemConfig("eosc1_clk_hz")) 156 + eosc2 = int(self.hpsModel.getSystemConfig("eosc2_clk_hz")) 157 + m = int(self.emifModel.getPllDefine("PLL_MEM_CLK_MULT")) 158 + n = int(self.emifModel.getPllDefine("PLL_MEM_CLK_DIV")) 159 + vco = int(round(eosc1 * (m + 1) / (n + 1))) 160 + doc.c_source.define(self.doc, "CFG_HPS_CLK_SDRVCO_HZ", str(vco) ) 161 + 162 + paramMap = collections.OrderedDict() 163 + paramMap["EMAC0"] = "emac0_clk_hz" 164 + paramMap["EMAC1"] = "emac1_clk_hz" 165 + paramMap["USBCLK"] = "usb_mp_clk_hz" 166 + paramMap["NAND"] = "nand_clk_hz" 167 + paramMap["SDMMC"] = "sdmmc_clk_hz" 168 + paramMap["QSPI"] = "qspi_clk_hz" 169 + paramMap["SPIM"] = "spi_m_clk_hz" 170 + paramMap["CAN0"] = "can0_clk_hz" 171 + paramMap["CAN1"] = "can1_clk_hz" 172 + paramMap["GPIODB"] = "gpio_db_clk_hz" 173 + paramMap["L4_MP"] = "l4_mp_clk_hz" 174 + paramMap["L4_SP"] = "l4_sp_clk_hz" 175 + 176 + for key in paramMap.keys(): 177 + id = "CFG_HPS_CLK_" + key + "_HZ" 178 + value = self.hpsModel.getSystemConfig(paramMap[key]) 179 + doc.c_source.define(self.doc, id, value ) 180 + 181 + def addAlteraSettings(self): 182 + """ add Altera-related settings to the file """ 183 + paramMap = collections.OrderedDict() 184 + paramMap["MPUCLK"] = "main_pll_c0_internal" 185 + paramMap["MAINCLK"] = "main_pll_c1_internal" 186 + paramMap["DBGATCLK"] = "main_pll_c2_internal" 187 + 188 + for key in paramMap.keys(): 189 + id = "CFG_HPS_ALTERAGRP_" + key 190 + value = self.hpsModel.getSystemConfig(paramMap[key]) 191 + doc.c_source.define(self.doc, id, value ) 192 + 193 + def __str__(self): 194 + """ convert to string """ 195 + self.createContent() 196 + return str(self.doc)
+5
tools/cv_bsp_generator/requirements.txt
··· 1 + # requirements.txt for cv_bsp_generator.py 2 + # All dependencies are either standard library modules 3 + # or local Python files included in this BSP tool. 4 + # No external pip packages are required. 5 +
+102
tools/cv_bsp_generator/streamer.py
··· 1 + # SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 + """ 3 + Generate license, file header and close tag. 4 + 5 + Copyright (C) 2022 Intel Corporation <www.intel.com> 6 + 7 + Author: Lee, Kah Jing <kah.jing.lee@intel.com> 8 + """ 9 + import os 10 + import struct 11 + import doc 12 + 13 + class Streamer(object): 14 + """ Streamer class to generate license, header, and close tag. 15 + """ 16 + def __init__(self, fileName, mode='r'): 17 + """ Streamer initialization """ 18 + self.fileName = fileName 19 + self.mode = mode 20 + self.file = None 21 + self.sentinel = None 22 + if '+' in mode or 'w' in mode or 'a' in mode: 23 + self.fileMode = 'write' 24 + else: 25 + self.fileMode = 'read' 26 + 27 + def close(self): 28 + """ file close """ 29 + if self.file != None: 30 + self.file.close() 31 + self.file = None 32 + 33 + def open(self): 34 + """ file open """ 35 + if self.fileName != None: 36 + if self.file == None: 37 + if self.fileMode == 'write': 38 + print ("Generating file: %s..." % self.fileName) 39 + else: 40 + print ("Reading file: %s..." % self.fileName) 41 + self.file = open(self.fileName, self.mode) 42 + 43 + def read(self, numBytes): 44 + """ file read number of bytes """ 45 + if self.file == None: 46 + print ("***Error: Attempted to read from unopened file %s" \ 47 + % (self.fileName)) 48 + exit(-1) 49 + 50 + else: 51 + return self.file.read(numBytes) 52 + 53 + def readUnsignedInt(self): 54 + """ read unsigned integer """ 55 + return struct.unpack('I', self.read(4))[0] 56 + 57 + def readUnsignedShort(self): 58 + """ read unsigned short """ 59 + return struct.unpack('H', self.read(2))[0] 60 + 61 + def readBytesAsString(self, numBytes): 62 + """ Read some bytes from a binary file 63 + and interpret the data values as a String 64 + """ 65 + bytes = self.read(numBytes) 66 + s = bytes.decode('utf-8') 67 + 68 + return s 69 + 70 + def write(self, str): 71 + """ file write """ 72 + if self.file == None: 73 + print ("***Error: Attempted to write to unopened file %s" \ 74 + % (self.fileName)) 75 + exit(-1) 76 + 77 + else: 78 + self.file.write("%s" % str) 79 + 80 + def writeLicenseHeader(self): 81 + """ write license & copyright """ 82 + # format the license header 83 + licenseHeader = "/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */\n" 84 + self.file.write("%s" % licenseHeader) 85 + copyrightHeader = "/*\n * Copyright (C) 2022 Intel Corporation <www.intel.com>\n *\n */\n" 86 + self.file.write("%s" % copyrightHeader) 87 + 88 + def writeSentinelStart(self, sentinel): 89 + """ start header """ 90 + if sentinel == None: 91 + return -1 92 + self.sentinel = sentinel 93 + self.file.write("%s\n%s\n\n" % (\ 94 + "#ifndef " + self.sentinel, 95 + "#define " + self.sentinel)) 96 + 97 + def writeSentinelEnd(self, sentinel): 98 + """ end header """ 99 + if sentinel == None: 100 + return -1 101 + self.sentinel = sentinel 102 + self.file.write("\n%s\n" % ("#endif /* " + self.sentinel + " */"))
+32
tools/cv_bsp_generator/xmlgrok.py
··· 1 + # SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 + """ 3 + XML node parser 4 + 5 + Copyright (C) 2022 Intel Corporation <www.intel.com> 6 + 7 + Author: Lee, Kah Jing <kah.jing.lee@intel.com> 8 + """ 9 + import xml.dom 10 + 11 + def isElementNode(XMLNode): 12 + """ check if the node is element node """ 13 + return XMLNode.nodeType == xml.dom.Node.ELEMENT_NODE 14 + 15 + def firstElementChild(XMLNode): 16 + """ Calling firstChild on an Node of type Element often (always?) 17 + returns a Node of Text type. How annoying! Return the first Element 18 + child 19 + """ 20 + child = XMLNode.firstChild 21 + while child != None and not isElementNode(child): 22 + child = nextElementSibling(child) 23 + return child 24 + 25 + def nextElementSibling(XMLNode): 26 + """ nextElementSibling will return the next sibling of XMLNode that is 27 + an Element Node Type 28 + """ 29 + sib = XMLNode.nextSibling 30 + while sib != None and not isElementNode(sib): 31 + sib = sib.nextSibling 32 + return sib
+1
tools/docker/Dockerfile
··· 129 129 python3-pip \ 130 130 python3-pyelftools \ 131 131 python3-sphinx \ 132 + python3-tk \ 132 133 python3-tomli \ 133 134 python3-venv \ 134 135 rpm2cpio \
+280
tools/logos/u-boot_logo_with_text.svg
··· 1 + <?xml version="1.0" encoding="UTF-8" standalone="no"?> 2 + <!-- SPDX-License-Identifier: CC-BY-SA-4.0 --> 3 + 4 + <!-- Copyright (c) 2018, Heinrich Schuchardt <xypron.glpk@gmx.de> --> 5 + 6 + <svg 7 + xmlns:dc="http://purl.org/dc/elements/1.1/" 8 + xmlns:cc="http://creativecommons.org/ns#" 9 + xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" 10 + xmlns:svg="http://www.w3.org/2000/svg" 11 + xmlns="http://www.w3.org/2000/svg" 12 + xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd" 13 + xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape" 14 + width="186" 15 + height="244" 16 + viewBox="0 0 186 244" 17 + id="svg2" 18 + version="1.1" 19 + inkscape:version="0.92.4 (5da689c313, 2019-01-14)" 20 + sodipodi:docname="u-boot_logo.svg" 21 + inkscape:export-filename="tools/logos/u-boot_logo.png" 22 + inkscape:export-xdpi="41.290001" 23 + inkscape:export-ydpi="41.290001"> 24 + <title 25 + id="title30">U-Boot Logo</title> 26 + <metadata 27 + id="metadata31"> 28 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