"Das U-Boot" Source Tree
rockchip: rk3128: Switch to TPL/SPL
Signed-off-by: Alex Bee <knaerzche@gmail.com>
+208
-1
+61
arch/arm/dts/rk3128-u-boot.dtsi
+61
arch/arm/dts/rk3128-u-boot.dtsi
···
3
3
#include "rockchip-u-boot.dtsi"
4
4
5
5
/ {
6
+
chosen {
7
+
u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
8
+
};
9
+
6
10
dmc: dmc@20004000 {
7
11
compatible = "rockchip,rk3128-dmc", "syscon";
8
12
reg = <0x0 0x20004000 0x0 0x1000>;
···
23
27
fifo-mode;
24
28
};
25
29
30
+
&emmc_clk {
31
+
bootph-pre-ram;
32
+
bootph-some-ram;
33
+
};
34
+
35
+
&emmc_cmd {
36
+
bootph-pre-ram;
37
+
bootph-some-ram;
38
+
};
39
+
40
+
&emmc_pwr {
41
+
bootph-pre-ram;
42
+
bootph-some-ram;
43
+
};
44
+
45
+
&emmc_bus8 {
46
+
bootph-pre-ram;
47
+
bootph-some-ram;
48
+
};
49
+
50
+
&gpio1 {
51
+
bootph-pre-ram;
52
+
bootph-some-ram;
53
+
};
54
+
26
55
&grf {
27
56
bootph-all;
28
57
};
···
40
69
};
41
70
42
71
&sdmmc {
72
+
bootph-pre-ram;
73
+
bootph-some-ram;
43
74
fifo-mode;
75
+
};
76
+
77
+
&sdmmc_clk {
78
+
bootph-pre-ram;
79
+
bootph-some-ram;
80
+
};
81
+
82
+
&sdmmc_cmd {
83
+
bootph-pre-ram;
84
+
bootph-some-ram;
85
+
};
86
+
87
+
&sdmmc_det {
88
+
bootph-pre-ram;
89
+
bootph-some-ram;
90
+
};
91
+
92
+
&sdmmc_wp {
93
+
bootph-pre-ram;
94
+
bootph-some-ram;
95
+
};
96
+
97
+
&sdmmc_pwren {
98
+
bootph-pre-ram;
99
+
bootph-some-ram;
100
+
};
101
+
102
+
&sdmmc_bus4 {
103
+
bootph-pre-ram;
104
+
bootph-some-ram;
44
105
};
45
106
46
107
&uart0 {
+28
arch/arm/mach-rockchip/Kconfig
+28
arch/arm/mach-rockchip/Kconfig
···
73
73
select PINCTRL
74
74
select RAM
75
75
select REGMAP
76
+
select SUPPORT_SPL
76
77
select SYSCON
77
78
select SYS_ARCH_TIMER
79
+
select SUPPORT_TPL
78
80
imply BOOTSTD_FULL
79
81
imply MISC
80
82
imply MISC_INIT_R
···
83
85
imply ROCKCHIP_SDRAM_COMMON
84
86
imply SKIP_LOWLEVEL_INIT
85
87
imply OF_UPSTREAM
88
+
imply SPL
89
+
imply SPL_SERIAL
90
+
imply SPL_ROCKCHIP_COMMON_BOARD
91
+
imply SPL_SYS_MALLOC_F
92
+
imply SPL_SYS_MALLOC_SIMPLE
93
+
imply SPL_LIBCOMMON_SUPPORT
94
+
imply SPL_LIBGENERIC_SUPPORT
95
+
imply SPL_RAM
96
+
imply SPL_CLK
97
+
imply SPL_DM_SEQ_ALIAS
98
+
select SPL_LOAD_FIT
99
+
imply SPL_FIT_SIGNATURE
100
+
imply SPL_PINCTRL
101
+
imply SPL_RAM
102
+
imply SPL_REGMAP
103
+
imply SPL_SERIAL
104
+
imply SPL_SYSCON
105
+
imply SPL_OF_CONTROL
106
+
imply TPL if !ROCKCHIP_EXTERNAL_TPL
107
+
imply TPL_LIBGENERIC_SUPPORT if TPL
108
+
imply TPL_NEEDS_SEPARATE_STACK if TPL
109
+
imply TPL_RAM if TPL
110
+
imply TPL_ROCKCHIP_BACK_TO_BROM if TPL
111
+
imply TPL_SERIAL if TPL
112
+
imply TPL_TINY_MEMSET if TPL
113
+
imply TPL_SKIP_LOWLEVEL_INIT_ONLY if TPL
86
114
help
87
115
The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
88
116
including NEON and GPU, Mali-400 graphics, several DDR3 options
+1
arch/arm/mach-rockchip/Makefile
+1
arch/arm/mach-rockchip/Makefile
···
12
12
obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
13
13
obj-tpl-$(CONFIG_TPL_ROCKCHIP_COMMON_BOARD) += tpl.o spl_common.o
14
14
obj-tpl-$(CONFIG_ROCKCHIP_PX30) += px30-board-tpl.o
15
+
obj-tpl-$(CONFIG_ROCKCHIP_RK3128) += rk3128-board-tpl.o spl_common.o
15
16
16
17
obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
17
18
+66
arch/arm/mach-rockchip/rk3128-board-tpl.c
+66
arch/arm/mach-rockchip/rk3128-board-tpl.c
···
1
+
// SPDX-License-Identifier: GPL-2.0+
2
+
3
+
#include <debug_uart.h>
4
+
#include <init.h>
5
+
#include <ram.h>
6
+
#include <spl.h>
7
+
#include <asm/io.h>
8
+
#include <asm/arch-rockchip/bootrom.h>
9
+
#include <asm/arch-rockchip/sdram_rk3128.h>
10
+
#include <asm/arch-rockchip/timer.h>
11
+
12
+
#if CONFIG_IS_ENABLED(BANNER_PRINT) && !IS_ENABLED(CONFIG_RAM_ROCKCHIP_DEBUG)
13
+
#include <timestamp.h>
14
+
#include <version.h>
15
+
#endif
16
+
17
+
__weak void get_dram_config(enum rk3128_dram_config *dram_config)
18
+
{
19
+
printascii("\nDefine get_dram_config!\n");
20
+
*dram_config = DRAM_INVALID;
21
+
}
22
+
23
+
__weak void tpl_board_init(void)
24
+
{
25
+
}
26
+
27
+
void board_init_f(ulong dummy)
28
+
{
29
+
#if IS_ENABLED(CONFIG_DEBUG_UART) && CONFIG_IS_ENABLED(SERIAL)
30
+
/*
31
+
* Debug UART can be used from here if required:
32
+
*
33
+
* debug_uart_init();
34
+
* printch('a');
35
+
* printhex8(0x1234);
36
+
* printascii("string");
37
+
*/
38
+
debug_uart_init();
39
+
40
+
#if CONFIG_IS_ENABLED(BANNER_PRINT) && !IS_ENABLED(CONFIG_RAM_ROCKCHIP_DEBUG)
41
+
printascii("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - " U_BOOT_TIME ")\n");
42
+
#endif
43
+
#endif
44
+
45
+
/* Init secure timer */
46
+
rockchip_stimer_init();
47
+
48
+
/* Init ARM arch timer */
49
+
timer_init();
50
+
51
+
if (CONFIG_IS_ENABLED(BOARD_INIT))
52
+
tpl_board_init();
53
+
54
+
if (CONFIG_IS_ENABLED(RAM)) {
55
+
enum rk3128_dram_config dram_config = DRAM_INVALID;
56
+
57
+
get_dram_config(&dram_config);
58
+
59
+
if (dram_config >= DRAM_INVALID ||
60
+
rk3128_sdram_init(dram_config))
61
+
printascii("\nDRAM init failed\n");
62
+
}
63
+
64
+
/* Return to bootrom */
65
+
back_to_bootrom(BROM_BOOT_NEXTSTAGE);
66
+
}
+51
arch/arm/mach-rockchip/rk3128/Kconfig
+51
arch/arm/mach-rockchip/rk3128/Kconfig
···
19
19
config ROCKCHIP_STIMER_BASE
20
20
default 0x200440a0
21
21
22
+
config RAM_ROCKCHIP_DEBUG
23
+
default n
24
+
25
+
config SPL_SYS_MALLOC_F_LEN
26
+
default 0x8000
27
+
28
+
config SPL_STACK_R
29
+
default y
30
+
31
+
config SPL_STACK_R_MALLOC_SIMPLE_LEN
32
+
default 0x200000
33
+
34
+
config SPL_TEXT_BASE
35
+
default 0x60000000
36
+
37
+
config SPL_BSS_START_ADDR
38
+
default 0x63f80000
39
+
40
+
config SPL_BSS_MAX_SIZE
41
+
default 0x8000
42
+
43
+
config SPL_STACK_R
44
+
default y
45
+
46
+
config SPL_STACK_R_ADDR
47
+
default 0x63e00000
48
+
49
+
config SPL_PAD_TO
50
+
default 0x7f8000
51
+
52
+
config OF_SPL_REMOVE_PROPS
53
+
default "clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
54
+
22
55
config SYS_SOC
23
56
default "rk3128"
24
57
25
58
config SYS_MALLOC_F_LEN
26
59
default 0x10000
60
+
61
+
config TEXT_BASE
62
+
default 0x60020000
63
+
64
+
config TPL_FRAMEWORK
65
+
default n if TPL
66
+
67
+
config TPL_MAX_SIZE
68
+
default 0x1800 if TPL
69
+
70
+
config TPL_STACK
71
+
default 0x10082000 if TPL
72
+
73
+
config TPL_TEXT_BASE
74
+
default 0x10080800 if TPL
75
+
76
+
config TPL_SYS_MALLOC_F_LEN
77
+
default 0x0 if TPL
27
78
28
79
config CUSTOM_SYS_INIT_SP_ADDR
29
80
default 0x63f00000
+1
-1
configs/evb-rk3128_defconfig
+1
-1
configs/evb-rk3128_defconfig
···
1
1
CONFIG_ARM=y
2
2
CONFIG_ARCH_ROCKCHIP=y
3
-
CONFIG_TEXT_BASE=0x60000000
4
3
CONFIG_NR_DRAM_BANKS=2
5
4
CONFIG_SF_DEFAULT_SPEED=20000000
6
5
CONFIG_ENV_OFFSET=0x0
7
6
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3128-evb"
8
7
CONFIG_ROCKCHIP_RK3128=y
8
+
CONFIG_ROCKCHIP_EXTERNAL_TPL=y
9
9
CONFIG_SYS_BOOTM_LEN=0x4000000
10
10
CONFIG_SYS_LOAD_ADDR=0x60800800
11
11
CONFIG_DEBUG_UART_BASE=0x20068000