Merge tag 'mmc-for-2026.04-rc2' of https://source.denx.de/u-boot/custodians/u-boot-mmc

+32 -23

cmd/mmc.c

··· 16 16 #include <sparse_format.h> 17 17 #include <image-sparse.h> 18 18 #include <vsprintf.h> 19 + #include <linux/compiler_attributes.h> 19 20 #include <linux/ctype.h> 20 21 21 22 static int curr_device = -1; ··· 556 557 static int do_mmc_dev(struct cmd_tbl *cmdtp, int flag, 557 558 int argc, char *const argv[]) 558 559 { 559 - int dev, part = 0, ret; 560 + enum bus_mode speed_mode = MMC_MODES_END; 561 + int dev = curr_device, part = 0, ret; 562 + char *endp; 560 563 struct mmc *mmc; 561 564 562 - if (argc == 1) { 563 - dev = curr_device; 564 - mmc = init_mmc_device(dev, true); 565 - } else if (argc == 2) { 566 - dev = (int)dectoul(argv[1], NULL); 567 - mmc = init_mmc_device(dev, true); 568 - } else if (argc == 3) { 569 - dev = (int)dectoul(argv[1], NULL); 570 - part = (int)dectoul(argv[2], NULL); 571 - if (part > PART_ACCESS_MASK) { 572 - printf("#part_num shouldn't be larger than %d\n", 573 - PART_ACCESS_MASK); 574 - return CMD_RET_FAILURE; 565 + switch (argc) { 566 + case 4: 567 + speed_mode = (int)dectoul(argv[3], &endp); 568 + if (*endp) { 569 + printf("Invalid speed mode index '%s', did you specify a mode name?\n", 570 + argv[3]); 571 + return CMD_RET_USAGE; 575 572 } 576 - mmc = init_mmc_device(dev, true); 577 - } else if (argc == 4) { 578 - enum bus_mode speed_mode; 579 573 580 - dev = (int)dectoul(argv[1], NULL); 581 - part = (int)dectoul(argv[2], NULL); 582 - if (part > PART_ACCESS_MASK) { 574 + fallthrough; 575 + case 3: 576 + part = (int)dectoul(argv[2], &endp); 577 + if (*endp) { 578 + printf("Invalid part number '%s'\n", argv[2]); 579 + return CMD_RET_USAGE; 580 + } else if (part > PART_ACCESS_MASK) { 583 581 printf("#part_num shouldn't be larger than %d\n", 584 582 PART_ACCESS_MASK); 585 583 return CMD_RET_FAILURE; 586 584 } 587 - speed_mode = (int)dectoul(argv[3], NULL); 585 + 586 + fallthrough; 587 + case 2: 588 + dev = (int)dectoul(argv[1], &endp); 589 + if (*endp) { 590 + printf("Invalid device number '%s'\n", argv[1]); 591 + return CMD_RET_USAGE; 592 + } 593 + 594 + fallthrough; 595 + case 1: 588 596 mmc = __init_mmc_device(dev, true, speed_mode); 589 - } else { 597 + break; 598 + default: 590 599 return CMD_RET_USAGE; 591 600 } 592 601 ··· 597 606 printf("switch to partitions #%d, %s\n", 598 607 part, (!ret) ? "OK" : "ERROR"); 599 608 if (ret) 600 - return 1; 609 + return CMD_RET_FAILURE; 601 610 602 611 curr_device = dev; 603 612 if (mmc->part_config == MMCPART_NOAVAILABLE)

+3 -3

drivers/mmc/mmc.c

··· 889 889 return ret; 890 890 891 891 /* 892 - * In cases when neiter allowed to poll by using CMD13 nor we are 892 + * In cases when neither allowed to poll by using CMD13 nor we are 893 893 * capable of polling by using mmc_wait_dat0, then rely on waiting the 894 894 * stated timeout to be sufficient. 895 895 */ ··· 1663 1663 return 4; 1664 1664 if (cap == MMC_MODE_1BIT) 1665 1665 return 1; 1666 - pr_warn("invalid bus witdh capability 0x%x\n", cap); 1666 + pr_warn("invalid bus width capability 0x%x\n", cap); 1667 1667 return 0; 1668 1668 } 1669 1669 ··· 2200 2200 return 0; 2201 2201 2202 2202 if (!mmc->ext_csd) { 2203 - pr_debug("No ext_csd found!\n"); /* this should enver happen */ 2203 + pr_debug("No ext_csd found!\n"); /* this should never happen */ 2204 2204 return -ENOTSUPP; 2205 2205 } 2206 2206

+301 -218

drivers/mmc/mtk-sd.c

··· 7 7 */ 8 8 9 9 #include <clk.h> 10 + #include <cpu_func.h> 10 11 #include <dm.h> 11 12 #include <mmc.h> 12 13 #include <errno.h> ··· 14 15 #include <mapmem.h> 15 16 #include <stdbool.h> 16 17 #include <asm/gpio.h> 18 + #include <asm/types.h> 17 19 #include <dm/device_compat.h> 18 20 #include <dm/pinctrl.h> 21 + #include <linux/bitfield.h> 19 22 #include <linux/bitops.h> 20 23 #include <linux/io.h> 21 24 #include <linux/iopoll.h> ··· 23 26 24 27 /* MSDC_CFG */ 25 28 #define MSDC_CFG_HS400_CK_MODE_EXT BIT(22) 26 - #define MSDC_CFG_CKMOD_EXT_M 0x300000 27 - #define MSDC_CFG_CKMOD_EXT_S 20 28 - #define MSDC_CFG_CKDIV_EXT_M 0xfff00 29 - #define MSDC_CFG_CKDIV_EXT_S 8 29 + #define MSDC_CFG_CKMOD_EXT GENMASK(21, 20) 30 + #define MSDC_CFG_CKDIV_EXT GENMASK(19, 8) 30 31 #define MSDC_CFG_HS400_CK_MODE BIT(18) 31 - #define MSDC_CFG_CKMOD_M 0x30000 32 - #define MSDC_CFG_CKMOD_S 16 33 - #define MSDC_CFG_CKDIV_M 0xff00 34 - #define MSDC_CFG_CKDIV_S 8 32 + #define MSDC_CFG_CKMOD GENMASK(17, 16) 33 + #define MSDC_CFG_CKDIV GENMASK(15, 8) 35 34 #define MSDC_CFG_CKSTB BIT(7) 36 35 #define MSDC_CFG_PIO BIT(3) 37 36 #define MSDC_CFG_RST BIT(2) ··· 45 44 46 45 /* MSDC_PS */ 47 46 #define MSDC_PS_DAT0 BIT(16) 48 - #define MSDC_PS_CDDBCE_M 0xf000 49 - #define MSDC_PS_CDDBCE_S 12 47 + #define MSDC_PS_CDDBCE GENMASK(15, 12) 50 48 #define MSDC_PS_CDSTS BIT(1) 51 49 #define MSDC_PS_CDEN BIT(0) 52 50 ··· 60 58 #define MSDC_INT_XFER_COMPL BIT(12) 61 59 #define MSDC_INT_DATTMO BIT(14) 62 60 #define MSDC_INT_DATCRCERR BIT(15) 61 + #define MSDC_INT_BDCSERR BIT(17) 62 + #define MSDC_INT_GPDCSERR BIT(18) 63 63 64 64 /* MSDC_FIFOCS */ 65 65 #define MSDC_FIFOCS_CLR BIT(31) 66 - #define MSDC_FIFOCS_TXCNT_M 0xff0000 67 - #define MSDC_FIFOCS_TXCNT_S 16 68 - #define MSDC_FIFOCS_RXCNT_M 0xff 69 - #define MSDC_FIFOCS_RXCNT_S 0 66 + #define MSDC_FIFOCS_TXCNT GENMASK(23, 16) 67 + #define MSDC_FIFOCS_RXCNT GENMASK(7, 0) 70 68 71 69 /* #define SDC_CFG */ 72 - #define SDC_CFG_DTOC_M 0xff000000 73 - #define SDC_CFG_DTOC_S 24 70 + #define SDC_CFG_DTOC GENMASK(31, 24) 74 71 #define SDC_CFG_SDIOIDE BIT(20) 75 72 #define SDC_CFG_SDIO BIT(19) 76 - #define SDC_CFG_BUSWIDTH_M 0x30000 77 - #define SDC_CFG_BUSWIDTH_S 16 73 + #define SDC_CFG_BUSWIDTH GENMASK(17, 16) 78 74 79 75 /* SDC_CMD */ 80 - #define SDC_CMD_BLK_LEN_M 0xfff0000 81 - #define SDC_CMD_BLK_LEN_S 16 76 + #define SDC_CMD_BLK_LEN GENMASK(27, 16) 82 77 #define SDC_CMD_STOP BIT(14) 83 78 #define SDC_CMD_WR BIT(13) 84 - #define SDC_CMD_DTYPE_M 0x1800 85 - #define SDC_CMD_DTYPE_S 11 86 - #define SDC_CMD_RSPTYP_M 0x380 87 - #define SDC_CMD_RSPTYP_S 7 88 - #define SDC_CMD_CMD_M 0x3f 89 - #define SDC_CMD_CMD_S 0 79 + #define SDC_CMD_DTYPE GENMASK(12, 11) 80 + #define SDC_CMD_RSPTYP GENMASK(9, 7) 81 + #define SDC_CMD_CMD GENMASK(5, 0) 90 82 91 83 /* SDC_STS */ 92 84 #define SDC_STS_CMDBUSY BIT(1) ··· 95 87 /* SDC_ADV_CFG0 */ 96 88 #define SDC_RX_ENHANCE_EN BIT(20) 97 89 90 + /* MSDC_DMA_CTRL */ 91 + #define MSDC_DMA_CTRL_BURSTSZ GENMASK(14, 12) 92 + #define MSDC_DMA_CTRL_LASTBUF BIT(10) 93 + #define MSDC_DMA_CTRL_MODE BIT(8) 94 + #define MSDC_DMA_CTRL_STOP BIT(1) 95 + #define MSDC_DMA_CTRL_START BIT(0) 96 + 97 + /* DMA_CFG */ 98 + #define MSDC_DMA_CFG_STS BIT(0) 99 + 98 100 /* PATCH_BIT0 */ 99 - #define MSDC_INT_DAT_LATCH_CK_SEL_M 0x380 100 - #define MSDC_INT_DAT_LATCH_CK_SEL_S 7 101 + #define MSDC_INT_DAT_LATCH_CK_SEL GENMASK(9, 7) 101 102 102 103 /* PATCH_BIT1 */ 103 - #define MSDC_PB1_STOP_DLY_M 0xf00 104 - #define MSDC_PB1_STOP_DLY_S 8 104 + #define MSDC_PB1_STOP_DLY GENMASK(11, 8) 105 105 106 106 /* PATCH_BIT2 */ 107 - #define MSDC_PB2_CRCSTSENSEL_M 0xe0000000 108 - #define MSDC_PB2_CRCSTSENSEL_S 29 107 + #define MSDC_PB2_CRCSTSENSEL GENMASK(31, 29) 109 108 #define MSDC_PB2_CFGCRCSTS BIT(28) 110 - #define MSDC_PB2_RESPSTSENSEL_M 0x70000 111 - #define MSDC_PB2_RESPSTSENSEL_S 16 109 + #define MSDC_PB2_RESPSTSENSEL GENMASK(18, 16) 112 110 #define MSDC_PB2_CFGRESP BIT(15) 113 - #define MSDC_PB2_RESPWAIT_M 0x0c 114 - #define MSDC_PB2_RESPWAIT_S 2 111 + #define MSDC_PB2_RESPWAIT GENMASK(3, 2) 115 112 116 113 /* MSDC_PAD_CTRL0 */ 117 - #define MSDC_PAD_CTRL0_CLKRDSEL_M 0xff000000 118 - #define MSDC_PAD_CTRL0_CLKRDSEL_S 24 114 + #define MSDC_PAD_CTRL0_CLKRDSEL GENMASK(31, 24) 119 115 #define MSDC_PAD_CTRL0_CLKTDSEL BIT(20) 120 116 #define MSDC_PAD_CTRL0_CLKIES BIT(19) 121 117 #define MSDC_PAD_CTRL0_CLKSMT BIT(18) 122 118 #define MSDC_PAD_CTRL0_CLKPU BIT(17) 123 119 #define MSDC_PAD_CTRL0_CLKPD BIT(16) 124 120 #define MSDC_PAD_CTRL0_CLKSR BIT(8) 125 - #define MSDC_PAD_CTRL0_CLKDRVP_M 0x70 126 - #define MSDC_PAD_CTRL0_CLKDRVP_S 4 127 - #define MSDC_PAD_CTRL0_CLKDRVN_M 0x7 128 - #define MSDC_PAD_CTRL0_CLKDRVN_S 0 121 + #define MSDC_PAD_CTRL0_CLKDRVP GENMASK(6, 4) 122 + #define MSDC_PAD_CTRL0_CLKDRVN GENMASK(2, 0) 129 123 130 124 /* MSDC_PAD_CTRL1 */ 131 - #define MSDC_PAD_CTRL1_CMDRDSEL_M 0xff000000 132 - #define MSDC_PAD_CTRL1_CMDRDSEL_S 24 125 + #define MSDC_PAD_CTRL1_CMDRDSEL GENMASK(31, 24) 133 126 #define MSDC_PAD_CTRL1_CMDTDSEL BIT(20) 134 127 #define MSDC_PAD_CTRL1_CMDIES BIT(19) 135 128 #define MSDC_PAD_CTRL1_CMDSMT BIT(18) 136 129 #define MSDC_PAD_CTRL1_CMDPU BIT(17) 137 130 #define MSDC_PAD_CTRL1_CMDPD BIT(16) 138 131 #define MSDC_PAD_CTRL1_CMDSR BIT(8) 139 - #define MSDC_PAD_CTRL1_CMDDRVP_M 0x70 140 - #define MSDC_PAD_CTRL1_CMDDRVP_S 4 141 - #define MSDC_PAD_CTRL1_CMDDRVN_M 0x7 142 - #define MSDC_PAD_CTRL1_CMDDRVN_S 0 143 - 132 + #define MSDC_PAD_CTRL1_CMDDRVP GENMASK(6, 4) 133 + #define MSDC_PAD_CTRL1_CMDDRVN GENMASK(2, 0) 144 134 /* MSDC_PAD_CTRL2 */ 145 - #define MSDC_PAD_CTRL2_DATRDSEL_M 0xff000000 146 - #define MSDC_PAD_CTRL2_DATRDSEL_S 24 135 + #define MSDC_PAD_CTRL2_DATRDSEL GENMASK(31, 24) 147 136 #define MSDC_PAD_CTRL2_DATTDSEL BIT(20) 148 137 #define MSDC_PAD_CTRL2_DATIES BIT(19) 149 138 #define MSDC_PAD_CTRL2_DATSMT BIT(18) 150 139 #define MSDC_PAD_CTRL2_DATPU BIT(17) 151 140 #define MSDC_PAD_CTRL2_DATPD BIT(16) 152 141 #define MSDC_PAD_CTRL2_DATSR BIT(8) 153 - #define MSDC_PAD_CTRL2_DATDRVP_M 0x70 154 - #define MSDC_PAD_CTRL2_DATDRVP_S 4 155 - #define MSDC_PAD_CTRL2_DATDRVN_M 0x7 156 - #define MSDC_PAD_CTRL2_DATDRVN_S 0 142 + #define MSDC_PAD_CTRL2_DATDRVP GENMASK(6, 4) 143 + #define MSDC_PAD_CTRL2_DATDRVN GENMASK(2, 0) 157 144 158 145 /* PAD_TUNE */ 159 - #define MSDC_PAD_TUNE_CLKTDLY_M 0xf8000000 160 - #define MSDC_PAD_TUNE_CLKTDLY_S 27 161 - #define MSDC_PAD_TUNE_CMDRRDLY_M 0x7c00000 162 - #define MSDC_PAD_TUNE_CMDRRDLY_S 22 146 + #define MSDC_PAD_TUNE_CLKTDLY GENMASK(31, 27) 147 + #define MSDC_PAD_TUNE_CMDRRDLY GENMASK(26, 22) 163 148 #define MSDC_PAD_TUNE_CMD_SEL BIT(21) 164 - #define MSDC_PAD_TUNE_CMDRDLY_M 0x1f0000 165 - #define MSDC_PAD_TUNE_CMDRDLY_S 16 149 + #define MSDC_PAD_TUNE_CMDRDLY GENMASK(20, 16) 166 150 #define MSDC_PAD_TUNE_RXDLYSEL BIT(15) 167 151 #define MSDC_PAD_TUNE_RD_SEL BIT(13) 168 - #define MSDC_PAD_TUNE_DATRRDLY_M 0x1f00 169 - #define MSDC_PAD_TUNE_DATRRDLY_S 8 170 - #define MSDC_PAD_TUNE_DATWRDLY_M 0x1f 171 - #define MSDC_PAD_TUNE_DATWRDLY_S 0 152 + #define MSDC_PAD_TUNE_DATRRDLY GENMASK(12, 8) 153 + #define MSDC_PAD_TUNE_DATWRDLY GENMASK(4, 0) 172 154 173 - #define PAD_CMD_TUNE_RX_DLY3 0x3E 174 - #define PAD_CMD_TUNE_RX_DLY3_S 1 155 + #define PAD_CMD_TUNE_RX_DLY3 GENMASK(5, 1) 175 156 176 157 /* PAD_TUNE0 */ 177 - #define MSDC_PAD_TUNE0_DAT0RDDLY_M 0x1f000000 178 - #define MSDC_PAD_TUNE0_DAT0RDDLY_S 24 179 - #define MSDC_PAD_TUNE0_DAT1RDDLY_M 0x1f0000 180 - #define MSDC_PAD_TUNE0_DAT1RDDLY_S 16 181 - #define MSDC_PAD_TUNE0_DAT2RDDLY_M 0x1f00 182 - #define MSDC_PAD_TUNE0_DAT2RDDLY_S 8 183 - #define MSDC_PAD_TUNE0_DAT3RDDLY_M 0x1f 184 - #define MSDC_PAD_TUNE0_DAT3RDDLY_S 0 158 + #define MSDC_PAD_TUNE0_DAT0RDDLY GENMASK(28, 24) 159 + #define MSDC_PAD_TUNE0_DAT1RDDLY GENMASK(20, 16) 160 + #define MSDC_PAD_TUNE0_DAT2RDDLY GENMASK(12, 8) 161 + #define MSDC_PAD_TUNE0_DAT3RDDLY GENMASK(4, 0) 185 162 186 163 /* PAD_TUNE1 */ 187 - #define MSDC_PAD_TUNE1_DAT4RDDLY_M 0x1f000000 188 - #define MSDC_PAD_TUNE1_DAT4RDDLY_S 24 189 - #define MSDC_PAD_TUNE1_DAT5RDDLY_M 0x1f0000 190 - #define MSDC_PAD_TUNE1_DAT5RDDLY_S 16 191 - #define MSDC_PAD_TUNE1_DAT6RDDLY_M 0x1f00 192 - #define MSDC_PAD_TUNE1_DAT6RDDLY_S 8 193 - #define MSDC_PAD_TUNE1_DAT7RDDLY_M 0x1f 194 - #define MSDC_PAD_TUNE1_DAT7RDDLY_S 0 164 + #define MSDC_PAD_TUNE1_DAT4RDDLY GENMASK(28, 24) 165 + #define MSDC_PAD_TUNE1_DAT5RDDLY GENMASK(20, 16) 166 + #define MSDC_PAD_TUNE1_DAT6RDDLY GENMASK(12, 8) 167 + #define MSDC_PAD_TUNE1_DAT7RDDLY GENMASK(4, 0) 195 168 196 169 /* EMMC50_CFG0 */ 197 170 #define EMMC50_CFG_CFCSTS_SEL BIT(4) ··· 203 176 /* EMMC_TOP_CONTROL mask */ 204 177 #define PAD_RXDLY_SEL BIT(0) 205 178 #define DELAY_EN BIT(1) 206 - #define PAD_DAT_RD_RXDLY2 (0x1f << 2) 207 - #define PAD_DAT_RD_RXDLY (0x1f << 7) 208 - #define PAD_DAT_RD_RXDLY_S 7 179 + #define PAD_DAT_RD_RXDLY2 GENMASK(6, 2) 180 + #define PAD_DAT_RD_RXDLY GENMASK(11, 7) 209 181 #define PAD_DAT_RD_RXDLY2_SEL BIT(12) 210 182 #define PAD_DAT_RD_RXDLY_SEL BIT(13) 211 183 #define DATA_K_VALUE_SEL BIT(14) 212 184 #define SDC_RX_ENH_EN BIT(15) 213 185 214 186 /* EMMC_TOP_CMD mask */ 215 - #define PAD_CMD_RXDLY2 (0x1f << 0) 216 - #define PAD_CMD_RXDLY (0x1f << 5) 217 - #define PAD_CMD_RXDLY_S 5 187 + #define PAD_CMD_RXDLY2 GENMASK(4, 0) 188 + #define PAD_CMD_RXDLY GENMASK(9, 5) 218 189 #define PAD_CMD_RD_RXDLY2_SEL BIT(10) 219 190 #define PAD_CMD_RD_RXDLY_SEL BIT(11) 220 - #define PAD_CMD_TX_DLY (0x1f << 12) 191 + #define PAD_CMD_TX_DLY GENMASK(16, 12) 221 192 222 193 /* SDC_CFG_BUSWIDTH */ 223 194 #define MSDC_BUS_1BITS 0x0 ··· 238 209 (MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO) 239 210 240 211 #define DATA_INTS_MASK \ 241 - (MSDC_INT_XFER_COMPL | MSDC_INT_DATTMO | MSDC_INT_DATCRCERR) 212 + (MSDC_INT_XFER_COMPL | MSDC_INT_DATTMO | MSDC_INT_DATCRCERR | \ 213 + MSDC_INT_BDCSERR | MSDC_INT_GPDCSERR) 242 214 243 215 /* Register offset */ 244 216 struct mtk_sd_regs { ··· 337 309 bool builtin_pad_ctrl; 338 310 bool default_pad_dly; 339 311 bool use_internal_cd; 312 + bool use_dma_mode; 340 313 }; 341 314 342 315 struct msdc_delay_phase { ··· 428 401 429 402 static u32 msdc_fifo_rx_bytes(struct msdc_host *host) 430 403 { 431 - return (readl(&host->base->msdc_fifocs) & 432 - MSDC_FIFOCS_RXCNT_M) >> MSDC_FIFOCS_RXCNT_S; 404 + return FIELD_GET(MSDC_FIFOCS_RXCNT, readl(&host->base->msdc_fifocs)); 433 405 } 434 406 435 407 static u32 msdc_fifo_tx_bytes(struct msdc_host *host) 436 408 { 437 - return (readl(&host->base->msdc_fifocs) & 438 - MSDC_FIFOCS_TXCNT_M) >> MSDC_FIFOCS_TXCNT_S; 409 + return FIELD_GET(MSDC_FIFOCS_TXCNT, readl(&host->base->msdc_fifocs)); 439 410 } 440 411 441 412 static u32 msdc_cmd_find_resp(struct msdc_host *host, struct mmc_cmd *cmd) ··· 504 475 blocksize = data->blocksize; 505 476 } 506 477 507 - rawcmd |= ((opcode << SDC_CMD_CMD_S) & SDC_CMD_CMD_M) | 508 - ((resp_type << SDC_CMD_RSPTYP_S) & SDC_CMD_RSPTYP_M) | 509 - ((blocksize << SDC_CMD_BLK_LEN_S) & SDC_CMD_BLK_LEN_M) | 510 - ((dtype << SDC_CMD_DTYPE_S) & SDC_CMD_DTYPE_M); 478 + rawcmd |= FIELD_PREP(SDC_CMD_CMD, opcode) | 479 + FIELD_PREP(SDC_CMD_RSPTYP, resp_type) | 480 + FIELD_PREP(SDC_CMD_BLK_LEN, blocksize) | 481 + FIELD_PREP(SDC_CMD_DTYPE, dtype); 511 482 512 483 if (opcode == MMC_CMD_STOP_TRANSMISSION) 513 484 rawcmd |= SDC_CMD_STOP; ··· 547 518 ret = -EIO; 548 519 } 549 520 521 + /* Clear CMD interrupt */ 522 + writel(events & CMD_INTS_MASK, &host->base->msdc_int); 523 + 550 524 return ret; 551 525 } 552 526 ··· 590 564 if (!msdc_cmd_is_ready(host)) 591 565 return -EIO; 592 566 593 - if ((readl(&host->base->msdc_fifocs) & 594 - MSDC_FIFOCS_TXCNT_M) >> MSDC_FIFOCS_TXCNT_S || 595 - (readl(&host->base->msdc_fifocs) & 596 - MSDC_FIFOCS_RXCNT_M) >> MSDC_FIFOCS_RXCNT_S) { 567 + if (FIELD_GET(MSDC_FIFOCS_TXCNT, readl(&host->base->msdc_fifocs)) || 568 + FIELD_GET(MSDC_FIFOCS_RXCNT, readl(&host->base->msdc_fifocs))) { 597 569 pr_err("TX/RX FIFO non-empty before start of IO. Reset\n"); 598 570 msdc_reset_hw(host); 571 + msdc_fifo_clr(host); 599 572 } 600 573 601 - msdc_fifo_clr(host); 602 - 603 574 host->last_resp_type = cmd->resp_type; 604 575 host->last_data_write = 0; 605 576 ··· 608 579 if (data) 609 580 blocks = data->blocks; 610 581 611 - writel(CMD_INTS_MASK, &host->base->msdc_int); 612 - writel(DATA_INTS_MASK, &host->base->msdc_int); 613 582 writel(blocks, &host->base->sdc_blk_num); 614 583 writel(cmd->cmdarg, &host->base->sdc_arg); 615 584 writel(rawcmd, &host->base->sdc_cmd); ··· 704 673 705 674 break; 706 675 } 707 - } 676 + } 708 677 709 678 return ret; 710 679 } ··· 751 720 return ret; 752 721 } 753 722 754 - static int msdc_start_data(struct msdc_host *host, struct mmc_data *data) 723 + static int msdc_pio_transfer(struct msdc_host *host, struct mmc_data *data) 755 724 { 756 725 u32 size; 757 726 int ret; 758 727 728 + size = data->blocks * data->blocksize; 729 + 759 730 if (data->flags == MMC_DATA_WRITE) 760 - host->last_data_write = 1; 731 + ret = msdc_pio_write(host, (const u8 *)data->src, size); 732 + else 733 + ret = msdc_pio_read(host, (u8 *)data->dest, size); 734 + 735 + return ret; 736 + } 737 + 738 + static dma_addr_t msdc_flush_membuf(const void *ptr, size_t size, enum dma_data_direction dir) 739 + { 740 + dma_addr_t addr = (dma_addr_t)ptr; 741 + 742 + if (dir == DMA_FROM_DEVICE) 743 + invalidate_dcache_range(addr, addr + size); 744 + else 745 + flush_dcache_range(addr, addr + size); 746 + 747 + return addr; 748 + } 749 + 750 + static void msdc_dma_start(struct msdc_host *host, dma_addr_t addr, u32 size) 751 + { 752 + writel((u32)addr, &host->base->dma_sa); 753 + clrsetbits_le32(&host->base->dma_ctrl, MSDC_DMA_CTRL_BURSTSZ, 754 + FIELD_PREP(MSDC_DMA_CTRL_BURSTSZ, 6)); 755 + 756 + /* BASIC_DMA mode */ 757 + clrbits_le32(&host->base->dma_ctrl, MSDC_DMA_CTRL_MODE); 758 + 759 + /* This is the last buffer */ 760 + setbits_le32(&host->base->dma_ctrl, MSDC_DMA_CTRL_LASTBUF); 761 + 762 + /* Total transfer size */ 763 + writel(size, &host->base->dma_length); 764 + 765 + /* Trigger DMA start */ 766 + setbits_le32(&host->base->dma_ctrl, MSDC_DMA_CTRL_START); 767 + } 768 + 769 + static void msdc_dma_stop(struct msdc_host *host) 770 + { 771 + u32 reg; 772 + 773 + setbits_le32(&host->base->dma_ctrl, MSDC_DMA_CTRL_STOP); 774 + readl_poll_timeout(&host->base->dma_cfg, reg, 775 + !(reg & MSDC_DMA_CFG_STS), 1000000); 776 + } 777 + 778 + static int msdc_dma_done(struct msdc_host *host, int events) 779 + { 780 + int ret = 0; 781 + u32 rawcmd, arg; 782 + 783 + if (!(events & MSDC_INT_XFER_COMPL)) { 784 + rawcmd = readl(&host->base->sdc_cmd); 785 + arg = readl(&host->base->sdc_arg); 786 + 787 + if (events & MSDC_INT_DATTMO) 788 + ret = -ETIMEDOUT; 789 + else if (events & (MSDC_INT_DATCRCERR | MSDC_INT_GPDCSERR | MSDC_INT_BDCSERR)) 790 + ret = -EIO; 791 + else 792 + ret = -EBADRQC; 793 + 794 + pr_err("MSDC: start data failure with %d, INT(0x%x), rawcmd=0x%x, arg=0x%x\n", 795 + ret, events, rawcmd, arg); 796 + } 797 + 798 + /* Clear DAT interrupt */ 799 + writel(events & DATA_INTS_MASK, &host->base->msdc_int); 800 + 801 + return ret; 802 + } 803 + 804 + static int msdc_dma_transfer(struct msdc_host *host, struct mmc_data *data) 805 + { 806 + u32 size, status; 807 + int ret; 808 + const void *buf; 809 + enum dma_data_direction dir; 810 + dma_addr_t dma_addr; 761 811 762 812 size = data->blocks * data->blocksize; 813 + if (data->flags == MMC_DATA_WRITE) { 814 + buf = data->src; 815 + dir = DMA_TO_DEVICE; 816 + } else { 817 + buf = data->dest; 818 + dir = DMA_FROM_DEVICE; 819 + } 820 + 821 + dma_addr = msdc_flush_membuf(buf, size, dir); 822 + msdc_dma_start(host, dma_addr, size); 823 + 824 + ret = readl_poll_timeout(&host->base->msdc_int, status, 825 + status & DATA_INTS_MASK, 5000000); 826 + if (ret) 827 + status = MSDC_INT_DATTMO; 828 + 829 + msdc_dma_stop(host); 830 + 831 + /* 832 + * Need invalidate the dcache again to avoid any 833 + * cache-refill during the DMA operations (pre-fetching) 834 + */ 835 + if (data->flags & MMC_DATA_READ) 836 + invalidate_dcache_range(dma_addr, dma_addr + size); 837 + 838 + return msdc_dma_done(host, status); 839 + } 840 + 841 + static int msdc_start_data(struct msdc_host *host, struct mmc_data *data) 842 + { 843 + int ret; 763 844 764 845 if (data->flags == MMC_DATA_WRITE) 765 - ret = msdc_pio_write(host, (const u8 *)data->src, size); 846 + host->last_data_write = 1; 847 + 848 + if (host->dev_comp->use_dma_mode) 849 + ret = msdc_dma_transfer(host, data); 766 850 else 767 - ret = msdc_pio_read(host, (u8 *)data->dest, size); 851 + ret = msdc_pio_transfer(host, data); 768 852 769 853 if (ret) { 770 854 msdc_reset_hw(host); ··· 814 898 /* unit is 1048576 sclk cycles */ 815 899 timeout = (timeout + (0x1 << shift) - 1) >> shift; 816 900 if (host->dev_comp->clk_div_bits == 8) 817 - mode = (readl(&host->base->msdc_cfg) & 818 - MSDC_CFG_CKMOD_M) >> MSDC_CFG_CKMOD_S; 901 + mode = FIELD_GET(MSDC_CFG_CKMOD, readl(&host->base->msdc_cfg)); 819 902 else 820 - mode = (readl(&host->base->msdc_cfg) & 821 - MSDC_CFG_CKMOD_EXT_M) >> MSDC_CFG_CKMOD_EXT_S; 903 + mode = FIELD_GET(MSDC_CFG_CKMOD_EXT, readl(&host->base->msdc_cfg)); 822 904 /* DDR mode will double the clk cycles for data timeout */ 823 905 timeout = mode >= 2 ? timeout * 2 : timeout; 824 906 timeout = timeout > 1 ? timeout - 1 : 0; 825 907 timeout = timeout > 255 ? 255 : timeout; 826 908 } 827 909 828 - clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M, 829 - timeout << SDC_CFG_DTOC_S); 910 + clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC, 911 + FIELD_PREP(SDC_CFG_DTOC, timeout)); 830 912 } 831 913 832 914 static void msdc_set_buswidth(struct msdc_host *host, u32 width) 833 915 { 834 916 u32 val = readl(&host->base->sdc_cfg); 835 917 836 - val &= ~SDC_CFG_BUSWIDTH_M; 918 + val &= ~SDC_CFG_BUSWIDTH; 837 919 838 920 switch (width) { 839 921 default: 840 922 case 1: 841 - val |= (MSDC_BUS_1BITS << SDC_CFG_BUSWIDTH_S); 923 + val |= FIELD_PREP(SDC_CFG_BUSWIDTH, MSDC_BUS_1BITS); 842 924 break; 843 925 case 4: 844 - val |= (MSDC_BUS_4BITS << SDC_CFG_BUSWIDTH_S); 926 + val |= FIELD_PREP(SDC_CFG_BUSWIDTH, MSDC_BUS_4BITS); 845 927 break; 846 928 case 8: 847 - val |= (MSDC_BUS_8BITS << SDC_CFG_BUSWIDTH_S); 929 + val |= FIELD_PREP(SDC_CFG_BUSWIDTH, MSDC_BUS_8BITS); 848 930 break; 849 931 } 850 932 ··· 918 1000 clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN); 919 1001 920 1002 if (host->dev_comp->clk_div_bits == 8) { 921 - div = min(div, (u32)(MSDC_CFG_CKDIV_M >> MSDC_CFG_CKDIV_S)); 1003 + div = min(div, (u32)FIELD_MAX(MSDC_CFG_CKDIV)); 922 1004 clrsetbits_le32(&host->base->msdc_cfg, 923 - MSDC_CFG_CKMOD_M | MSDC_CFG_CKDIV_M, 924 - (mode << MSDC_CFG_CKMOD_S) | 925 - (div << MSDC_CFG_CKDIV_S)); 1005 + MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, 1006 + FIELD_PREP(MSDC_CFG_CKMOD, mode) | 1007 + FIELD_PREP(MSDC_CFG_CKDIV, div)); 926 1008 } else { 927 - div = min(div, (u32)(MSDC_CFG_CKDIV_EXT_M >> 928 - MSDC_CFG_CKDIV_EXT_S)); 1009 + div = min(div, (u32)FIELD_MAX(MSDC_CFG_CKDIV_EXT)); 929 1010 clrsetbits_le32(&host->base->msdc_cfg, 930 - MSDC_CFG_CKMOD_EXT_M | MSDC_CFG_CKDIV_EXT_M, 931 - (mode << MSDC_CFG_CKMOD_EXT_S) | 932 - (div << MSDC_CFG_CKDIV_EXT_S)); 1011 + MSDC_CFG_CKMOD_EXT | MSDC_CFG_CKDIV_EXT, 1012 + FIELD_PREP(MSDC_CFG_CKMOD_EXT, mode) | 1013 + FIELD_PREP(MSDC_CFG_CKDIV_EXT, div)); 933 1014 } 934 1015 935 1016 readl_poll_timeout(&host->base->msdc_cfg, reg, ··· 1085 1166 1086 1167 if (host->top_base) 1087 1168 clrsetbits_le32(&host->top_base->emmc_top_cmd, PAD_CMD_RXDLY, 1088 - value << PAD_CMD_RXDLY_S); 1169 + FIELD_PREP(PAD_CMD_RXDLY, value)); 1089 1170 else 1090 - clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M, 1091 - value << MSDC_PAD_TUNE_CMDRDLY_S); 1171 + clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY, 1172 + FIELD_PREP(MSDC_PAD_TUNE_CMDRDLY, value)); 1092 1173 } 1093 1174 1094 1175 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value) ··· 1100 1181 1101 1182 if (host->top_base) 1102 1183 clrsetbits_le32(&host->top_base->emmc_top_control, 1103 - PAD_DAT_RD_RXDLY, value << PAD_DAT_RD_RXDLY_S); 1184 + PAD_DAT_RD_RXDLY, FIELD_PREP(PAD_DAT_RD_RXDLY, value)); 1104 1185 else 1105 - clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M, 1106 - value << MSDC_PAD_TUNE_DATRRDLY_S); 1186 + clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY, 1187 + FIELD_PREP(MSDC_PAD_TUNE_DATRRDLY, value)); 1107 1188 } 1108 1189 1109 1190 static int hs400_tune_response(struct udevice *dev, u32 opcode) ··· 1122 1203 1123 1204 if (mmc->selected_mode == MMC_HS_200 || 1124 1205 mmc->selected_mode == UHS_SDR104) 1125 - clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M, 1126 - host->hs200_cmd_int_delay << 1127 - MSDC_PAD_TUNE_CMDRRDLY_S); 1206 + clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY, 1207 + FIELD_PREP(MSDC_PAD_TUNE_CMDRRDLY, 1208 + host->hs200_cmd_int_delay)); 1128 1209 1129 1210 if (host->r_smpl) 1130 1211 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL); ··· 1133 1214 1134 1215 for (i = 0; i < PAD_DELAY_MAX; i++) { 1135 1216 clrsetbits_le32(tune_reg, PAD_CMD_TUNE_RX_DLY3, 1136 - i << PAD_CMD_TUNE_RX_DLY3_S); 1217 + FIELD_PREP(PAD_CMD_TUNE_RX_DLY3, i)); 1137 1218 1138 1219 for (j = 0; j < 3; j++) { 1139 1220 cmd_err = mmc_send_tuning(mmc, opcode); ··· 1148 1229 1149 1230 final_cmd_delay = get_best_delay(dev, host, cmd_delay); 1150 1231 clrsetbits_le32(tune_reg, PAD_CMD_TUNE_RX_DLY3, 1151 - final_cmd_delay.final_phase << 1152 - PAD_CMD_TUNE_RX_DLY3_S); 1232 + FIELD_PREP(PAD_CMD_TUNE_RX_DLY3, final_cmd_delay.final_phase)); 1153 1233 final_delay = final_cmd_delay.final_phase; 1154 1234 1155 1235 dev_info(dev, "Final cmd pad delay: %x\n", final_delay); ··· 1175 1255 1176 1256 if (mmc->selected_mode == MMC_HS_200 || 1177 1257 mmc->selected_mode == UHS_SDR104) 1178 - clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M, 1179 - host->hs200_cmd_int_delay << 1180 - MSDC_PAD_TUNE_CMDRRDLY_S); 1258 + clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY, 1259 + FIELD_PREP(MSDC_PAD_TUNE_CMDRRDLY, 1260 + host->hs200_cmd_int_delay)); 1181 1261 1182 1262 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL); 1183 1263 1184 1264 for (i = 0; i < PAD_DELAY_MAX; i++) { 1185 - clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M, 1186 - i << MSDC_PAD_TUNE_CMDRDLY_S); 1265 + clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY, 1266 + FIELD_PREP(MSDC_PAD_TUNE_CMDRDLY, i)); 1187 1267 1188 1268 for (j = 0; j < 3; j++) { 1189 1269 cmd_err = mmc_send_tuning(mmc, opcode); ··· 1204 1284 1205 1285 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL); 1206 1286 for (i = 0; i < PAD_DELAY_MAX; i++) { 1207 - clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M, 1208 - i << MSDC_PAD_TUNE_CMDRDLY_S); 1287 + clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY, 1288 + FIELD_PREP(MSDC_PAD_TUNE_CMDRDLY, i)); 1209 1289 1210 1290 for (j = 0; j < 3; j++) { 1211 1291 cmd_err = mmc_send_tuning(mmc, opcode); ··· 1224 1304 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 1225 1305 if (final_maxlen == final_rise_delay.maxlen) { 1226 1306 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL); 1227 - clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M, 1228 - final_rise_delay.final_phase << 1229 - MSDC_PAD_TUNE_CMDRDLY_S); 1307 + clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY, 1308 + FIELD_PREP(MSDC_PAD_TUNE_CMDRDLY, 1309 + final_rise_delay.final_phase)); 1230 1310 final_delay = final_rise_delay.final_phase; 1231 1311 } else { 1232 1312 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL); 1233 - clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M, 1234 - final_fall_delay.final_phase << 1235 - MSDC_PAD_TUNE_CMDRDLY_S); 1313 + clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY, 1314 + FIELD_PREP(MSDC_PAD_TUNE_CMDRDLY, 1315 + final_fall_delay.final_phase)); 1236 1316 final_delay = final_fall_delay.final_phase; 1237 1317 } 1238 1318 ··· 1240 1320 goto skip_internal; 1241 1321 1242 1322 for (i = 0; i < PAD_DELAY_MAX; i++) { 1243 - clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M, 1244 - i << MSDC_PAD_TUNE_CMDRRDLY_S); 1245 - 1323 + clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY, 1324 + FIELD_PREP(MSDC_PAD_TUNE_CMDRRDLY, i)); 1246 1325 cmd_err = mmc_send_tuning(mmc, opcode); 1247 1326 if (!cmd_err) 1248 1327 internal_delay |= (1 << i); ··· 1251 1330 dev_dbg(dev, "Final internal delay: 0x%x\n", internal_delay); 1252 1331 1253 1332 internal_delay_phase = get_best_delay(dev, host, internal_delay); 1254 - clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M, 1255 - internal_delay_phase.final_phase << 1256 - MSDC_PAD_TUNE_CMDRRDLY_S); 1333 + clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY, 1334 + FIELD_PREP(MSDC_PAD_TUNE_CMDRRDLY, 1335 + internal_delay_phase.final_phase)); 1257 1336 1258 1337 skip_internal: 1259 1338 dev_dbg(dev, "Final cmd pad delay: %x\n", final_delay); ··· 1278 1357 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL); 1279 1358 1280 1359 for (i = 0; i < PAD_DELAY_MAX; i++) { 1281 - clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M, 1282 - i << MSDC_PAD_TUNE_DATRRDLY_S); 1360 + clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY, 1361 + FIELD_PREP(MSDC_PAD_TUNE_DATRRDLY, i)); 1283 1362 1284 1363 ret = mmc_send_tuning(mmc, opcode); 1285 1364 if (!ret) { ··· 1301 1380 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL); 1302 1381 1303 1382 for (i = 0; i < PAD_DELAY_MAX; i++) { 1304 - clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M, 1305 - i << MSDC_PAD_TUNE_DATRRDLY_S); 1383 + clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY, 1384 + FIELD_PREP(MSDC_PAD_TUNE_DATRRDLY, i)); 1306 1385 1307 1386 ret = mmc_send_tuning(mmc, opcode); 1308 1387 if (!ret) { ··· 1322 1401 if (final_maxlen == final_rise_delay.maxlen) { 1323 1402 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL); 1324 1403 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL); 1325 - clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M, 1326 - final_rise_delay.final_phase << 1327 - MSDC_PAD_TUNE_DATRRDLY_S); 1404 + clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY, 1405 + FIELD_PREP(MSDC_PAD_TUNE_DATRRDLY, 1406 + final_rise_delay.final_phase)); 1328 1407 final_delay = final_rise_delay.final_phase; 1329 1408 } else { 1330 1409 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL); 1331 1410 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL); 1332 - clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M, 1333 - final_fall_delay.final_phase << 1334 - MSDC_PAD_TUNE_DATRRDLY_S); 1411 + clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY, 1412 + FIELD_PREP(MSDC_PAD_TUNE_DATRRDLY, 1413 + final_fall_delay.final_phase)); 1335 1414 final_delay = final_fall_delay.final_phase; 1336 1415 } 1337 1416 1338 1417 if (mmc->selected_mode == MMC_HS_200 || 1339 1418 mmc->selected_mode == UHS_SDR104) 1340 - clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATWRDLY_M, 1341 - host->hs200_write_int_delay << 1342 - MSDC_PAD_TUNE_DATWRDLY_S); 1419 + clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATWRDLY, 1420 + FIELD_PREP(MSDC_PAD_TUNE_DATWRDLY, 1421 + host->hs200_write_int_delay)); 1343 1422 1344 1423 dev_dbg(dev, "Final data pad delay: %x\n", final_delay); 1345 1424 ··· 1426 1505 clrbits_le32(&host->base->msdc_iocon, 1427 1506 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 1428 1507 clrsetbits_le32(&host->base->pad_tune, 1429 - MSDC_PAD_TUNE_DATRRDLY_M, 0); 1508 + MSDC_PAD_TUNE_DATRRDLY, 0); 1430 1509 1431 1510 writel(host->hs400_ds_delay, &host->base->pad_ds_tune); 1432 1511 /* for hs400 mode it must be set to 0 */ ··· 1479 1558 /* Configure to MMC/SD mode, clock free running */ 1480 1559 setbits_le32(&host->base->msdc_cfg, MSDC_CFG_MODE); 1481 1560 1482 - /* Use PIO mode */ 1483 - setbits_le32(&host->base->msdc_cfg, MSDC_CFG_PIO); 1561 + /* Data transfer mode */ 1562 + if (host->dev_comp->use_dma_mode) 1563 + clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_PIO); 1564 + else 1565 + setbits_le32(&host->base->msdc_cfg, MSDC_CFG_PIO); 1484 1566 1485 1567 /* Reset */ 1486 1568 msdc_reset_hw(host); ··· 1488 1570 /* Enable/disable hw card detection according to fdt option */ 1489 1571 if (host->builtin_cd) 1490 1572 clrsetbits_le32(&host->base->msdc_ps, 1491 - MSDC_PS_CDDBCE_M, 1492 - (DEFAULT_CD_DEBOUNCE << MSDC_PS_CDDBCE_S) | 1573 + MSDC_PS_CDDBCE, 1574 + FIELD_PREP(MSDC_PS_CDDBCE, DEFAULT_CD_DEBOUNCE) | 1493 1575 MSDC_PS_CDEN); 1494 1576 else 1495 1577 clrbits_le32(&host->base->msdc_ps, MSDC_PS_CDEN); ··· 1518 1600 writel(0xffff4089, &host->base->patch_bit1); 1519 1601 1520 1602 if (host->dev_comp->stop_clk_fix) { 1521 - clrsetbits_le32(&host->base->patch_bit1, MSDC_PB1_STOP_DLY_M, 1522 - 3 << MSDC_PB1_STOP_DLY_S); 1603 + clrsetbits_le32(&host->base->patch_bit1, MSDC_PB1_STOP_DLY, 1604 + FIELD_PREP(MSDC_PB1_STOP_DLY, 3)); 1523 1605 clrbits_le32(&host->base->sdc_fifo_cfg, 1524 1606 SDC_FIFO_CFG_WRVALIDSEL); 1525 1607 clrbits_le32(&host->base->sdc_fifo_cfg, ··· 1532 1614 setbits_le32(&host->base->emmc50_cfg0, EMMC50_CFG_CFCSTS_SEL); 1533 1615 1534 1616 if (host->dev_comp->async_fifo) { 1535 - clrsetbits_le32(&host->base->patch_bit2, MSDC_PB2_RESPWAIT_M, 1536 - 3 << MSDC_PB2_RESPWAIT_S); 1617 + clrsetbits_le32(&host->base->patch_bit2, MSDC_PB2_RESPWAIT, 1618 + FIELD_PREP(MSDC_PB2_RESPWAIT, 3)); 1537 1619 1538 1620 if (host->dev_comp->enhance_rx) { 1539 1621 if (host->top_base) ··· 1544 1626 SDC_RX_ENHANCE_EN); 1545 1627 } else { 1546 1628 clrsetbits_le32(&host->base->patch_bit2, 1547 - MSDC_PB2_RESPSTSENSEL_M, 1548 - 2 << MSDC_PB2_RESPSTSENSEL_S); 1629 + MSDC_PB2_RESPSTSENSEL, 1630 + FIELD_PREP(MSDC_PB2_RESPSTSENSEL, 2)); 1549 1631 clrsetbits_le32(&host->base->patch_bit2, 1550 - MSDC_PB2_CRCSTSENSEL_M, 1551 - 2 << MSDC_PB2_CRCSTSENSEL_S); 1632 + MSDC_PB2_CRCSTSENSEL, 1633 + FIELD_PREP(MSDC_PB2_CRCSTSENSEL, 2)); 1552 1634 } 1553 1635 1554 1636 /* use async fifo to avoid tune internal delay */ ··· 1574 1656 setbits_le32(tune_reg, 1575 1657 MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL); 1576 1658 clrsetbits_le32(&host->base->patch_bit0, 1577 - MSDC_INT_DAT_LATCH_CK_SEL_M, 1578 - host->latch_ck << 1579 - MSDC_INT_DAT_LATCH_CK_SEL_S); 1659 + MSDC_INT_DAT_LATCH_CK_SEL, 1660 + FIELD_PREP(MSDC_INT_DAT_LATCH_CK_SEL, 1661 + host->latch_ck)); 1580 1662 } 1581 1663 } else { 1582 1664 /* choose clock tune */ ··· 1590 1672 if (host->dev_comp->builtin_pad_ctrl) { 1591 1673 /* Set pins driving strength */ 1592 1674 writel(MSDC_PAD_CTRL0_CLKPD | MSDC_PAD_CTRL0_CLKSMT | 1593 - MSDC_PAD_CTRL0_CLKIES | (4 << MSDC_PAD_CTRL0_CLKDRVN_S) | 1594 - (4 << MSDC_PAD_CTRL0_CLKDRVP_S), &host->base->pad_ctrl0); 1675 + MSDC_PAD_CTRL0_CLKIES | FIELD_PREP(MSDC_PAD_CTRL0_CLKDRVN, 4) | 1676 + FIELD_PREP(MSDC_PAD_CTRL0_CLKDRVP, 4), &host->base->pad_ctrl0); 1595 1677 writel(MSDC_PAD_CTRL1_CMDPU | MSDC_PAD_CTRL1_CMDSMT | 1596 - MSDC_PAD_CTRL1_CMDIES | (4 << MSDC_PAD_CTRL1_CMDDRVN_S) | 1597 - (4 << MSDC_PAD_CTRL1_CMDDRVP_S), &host->base->pad_ctrl1); 1678 + MSDC_PAD_CTRL1_CMDIES | FIELD_PREP(MSDC_PAD_CTRL1_CMDDRVN, 4) | 1679 + FIELD_PREP(MSDC_PAD_CTRL1_CMDDRVP, 4), &host->base->pad_ctrl1); 1598 1680 writel(MSDC_PAD_CTRL2_DATPU | MSDC_PAD_CTRL2_DATSMT | 1599 - MSDC_PAD_CTRL2_DATIES | (4 << MSDC_PAD_CTRL2_DATDRVN_S) | 1600 - (4 << MSDC_PAD_CTRL2_DATDRVP_S), &host->base->pad_ctrl2); 1681 + MSDC_PAD_CTRL2_DATIES | FIELD_PREP(MSDC_PAD_CTRL2_DATDRVN, 4) | 1682 + FIELD_PREP(MSDC_PAD_CTRL2_DATDRVP, 4), &host->base->pad_ctrl2); 1601 1683 } 1602 1684 1603 1685 if (host->dev_comp->default_pad_dly) { 1604 1686 /* Default pad delay may be needed if tuning not enabled */ 1605 - clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CLKTDLY_M | 1606 - MSDC_PAD_TUNE_CMDRRDLY_M | 1607 - MSDC_PAD_TUNE_CMDRDLY_M | 1608 - MSDC_PAD_TUNE_DATRRDLY_M | 1609 - MSDC_PAD_TUNE_DATWRDLY_M, 1610 - (0x10 << MSDC_PAD_TUNE_CLKTDLY_S) | 1611 - (0x10 << MSDC_PAD_TUNE_CMDRRDLY_S) | 1612 - (0x10 << MSDC_PAD_TUNE_CMDRDLY_S) | 1613 - (0x10 << MSDC_PAD_TUNE_DATRRDLY_S) | 1614 - (0x10 << MSDC_PAD_TUNE_DATWRDLY_S)); 1615 - 1616 - writel((0x10 << MSDC_PAD_TUNE0_DAT0RDDLY_S) | 1617 - (0x10 << MSDC_PAD_TUNE0_DAT1RDDLY_S) | 1618 - (0x10 << MSDC_PAD_TUNE0_DAT2RDDLY_S) | 1619 - (0x10 << MSDC_PAD_TUNE0_DAT3RDDLY_S), 1687 + clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CLKTDLY | 1688 + MSDC_PAD_TUNE_CMDRRDLY | 1689 + MSDC_PAD_TUNE_CMDRDLY | 1690 + MSDC_PAD_TUNE_DATRRDLY | 1691 + MSDC_PAD_TUNE_DATWRDLY, 1692 + FIELD_PREP(MSDC_PAD_TUNE_CLKTDLY, 0x10) | 1693 + FIELD_PREP(MSDC_PAD_TUNE_CMDRRDLY, 0x10) | 1694 + FIELD_PREP(MSDC_PAD_TUNE_CMDRDLY, 0x10) | 1695 + FIELD_PREP(MSDC_PAD_TUNE_DATRRDLY, 0x10) | 1696 + FIELD_PREP(MSDC_PAD_TUNE_DATWRDLY, 0x10)); 1697 + writel(FIELD_PREP(MSDC_PAD_TUNE0_DAT0RDDLY, 0x10) | 1698 + FIELD_PREP(MSDC_PAD_TUNE0_DAT1RDDLY, 0x10) | 1699 + FIELD_PREP(MSDC_PAD_TUNE0_DAT2RDDLY, 0x10) | 1700 + FIELD_PREP(MSDC_PAD_TUNE0_DAT3RDDLY, 0x10), 1620 1701 rd_dly0_reg); 1621 1702 1622 - writel((0x10 << MSDC_PAD_TUNE1_DAT4RDDLY_S) | 1623 - (0x10 << MSDC_PAD_TUNE1_DAT5RDDLY_S) | 1624 - (0x10 << MSDC_PAD_TUNE1_DAT6RDDLY_S) | 1625 - (0x10 << MSDC_PAD_TUNE1_DAT7RDDLY_S), 1703 + writel(FIELD_PREP(MSDC_PAD_TUNE1_DAT4RDDLY, 0x10) | 1704 + FIELD_PREP(MSDC_PAD_TUNE1_DAT5RDDLY, 0x10) | 1705 + FIELD_PREP(MSDC_PAD_TUNE1_DAT6RDDLY, 0x10) | 1706 + FIELD_PREP(MSDC_PAD_TUNE1_DAT7RDDLY, 0x10), 1626 1707 rd_dly1_reg); 1627 1708 } 1628 1709 ··· 1633 1714 clrbits_le32(&host->base->sdc_cfg, SDC_CFG_SDIOIDE); 1634 1715 1635 1716 /* Configure to default data timeout */ 1636 - clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M, 1637 - 3 << SDC_CFG_DTOC_S); 1717 + clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC, 1718 + FIELD_PREP(SDC_CFG_DTOC, 3)); 1638 1719 1639 1720 host->def_tune_para.iocon = readl(&host->base->msdc_iocon); 1640 1721 host->def_tune_para.pad_tune = readl(&host->base->pad_tune); ··· 1894 1975 .data_tune = true, 1895 1976 .busy_check = true, 1896 1977 .stop_clk_fix = true, 1978 + .enhance_rx = true, 1979 + .use_dma_mode = true, 1897 1980 }; 1898 1981 1899 1982 static const struct udevice_id msdc_ids[] = {

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