"Das U-Boot" Source Tree
Merge tag 'xilinx-for-v2025.10-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
AMD/Xilinx changes for v2025.10-rc1
cmd:
- Introduce CMD_HELP Kconfig option
fpga:
- Fix in intel_smd_mb
mini:
- Remove simple-bus driver and description
- Disable CMD_HELP
firmware:
- Fix dependencies
- Switch to new SMC firmware format
cadence qspi:
- Fix read/write STIG mode
- Set tshsl_ns to at least one sclk_ns
sdhci:
- Call sdhci reset if wired
zynqmp-clk:
- Add support for DPLL clock source
zynqmp:
- Sync clock ID bindings with Linux
- defconfig updates
- Enable rng-seed generation
versal:
- Fix clock dependency
versal2:
- defconfig updates
- Enable sysreset
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# gpg: Signature made Tue 08 Jul 2025 07:15:24 AM CST
# gpg: using EDDSA key 97022C40ACF6D6A516A7596FAB07FEF04EF511F5
# gpg: Can't check signature: No public key
+383
-439
+14
-22
arch/arm/dts/versal-mini-emmc0.dts
+14
-22
arch/arm/dts/versal-mini-emmc0.dts
···
28
28
bootph-all;
29
29
};
30
30
31
-
amba: axi {
32
-
bootph-all;
33
-
compatible = "simple-bus";
34
-
#address-cells = <0x2>;
35
-
#size-cells = <0x2>;
36
-
ranges;
37
-
38
-
sdhci0: sdhci@f1040000 {
39
-
compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
40
-
status = "okay";
41
-
non-removable;
42
-
disable-wp;
43
-
no-sd;
44
-
no-sdio;
45
-
cap-mmc-hw-reset;
46
-
bus-width = <8>;
47
-
reg = <0x0 0xf1040000 0x0 0x10000>;
48
-
clock-names = "clk_xin", "clk_ahb";
49
-
clocks = <&clk200 &clk200>;
50
-
no-1-8-v;
51
-
xlnx,mio-bank = <0>;
52
-
};
31
+
sdhci0: sdhci@f1040000 {
32
+
compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
33
+
status = "okay";
34
+
non-removable;
35
+
disable-wp;
36
+
no-sd;
37
+
no-sdio;
38
+
cap-mmc-hw-reset;
39
+
bus-width = <8>;
40
+
reg = <0x0 0xf1040000 0x0 0x10000>;
41
+
clock-names = "clk_xin", "clk_ahb";
42
+
clocks = <&clk200 &clk200>;
43
+
no-1-8-v;
44
+
xlnx,mio-bank = <0>;
53
45
};
54
46
55
47
aliases {
+14
-22
arch/arm/dts/versal-mini-emmc1.dts
+14
-22
arch/arm/dts/versal-mini-emmc1.dts
···
28
28
bootph-all;
29
29
};
30
30
31
-
amba: axi {
32
-
bootph-all;
33
-
compatible = "simple-bus";
34
-
#address-cells = <0x2>;
35
-
#size-cells = <0x2>;
36
-
ranges;
37
-
38
-
sdhci1: sdhci@f1050000 {
39
-
compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
40
-
status = "okay";
41
-
non-removable;
42
-
disable-wp;
43
-
no-sd;
44
-
no-sdio;
45
-
cap-mmc-hw-reset;
46
-
bus-width = <8>;
47
-
reg = <0x0 0xf1050000 0x0 0x10000>;
48
-
clock-names = "clk_xin", "clk_ahb";
49
-
clocks = <&clk200 &clk200>;
50
-
no-1-8-v;
51
-
xlnx,mio-bank = <0>;
52
-
};
31
+
sdhci1: sdhci@f1050000 {
32
+
compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
33
+
status = "okay";
34
+
non-removable;
35
+
disable-wp;
36
+
no-sd;
37
+
no-sdio;
38
+
cap-mmc-hw-reset;
39
+
bus-width = <8>;
40
+
reg = <0x0 0xf1050000 0x0 0x10000>;
41
+
clock-names = "clk_xin", "clk_ahb";
42
+
clocks = <&clk200 &clk200>;
43
+
no-1-8-v;
44
+
xlnx,mio-bank = <0>;
53
45
};
54
46
55
47
aliases {
+22
-30
arch/arm/dts/versal-mini-ospi.dtsi
+22
-30
arch/arm/dts/versal-mini-ospi.dtsi
···
28
28
bootph-all;
29
29
};
30
30
31
-
amba: axi {
32
-
bootph-all;
33
-
compatible = "simple-bus";
34
-
#address-cells = <0x2>;
35
-
#size-cells = <0x2>;
36
-
ranges;
37
-
38
-
ospi: spi@f1010000 {
39
-
compatible = "cdns,qspi-nor";
40
-
status = "okay";
41
-
reg = <0 0xf1010000 0 0x10000 0 0xc0000000 0 0x20000000>;
42
-
clock-names = "ref_clk", "pclk";
43
-
clocks = <&clk125 &clk125>;
44
-
bus-num = <2>;
45
-
num-cs = <1>;
46
-
cdns,fifo-depth = <256>;
47
-
cdns,fifo-width = <4>;
48
-
cdns,is-dma = <1>;
49
-
cdns,trigger-address = <0xc0000000>;
50
-
#address-cells = <1>;
51
-
#size-cells = <0>;
31
+
ospi: spi@f1010000 {
32
+
compatible = "cdns,qspi-nor";
33
+
status = "okay";
34
+
reg = <0 0xf1010000 0 0x10000 0 0xc0000000 0 0x20000000>;
35
+
clock-names = "ref_clk", "pclk";
36
+
clocks = <&clk125 &clk125>;
37
+
bus-num = <2>;
38
+
num-cs = <1>;
39
+
cdns,fifo-depth = <256>;
40
+
cdns,fifo-width = <4>;
41
+
cdns,is-dma = <1>;
42
+
cdns,trigger-address = <0xc0000000>;
43
+
#address-cells = <1>;
44
+
#size-cells = <0>;
52
45
53
-
flash0: flash@0 {
54
-
compatible = "n25q512a", "micron,m25p80",
55
-
"jedec,spi-nor";
56
-
reg = <0x0>;
57
-
spi-tx-bus-width = <8>;
58
-
spi-rx-bus-width = <8>;
59
-
spi-max-frequency = <20000000>;
60
-
no-wp;
61
-
};
46
+
flash0: flash@0 {
47
+
compatible = "n25q512a", "micron,m25p80",
48
+
"jedec,spi-nor";
49
+
reg = <0x0>;
50
+
spi-tx-bus-width = <8>;
51
+
spi-rx-bus-width = <8>;
52
+
spi-max-frequency = <20000000>;
53
+
no-wp;
62
54
};
63
55
};
64
56
+16
-24
arch/arm/dts/versal-mini-qspi.dtsi
+16
-24
arch/arm/dts/versal-mini-qspi.dtsi
···
28
28
bootph-all;
29
29
};
30
30
31
-
amba: axi {
32
-
bootph-all;
33
-
compatible = "simple-bus";
34
-
#address-cells = <0x2>;
35
-
#size-cells = <0x2>;
36
-
ranges;
37
-
38
-
qspi: spi@f1030000 {
39
-
compatible = "xlnx,versal-qspi-1.0";
40
-
status = "okay";
41
-
clock-names = "ref_clk", "pclk";
42
-
num-cs = <0x1>;
43
-
reg = <0x0 0xf1030000 0x0 0x1000>;
44
-
#address-cells = <1>;
45
-
#size-cells = <0>;
46
-
clocks = <&clk150 &clk150>;
31
+
qspi: spi@f1030000 {
32
+
compatible = "xlnx,versal-qspi-1.0";
33
+
status = "okay";
34
+
clock-names = "ref_clk", "pclk";
35
+
num-cs = <0x1>;
36
+
reg = <0x0 0xf1030000 0x0 0x1000>;
37
+
#address-cells = <1>;
38
+
#size-cells = <0>;
39
+
clocks = <&clk150 &clk150>;
47
40
48
-
flash0: flash@0 {
49
-
compatible = "n25q512a", "micron,m25p80",
50
-
"jedec,spi-nor";
51
-
reg = <0x0>;
52
-
spi-tx-bus-width = <4>;
53
-
spi-rx-bus-width = <4>;
54
-
spi-max-frequency = <20000000>;
55
-
};
41
+
flash0: flash@0 {
42
+
compatible = "n25q512a", "micron,m25p80",
43
+
"jedec,spi-nor";
44
+
reg = <0x0>;
45
+
spi-tx-bus-width = <4>;
46
+
spi-rx-bus-width = <4>;
47
+
spi-max-frequency = <20000000>;
56
48
};
57
49
};
58
50
+14
-22
arch/arm/dts/versal-net-mini-emmc.dts
+14
-22
arch/arm/dts/versal-net-mini-emmc.dts
···
2
2
/*
3
3
* dts file for Xilinx Versal NET Mini eMMC Configuration
4
4
*
5
-
* (C) Copyright 2023, Advanced Micro Devices, Inc.
5
+
* (C) Copyright 2023-2025, Advanced Micro Devices, Inc.
6
6
*
7
7
* Michal Simek <michal.simek@amd.com>
8
8
* Ashok Reddy Soma <ashok.reddy.soma@amd.com>
···
42
42
bootph-all;
43
43
};
44
44
45
-
amba: axi {
46
-
bootph-all;
47
-
compatible = "simple-bus";
48
-
#address-cells = <2>;
49
-
#size-cells = <2>;
50
-
ranges;
51
-
52
-
sdhci1: mmc@f1050000 {
53
-
compatible = "xlnx,versal-net-emmc";
54
-
status = "okay";
55
-
non-removable;
56
-
disable-wp;
57
-
no-sd;
58
-
no-sdio;
59
-
cap-mmc-hw-reset;
60
-
bus-width = <8>;
61
-
reg = <0 0xf1050000 0 0x10000>;
62
-
clock-names = "clk_xin", "clk_ahb";
63
-
clocks = <&clk200>, <&clk200>;
64
-
xlnx,mio-bank = <0>;
65
-
};
45
+
sdhci1: mmc@f1050000 {
46
+
compatible = "xlnx,versal-net-emmc";
47
+
status = "okay";
48
+
non-removable;
49
+
disable-wp;
50
+
no-sd;
51
+
no-sdio;
52
+
cap-mmc-hw-reset;
53
+
bus-width = <8>;
54
+
reg = <0 0xf1050000 0 0x10000>;
55
+
clock-names = "clk_xin", "clk_ahb";
56
+
clocks = <&clk200>, <&clk200>;
57
+
xlnx,mio-bank = <0>;
66
58
};
67
59
};
+24
-32
arch/arm/dts/versal-net-mini-ospi.dtsi
+24
-32
arch/arm/dts/versal-net-mini-ospi.dtsi
···
2
2
/*
3
3
* dts file for Xilinx Versal NET Mini OSPI Configuration
4
4
*
5
-
* (C) Copyright 2023, Advanced Micro Devices, Inc.
5
+
* (C) Copyright 2023-2025, Advanced Micro Devices, Inc.
6
6
*
7
7
* Michal Simek <michal.simek@amd.com>
8
8
* Ashok Reddy Soma <ashok.reddy.soma@amd.com>
···
42
42
bootph-all;
43
43
};
44
44
45
-
amba: axi {
46
-
bootph-all;
47
-
compatible = "simple-bus";
48
-
#address-cells = <0x2>;
49
-
#size-cells = <0x2>;
50
-
ranges;
51
-
52
-
ospi: spi@f1010000 {
53
-
compatible = "cdns,qspi-nor";
54
-
status = "okay";
55
-
reg = <0 0xf1010000 0 0x10000>, <0 0xc0000000 0 0x20000000>;
56
-
clock-names = "ref_clk", "pclk";
57
-
clocks = <&clk125>, <&clk125>;
58
-
bus-num = <2>;
59
-
num-cs = <1>;
60
-
cdns,fifo-depth = <256>;
61
-
cdns,fifo-width = <4>;
62
-
cdns,is-dma = <1>;
63
-
cdns,is-stig-pgm = <1>;
64
-
cdns,trigger-address = <0xc0000000>;
65
-
#address-cells = <1>;
66
-
#size-cells = <0>;
45
+
ospi: spi@f1010000 {
46
+
compatible = "cdns,qspi-nor";
47
+
status = "okay";
48
+
reg = <0 0xf1010000 0 0x10000>, <0 0xc0000000 0 0x20000000>;
49
+
clock-names = "ref_clk", "pclk";
50
+
clocks = <&clk125>, <&clk125>;
51
+
bus-num = <2>;
52
+
num-cs = <1>;
53
+
cdns,fifo-depth = <256>;
54
+
cdns,fifo-width = <4>;
55
+
cdns,is-dma = <1>;
56
+
cdns,is-stig-pgm = <1>;
57
+
cdns,trigger-address = <0xc0000000>;
58
+
#address-cells = <1>;
59
+
#size-cells = <0>;
67
60
68
-
flash0: flash@0 {
69
-
compatible = "mt35xu02g", "micron,m25p80",
70
-
"jedec,spi-nor";
71
-
reg = <0>;
72
-
spi-tx-bus-width = <8>;
73
-
spi-rx-bus-width = <8>;
74
-
spi-max-frequency = <20000000>;
75
-
no-wp;
76
-
};
61
+
flash0: flash@0 {
62
+
compatible = "mt35xu02g", "micron,m25p80",
63
+
"jedec,spi-nor";
64
+
reg = <0>;
65
+
spi-tx-bus-width = <8>;
66
+
spi-rx-bus-width = <8>;
67
+
spi-max-frequency = <20000000>;
68
+
no-wp;
77
69
};
78
70
};
79
71
};
+17
-25
arch/arm/dts/versal-net-mini-qspi.dtsi
+17
-25
arch/arm/dts/versal-net-mini-qspi.dtsi
···
2
2
/*
3
3
* dts file for Xilinx Versal NET Mini QSPI Configuration
4
4
*
5
-
* (C) Copyright 2023, Advanced Micro Devices, Inc.
5
+
* (C) Copyright 2023-2025, Advanced Micro Devices, Inc.
6
6
*
7
7
* Michal Simek <michal.simek@amd.com>
8
8
* Ashok Reddy Soma <ashok.reddy.soma@amd.com>
···
42
42
bootph-all;
43
43
};
44
44
45
-
amba: axi {
46
-
bootph-all;
47
-
compatible = "simple-bus";
48
-
#address-cells = <2>;
49
-
#size-cells = <2>;
50
-
ranges;
51
-
52
-
qspi: spi@f1030000 {
53
-
compatible = "xlnx,versal-qspi-1.0";
54
-
status = "okay";
55
-
clock-names = "ref_clk", "pclk";
56
-
num-cs = <1>;
57
-
reg = <0 0xf1030000 0 0x1000>;
58
-
#address-cells = <1>;
59
-
#size-cells = <0>;
60
-
clocks = <&clk150>, <&clk150>;
45
+
qspi: spi@f1030000 {
46
+
compatible = "xlnx,versal-qspi-1.0";
47
+
status = "okay";
48
+
clock-names = "ref_clk", "pclk";
49
+
num-cs = <1>;
50
+
reg = <0 0xf1030000 0 0x1000>;
51
+
#address-cells = <1>;
52
+
#size-cells = <0>;
53
+
clocks = <&clk150>, <&clk150>;
61
54
62
-
flash0: flash@0 {
63
-
compatible = "n25q512a", "micron,m25p80",
64
-
"jedec,spi-nor";
65
-
reg = <0>;
66
-
spi-tx-bus-width = <4>;
67
-
spi-rx-bus-width = <4>;
68
-
spi-max-frequency = <20000000>;
69
-
};
55
+
flash0: flash@0 {
56
+
compatible = "n25q512a", "micron,m25p80",
57
+
"jedec,spi-nor";
58
+
reg = <0>;
59
+
spi-tx-bus-width = <4>;
60
+
spi-rx-bus-width = <4>;
61
+
spi-max-frequency = <20000000>;
70
62
};
71
63
};
72
64
};
+9
-17
arch/arm/dts/versal-net-mini.dts
+9
-17
arch/arm/dts/versal-net-mini.dts
···
3
3
* dts file for Xilinx Versal NET
4
4
*
5
5
* Copyright (C) 2021 - 2022, Xilinx, Inc.
6
-
* Copyright (C) 2022, Advanced Micro Devices, Inc.
6
+
* Copyright (C) 2022-2025, Advanced Micro Devices, Inc.
7
7
*
8
8
* Michal Simek <michal.simek@amd.com>
9
9
*/
···
45
45
bootph-all;
46
46
};
47
47
48
-
amba: axi {
49
-
compatible = "simple-bus";
48
+
serial0: serial@f1920000 {
50
49
bootph-all;
51
-
#address-cells = <2>;
52
-
#size-cells = <2>;
53
-
ranges;
54
-
55
-
serial0: serial@f1920000 {
56
-
bootph-all;
57
-
compatible = "arm,pl011", "arm,primecell";
58
-
reg = <0 0xf1920000 0 0x1000>;
59
-
reg-io-width = <4>;
60
-
clock-names = "uartclk", "apb_pclk";
61
-
clocks = <&clk1>, <&clk1>;
62
-
clock = <1000000>;
63
-
skip-init;
64
-
};
50
+
compatible = "arm,pl011", "arm,primecell";
51
+
reg = <0 0xf1920000 0 0x1000>;
52
+
reg-io-width = <4>;
53
+
clock-names = "uartclk", "apb_pclk";
54
+
clocks = <&clk1>, <&clk1>;
55
+
clock = <1000000>;
56
+
skip-init;
65
57
};
66
58
};
+1
-1
arch/arm/dts/zynqmp-clk-ccf.dtsi
+1
-1
arch/arm/dts/zynqmp-clk-ccf.dtsi
+12
-19
arch/arm/dts/zynqmp-mini-emmc0.dts
+12
-19
arch/arm/dts/zynqmp-mini-emmc0.dts
···
41
41
clock-frequency = <200000000>;
42
42
};
43
43
44
-
amba: axi {
45
-
compatible = "simple-bus";
46
-
#address-cells = <2>;
47
-
#size-cells = <2>;
48
-
ranges;
49
-
50
-
sdhci0: mmc@ff160000 {
51
-
bootph-all;
52
-
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
53
-
status = "disabled";
54
-
non-removable;
55
-
no-sd;
56
-
no-sdio;
57
-
cap-mmc-hw-reset;
58
-
bus-width = <8>;
59
-
reg = <0x0 0xff160000 0x0 0x1000>;
60
-
clock-names = "clk_xin", "clk_ahb";
61
-
clocks = <&clk_xin &clk_xin>;
62
-
};
44
+
sdhci0: mmc@ff160000 {
45
+
bootph-all;
46
+
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
47
+
status = "disabled";
48
+
non-removable;
49
+
no-sd;
50
+
no-sdio;
51
+
cap-mmc-hw-reset;
52
+
bus-width = <8>;
53
+
reg = <0x0 0xff160000 0x0 0x1000>;
54
+
clock-names = "clk_xin", "clk_ahb";
55
+
clocks = <&clk_xin &clk_xin>;
63
56
};
64
57
};
65
58
+12
-19
arch/arm/dts/zynqmp-mini-emmc1.dts
+12
-19
arch/arm/dts/zynqmp-mini-emmc1.dts
···
41
41
clock-frequency = <200000000>;
42
42
};
43
43
44
-
amba: axi {
45
-
compatible = "simple-bus";
46
-
#address-cells = <2>;
47
-
#size-cells = <2>;
48
-
ranges;
49
-
50
-
sdhci1: mmc@ff170000 {
51
-
bootph-all;
52
-
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
53
-
status = "disabled";
54
-
non-removable;
55
-
no-sd;
56
-
no-sdio;
57
-
cap-mmc-hw-reset;
58
-
bus-width = <8>;
59
-
reg = <0x0 0xff170000 0x0 0x1000>;
60
-
clock-names = "clk_xin", "clk_ahb";
61
-
clocks = <&clk_xin &clk_xin>;
62
-
};
44
+
sdhci1: mmc@ff170000 {
45
+
bootph-all;
46
+
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
47
+
status = "disabled";
48
+
non-removable;
49
+
no-sd;
50
+
no-sdio;
51
+
cap-mmc-hw-reset;
52
+
bus-width = <8>;
53
+
reg = <0x0 0xff170000 0x0 0x1000>;
54
+
clock-names = "clk_xin", "clk_ahb";
55
+
clocks = <&clk_xin &clk_xin>;
63
56
};
64
57
};
65
58
+14
-21
arch/arm/dts/zynqmp-mini-nand.dts
+14
-21
arch/arm/dts/zynqmp-mini-nand.dts
···
35
35
bootph-all;
36
36
};
37
37
38
-
amba: axi {
39
-
compatible = "simple-bus";
40
-
#address-cells = <2>;
41
-
#size-cells = <1>;
42
-
ranges;
43
-
44
-
nand0: nand@ff100000 {
45
-
compatible = "arasan,nfc-v3p10";
46
-
status = "okay";
47
-
reg = <0x0 0xff100000 0x1000>;
48
-
clock-names = "clk_sys", "clk_flash";
49
-
#address-cells = <1>;
50
-
#size-cells = <0>;
51
-
arasan,has-mdma;
52
-
num-cs = <2>;
53
-
nand@0 {
54
-
reg = <0>;
55
-
#address-cells = <2>;
56
-
#size-cells = <1>;
57
-
nand-ecc-mode = "hw";
58
-
};
38
+
nand0: nand@ff100000 {
39
+
compatible = "arasan,nfc-v3p10";
40
+
status = "okay";
41
+
reg = <0x0 0xff100000 0x1000>;
42
+
clock-names = "clk_sys", "clk_flash";
43
+
#address-cells = <1>;
44
+
#size-cells = <0>;
45
+
arasan,has-mdma;
46
+
num-cs = <2>;
47
+
nand@0 {
48
+
reg = <0>;
49
+
#address-cells = <2>;
50
+
#size-cells = <1>;
51
+
nand-ecc-mode = "hw";
59
52
};
60
53
};
61
54
};
+9
-16
arch/arm/dts/zynqmp-mini-qspi.dts
+9
-16
arch/arm/dts/zynqmp-mini-qspi.dts
···
42
42
clock-frequency = <125000000>;
43
43
};
44
44
45
-
amba: axi {
46
-
compatible = "simple-bus";
47
-
#address-cells = <2>;
48
-
#size-cells = <1>;
49
-
ranges;
50
-
51
-
qspi: spi@ff0f0000 {
52
-
compatible = "xlnx,zynqmp-qspi-1.0";
53
-
status = "disabled";
54
-
clock-names = "ref_clk", "pclk";
55
-
clocks = <&misc_clk &misc_clk>;
56
-
num-cs = <1>;
57
-
reg = <0x0 0xff0f0000 0x1000 0x0 0xc0000000 0x8000000>;
58
-
#address-cells = <1>;
59
-
#size-cells = <0>;
60
-
};
45
+
qspi: spi@ff0f0000 {
46
+
compatible = "xlnx,zynqmp-qspi-1.0";
47
+
status = "disabled";
48
+
clock-names = "ref_clk", "pclk";
49
+
clocks = <&misc_clk &misc_clk>;
50
+
num-cs = <1>;
51
+
reg = <0x0 0xff0f0000 0x1000 0x0 0xc0000000 0x8000000>;
52
+
#address-cells = <1>;
53
+
#size-cells = <0>;
61
54
};
62
55
};
63
56
+2
board/amd/versal2/board.c
+2
board/amd/versal2/board.c
+32
-1
board/xilinx/common/board.c
+32
-1
board/xilinx/common/board.c
···
1
1
// SPDX-License-Identifier: GPL-2.0+
2
2
/*
3
3
* (C) Copyright 2014 - 2022, Xilinx, Inc.
4
-
* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
4
+
* (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc.
5
5
*
6
6
* Michal Simek <michal.simek@amd.com>
7
7
*/
···
712
712
}
713
713
714
714
#endif
715
+
716
+
#if IS_ENABLED(CONFIG_BOARD_RNG_SEED)
717
+
/* Use hardware rng to seed Linux random. */
718
+
__weak int board_rng_seed(struct abuf *buf)
719
+
{
720
+
struct udevice *dev;
721
+
ulong len = 64;
722
+
u64 *data;
723
+
724
+
if (uclass_get_device(UCLASS_RNG, 0, &dev) || !dev) {
725
+
printf("No RNG device\n");
726
+
return -ENODEV;
727
+
}
728
+
729
+
data = malloc(len);
730
+
if (!data) {
731
+
printf("Out of memory\n");
732
+
return -ENOMEM;
733
+
}
734
+
735
+
if (dm_rng_read(dev, data, len)) {
736
+
printf("Reading RNG failed\n");
737
+
free(data);
738
+
return -EIO;
739
+
}
740
+
741
+
abuf_init_set(buf, data, len);
742
+
743
+
return 0;
744
+
}
745
+
#endif
+6
cmd/Kconfig
+6
cmd/Kconfig
···
190
190
help
191
191
Command to read the metadata and dump it's contents
192
192
193
+
config CMD_HELP
194
+
bool "help"
195
+
default y
196
+
help
197
+
Command to show help information about other commands.
198
+
193
199
config CMD_HISTORY
194
200
bool "history"
195
201
depends on CMDLINE_EDITING
+1
-1
cmd/Makefile
+1
-1
cmd/Makefile
-6
cmd/help.c
-6
cmd/help.c
···
9
9
static int do_help(struct cmd_tbl *cmdtp, int flag, int argc,
10
10
char *const argv[])
11
11
{
12
-
#ifdef CONFIG_CMDLINE
13
12
struct cmd_tbl *start = ll_entry_start(struct cmd_tbl, cmd);
14
13
const int len = ll_entry_count(struct cmd_tbl, cmd);
15
14
return _do_help(start, len, cmdtp, flag, argc, argv);
16
-
#else
17
-
return 0;
18
-
#endif
19
15
}
20
16
21
17
U_BOOT_CMD(
···
27
23
" - print detailed usage of 'command'"
28
24
);
29
25
30
-
#ifdef CONFIG_CMDLINE
31
26
/*
32
27
* This does not use the U_BOOT_CMD macro as ? can't be used in symbol names
33
28
* nor can we rely on the CONFIG_SYS_LONGHELP helper macro
···
39
34
""
40
35
#endif /* CONFIG_SYS_LONGHELP */
41
36
};
42
-
#endif
+2
configs/amd_versal2_mini_defconfig
+2
configs/amd_versal2_mini_defconfig
···
32
32
# CONFIG_SYS_LONGHELP is not set
33
33
CONFIG_SYS_PROMPT="versal2> "
34
34
# CONFIG_CMD_CONSOLE is not set
35
+
# CONFIG_CMD_HELP is not set
35
36
# CONFIG_CMD_BOOTD is not set
36
37
# CONFIG_CMD_BOOTM is not set
37
38
# CONFIG_CMD_BOOTI is not set
···
63
64
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
64
65
CONFIG_NO_NET=y
65
66
# CONFIG_DM_DEVICE_REMOVE is not set
67
+
# CONFIG_SIMPLE_BUS is not set
66
68
# CONFIG_GPIO is not set
67
69
# CONFIG_I2C is not set
68
70
# CONFIG_INPUT is not set
+2
configs/amd_versal2_mini_emmc_defconfig
+2
configs/amd_versal2_mini_emmc_defconfig
···
26
26
CONFIG_SYS_PROMPT="versal2> "
27
27
# CONFIG_CMD_BDI is not set
28
28
# CONFIG_CMD_CONSOLE is not set
29
+
# CONFIG_CMD_HELP is not set
29
30
# CONFIG_CMD_BOOTD is not set
30
31
# CONFIG_CMD_BOOTM is not set
31
32
# CONFIG_CMD_BOOTI is not set
···
54
55
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
55
56
CONFIG_NO_NET=y
56
57
# CONFIG_DM_DEVICE_REMOVE is not set
58
+
# CONFIG_SIMPLE_BUS is not set
57
59
CONFIG_MMC_HS200_SUPPORT=y
58
60
CONFIG_MMC_SDHCI=y
59
61
CONFIG_MMC_SDHCI_ZYNQ=y
+4
-1
configs/amd_versal2_mini_ospi_defconfig
+4
-1
configs/amd_versal2_mini_ospi_defconfig
···
9
9
CONFIG_SYS_MALLOC_F_LEN=0x4000
10
10
CONFIG_NR_DRAM_BANKS=3
11
11
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
12
-
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xBBF20000
12
+
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xBBFF8000
13
13
CONFIG_ENV_SIZE=0x80
14
14
CONFIG_DEFAULT_DEVICE_TREE="amd-versal2-mini"
15
15
CONFIG_SYS_LOAD_ADDR=0xBBF80000
···
30
30
# CONFIG_SYS_LONGHELP is not set
31
31
CONFIG_SYS_PROMPT="versal2> "
32
32
# CONFIG_CMD_CONSOLE is not set
33
+
# CONFIG_CMD_HELP is not set
33
34
# CONFIG_CMD_BOOTD is not set
34
35
# CONFIG_CMD_BOOTM is not set
35
36
# CONFIG_CMD_BOOTI is not set
···
57
58
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
58
59
CONFIG_NO_NET=y
59
60
# CONFIG_DM_DEVICE_REMOVE is not set
61
+
# CONFIG_SIMPLE_BUS is not set
62
+
# CONFIG_ZYNQMP_FIRMWARE is not set
60
63
# CONFIG_GPIO is not set
61
64
# CONFIG_I2C is not set
62
65
# CONFIG_INPUT is not set
+2
configs/amd_versal2_mini_qspi_defconfig
+2
configs/amd_versal2_mini_qspi_defconfig
···
30
30
# CONFIG_SYS_LONGHELP is not set
31
31
CONFIG_SYS_PROMPT="versal2> "
32
32
# CONFIG_CMD_CONSOLE is not set
33
+
# CONFIG_CMD_HELP is not set
33
34
# CONFIG_CMD_BOOTD is not set
34
35
# CONFIG_CMD_BOOTM is not set
35
36
# CONFIG_CMD_BOOTI is not set
···
57
58
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
58
59
CONFIG_NO_NET=y
59
60
# CONFIG_DM_DEVICE_REMOVE is not set
61
+
# CONFIG_SIMPLE_BUS is not set
60
62
# CONFIG_GPIO is not set
61
63
# CONFIG_I2C is not set
62
64
# CONFIG_INPUT is not set
+5
-1
configs/amd_versal2_virt_defconfig
+5
-1
configs/amd_versal2_virt_defconfig
···
1
1
CONFIG_ARM=y
2
-
CONFIG_COUNTER_FREQUENCY=375000
2
+
CONFIG_COUNTER_FREQUENCY=100000000
3
3
CONFIG_POSITION_INDEPENDENT=y
4
4
CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864
5
5
CONFIG_ARCH_VERSAL2=y
···
43
43
CONFIG_MMC_SPEED_MODE_SET=y
44
44
CONFIG_CMD_OPTEE=y
45
45
CONFIG_CMD_MTD=y
46
+
CONFIG_CMD_POWEROFF=y
46
47
CONFIG_CMD_SF_TEST=y
47
48
CONFIG_CMD_SPI=y
48
49
CONFIG_CMD_UFS=y
···
130
131
CONFIG_CADENCE_OSPI_VERSAL=y
131
132
CONFIG_ZYNQ_SPI=y
132
133
CONFIG_ZYNQMP_GQSPI=y
134
+
CONFIG_SPI_STACKED_PARALLEL=y
135
+
CONFIG_SYSRESET=y
136
+
CONFIG_SYSRESET_PSCI=y
133
137
CONFIG_TEE=y
134
138
CONFIG_OPTEE=y
135
139
CONFIG_TPM2_TIS_SPI=y
+2
configs/xilinx_versal_mini_defconfig
+2
configs/xilinx_versal_mini_defconfig
···
33
33
# CONFIG_SYS_LONGHELP is not set
34
34
CONFIG_SYS_PROMPT="Versal> "
35
35
# CONFIG_CMD_CONSOLE is not set
36
+
# CONFIG_CMD_HELP is not set
36
37
# CONFIG_CMD_BOOTD is not set
37
38
# CONFIG_CMD_BOOTM is not set
38
39
# CONFIG_CMD_BOOTI is not set
···
60
61
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
61
62
CONFIG_NO_NET=y
62
63
# CONFIG_DM_DEVICE_REMOVE is not set
64
+
# CONFIG_SIMPLE_BUS is not set
63
65
# CONFIG_MMC is not set
64
66
CONFIG_ARM_DCC=y
65
67
# CONFIG_GZIP is not set
+2
configs/xilinx_versal_mini_emmc0_defconfig
+2
configs/xilinx_versal_mini_emmc0_defconfig
···
31
31
CONFIG_SYS_PROMPT="Versal> "
32
32
# CONFIG_CMD_BDI is not set
33
33
# CONFIG_CMD_CONSOLE is not set
34
+
# CONFIG_CMD_HELP is not set
34
35
# CONFIG_CMD_BOOTD is not set
35
36
# CONFIG_CMD_BOOTM is not set
36
37
# CONFIG_CMD_BOOTI is not set
···
59
60
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
60
61
CONFIG_NO_NET=y
61
62
# CONFIG_DM_DEVICE_REMOVE is not set
63
+
# CONFIG_SIMPLE_BUS is not set
62
64
CONFIG_MMC_SDHCI=y
63
65
CONFIG_MMC_SDHCI_ZYNQ=y
64
66
CONFIG_ARM_DCC=y
+2
configs/xilinx_versal_mini_emmc1_defconfig
+2
configs/xilinx_versal_mini_emmc1_defconfig
···
31
31
CONFIG_SYS_PROMPT="Versal> "
32
32
# CONFIG_CMD_BDI is not set
33
33
# CONFIG_CMD_CONSOLE is not set
34
+
# CONFIG_CMD_HELP is not set
34
35
# CONFIG_CMD_BOOTD is not set
35
36
# CONFIG_CMD_BOOTM is not set
36
37
# CONFIG_CMD_BOOTI is not set
···
59
60
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
60
61
CONFIG_NO_NET=y
61
62
# CONFIG_DM_DEVICE_REMOVE is not set
63
+
# CONFIG_SIMPLE_BUS is not set
62
64
CONFIG_MMC_SDHCI=y
63
65
CONFIG_MMC_SDHCI_ZYNQ=y
64
66
CONFIG_ARM_DCC=y
+2
configs/xilinx_versal_mini_ospi_defconfig
+2
configs/xilinx_versal_mini_ospi_defconfig
···
31
31
CONFIG_SYS_PROMPT="Versal> "
32
32
# CONFIG_CMD_BDI is not set
33
33
# CONFIG_CMD_CONSOLE is not set
34
+
# CONFIG_CMD_HELP is not set
34
35
# CONFIG_CMD_BOOTD is not set
35
36
# CONFIG_CMD_BOOTM is not set
36
37
# CONFIG_CMD_BOOTI is not set
···
54
55
# CONFIG_CMD_SETEXPR is not set
55
56
CONFIG_NO_NET=y
56
57
# CONFIG_DM_DEVICE_REMOVE is not set
58
+
# CONFIG_SIMPLE_BUS is not set
57
59
# CONFIG_MMC is not set
58
60
CONFIG_MTD=y
59
61
CONFIG_DM_SPI_FLASH=y
+2
configs/xilinx_versal_mini_qspi_defconfig
+2
configs/xilinx_versal_mini_qspi_defconfig
···
32
32
# CONFIG_SYS_XTRACE is not set
33
33
# CONFIG_CMD_BDI is not set
34
34
# CONFIG_CMD_CONSOLE is not set
35
+
# CONFIG_CMD_HELP is not set
35
36
# CONFIG_CMD_BOOTD is not set
36
37
# CONFIG_CMD_BOOTM is not set
37
38
# CONFIG_CMD_BOOTI is not set
···
56
57
# CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG is not set
57
58
CONFIG_NO_NET=y
58
59
# CONFIG_DM_DEVICE_REMOVE is not set
60
+
# CONFIG_SIMPLE_BUS is not set
59
61
# CONFIG_GPIO is not set
60
62
# CONFIG_I2C is not set
61
63
# CONFIG_INPUT is not set
+2
configs/xilinx_versal_net_mini_defconfig
+2
configs/xilinx_versal_net_mini_defconfig
···
33
33
# CONFIG_SYS_LONGHELP is not set
34
34
CONFIG_SYS_PROMPT="Versal NET> "
35
35
# CONFIG_CMD_CONSOLE is not set
36
+
# CONFIG_CMD_HELP is not set
36
37
# CONFIG_CMD_BOOTD is not set
37
38
# CONFIG_CMD_BOOTM is not set
38
39
# CONFIG_CMD_BOOTI is not set
···
64
65
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
65
66
CONFIG_NO_NET=y
66
67
# CONFIG_DM_DEVICE_REMOVE is not set
68
+
# CONFIG_SIMPLE_BUS is not set
67
69
# CONFIG_GPIO is not set
68
70
# CONFIG_I2C is not set
69
71
# CONFIG_INPUT is not set
+2
configs/xilinx_versal_net_mini_emmc_defconfig
+2
configs/xilinx_versal_net_mini_emmc_defconfig
···
26
26
CONFIG_SYS_PROMPT="Versal NET> "
27
27
# CONFIG_CMD_BDI is not set
28
28
# CONFIG_CMD_CONSOLE is not set
29
+
# CONFIG_CMD_HELP is not set
29
30
# CONFIG_CMD_BOOTD is not set
30
31
# CONFIG_CMD_BOOTM is not set
31
32
# CONFIG_CMD_BOOTI is not set
···
54
55
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
55
56
CONFIG_NO_NET=y
56
57
# CONFIG_DM_DEVICE_REMOVE is not set
58
+
# CONFIG_SIMPLE_BUS is not set
57
59
CONFIG_MMC_HS200_SUPPORT=y
58
60
CONFIG_MMC_SDHCI=y
59
61
CONFIG_MMC_SDHCI_ZYNQ=y
+2
configs/xilinx_versal_net_mini_ospi_defconfig
+2
configs/xilinx_versal_net_mini_ospi_defconfig
···
30
30
CONFIG_SYS_PROMPT="Versal NET> "
31
31
# CONFIG_CMD_BDI is not set
32
32
# CONFIG_CMD_CONSOLE is not set
33
+
# CONFIG_CMD_HELP is not set
33
34
# CONFIG_CMD_BOOTD is not set
34
35
# CONFIG_CMD_BOOTM is not set
35
36
# CONFIG_CMD_BOOTI is not set
···
53
54
# CONFIG_CMD_SETEXPR is not set
54
55
CONFIG_NO_NET=y
55
56
# CONFIG_DM_DEVICE_REMOVE is not set
57
+
# CONFIG_SIMPLE_BUS is not set
56
58
# CONFIG_MMC is not set
57
59
CONFIG_MTD=y
58
60
CONFIG_DM_SPI_FLASH=y
+2
configs/xilinx_versal_net_mini_qspi_defconfig
+2
configs/xilinx_versal_net_mini_qspi_defconfig
···
31
31
# CONFIG_SYS_XTRACE is not set
32
32
# CONFIG_CMD_BDI is not set
33
33
# CONFIG_CMD_CONSOLE is not set
34
+
# CONFIG_CMD_HELP is not set
34
35
# CONFIG_CMD_BOOTD is not set
35
36
# CONFIG_CMD_BOOTM is not set
36
37
# CONFIG_CMD_BOOTI is not set
···
55
56
# CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG is not set
56
57
CONFIG_NO_NET=y
57
58
# CONFIG_DM_DEVICE_REMOVE is not set
59
+
# CONFIG_SIMPLE_BUS is not set
58
60
# CONFIG_GPIO is not set
59
61
# CONFIG_I2C is not set
60
62
# CONFIG_INPUT is not set
+1
configs/xilinx_versal_net_virt_defconfig
+1
configs/xilinx_versal_net_virt_defconfig
+1
configs/xilinx_versal_virt_defconfig
+1
configs/xilinx_versal_virt_defconfig
+1
configs/xilinx_zynqmp_kria_defconfig
+1
configs/xilinx_zynqmp_kria_defconfig
+2
configs/xilinx_zynqmp_mini_defconfig
+2
configs/xilinx_zynqmp_mini_defconfig
···
26
26
# CONFIG_SYS_LONGHELP is not set
27
27
# CONFIG_CMD_BDI is not set
28
28
# CONFIG_CMD_CONSOLE is not set
29
+
# CONFIG_CMD_HELP is not set
29
30
# CONFIG_CMD_BOOTD is not set
30
31
# CONFIG_CMD_BOOTM is not set
31
32
# CONFIG_CMD_BOOTI is not set
···
56
57
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
57
58
CONFIG_NO_NET=y
58
59
# CONFIG_DM_DEVICE_REMOVE is not set
60
+
# CONFIG_SIMPLE_BUS is not set
59
61
# CONFIG_DM_MAILBOX is not set
60
62
# CONFIG_MMC is not set
61
63
CONFIG_ARM_DCC=y
+2
configs/xilinx_zynqmp_mini_emmc0_defconfig
+2
configs/xilinx_zynqmp_mini_emmc0_defconfig
···
40
40
# CONFIG_AUTO_COMPLETE is not set
41
41
# CONFIG_CMD_BDI is not set
42
42
# CONFIG_CMD_CONSOLE is not set
43
+
# CONFIG_CMD_HELP is not set
43
44
# CONFIG_CMD_BOOTD is not set
44
45
# CONFIG_CMD_BOOTM is not set
45
46
# CONFIG_CMD_BOOTI is not set
···
71
72
CONFIG_NO_NET=y
72
73
# CONFIG_DM_DEVICE_REMOVE is not set
73
74
CONFIG_SPL_DM_SEQ_ALIAS=y
75
+
# CONFIG_SIMPLE_BUS is not set
74
76
# CONFIG_DM_MAILBOX is not set
75
77
CONFIG_SUPPORT_EMMC_BOOT=y
76
78
CONFIG_MMC_SDHCI=y
+2
configs/xilinx_zynqmp_mini_emmc1_defconfig
+2
configs/xilinx_zynqmp_mini_emmc1_defconfig
···
40
40
# CONFIG_AUTO_COMPLETE is not set
41
41
# CONFIG_CMD_BDI is not set
42
42
# CONFIG_CMD_CONSOLE is not set
43
+
# CONFIG_CMD_HELP is not set
43
44
# CONFIG_CMD_BOOTD is not set
44
45
# CONFIG_CMD_BOOTM is not set
45
46
# CONFIG_CMD_BOOTI is not set
···
71
72
CONFIG_NO_NET=y
72
73
# CONFIG_DM_DEVICE_REMOVE is not set
73
74
CONFIG_SPL_DM_SEQ_ALIAS=y
75
+
# CONFIG_SIMPLE_BUS is not set
74
76
# CONFIG_DM_MAILBOX is not set
75
77
CONFIG_SUPPORT_EMMC_BOOT=y
76
78
CONFIG_MMC_SDHCI=y
+2
configs/xilinx_zynqmp_mini_nand_defconfig
+2
configs/xilinx_zynqmp_mini_nand_defconfig
···
27
27
# CONFIG_SYS_LONGHELP is not set
28
28
# CONFIG_CMD_BDI is not set
29
29
# CONFIG_CMD_CONSOLE is not set
30
+
# CONFIG_CMD_HELP is not set
30
31
# CONFIG_CMD_BOOTD is not set
31
32
# CONFIG_CMD_BOOTM is not set
32
33
# CONFIG_CMD_BOOTI is not set
···
51
52
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
52
53
CONFIG_NO_NET=y
53
54
# CONFIG_DM_DEVICE_REMOVE is not set
55
+
# CONFIG_SIMPLE_BUS is not set
54
56
# CONFIG_DM_MAILBOX is not set
55
57
# CONFIG_MMC is not set
56
58
CONFIG_DM_MTD=y
+2
configs/xilinx_zynqmp_mini_nand_single_defconfig
+2
configs/xilinx_zynqmp_mini_nand_single_defconfig
···
27
27
# CONFIG_SYS_LONGHELP is not set
28
28
# CONFIG_CMD_BDI is not set
29
29
# CONFIG_CMD_CONSOLE is not set
30
+
# CONFIG_CMD_HELP is not set
30
31
# CONFIG_CMD_BOOTD is not set
31
32
# CONFIG_CMD_BOOTM is not set
32
33
# CONFIG_CMD_BOOTI is not set
···
51
52
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
52
53
CONFIG_NO_NET=y
53
54
# CONFIG_DM_DEVICE_REMOVE is not set
55
+
# CONFIG_SIMPLE_BUS is not set
54
56
# CONFIG_DM_MAILBOX is not set
55
57
# CONFIG_MMC is not set
56
58
CONFIG_DM_MTD=y
+2
configs/xilinx_zynqmp_mini_qspi_defconfig
+2
configs/xilinx_zynqmp_mini_qspi_defconfig
···
43
43
# CONFIG_SYS_LONGHELP is not set
44
44
# CONFIG_CMD_BDI is not set
45
45
# CONFIG_CMD_CONSOLE is not set
46
+
# CONFIG_CMD_HELP is not set
46
47
# CONFIG_CMD_BOOTD is not set
47
48
# CONFIG_CMD_BOOTM is not set
48
49
# CONFIG_CMD_BOOTI is not set
···
73
74
CONFIG_NO_NET=y
74
75
# CONFIG_DM_DEVICE_REMOVE is not set
75
76
CONFIG_SPL_DM_SEQ_ALIAS=y
77
+
# CONFIG_SIMPLE_BUS is not set
76
78
# CONFIG_FIRMWARE is not set
77
79
# CONFIG_GPIO is not set
78
80
# CONFIG_I2C is not set
+1
-1
configs/xilinx_zynqmp_virt_defconfig
+1
-1
configs/xilinx_zynqmp_virt_defconfig
···
163
163
CONFIG_NAND_ARASAN=y
164
164
CONFIG_SYS_NAND_ONFI_DETECTION=y
165
165
CONFIG_SYS_NAND_MAX_CHIPS=2
166
-
CONFIG_SPI_FLASH_BAR=y
167
166
CONFIG_SPI_FLASH_GIGADEVICE=y
168
167
CONFIG_SPI_FLASH_ISSI=y
169
168
CONFIG_SPI_FLASH_MACRONIX=y
···
182
181
CONFIG_PHY_REALTEK=y
183
182
CONFIG_PHY_TI_DP83867=y
184
183
CONFIG_PHY_VITESSE=y
184
+
CONFIG_PHY_XILINX=y
185
185
CONFIG_PHY_XILINX_GMII2RGMII=y
186
186
CONFIG_PHY_FIXED=y
187
187
CONFIG_DM_ETH_PHY=y
+1
-1
drivers/clk/Kconfig
+1
-1
drivers/clk/Kconfig
···
225
225
config CLK_VERSAL
226
226
bool "Enable clock driver support for Versal"
227
227
depends on (ARCH_VERSAL || ARCH_VERSAL_NET)
228
-
imply ZYNQMP_FIRMWARE
228
+
depends on ZYNQMP_FIRMWARE
229
229
help
230
230
This clock driver adds support for clock realted settings for
231
231
Versal platform.
+20
drivers/clk/clk_zynqmp.c
+20
drivers/clk/clk_zynqmp.c
···
108
108
#define PLLCTRL_POST_SRC_MASK (0x7 << PLLCTRL_POST_SRC_SHFT)
109
109
#define PLLCTRL_PRE_SRC_SHFT 20
110
110
#define PLLCTRL_PRE_SRC_MASK (0x7 << PLLCTRL_PRE_SRC_SHFT)
111
+
#define PLL_TO_LPD_DIV_SHIFT 8
112
+
#define PLL_TO_LPD_DIV_MASK (0x3f << PLL_TO_LPD_DIV_SHIFT)
111
113
112
114
#define NUM_MIO_PINS 77
113
115
···
334
336
return CRF_APB_TOPSW_LSBUS_CTRL;
335
337
case iopll_to_fpd:
336
338
return CRL_APB_IOPLL_TO_FPD_CTRL;
339
+
case dpll_to_lpd:
340
+
return CRF_APB_DPLL_TO_LPD_CTRL;
337
341
default:
338
342
debug("Invalid clk id%d\n", id);
339
343
}
···
396
400
397
401
if (clk_ctrl & (1 << 16))
398
402
freq /= 2;
403
+
404
+
if (id == dpll) {
405
+
u32 dpll_lpd_reg, cross_div;
406
+
407
+
dpll_lpd_reg = zynqmp_clk_get_register(dpll_to_lpd);
408
+
409
+
ret = zynqmp_mmio_read(dpll_lpd_reg, &cross_div);
410
+
if (ret) {
411
+
printf("%s mio read fail\n", __func__);
412
+
return -EIO;
413
+
}
414
+
415
+
cross_div = (cross_div & PLL_TO_LPD_DIV_MASK) >>
416
+
PLL_TO_LPD_DIV_SHIFT;
417
+
freq /= cross_div;
418
+
}
399
419
400
420
return freq;
401
421
}
+1
drivers/firmware/Kconfig
+1
drivers/firmware/Kconfig
+35
-25
drivers/firmware/firmware-zynqmp.c
+35
-25
drivers/firmware/firmware-zynqmp.c
···
422
422
};
423
423
#endif
424
424
425
+
smc_call_handler_t __data smc_call_handler;
426
+
427
+
static int smc_call_legacy(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
428
+
u32 arg3, u32 *ret_payload)
429
+
{
430
+
struct pt_regs regs;
431
+
432
+
regs.regs[0] = PM_SIP_SVC | api_id;
433
+
regs.regs[1] = ((u64)arg1 << 32) | arg0;
434
+
regs.regs[2] = ((u64)arg3 << 32) | arg2;
435
+
436
+
smc_call(®s);
437
+
438
+
if (ret_payload) {
439
+
ret_payload[0] = (u32)regs.regs[0];
440
+
ret_payload[1] = upper_32_bits(regs.regs[0]);
441
+
ret_payload[2] = (u32)regs.regs[1];
442
+
ret_payload[3] = upper_32_bits(regs.regs[1]);
443
+
ret_payload[4] = (u32)regs.regs[2];
444
+
}
445
+
446
+
return (ret_payload) ? ret_payload[0] : 0;
447
+
}
448
+
425
449
int __maybe_unused xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
426
450
u32 arg3, u32 *ret_payload)
427
451
{
···
450
474
PAYLOAD_ARG_CNT);
451
475
if (ret)
452
476
return ret;
477
+
478
+
return (ret_payload) ? ret_payload[0] : 0;
453
479
#else
454
480
return -EPERM;
455
481
#endif
456
-
} else {
457
-
/*
458
-
* Added SIP service call Function Identifier
459
-
* Make sure to stay in x0 register
460
-
*/
461
-
struct pt_regs regs;
462
-
463
-
regs.regs[0] = PM_SIP_SVC | api_id;
464
-
regs.regs[1] = ((u64)arg1 << 32) | arg0;
465
-
regs.regs[2] = ((u64)arg3 << 32) | arg2;
466
-
467
-
smc_call(®s);
468
-
469
-
if (ret_payload) {
470
-
ret_payload[0] = (u32)regs.regs[0];
471
-
ret_payload[1] = upper_32_bits(regs.regs[0]);
472
-
ret_payload[2] = (u32)regs.regs[1];
473
-
ret_payload[3] = upper_32_bits(regs.regs[1]);
474
-
ret_payload[4] = (u32)regs.regs[2];
475
-
}
476
-
477
482
}
478
-
return (ret_payload) ? ret_payload[0] : 0;
483
+
484
+
return smc_call_handler(api_id, arg0, arg1, arg2, arg3, ret_payload);
479
485
}
480
486
481
487
static const struct udevice_id zynqmp_firmware_ids[] = {
482
-
{ .compatible = "xlnx,zynqmp-firmware" },
483
-
{ .compatible = "xlnx,versal-firmware"},
484
-
{ .compatible = "xlnx,versal-net-firmware"},
488
+
{ .compatible = "xlnx,zynqmp-firmware", .data = (ulong)smc_call_legacy },
489
+
{ .compatible = "xlnx,versal-firmware", .data = (ulong)smc_call_legacy},
490
+
{ .compatible = "xlnx,versal-net-firmware", .data = (ulong)smc_call_legacy },
485
491
{ }
486
492
};
487
493
···
489
495
{
490
496
int ret;
491
497
struct udevice *child;
498
+
499
+
smc_call_handler = (smc_call_handler_t)dev_get_driver_data(dev);
500
+
if (!smc_call_handler)
501
+
return -EINVAL;
492
502
493
503
if ((IS_ENABLED(CONFIG_XPL_BUILD) &&
494
504
IS_ENABLED(CONFIG_SPL_POWER_DOMAIN) &&
+2
-1
drivers/fpga/intel_sdm_mb.c
+2
-1
drivers/fpga/intel_sdm_mb.c
+22
drivers/mmc/zynq_sdhci.c
+22
drivers/mmc/zynq_sdhci.c
···
1127
1127
if (arasan_sdhci_is_compatible(dev, SDHCI_COMPATIBLE_VERSAL_NET_EMMC))
1128
1128
priv->internal_phy_reg = true;
1129
1129
1130
+
ret = reset_get_bulk(dev, &priv->resets);
1131
+
if (ret == -ENOTSUPP || ret == -ENOENT) {
1132
+
dev_warn(dev, "Reset not found\n");
1133
+
} else if (ret) {
1134
+
dev_err(dev, "Reset failed\n");
1135
+
return ret;
1136
+
}
1137
+
1138
+
if (!ret) {
1139
+
ret = reset_assert_bulk(&priv->resets);
1140
+
if (ret) {
1141
+
dev_err(dev, "Reset assert failed\n");
1142
+
return ret;
1143
+
}
1144
+
1145
+
ret = reset_deassert_bulk(&priv->resets);
1146
+
if (ret) {
1147
+
dev_err(dev, "Reset release failed\n");
1148
+
return ret;
1149
+
}
1150
+
}
1151
+
1130
1152
ret = clk_get_by_index(dev, 0, &clk);
1131
1153
if (ret < 0) {
1132
1154
dev_err(dev, "failed to get clock\n");
+11
-1
drivers/spi/cadence_ospi_versal.c
+11
-1
drivers/spi/cadence_ospi_versal.c
···
20
20
int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv,
21
21
const struct spi_mem_op *op)
22
22
{
23
-
u32 reg, ret, rx_rem, n_rx, bytes_to_dma, data;
23
+
u32 reg, ret, rx_rem, n_rx, bytes_to_dma, data, status;
24
24
u8 opcode, addr_bytes, *rxbuf, dummy_cycles;
25
25
26
26
n_rx = op->data.nbytes;
···
87
87
CQSPI_REG_SIZE_ADDRESS_MASK;
88
88
89
89
opcode = CMD_4BYTE_FAST_READ;
90
+
91
+
/* Set up command opcode extension. */
92
+
status = readl(priv->regbase + CQSPI_REG_CONFIG);
93
+
if (status & CQSPI_REG_CONFIG_DTR_PROTO) {
94
+
ret = cadence_qspi_setup_opcode_ext(priv, op,
95
+
CQSPI_REG_OP_EXT_STIG_LSB);
96
+
if (ret)
97
+
return ret;
98
+
}
99
+
90
100
dummy_cycles = 8;
91
101
writel((dummy_cycles << CQSPI_REG_RD_INSTR_DUMMY_LSB) | opcode,
92
102
priv->regbase + CQSPI_REG_RD_INSTR);
+3
-1
drivers/spi/cadence_qspi.h
+3
-1
drivers/spi/cadence_qspi.h
···
320
320
ofnode cadence_qspi_get_subnode(struct udevice *dev);
321
321
void cadence_qspi_apb_enable_linear_mode(bool enable);
322
322
int cadence_device_reset(struct udevice *dev);
323
-
323
+
int cadence_qspi_setup_opcode_ext(struct cadence_spi_priv *priv,
324
+
const struct spi_mem_op *op,
325
+
unsigned int shift);
324
326
#endif /* __CADENCE_QSPI_H__ */
+10
-3
drivers/spi/cadence_qspi_apb.c
+10
-3
drivers/spi/cadence_qspi_apb.c
···
303
303
tshsl_ns -= sclk_ns + ref_clk_ns;
304
304
if (tchsh_ns >= sclk_ns + 3 * ref_clk_ns)
305
305
tchsh_ns -= sclk_ns + 3 * ref_clk_ns;
306
+
307
+
if (tshsl_ns < sclk_ns)
308
+
tshsl_ns = sclk_ns;
309
+
306
310
tshsl = DIV_ROUND_UP(tshsl_ns, ref_clk_ns);
307
311
tchsh = DIV_ROUND_UP(tchsh_ns, ref_clk_ns);
308
312
tslch = DIV_ROUND_UP(tslch_ns, ref_clk_ns);
···
380
384
return 0;
381
385
}
382
386
383
-
static int cadence_qspi_setup_opcode_ext(struct cadence_spi_priv *priv,
384
-
const struct spi_mem_op *op,
385
-
unsigned int shift)
387
+
int cadence_qspi_setup_opcode_ext(struct cadence_spi_priv *priv,
388
+
const struct spi_mem_op *op,
389
+
unsigned int shift)
386
390
{
387
391
unsigned int reg;
388
392
u8 ext;
···
553
557
const void *txbuf = op->data.buf.out;
554
558
void *reg_base = priv->regbase;
555
559
u8 opcode;
560
+
561
+
if (priv->dtr)
562
+
txlen += txlen & 1;
556
563
557
564
if (priv->dtr)
558
565
opcode = op->cmd.opcode >> 8;
-126
include/dt-bindings/clock/xlnx-zynqmp-clk.h
-126
include/dt-bindings/clock/xlnx-zynqmp-clk.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0 */
2
-
/*
3
-
* Xilinx Zynq MPSoC Firmware layer
4
-
*
5
-
* Copyright (C) 2014-2018 Xilinx, Inc.
6
-
*
7
-
*/
8
-
9
-
#ifndef _DT_BINDINGS_CLK_ZYNQMP_H
10
-
#define _DT_BINDINGS_CLK_ZYNQMP_H
11
-
12
-
#define IOPLL 0
13
-
#define RPLL 1
14
-
#define APLL 2
15
-
#define DPLL 3
16
-
#define VPLL 4
17
-
#define IOPLL_TO_FPD 5
18
-
#define RPLL_TO_FPD 6
19
-
#define APLL_TO_LPD 7
20
-
#define DPLL_TO_LPD 8
21
-
#define VPLL_TO_LPD 9
22
-
#define ACPU 10
23
-
#define ACPU_HALF 11
24
-
#define DBF_FPD 12
25
-
#define DBF_LPD 13
26
-
#define DBG_TRACE 14
27
-
#define DBG_TSTMP 15
28
-
#define DP_VIDEO_REF 16
29
-
#define DP_AUDIO_REF 17
30
-
#define DP_STC_REF 18
31
-
#define GDMA_REF 19
32
-
#define DPDMA_REF 20
33
-
#define DDR_REF 21
34
-
#define SATA_REF 22
35
-
#define PCIE_REF 23
36
-
#define GPU_REF 24
37
-
#define GPU_PP0_REF 25
38
-
#define GPU_PP1_REF 26
39
-
#define TOPSW_MAIN 27
40
-
#define TOPSW_LSBUS 28
41
-
#define GTGREF0_REF 29
42
-
#define LPD_SWITCH 30
43
-
#define LPD_LSBUS 31
44
-
#define USB0_BUS_REF 32
45
-
#define USB1_BUS_REF 33
46
-
#define USB3_DUAL_REF 34
47
-
#define USB0 35
48
-
#define USB1 36
49
-
#define CPU_R5 37
50
-
#define CPU_R5_CORE 38
51
-
#define CSU_SPB 39
52
-
#define CSU_PLL 40
53
-
#define PCAP 41
54
-
#define IOU_SWITCH 42
55
-
#define GEM_TSU_REF 43
56
-
#define GEM_TSU 44
57
-
#define GEM0_TX 45
58
-
#define GEM1_TX 46
59
-
#define GEM2_TX 47
60
-
#define GEM3_TX 48
61
-
#define GEM0_RX 49
62
-
#define GEM1_RX 50
63
-
#define GEM2_RX 51
64
-
#define GEM3_RX 52
65
-
#define QSPI_REF 53
66
-
#define SDIO0_REF 54
67
-
#define SDIO1_REF 55
68
-
#define UART0_REF 56
69
-
#define UART1_REF 57
70
-
#define SPI0_REF 58
71
-
#define SPI1_REF 59
72
-
#define NAND_REF 60
73
-
#define I2C0_REF 61
74
-
#define I2C1_REF 62
75
-
#define CAN0_REF 63
76
-
#define CAN1_REF 64
77
-
#define CAN0 65
78
-
#define CAN1 66
79
-
#define DLL_REF 67
80
-
#define ADMA_REF 68
81
-
#define TIMESTAMP_REF 69
82
-
#define AMS_REF 70
83
-
#define PL0_REF 71
84
-
#define PL1_REF 72
85
-
#define PL2_REF 73
86
-
#define PL3_REF 74
87
-
#define WDT 75
88
-
#define IOPLL_INT 76
89
-
#define IOPLL_PRE_SRC 77
90
-
#define IOPLL_HALF 78
91
-
#define IOPLL_INT_MUX 79
92
-
#define IOPLL_POST_SRC 80
93
-
#define RPLL_INT 81
94
-
#define RPLL_PRE_SRC 82
95
-
#define RPLL_HALF 83
96
-
#define RPLL_INT_MUX 84
97
-
#define RPLL_POST_SRC 85
98
-
#define APLL_INT 86
99
-
#define APLL_PRE_SRC 87
100
-
#define APLL_HALF 88
101
-
#define APLL_INT_MUX 89
102
-
#define APLL_POST_SRC 90
103
-
#define DPLL_INT 91
104
-
#define DPLL_PRE_SRC 92
105
-
#define DPLL_HALF 93
106
-
#define DPLL_INT_MUX 94
107
-
#define DPLL_POST_SRC 95
108
-
#define VPLL_INT 96
109
-
#define VPLL_PRE_SRC 97
110
-
#define VPLL_HALF 98
111
-
#define VPLL_INT_MUX 99
112
-
#define VPLL_POST_SRC 100
113
-
#define CAN0_MIO 101
114
-
#define CAN1_MIO 102
115
-
#define ACPU_FULL 103
116
-
#define GEM0_REF 104
117
-
#define GEM1_REF 105
118
-
#define GEM2_REF 106
119
-
#define GEM3_REF 107
120
-
#define GEM0_REF_UNG 108
121
-
#define GEM1_REF_UNG 109
122
-
#define GEM2_REF_UNG 110
123
-
#define GEM3_REF_UNG 111
124
-
#define LPD_WDT 112
125
-
126
-
#endif
+9
include/zynqmp_firmware.h
+9
include/zynqmp_firmware.h
···
8
8
#ifndef _ZYNQMP_FIRMWARE_H_
9
9
#define _ZYNQMP_FIRMWARE_H_
10
10
11
+
#include <compiler.h>
12
+
11
13
enum pm_api_id {
12
14
PM_GET_API_VERSION = 1,
13
15
PM_SET_CONFIGURATION = 2,
···
511
513
512
514
#define PM_REG_PMC_GLOBAL_NODE 0x30000004
513
515
#define PMC_MULTI_BOOT_MODE_REG_OFFSET 0x4
516
+
517
+
#define __data __section(".data")
518
+
519
+
typedef int (*smc_call_handler_t)(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
520
+
u32 arg3, u32 *ret_payload);
521
+
522
+
extern smc_call_handler_t __data smc_call_handler;
514
523
515
524
#endif /* _ZYNQMP_FIRMWARE_H_ */