"Das U-Boot" Source Tree
Merge tag 'u-boot-socfpga-next-20251217' of https://source.denx.de/u-boot/custodians/u-boot-socfpga into next
This pull request brings together a set of fixes and enhancements across
the SoCFPGA platform family, with a focus on MMC/SPL robustness, EFI
boot enablement, and Agilex5 SD/eMMC support.
CI: https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/28776
Highlights:
*
SPL / MMC:
o
Fix Kconfig handling for
SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
o
Correct raw sector calculations and respect explicit sector values
when loading U-Boot from MMC in SPL
o
Adjust raw MMC loading logic for SoCFPGA platforms
*
EFI boot:
o
Permit EFI booting on SoCFPGA platforms
o
Disable mkeficapsule tool build for Arria 10 where unsupported
*
Agilex5:
o
Upgrade SDHCI controller from SD4HC to SD6HC
o
Enable MMC and Cadence SDHCI support in defconfig
o
Add dedicated eMMC device tree and defconfig for Agilex5 SoCDK
o
Revert incorrect GPIO configuration for SDIO_SEL
o
Refine U-Boot DT handling for SD and eMMC boot variants
*
SPI:
o
Allow disabling the DesignWare SPI driver in SPL via Kconfig
*
Board / configuration fixes:
o
Enable random MAC address generation for Cyclone V
o
Fix DE0-Nano-SoC boot configuration
o
Remove obsolete or conflicting options from multiple legacy
SoCFPGA defconfigs
+678
-195
+1
arch/arm/dts/Makefile
+1
arch/arm/dts/Makefile
+3
arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi
+3
arch/arm/dts/rk3588-rock-5b-plus-u-boot.dtsi
+5
arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+5
arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+3
arch/arm/dts/rk3588-rock-5t-u-boot.dtsi
+3
arch/arm/dts/rk3588-rock-5t-u-boot.dtsi
+33
arch/arm/dts/rockchip-u-boot.dtsi
+33
arch/arm/dts/rockchip-u-boot.dtsi
···
226
226
};
227
227
};
228
228
#endif /* CONFIG_ROCKCHIP_SPI_IMAGE */
229
+
230
+
#ifdef CONFIG_ROCKCHIP_MASKROM_IMAGE
231
+
simple-bin-usb471 {
232
+
filename = "u-boot-rockchip-usb471.bin";
233
+
234
+
#ifdef CONFIG_ROCKCHIP_EXTERNAL_TPL
235
+
rockchip-tpl {
236
+
};
237
+
#elif defined(CONFIG_TPL)
238
+
u-boot-tpl {
239
+
no-write-symbols;
240
+
};
241
+
#endif
242
+
};
243
+
244
+
simple-bin-usb472 {
245
+
filename = "u-boot-rockchip-usb472.bin";
246
+
pad-byte = <0x00>;
247
+
248
+
u-boot-spl {
249
+
no-write-symbols;
250
+
};
251
+
252
+
#ifdef HAS_FIT
253
+
fit {
254
+
insert-template = <&fit_template>;
255
+
#else
256
+
u-boot-img {
257
+
#endif
258
+
offset = <(CONFIG_SPL_LOAD_FIT_ADDRESS - CFG_SYS_SDRAM_BASE)>;
259
+
};
260
+
};
261
+
#endif /* CONFIG_ROCKCHIP_MASKROM_IMAGE */
229
262
};
230
263
#endif /* CONFIG_SPL */
+2
-12
arch/arm/dts/socfpga_agilex5-u-boot.dtsi
+2
-12
arch/arm/dts/socfpga_agilex5-u-boot.dtsi
···
681
681
bootph-all;
682
682
};
683
683
684
-
&gpio1 {
685
-
/* Configure GPIO 1 pin 3 as output pin with value 0 during GPIO probe */
686
-
portb: gpio-controller@0{
687
-
sdio_sel {
688
-
gpio-hog;
689
-
gpios = <3 GPIO_ACTIVE_HIGH>;
690
-
output-low;
691
-
};
692
-
};
693
-
};
694
-
695
684
&i2c0 {
696
685
reset-names = "i2c";
697
686
};
···
709
698
};
710
699
711
700
&mmc {
712
-
resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
701
+
resets = <&rst COMBOPHY_RESET>, <&rst SDMMC_OCP_RESET>, <&rst SDMMC_RESET>;
702
+
reset-names = "combophy", "sdmmc-ocp", "sdhc-reset";
713
703
};
714
704
715
705
&porta {
+16
-13
arch/arm/dts/socfpga_agilex5.dtsi
+16
-13
arch/arm/dts/socfpga_agilex5.dtsi
···
303
303
status = "disabled";
304
304
};
305
305
306
-
combophy0: combophy@0 {
307
-
#phy-cells = <0>;
308
-
phy-type = <1>;
309
-
compatible = "cdns,combophy";
310
-
reg = <0x10808000 0x1000>;
311
-
resets = <&rst COMBOPHY_RESET>;
312
-
reset-names = "reset";
313
-
status = "disabled";
306
+
sd_emmc_power: regulator-fixed-3p3v {
307
+
compatible = "regulator-fixed";
308
+
regulator-name = "card-power";
309
+
regulator-min-microvolt = <3300000>;
310
+
regulator-max-microvolt = <3300000>;
311
+
regulator-always-on;
312
+
};
313
+
314
+
sd_io_1v8_reg: regulator-1p8v {
315
+
compatible = "regulator-gpio";
316
+
regulator-name = "sd-bus-io-power";
317
+
regulator-min-microvolt = <1800000>;
318
+
regulator-max-microvolt = <3300000>;
319
+
states = <1800000 0x1>,
320
+
<3300000 0x0>;
314
321
};
315
322
316
323
mmc: mmc0@10808000 {
317
324
#address-cells = <1>;
318
325
#size-cells = <0>;
319
-
compatible = "cdns,sd4hc";
326
+
compatible = "altr,agilex5-sd6hc", "cdns,sd6hc";
320
327
reg = <0x10808000 0x1000>;
321
328
interrupts = <0 96 4>;
322
-
phys = <&combophy0>;
323
-
phy-names = "combo-phy";
324
329
clocks = <&clkmgr AGILEX5_L4_MP_CLK>,
325
330
<&clkmgr AGILEX5_SDMMC_CLK>;
326
331
clock-names = "biu", "ciu";
327
332
fifo-depth = <0x800>;
328
-
resets = <&rst SDMMC_RESET>;
329
-
reset-names = "reset";
330
333
iommus = <&smmu 5>;
331
334
status = "disabled";
332
335
};
+35
-42
arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
+35
-42
arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
···
91
91
bootph-all;
92
92
};
93
93
94
-
&mmc {
95
-
status = "okay";
96
-
bus-width = <4>;
97
-
sd-uhs-sdr50;
98
-
cap-mmc-highspeed;
94
+
&gpio1 {
95
+
portb: gpio-controller@0 {
96
+
bootph-all;
97
+
};
98
+
};
99
+
100
+
&sd_emmc_power {
99
101
bootph-all;
100
102
};
101
103
102
-
&combophy0 {
104
+
&sd_io_1v8_reg {
105
+
gpios = <&portb 3 GPIO_ACTIVE_HIGH>;
106
+
bootph-all;
107
+
};
108
+
109
+
&mmc {
103
110
status = "okay";
111
+
112
+
no-mmc;
113
+
no-1-8-v;
114
+
disable-wp;
115
+
cap-sd-highspeed;
116
+
vmmc-supply = <&sd_emmc_power>;
117
+
vqmmc-supply = <&sd_io_1v8_reg>;
118
+
max-frequency = <200000000>;
119
+
120
+
/* SD card default speed (DS) and UHS-I SDR12 mode timing configuration */
121
+
cdns,phy-dqs-timing-delay-sd-ds = <0x00780000>;
122
+
cdns,phy-gate-lpbk_ctrl-delay-sd-ds = <0x81a40040>;
123
+
cdns,phy-dll-slave-ctrl-sd-ds = <0x00a000fe>;
124
+
cdns,phy-dq-timing-delay-sd-ds = <0x28000001>;
125
+
126
+
/* SD card high speed and UHS-I SDR25 mode timing configuration */
127
+
cdns,phy-dqs-timing-delay-sd-hs = <0x780001>;
128
+
cdns,phy-gate-lpbk_ctrl-delay-sd-hs = <0x81a40040>;
129
+
cdns,phy-dq-timing-delay-sd-hs = <0x10000001>;
130
+
cdns,ctrl-hrs16-slave-ctrl-sd-hs = <0x101>;
131
+
cdns,ctrl-hrs07-timing-delay-sd-hs = <0xA0001>;
132
+
104
133
bootph-all;
105
-
cdns,phy-use-ext-lpbk-dqs = <1>;
106
-
cdns,phy-use-lpbk-dqs = <1>;
107
-
cdns,phy-use-phony-dqs = <1>;
108
-
cdns,phy-use-phony-dqs-cmd = <1>;
109
-
cdns,phy-io-mask-always-on = <0>;
110
-
cdns,phy-io-mask-end = <5>;
111
-
cdns,phy-io-mask-start = <0>;
112
-
cdns,phy-data-select-oe-end = <1>;
113
-
cdns,phy-sync-method = <1>;
114
-
cdns,phy-sw-half-cycle-shift = <0>;
115
-
cdns,phy-rd-del-sel = <52>;
116
-
cdns,phy-underrun-suppress = <1>;
117
-
cdns,phy-gate-cfg-always-on = <1>;
118
-
cdns,phy-param-dll-bypass-mode = <1>;
119
-
cdns,phy-param-phase-detect-sel = <2>;
120
-
cdns,phy-param-dll-start-point = <254>;
121
-
cdns,phy-read-dqs-cmd-delay = <0>;
122
-
cdns,phy-clk-wrdqs-delay = <0>;
123
-
cdns,phy-clk-wr-delay = <0>;
124
-
cdns,phy-read-dqs-delay = <0>;
125
-
cdns,phy-phony-dqs-timing = <0>;
126
-
cdns,hrs09-rddata-en = <1>;
127
-
cdns,hrs09-rdcmd-en = <1>;
128
-
cdns,hrs09-extended-wr-mode = <1>;
129
-
cdns,hrs09-extended-rd-mode = <1>;
130
-
cdns,hrs10-hcsdclkadj = <3>;
131
-
cdns,hrs16-wrdata1-sdclk-dly = <0>;
132
-
cdns,hrs16-wrdata0-sdclk-dly = <0>;
133
-
cdns,hrs16-wrcmd1-sdclk-dly = <0>;
134
-
cdns,hrs16-wrcmd0-sdclk-dly = <0>;
135
-
cdns,hrs16-wrdata1-dly = <0>;
136
-
cdns,hrs16-wrdata0-dly = <0>;
137
-
cdns,hrs16-wrcmd1-dly = <0>;
138
-
cdns,hrs16-wrcmd0-dly = <0>;
139
-
cdns,hrs07-rw-compensate = <10>;
140
-
cdns,hrs07-idelay-val = <0>;
141
134
};
142
135
143
136
&qspi {
+172
arch/arm/dts/socfpga_agilex5_socdk_emmc-u-boot.dtsi
+172
arch/arm/dts/socfpga_agilex5_socdk_emmc-u-boot.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0+
2
+
/*
3
+
* U-Boot additions for Agilex5 SocDK eMMC
4
+
*
5
+
* Copyright (C) 2025 Altera Corporation <www.altera.com>
6
+
*/
7
+
8
+
#include "socfpga_agilex5-u-boot.dtsi"
9
+
10
+
/{
11
+
aliases {
12
+
spi0 = &qspi;
13
+
freeze_br0 = &freeze_controller;
14
+
};
15
+
16
+
soc {
17
+
freeze_controller: freeze_controller@0x20000450 {
18
+
compatible = "altr,freeze-bridge-controller";
19
+
reg = <0x20000450 0x00000010>;
20
+
status = "disabled";
21
+
};
22
+
};
23
+
24
+
/*
25
+
* Both Memory base address and size default info is retrieved from HW setting.
26
+
* Reconfiguration / Overwrite these info can be done with examples below.
27
+
*
28
+
* When LPDDR ECC is enabled, the last 1/8 of the memory region must
29
+
* be reserved for the Inline ECC buffer.
30
+
*
31
+
* Example for memory size with 2GB:
32
+
* memory {
33
+
* reg = <0x0 0x80000000 0x0 0x80000000>;
34
+
* };
35
+
*
36
+
* Example for memory size with 8GB:
37
+
* memory {
38
+
* reg = <0x0 0x80000000 0x0 0x80000000>,
39
+
* <0x8 0x80000000 0x1 0x80000000>;
40
+
* };
41
+
*
42
+
* Example for memory size with 32GB:
43
+
* memory {
44
+
* reg = <0x0 0x80000000 0x0 0x80000000>,
45
+
* <0x8 0x80000000 0x7 0x80000000>;
46
+
* };
47
+
*
48
+
* Example for memory size with 512GB:
49
+
* memory {
50
+
* reg = <0x0 0x80000000 0x0 0x80000000>,
51
+
* <0x8 0x80000000 0x7 0x80000000>,
52
+
* <0x88 0x00000000 0x78 0x00000000>;
53
+
* };
54
+
*
55
+
* Example for memory size with 2GB with LPDDR Inline ECC ON:
56
+
* memory {
57
+
* reg = <0x0 0x80000000 0x0 0x70000000>;
58
+
* };
59
+
*
60
+
* Example for memory size with 8GB with LPDDR Inline ECC ON:
61
+
* memory {
62
+
* reg = <0x0 0x80000000 0x0 0x80000000>,
63
+
* <0x8 0x80000000 0x1 0x40000000>;
64
+
* };
65
+
*/
66
+
67
+
chosen {
68
+
stdout-path = "serial0:115200n8";
69
+
u-boot,spl-boot-order = &mmc,&flash0,&nand,"/memory";
70
+
};
71
+
};
72
+
73
+
&flash0 {
74
+
compatible = "jedec,spi-nor";
75
+
spi-tx-bus-width = <4>;
76
+
spi-rx-bus-width = <4>;
77
+
bootph-all;
78
+
/delete-property/ cdns,read-delay;
79
+
};
80
+
81
+
&flash1 {
82
+
bootph-all;
83
+
};
84
+
85
+
&i3c0 {
86
+
bootph-all;
87
+
};
88
+
89
+
&i3c1 {
90
+
bootph-all;
91
+
};
92
+
93
+
&gpio1 {
94
+
portb: gpio-controller@0 {
95
+
bootph-all;
96
+
};
97
+
};
98
+
99
+
&sd_emmc_power {
100
+
bootph-all;
101
+
};
102
+
103
+
&emmc_io_1v8_reg {
104
+
bootph-all;
105
+
};
106
+
107
+
&mmc {
108
+
bootph-all;
109
+
};
110
+
111
+
&qspi {
112
+
status = "okay";
113
+
};
114
+
115
+
&nand {
116
+
status = "disabled";
117
+
bootph-all;
118
+
};
119
+
120
+
&timer0 {
121
+
bootph-all;
122
+
};
123
+
124
+
&timer1 {
125
+
bootph-all;
126
+
};
127
+
128
+
&timer2 {
129
+
bootph-all;
130
+
};
131
+
132
+
&timer3 {
133
+
bootph-all;
134
+
};
135
+
136
+
&watchdog0 {
137
+
bootph-all;
138
+
};
139
+
140
+
&gmac0 {
141
+
status = "okay";
142
+
phy-mode = "rgmii";
143
+
phy-handle = <&emac0_phy0>;
144
+
145
+
max-frame-size = <9000>;
146
+
147
+
mdio0 {
148
+
#address-cells = <1>;
149
+
#size-cells = <0>;
150
+
compatible = "snps,dwxgmac-mdio";
151
+
emac0_phy0: ethernet-phy@0 {
152
+
reg = <0>;
153
+
};
154
+
};
155
+
};
156
+
157
+
&gmac2 {
158
+
status = "okay";
159
+
phy-mode = "rgmii";
160
+
phy-handle = <&emac2_phy0>;
161
+
162
+
max-frame-size = <9000>;
163
+
164
+
mdio0 {
165
+
#address-cells = <1>;
166
+
#size-cells = <0>;
167
+
compatible = "snps,dwxgmac-mdio";
168
+
emac2_phy0: ethernet-phy@0 {
169
+
reg = <0>;
170
+
};
171
+
};
172
+
};
+49
arch/arm/dts/socfpga_agilex5_socdk_emmc.dts
+49
arch/arm/dts/socfpga_agilex5_socdk_emmc.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (C) 2025 Altera Corporation <www.altera.com>
4
+
*/
5
+
6
+
#include "socfpga_agilex5_socdk.dts"
7
+
8
+
/ {
9
+
soc {
10
+
emmc_io_1v8_reg: regulator-fixed-1p8v {
11
+
compatible = "regulator-fixed";
12
+
regulator-name = "emmc-io-power";
13
+
regulator-min-microvolt = <1800000>;
14
+
regulator-max-microvolt = <1800000>;
15
+
regulator-always-on;
16
+
};
17
+
};
18
+
};
19
+
20
+
&mmc {
21
+
status = "okay";
22
+
23
+
no-sd;
24
+
no-sdio;
25
+
disable-wp;
26
+
non-removable;
27
+
cap-mmc-highspeed;
28
+
29
+
bus-width = <8>;
30
+
vmmc-supply = <&sd_emmc_power>;
31
+
vqmmc-supply = <&emmc_io_1v8_reg>;
32
+
max-frequency = <200000000>;
33
+
34
+
/* eMMC legacy mode timing configuration */
35
+
cdns,phy-dqs-timing-delay-sd-ds = <0x00780000>;
36
+
cdns,phy-gate-lpbk-ctrl-delay-sd-ds = <0x81a40040>;
37
+
cdns,phy-dll-slave-ctrl-sd-ds = <0x00a000fe>;
38
+
cdns,phy-dq-timing-delay-sd-ds = <0x28000001>;
39
+
40
+
/* eMMC SDR mode timing configuration */
41
+
cdns,phy-dqs-timing-delay-emmc-sdr = <0x780001>;
42
+
cdns,phy-gate-lpbk-ctrl-delay-emmc-sdr = <0x81a40040>;
43
+
cdns,phy-dll-slave-ctrl-emmc-sdr = <0x00000000>;
44
+
cdns,phy-dq-timing-delay-emmc-sdr = <0x10000001>;
45
+
cdns,ctrl-hrs09-timing-delay-emmc-sdr = <0x1800c>;
46
+
cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-sdr = <0x30000>;
47
+
cdns,ctrl-hrs16-slave-ctrl-emmc-sdr = <0x101>;
48
+
cdns,ctrl-hrs07-timing-delay-emmc-sdr = <0xA0001>;
49
+
};
+3
arch/arm/include/asm/arch-rockchip/sdram.h
+3
arch/arm/include/asm/arch-rockchip/sdram.h
+11
-3
arch/arm/mach-rockchip/Kconfig
+11
-3
arch/arm/mach-rockchip/Kconfig
···
705
705
option to produce a SPI-flash image containing U-Boot. The image
706
706
is built by binman. U-Boot sits near the start of the image.
707
707
708
+
config ROCKCHIP_MASKROM_IMAGE
709
+
bool "Build a maskrom mode image for Rockchip"
710
+
depends on TPL || ROCKCHIP_EXTERNAL_TPL
711
+
select SPL_RAM_DEVICE
712
+
help
713
+
Rockchip SoCs support maskrom mode boot over USB. Enable this
714
+
option to produce maskrom mode boot images containing U-Boot.
715
+
708
716
config LNX_KRNL_IMG_TEXT_OFFSET_BASE
709
717
default TEXT_BASE
710
718
···
767
775
default 0x4000 if CUSTOM_SYS_INIT_SP_ADDR = 0x03f00000
768
776
769
777
config TEXT_BASE
770
-
default 0x60200000 if SPL_TEXT_BASE = 0x60000000
771
-
default 0x40200000 if SPL_TEXT_BASE = 0x40000000
772
-
default 0x00200000 if SPL_TEXT_BASE = 0x00000000
778
+
default 0x60800000 if SPL_TEXT_BASE = 0x60000000
779
+
default 0x40800000 if SPL_TEXT_BASE = 0x40000000
780
+
default 0x00800000 if SPL_TEXT_BASE = 0x00000000
773
781
774
782
config SPL_TEXT_BASE
775
783
default 0x60000000 if ROCKCHIP_RK3036 || ROCKCHIP_RK3066 || \
-3
arch/arm/mach-rockchip/rk3308/Kconfig
-3
arch/arm/mach-rockchip/rk3308/Kconfig
-3
arch/arm/mach-rockchip/rk3568/Kconfig
-3
arch/arm/mach-rockchip/rk3568/Kconfig
-3
arch/arm/mach-rockchip/rk3588/Kconfig
-3
arch/arm/mach-rockchip/rk3588/Kconfig
+15
arch/arm/mach-rockchip/sdram.c
+15
arch/arm/mach-rockchip/sdram.c
···
345
345
return 0;
346
346
}
347
347
348
+
u8 rockchip_sdram_type(phys_addr_t reg)
349
+
{
350
+
u32 dram_type, version;
351
+
u32 sys_reg2 = readl(reg);
352
+
u32 sys_reg3 = readl(reg + 4);
353
+
354
+
dram_type = (sys_reg2 >> SYS_REG_DDRTYPE_SHIFT) & SYS_REG_DDRTYPE_MASK;
355
+
version = (sys_reg3 >> SYS_REG_VERSION_SHIFT) & SYS_REG_VERSION_MASK;
356
+
if (version >= 3)
357
+
dram_type |= ((sys_reg3 >> SYS_REG_EXTEND_DDRTYPE_SHIFT) &
358
+
SYS_REG_EXTEND_DDRTYPE_MASK) << 3;
359
+
360
+
return dram_type;
361
+
}
362
+
348
363
size_t rockchip_sdram_size(phys_addr_t reg)
349
364
{
350
365
u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4;
+11
-3
arch/arm/mach-rockchip/spl-boot-order.c
+11
-3
arch/arm/mach-rockchip/spl-boot-order.c
···
8
8
#include <log.h>
9
9
#include <mmc.h>
10
10
#include <spl.h>
11
+
#include <asm/arch-rockchip/bootrom.h>
11
12
#include <asm/global_data.h>
12
13
#include <dm/uclass-internal.h>
13
14
···
98
99
99
100
void board_boot_order(u32 *spl_boot_list)
100
101
{
102
+
int idx = 0;
103
+
104
+
/* Add RAM boot for maskrom mode boot over USB */
105
+
if (BROM_BOOTSOURCE_ID_ADDR && CONFIG_IS_ENABLED(RAM_DEVICE) &&
106
+
read_brom_bootsource_id() == BROM_BOOTSOURCE_USB) {
107
+
spl_boot_list[idx++] = BOOT_DEVICE_RAM;
108
+
}
109
+
101
110
/* In case of no fdt (or only plat), use spl_boot_device() */
102
111
if (!CONFIG_IS_ENABLED(OF_CONTROL) || CONFIG_IS_ENABLED(OF_PLATDATA)) {
103
-
spl_boot_list[0] = spl_boot_device();
112
+
spl_boot_list[idx++] = spl_boot_device();
104
113
return;
105
114
}
106
115
107
116
const void *blob = gd->fdt_blob;
108
117
int chosen_node = fdt_path_offset(blob, "/chosen");
109
-
int idx = 0;
110
118
int elem;
111
119
int boot_device;
112
120
int node;
···
115
123
if (chosen_node < 0) {
116
124
debug("%s: /chosen not found, using spl_boot_device()\n",
117
125
__func__);
118
-
spl_boot_list[0] = spl_boot_device();
126
+
spl_boot_list[idx++] = spl_boot_device();
119
127
return;
120
128
}
121
129
+11
arch/arm/mach-socfpga/board.c
+11
arch/arm/mach-socfpga/board.c
···
14
14
#include <hang.h>
15
15
#include <handoff.h>
16
16
#include <image.h>
17
+
#include <spl.h>
17
18
#include <usb.h>
18
19
#include <usb/dwc2_udc.h>
19
20
#include <asm/global_data.h>
···
209
210
}
210
211
}
211
212
#endif
213
+
214
+
#if (defined(CONFIG_TARGET_SOCFPGA_ARRIA10) || \
215
+
defined(CONFIG_TARGET_SOCFPGA_GEN5)) && defined(CONFIG_XPL_BUILD)
216
+
unsigned long board_spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
217
+
unsigned long raw_sect)
218
+
{
219
+
/* offset of u-boot proper inside u-boot-with-spl.sfp image */
220
+
return (CONFIG_SPL_PAD_TO * 4) / 512 + raw_sect;
221
+
}
222
+
#endif
+2
-2
arch/sandbox/config.mk
+2
-2
arch/sandbox/config.mk
···
50
50
51
51
ifeq ($(HOST_ARCH),$(HOST_ARCH_X86_64))
52
52
EFI_LDS := ${SRCDIR}/../../../arch/x86/lib/elf_x86_64_efi.lds
53
-
EFI_TARGET := --target=efi-app-x86_64
53
+
EFI_TARGET := --output-target=efi-app-x86_64
54
54
else ifeq ($(HOST_ARCH),$(HOST_ARCH_X86))
55
55
EFI_LDS := ${SRCDIR}/../../../arch/x86/lib/elf_ia32_efi.lds
56
-
EFI_TARGET := --target=efi-app-ia32
56
+
EFI_TARGET := --output-target=efi-app-ia32
57
57
else ifeq ($(HOST_ARCH),$(HOST_ARCH_AARCH64))
58
58
EFI_LDS := ${SRCDIR}/../../../arch/arm/lib/elf_aarch64_efi.lds
59
59
OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .data \
+3
-3
arch/x86/config.mk
+3
-3
arch/x86/config.mk
···
69
69
70
70
LDSCRIPT_EFI := $(srctree)/arch/x86/lib/elf_$(EFIARCH)_efi.lds
71
71
EFISTUB := crt0_$(EFIARCH)_efi.o reloc_$(EFIARCH)_efi.o
72
-
OBJCOPYFLAGS_EFI += --target=efi-app-$(EFIARCH)
72
+
OBJCOPYFLAGS_EFI += --output-target=efi-app-$(EFIARCH)
73
73
74
74
CPPFLAGS_REMOVE_crt0-efi-$(EFIARCH).o += $(CFLAGS_NON_EFI)
75
75
CPPFLAGS_crt0-efi-$(EFIARCH).o += $(CFLAGS_EFI)
···
127
127
endif
128
128
129
129
ifdef CONFIG_X86_64
130
-
EFI_TARGET := --target=efi-app-x86_64
130
+
EFI_TARGET := --output-target=efi-app-x86_64
131
131
else
132
-
EFI_TARGET := --target=efi-app-ia32
132
+
EFI_TARGET := --output-target=efi-app-ia32
133
133
endif
+5
board/radxa/rock5b-rk3588/Kconfig
+5
board/radxa/rock5b-rk3588/Kconfig
+1
-2
board/radxa/rock5b-rk3588/MAINTAINERS
+1
-2
board/radxa/rock5b-rk3588/MAINTAINERS
+64
board/radxa/rock5b-rk3588/rock5b-rk3588.c
+64
board/radxa/rock5b-rk3588/rock5b-rk3588.c
···
3
3
* Copyright (c) 2023-2024 Collabora Ltd.
4
4
*/
5
5
6
+
#include <adc.h>
7
+
#include <env.h>
6
8
#include <fdtdec.h>
7
9
#include <fdt_support.h>
10
+
#include <asm/arch-rockchip/sdram.h>
11
+
#include <linux/errno.h>
12
+
13
+
#define PMU1GRF_BASE 0xfd58a000
14
+
#define OS_REG2_REG 0x208
15
+
16
+
#define HW_ID_CHANNEL 5
17
+
18
+
struct board_model {
19
+
unsigned int dram;
20
+
unsigned int low;
21
+
unsigned int high;
22
+
const char *fdtfile;
23
+
};
24
+
25
+
static const struct board_model board_models[] = {
26
+
{ LPDDR5, 926, 1106, "rockchip/rk3588-rock-5t.dtb" },
27
+
{ LPDDR5, 4005, 4185, "rockchip/rk3588-rock-5b-plus.dtb" },
28
+
};
29
+
30
+
static const struct board_model *get_board_model(void)
31
+
{
32
+
unsigned int val, dram_type;
33
+
int i, ret;
34
+
35
+
dram_type = rockchip_sdram_type(PMU1GRF_BASE + OS_REG2_REG);
36
+
37
+
ret = adc_channel_single_shot("adc@fec10000", HW_ID_CHANNEL, &val);
38
+
if (ret)
39
+
return NULL;
40
+
41
+
for (i = 0; i < ARRAY_SIZE(board_models); i++) {
42
+
unsigned int dram = board_models[i].dram;
43
+
unsigned int min = board_models[i].low;
44
+
unsigned int max = board_models[i].high;
45
+
46
+
if (dram == dram_type && min <= val && val <= max)
47
+
return &board_models[i];
48
+
}
49
+
50
+
return NULL;
51
+
}
52
+
53
+
int rk_board_late_init(void)
54
+
{
55
+
const struct board_model *model = get_board_model();
56
+
57
+
if (model)
58
+
env_set("fdtfile", model->fdtfile);
59
+
60
+
return 0;
61
+
}
62
+
63
+
int board_fit_config_name_match(const char *name)
64
+
{
65
+
const struct board_model *model = get_board_model();
66
+
67
+
if (model && !strcmp(name, model->fdtfile))
68
+
return 0;
69
+
70
+
return -EINVAL;
71
+
}
8
72
9
73
#ifdef CONFIG_OF_BOARD_SETUP
10
74
int ft_board_setup(void *blob, struct bd_info *bd)
+1
board/rockchip/rockchip-ramboot.config
+1
board/rockchip/rockchip-ramboot.config
···
1
+
CONFIG_ROCKCHIP_MASKROM_IMAGE=y
+3
boot/Kconfig
+3
boot/Kconfig
···
249
249
hex "load address of fit image"
250
250
depends on SPL_LOAD_FIT
251
251
default 0x44000000 if ARCH_IMX8M
252
+
default 0x60080000 if ARCH_ROCKCHIP && SPL_TEXT_BASE = 0x60000000
253
+
default 0x40200000 if ARCH_ROCKCHIP && SPL_TEXT_BASE = 0x40000000
254
+
default 0x00200000 if ARCH_ROCKCHIP && SPL_TEXT_BASE = 0x00000000
252
255
default 0x0
253
256
help
254
257
Specify the load address of the fit image that will be loaded
+1
common/spl/Kconfig
+1
common/spl/Kconfig
+9
-12
common/spl/spl_mmc.c
+9
-12
common/spl/spl_mmc.c
···
106
106
return 0;
107
107
}
108
108
109
-
#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
109
+
#if defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION) || \
110
+
defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE)
110
111
static int mmc_load_image_raw_partition(struct spl_image_info *spl_image,
111
112
struct spl_boot_device *bootdev,
112
113
struct mmc *mmc, int partition,
···
136
137
return ret;
137
138
}
138
139
139
-
#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
140
140
return mmc_load_image_raw_sector(spl_image, bootdev, mmc, info.start + sector);
141
-
#else
142
-
return mmc_load_image_raw_sector(spl_image, bootdev, mmc, info.start);
143
-
#endif
144
141
}
145
142
#endif
146
143
···
419
416
420
417
raw_sect = spl_mmc_get_uboot_raw_sector(mmc, raw_sect);
421
418
422
-
#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
423
-
ret = mmc_load_image_raw_partition(spl_image, bootdev,
424
-
mmc, raw_part,
425
-
raw_sect);
426
-
if (!ret)
427
-
return 0;
428
-
#endif
429
419
#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
430
420
ret = mmc_load_image_raw_sector(spl_image, bootdev, mmc,
431
421
raw_sect +
432
422
spl_mmc_raw_uboot_offset(part));
423
+
if (!ret)
424
+
return 0;
425
+
#elif defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION) || \
426
+
defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE)
427
+
ret = mmc_load_image_raw_partition(spl_image, bootdev,
428
+
mmc, raw_part,
429
+
raw_sect);
433
430
if (!ret)
434
431
return 0;
435
432
#endif
+1
configs/am43xx_hs_evm_defconfig
+1
configs/am43xx_hs_evm_defconfig
+1
configs/am43xx_hs_evm_qspi_defconfig
+1
configs/am43xx_hs_evm_qspi_defconfig
···
14
14
CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
15
15
CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000
16
16
CONFIG_ENV_OFFSET_REDUND=0x120000
17
+
CONFIG_SYS_MEM_TOP_HIDE=0x4000000
17
18
CONFIG_DISTRO_DEFAULTS=y
18
19
CONFIG_QSPI_BOOT=y
19
20
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
+1
configs/rock5b-rk3588_defconfig
+1
configs/rock5b-rk3588_defconfig
···
47
47
# CONFIG_SPL_DOS_PARTITION is not set
48
48
CONFIG_SPL_OF_CONTROL=y
49
49
CONFIG_OF_LIVE=y
50
+
CONFIG_OF_LIST="rockchip/rk3588-rock-5b rockchip/rk3588-rock-5b-plus rockchip/rk3588-rock-5t"
50
51
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
51
52
CONFIG_SPL_DM_SEQ_ALIAS=y
52
53
CONFIG_SPL_REGMAP=y
+18
-4
configs/socfpga_agilex5_defconfig
+18
-4
configs/socfpga_agilex5_defconfig
···
67
67
CONFIG_CMD_CACHE=y
68
68
CONFIG_CMD_TIMER=y
69
69
CONFIG_CMD_UBI=y
70
-
# CONFIG_ISO_PARTITION is not set
71
-
# CONFIG_EFI_PARTITION is not set
70
+
CONFIG_CMD_MMC=y
72
71
CONFIG_OF_LIST=""
73
72
CONFIG_ENV_IS_IN_FAT=y
74
73
CONFIG_ENV_IS_IN_UBI=y
···
79
78
CONFIG_NET_RANDOM_ETHADDR=y
80
79
CONFIG_SPL_DM_SEQ_ALIAS=y
81
80
CONFIG_SPL_ALTERA_SDRAM=y
82
-
CONFIG_GPIO_HOG=y
83
-
CONFIG_SPL_GPIO_HOG=y
84
81
CONFIG_DWAPB_GPIO=y
85
82
CONFIG_DM_I2C=y
86
83
CONFIG_SYS_I2C_DW=y
···
109
106
CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=3000
110
107
CONFIG_DESIGNWARE_WATCHDOG=y
111
108
CONFIG_WDT=y
109
+
CONFIG_DM_REGULATOR=y
110
+
CONFIG_DM_REGULATOR_FIXED=y
111
+
CONFIG_DM_REGULATOR_GPIO=y
112
+
CONFIG_SPL_DWAPB_GPIO=y
113
+
CONFIG_SPL_DM_REGULATOR=y
114
+
CONFIG_SPL_DM_REGULATOR_FIXED=y
115
+
CONFIG_SPL_DM_REGULATOR_GPIO=y
116
+
CONFIG_SPL_MMC=y
117
+
CONFIG_SPL_DM_MMC=y
118
+
CONFIG_SPL_MMC_IO_VOLTAGE=y
119
+
CONFIG_SPL_MMC_SDHCI_ADMA=y
120
+
CONFIG_MMC=y
121
+
CONFIG_MMC_SDHCI=y
122
+
CONFIG_DM_MMC=y
123
+
CONFIG_MMC_IO_VOLTAGE=y
124
+
CONFIG_MMC_SDHCI_ADMA=y
125
+
CONFIG_MMC_SDHCI_CADENCE=y
112
126
# CONFIG_SPL_USE_TINY_PRINTF is not set
113
127
CONFIG_PANIC_HANG=y
+6
configs/socfpga_agilex5_emmc_defconfig
+6
configs/socfpga_agilex5_emmc_defconfig
-2
configs/socfpga_agilex_defconfig
-2
configs/socfpga_agilex_defconfig
+1
configs/socfpga_arria10_defconfig
+1
configs/socfpga_arria10_defconfig
-2
configs/socfpga_arria5_defconfig
-2
configs/socfpga_arria5_defconfig
···
44
44
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
45
45
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)"
46
46
CONFIG_CMD_UBI=y
47
-
# CONFIG_ISO_PARTITION is not set
48
-
# CONFIG_EFI_PARTITION is not set
49
47
CONFIG_ENV_IS_IN_MMC=y
50
48
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
51
49
CONFIG_VERSION_VARIABLE=y
+1
-2
configs/socfpga_cyclone5_defconfig
+1
-2
configs/socfpga_cyclone5_defconfig
···
45
45
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
46
46
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)"
47
47
CONFIG_CMD_UBI=y
48
-
# CONFIG_ISO_PARTITION is not set
49
-
# CONFIG_EFI_PARTITION is not set
50
48
CONFIG_ENV_IS_IN_MMC=y
51
49
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
52
50
CONFIG_VERSION_VARIABLE=y
···
67
65
CONFIG_PHY_MICREL_KSZ90X1=y
68
66
CONFIG_ETH_DESIGNWARE=y
69
67
CONFIG_MII=y
68
+
CONFIG_NET_RANDOM_ETHADDR=y
70
69
CONFIG_SPI=y
71
70
CONFIG_CADENCE_QSPI=y
72
71
CONFIG_DESIGNWARE_SPI=y
+1
-2
configs/socfpga_de0_nano_soc_defconfig
+1
-2
configs/socfpga_de0_nano_soc_defconfig
···
28
28
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
29
29
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
30
30
CONFIG_SPL_HAVE_INIT_STACK=y
31
+
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE=y
31
32
CONFIG_SPL_SPI_LOAD=y
32
33
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
33
34
CONFIG_SYS_MAXARGS=32
···
45
46
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
46
47
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)"
47
48
CONFIG_CMD_UBI=y
48
-
# CONFIG_ISO_PARTITION is not set
49
-
# CONFIG_EFI_PARTITION is not set
50
49
CONFIG_ENV_IS_IN_MMC=y
51
50
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
52
51
CONFIG_VERSION_VARIABLE=y
-2
configs/socfpga_de10_nano_defconfig
-2
configs/socfpga_de10_nano_defconfig
-2
configs/socfpga_de10_standard_defconfig
-2
configs/socfpga_de10_standard_defconfig
-2
configs/socfpga_de1_soc_defconfig
-2
configs/socfpga_de1_soc_defconfig
-2
configs/socfpga_is1_defconfig
-2
configs/socfpga_is1_defconfig
···
44
44
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
45
45
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)"
46
46
CONFIG_CMD_UBI=y
47
-
# CONFIG_ISO_PARTITION is not set
48
-
# CONFIG_EFI_PARTITION is not set
49
47
CONFIG_ENV_IS_IN_SPI_FLASH=y
50
48
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
51
49
CONFIG_USE_BOOTFILE=y
-2
configs/socfpga_mcvevk_defconfig
-2
configs/socfpga_mcvevk_defconfig
-2
configs/socfpga_secu1_defconfig
-2
configs/socfpga_secu1_defconfig
···
63
63
CONFIG_MTDPARTS_DEFAULT="mtdparts=denali-nand:512k(nand.4spl),512k(nand.uboot),128k(nand.env1),128k(nand.env2),0x1000000(nand.rec),0x3ee40000(nand.ubi),0x80000@0x3ff80000(nand.bbt)"
64
64
CONFIG_CMD_UBI=y
65
65
# CONFIG_CMD_UBIFS is not set
66
-
# CONFIG_ISO_PARTITION is not set
67
-
# CONFIG_EFI_PARTITION is not set
68
66
CONFIG_ENV_OVERWRITE=y
69
67
CONFIG_ENV_IS_IN_NAND=y
70
68
CONFIG_ENV_REDUNDANT=y
-2
configs/socfpga_sockit_defconfig
-2
configs/socfpga_sockit_defconfig
···
44
44
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
45
45
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)"
46
46
CONFIG_CMD_UBI=y
47
-
# CONFIG_ISO_PARTITION is not set
48
-
# CONFIG_EFI_PARTITION is not set
49
47
CONFIG_ENV_IS_IN_MMC=y
50
48
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
51
49
CONFIG_VERSION_VARIABLE=y
-2
configs/socfpga_socrates_defconfig
-2
configs/socfpga_socrates_defconfig
···
44
44
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
45
45
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)"
46
46
CONFIG_CMD_UBI=y
47
-
# CONFIG_ISO_PARTITION is not set
48
-
# CONFIG_EFI_PARTITION is not set
49
47
CONFIG_ENV_IS_IN_MMC=y
50
48
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
51
49
CONFIG_VERSION_VARIABLE=y
-2
configs/socfpga_sr1500_defconfig
-2
configs/socfpga_sr1500_defconfig
···
51
51
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
52
52
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)"
53
53
CONFIG_CMD_UBI=y
54
-
# CONFIG_ISO_PARTITION is not set
55
-
# CONFIG_EFI_PARTITION is not set
56
54
CONFIG_ENV_IS_IN_SPI_FLASH=y
57
55
CONFIG_ENV_REDUNDANT=y
58
56
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
-2
configs/socfpga_vining_fpga_defconfig
-2
configs/socfpga_vining_fpga_defconfig
···
58
58
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
59
59
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),64k(env1),64k(env2),256k(softing1),256k(softing2),-(rcvrfs);"
60
60
CONFIG_CMD_UBI=y
61
-
# CONFIG_ISO_PARTITION is not set
62
-
# CONFIG_EFI_PARTITION is not set
63
61
CONFIG_ENV_IS_IN_SPI_FLASH=y
64
62
CONFIG_ENV_REDUNDANT=y
65
63
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
+1
disk/Kconfig
+1
disk/Kconfig
+1
-1
doc/board/rockchip/rockchip.rst
+1
-1
doc/board/rockchip/rockchip.rst
···
162
162
- Pine64 QuartzPro64 (quartzpro64-rk3588)
163
163
- Radxa ROCK 5 ITX (rock-5-itx-rk3588)
164
164
- Radxa ROCK 5A (rock5a-rk3588s)
165
-
- Radxa ROCK 5B (rock5b-rk3588)
165
+
- Radxa ROCK 5B/5B+/5T (rock5b-rk3588)
166
166
- Radxa ROCK 5C (rock-5c-rk3588s)
167
167
- Rockchip Toybrick TB-RK3588X (toybrick-rk3588)
168
168
- Theobroma Systems RK3588-SBC Jaguar (jaguar-rk3588)
+37
-9
doc/board/theobroma-systems/jaguar_rk3588.rst
+37
-9
doc/board/theobroma-systems/jaguar_rk3588.rst
···
32
32
Here is the step-by-step to boot to U-Boot on SBC-RK3588-AMR Jaguar from Theobroma
33
33
Systems.
34
34
35
-
Get the TF-A and DDR init (TPL) binaries
36
-
----------------------------------------
35
+
Get DDR init (TPL) binary
36
+
-------------------------
37
37
38
38
.. prompt:: bash
39
39
40
40
git clone https://github.com/rockchip-linux/rkbin
41
41
cd rkbin
42
-
export RKBIN=$(pwd)
43
-
export BL31=$RKBIN/bin/rk35/rk3588_bl31_v1.47.elf
44
-
export ROCKCHIP_TPL=$RKBIN/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.18.bin
42
+
export ROCKCHIP_TPL=$(readlink -f bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v*.bin | head -1)
45
43
sed -i 's/^uart baudrate=.*$/uart baudrate=115200/' tools/ddrbin_param.txt
46
-
./tools/ddrbin_tool rk3588 tools/ddrbin_param.txt "$ROCKCHIP_TPL"
44
+
sed -i 's/^uart iomux=.*$/uart iomux=0/' tools/ddrbin_param.txt
45
+
python3 ./tools/ddrbin_tool.py rk3588 tools/ddrbin_param.txt "$ROCKCHIP_TPL"
47
46
./tools/boot_merger RKBOOT/RK3588MINIALL.ini
48
-
export RKDB=$RKBIN/rk3588_spl_loader_v1.11.112.bin
47
+
export RKDB=$(readlink -f rk3588_spl_loader_v*.bin | head -1)
49
48
50
49
This will setup all required external dependencies for compiling U-Boot. This will
51
-
be updated in the future once upstream Trusted-Firmware-A supports RK3588 or U-Boot
52
-
gains support for open-source DRAM initialization in TPL.
50
+
be updated in the future once U-Boot gains support for open-source DRAM initialization
51
+
in TPL.
52
+
53
+
Get TF-A
54
+
--------
55
+
56
+
There are two possible options, pick one or the other. Note that the instructions need
57
+
to be run from the ``rkbin`` directory.
58
+
59
+
Prebuilt binary from Rockchip
60
+
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
61
+
62
+
.. prompt:: bash
63
+
64
+
export BL31=$(readlink -f bin/rk35/rk3588_bl31_v*.elf | head -1)
65
+
66
+
Upstream
67
+
~~~~~~~~
68
+
69
+
.. prompt:: bash
70
+
71
+
cd ../
72
+
git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
73
+
cd trusted-firmware-a
74
+
make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3588 bl31
75
+
export BL31=$PWD/build/rk3588/release/bl31/bl31.elf
53
76
54
77
Build U-Boot
55
78
------------
···
58
81
59
82
cd ../u-boot
60
83
make CROSS_COMPILE=aarch64-linux-gnu- jaguar-rk3588_defconfig all
84
+
85
+
.. note::
86
+
If using upstream TF-A, one should disable ``SPL_ATF_NO_PLATFORM_PARAM`` symbol in
87
+
U-Boot config (via e.g. ``make CROSS_COMPILE=aarch64-linux-gnu- menuconfig``) which
88
+
will, among other things, enable console output in TF-A.
61
89
62
90
This will build ``u-boot-rockchip.bin`` which can be written to an MMC device
63
91
(eMMC or SD card).
+4
-2
doc/board/theobroma-systems/puma_rk3399.rst
+4
-2
doc/board/theobroma-systems/puma_rk3399.rst
···
95
95
git clone https://github.com/rockchip-linux/rkbin.git
96
96
cd rkbin
97
97
./tools/boot_merger RKBOOT/RK3399MINIALL.ini
98
+
export RKDB=$(readlink -f rk3399_loader_v*.bin | head -1)
98
99
cd ..
99
-
./rkdeveloptool db rkbin/rk3399_loader_v1.30.130.bin
100
+
./rkdeveloptool db "$RKDB"
100
101
./rkdeveloptool wl 64 ../u-boot-rockchip.bin
101
102
102
103
NOR-Flash
···
121
122
git clone https://github.com/rockchip-linux/rkbin.git
122
123
cd rkbin
123
124
./tools/boot_merger RKBOOT/RK3399MINIALL_SPINOR.ini
125
+
export RKDB=$(readlink -f rk3399_loader_spinor_v*.bin | head -1)
124
126
cd ..
125
-
./rkdeveloptool db rkbin/rk3399_loader_spinor_v1.30.114.bin
127
+
./rkdeveloptool db "$RKDB"
126
128
./rkdeveloptool ef
127
129
./rkdeveloptool wl 0 ../u-boot-rockchip-spi.bin
+2
-1
doc/board/theobroma-systems/ringneck_px30.rst
+2
-1
doc/board/theobroma-systems/ringneck_px30.rst
···
90
90
git clone https://github.com/rockchip-linux/rkbin.git
91
91
cd rkbin
92
92
./tools/boot_merger RKBOOT/PX30MINIALL.ini
93
+
export RKDB=$(readlink -f px30_loader_v*.bin | head -1)
93
94
cd ..
94
-
./rkdeveloptool db rkbin/px30_loader_v2.08.135.bin
95
+
./rkdeveloptool db "$RKDB"
95
96
./rkdeveloptool wl 64 ../u-boot-rockchip.bin
+36
-9
doc/board/theobroma-systems/tiger_rk3588.rst
+36
-9
doc/board/theobroma-systems/tiger_rk3588.rst
···
39
39
Here is the step-by-step to boot to U-Boot on SOM-RK3588-Q7 Tiger from Theobroma
40
40
Systems.
41
41
42
-
Get the TF-A and DDR init (TPL) binaries
43
-
----------------------------------------
42
+
Get DDR init (TPL) binary
43
+
-------------------------
44
44
45
45
.. prompt:: bash
46
46
47
47
git clone https://github.com/rockchip-linux/rkbin
48
48
cd rkbin
49
-
export RKBIN=$(pwd)
50
-
export BL31=$RKBIN/bin/rk35/rk3588_bl31_v1.47.elf
51
-
export ROCKCHIP_TPL=$RKBIN/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.18.bin
49
+
export ROCKCHIP_TPL=$(readlink -f bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v*.bin | head -1)
52
50
sed -i 's/^uart baudrate=.*$/uart baudrate=115200/' tools/ddrbin_param.txt
53
51
sed -i 's/^uart iomux=.*$/uart iomux=2/' tools/ddrbin_param.txt
54
-
./tools/ddrbin_tool rk3588 tools/ddrbin_param.txt "$ROCKCHIP_TPL"
52
+
python3 ./tools/ddrbin_tool.py rk3588 tools/ddrbin_param.txt "$ROCKCHIP_TPL"
55
53
./tools/boot_merger RKBOOT/RK3588MINIALL.ini
56
-
export RKDB=$RKBIN/rk3588_spl_loader_v1.11.112.bin
54
+
export RKDB=$(readlink -f rk3588_spl_loader_v*.bin | head -1)
57
55
58
56
This will setup all required external dependencies for compiling U-Boot. This will
59
-
be updated in the future once upstream Trusted-Firmware-A supports RK3588 or U-Boot
60
-
gains support for open-source DRAM initialization in TPL.
57
+
be updated in the future once U-Boot gains support for open-source DRAM initialization
58
+
in TPL.
59
+
60
+
Get TF-A
61
+
--------
62
+
63
+
There are two possible options, pick one or the other. Note that the instructions need
64
+
to be run from the ``rkbin`` directory.
65
+
66
+
Prebuilt binary from Rockchip
67
+
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
68
+
69
+
.. prompt:: bash
70
+
71
+
export BL31=$(readlink -f bin/rk35/rk3588_bl31_v*.elf | head -1)
72
+
73
+
Upstream
74
+
~~~~~~~~
75
+
76
+
.. prompt:: bash
77
+
78
+
cd ../
79
+
git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
80
+
cd trusted-firmware-a
81
+
make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3588 bl31
82
+
export BL31=$PWD/build/rk3588/release/bl31/bl31.elf
61
83
62
84
Build U-Boot
63
85
------------
···
66
88
67
89
cd ../u-boot
68
90
make CROSS_COMPILE=aarch64-linux-gnu- tiger-rk3588_defconfig all
91
+
92
+
.. note::
93
+
If using upstream TF-A, one should disable ``SPL_ATF_NO_PLATFORM_PARAM`` symbol in
94
+
U-Boot config (via e.g. ``make CROSS_COMPILE=aarch64-linux-gnu- menuconfig``) which
95
+
will, among other things, enable console output in TF-A.
69
96
70
97
This will build ``u-boot-rockchip.bin`` which can be written to an MMC device
71
98
(eMMC or SD card).
+21
-2
doc/board/ti/j784s4_evm.rst
+21
-2
doc/board/ti/j784s4_evm.rst
···
1
1
.. SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
2
2
.. sectionauthor:: Apurva Nandan <a-nandan@ti.com>
3
3
4
-
J784S4 and AM69 Platforms
5
-
=========================
4
+
J742S2, J784S4 and AM69 Platforms
5
+
=================================
6
6
7
7
Introduction
8
8
------------
···
36
36
37
37
* https://www.ti.com/tool/J784S4XEVM
38
38
* https://www.ti.com/tool/SK-AM69
39
+
40
+
J742S2 is derivative of J784S24 SOC, More info can be found in
41
+
42
+
* TRM : https://www.ti.com/lit/ug/spruje3/spruje3.pdf
43
+
* Platform Information : https://www.ti.com/tool/J742S2XH01EVM
39
44
40
45
Boot Flow
41
46
---------
···
99
104
export UBOOT_CFG_CORTEXR=am69_sk_r5_defconfig
100
105
export UBOOT_CFG_CORTEXA=am69_sk_a72_defconfig
101
106
107
+
For J742S2-EVM, use the following U_BOOT_CFG instead:
108
+
109
+
.. prompt:: bash
110
+
111
+
export UBOOT_CFG_CORTEXR=j742s2_evm_r5_defconfig
112
+
export UBOOT_CFG_CORTEXA=j742s2_evm_a72_defconfig
113
+
102
114
.. j784s4_evm_rst_include_start_build_steps
103
115
104
116
1. Trusted Firmware-A
···
143
155
* tiboot3-j784s4-gp-evm.bin from :ref:`step 3.1 <j784s4_evm_rst_u_boot_r5>`
144
156
* tispl.bin_unsigned, u-boot.img_unsigned from :ref:`step 3.2 <j784s4_evm_rst_u_boot_a72>`
145
157
158
+
.. note::
159
+
160
+
For J742S2, GP variant is not available.
161
+
162
+
146
163
- HS-FS
147
164
148
165
* tiboot3-j784s4-hs-fs-evm.bin from :ref:`step 3.1 <j784s4_evm_rst_u_boot_r5>`
166
+
* tiboot3-j742s2-hs-fs-evm.bin from :ref:`step 3.1 <j784s4_evm_rst_u_boot_r5>`
149
167
* tispl.bin, u-boot.img from :ref:`step 3.2 <j784s4_evm_rst_u_boot_a72>`
150
168
151
169
- HS-SE
152
170
153
171
* tiboot3-j784s4-hs-evm.bin from :ref:`step 3.1 <j784s4_evm_rst_u_boot_r5>`
172
+
* tiboot3-j742s2-hs-evm.bin from :ref:`step 3.1 <j784s4_evm_rst_u_boot_r5>`
154
173
* tispl.bin, u-boot.img from :ref:`step 3.2 <j784s4_evm_rst_u_boot_a72>`
155
174
156
175
Image formats
+3
-3
doc/board/ti/k3.rst
+3
-3
doc/board/ti/k3.rst
···
653
653
Saving environment
654
654
------------------
655
655
656
-
SAVEENV is disabled by default and for the new flow uses Uenv.txt as the default
657
-
way for saving the environments. This has been done as Uenv.txt is more granular
658
-
then the saveenv command and can be used across various bootmodes too.
656
+
SAVEENV is disabled by default and for the new flow uses uEnv.txt as the default
657
+
way for saving the environments. This has been done as uEnv.txt is more granular
658
+
than the saveenv command and can be used across various bootmodes too.
659
659
660
660
**Writing to MMC/EMMC**
661
661
+1
-1
doc/usage/cmd/part.rst
+1
-1
doc/usage/cmd/part.rst
+1
-2
drivers/clk/mediatek/clk-mtk.h
+1
-2
drivers/clk/mediatek/clk-mtk.h
···
133
133
* struct mtk_composite - aggregate clock of mux, divider and gate clocks
134
134
*
135
135
* @id: index of clocks
136
-
* @parent: index of parnet clocks
137
-
* @parent: index of parnet clocks
136
+
* @parent: index of parent clocks
138
137
* @parent_flags: table of parent clocks with flags
139
138
* @mux_reg: hardware-specific mux register
140
139
* @gate_reg: hardware-specific gate register
+18
-9
drivers/i2c/rk_i2c.c
+18
-9
drivers/i2c/rk_i2c.c
···
137
137
writel(I2C_IPD_ALL_CLEAN, ®s->ipd);
138
138
139
139
writel(I2C_CON_EN | I2C_CON_STOP, ®s->con);
140
-
writel(I2C_CON_STOP, ®s->ien);
140
+
writel(I2C_STOPIEN, ®s->ien);
141
141
142
142
start = get_timer(0);
143
143
while (1) {
···
195
195
196
196
while (bytes_remain_len) {
197
197
if (bytes_remain_len > RK_I2C_FIFO_SIZE) {
198
-
con = I2C_CON_EN;
199
-
bytes_xferred = 32;
200
-
} else {
201
198
/*
202
199
* The hw can read up to 32 bytes at a time. If we need
203
-
* more than one chunk, send an ACK after the last byte.
200
+
* more than one chunk, send an ACK after the last byte
201
+
* of the current chunk.
204
202
*/
203
+
con = I2C_CON_EN;
204
+
bytes_xferred = 32;
205
+
} else {
205
206
con = I2C_CON_EN | I2C_CON_LASTACK;
206
207
bytes_xferred = bytes_remain_len;
207
208
}
···
254
255
}
255
256
256
257
i2c_exit:
257
-
rk_i2c_disable(i2c);
258
-
259
258
return err;
260
259
}
261
260
···
332
331
}
333
332
334
333
i2c_exit:
335
-
rk_i2c_disable(i2c);
336
-
337
334
return err;
338
335
}
339
336
···
358
355
ret = -EREMOTEIO;
359
356
break;
360
357
}
358
+
359
+
/*
360
+
* The HW is actually not capable of REPEATED START. But we can
361
+
* get the intended effect by resetting its internal state
362
+
* and issuing an ordinary START.
363
+
*
364
+
* Do NOT disable the controller after the last message (before
365
+
* sending the STOP condition) as this triggers an illegal
366
+
* START condition followed by a STOP condition.
367
+
*/
368
+
if (nmsgs > 1)
369
+
rk_i2c_disable(i2c);
361
370
}
362
371
363
372
rk_i2c_send_stop_bit(i2c);
+1
drivers/mmc/sdhci-cadence.c
+1
drivers/mmc/sdhci-cadence.c
+8
drivers/spi/Kconfig
+8
drivers/spi/Kconfig
···
677
677
Enable the Renesas Quad SPI controller driver. This driver can be
678
678
used on Renesas SoCs.
679
679
680
+
config SPL_DESIGNWARE_SPI
681
+
bool "Designware SPI driver in SPL"
682
+
depends on SPL_DM_SPI
683
+
default y if DESIGNWARE_SPI
684
+
help
685
+
Enable the Designware SPI driver during SPL.
686
+
See the help of DESIGNWARE_SPI for details.
687
+
680
688
config MXC_SPI
681
689
bool "MXC SPI Driver"
682
690
depends on MACH_IMX
+1
-1
drivers/spi/Makefile
+1
-1
drivers/spi/Makefile
···
35
35
obj-$(CONFIG_CORTINA_SFLASH) += ca_sflash.o
36
36
obj-$(CONFIG_CV1800B_SPIF) += cv1800b_spif.o
37
37
obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
38
-
obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o
38
+
obj-$(CONFIG_$(PHASE_)DESIGNWARE_SPI) += designware_spi.o
39
39
obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
40
40
obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o
41
41
obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
+5
fs/fat/fat.c
+5
fs/fat/fat.c
···
216
216
if (flush_dirty_fat_buffer(mydata) < 0)
217
217
return -1;
218
218
219
+
if (getsize > FATBUFBLOCKS) {
220
+
debug("getsize is too large for bufptr\n");
221
+
getsize = FATBUFBLOCKS;
222
+
}
223
+
219
224
if (disk_read(startblock, getsize, bufptr) < 0) {
220
225
debug("Error reading FAT blocks\n");
221
226
return ret;
-5
include/configs/am43xx_evm.h
-5
include/configs/am43xx_evm.h
···
148
148
#define NANDBOOT
149
149
#endif /* CONFIG_MTD_RAW_NAND */
150
150
151
-
#if defined(CONFIG_TI_SECURE_DEVICE)
152
-
/* Avoid relocating onto firewalled area at end of DRAM */
153
-
#define CFG_PRAM (64 * 1024)
154
-
#endif /* CONFIG_TI_SECURE_DEVICE */
155
-
156
151
#endif /* __CONFIG_AM43XX_EVM_H */
+2
-1
include/part.h
+2
-1
include/part.h
···
461
461
#ifdef CONFIG_XPL_BUILD
462
462
# define part_print_ptr(x) NULL
463
463
# if defined(CONFIG_SPL_FS_EXT4) || defined(CONFIG_SPL_FS_FAT) || \
464
-
defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION)
464
+
defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION) || \
465
+
defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE)
465
466
# define part_get_info_ptr(x) x
466
467
# else
467
468
# define part_get_info_ptr(x) NULL
+4
lib/uuid.c
+4
lib/uuid.c
+17
-6
test/dm/fdtdec.c
+17
-6
test/dm/fdtdec.c
···
14
14
15
15
DECLARE_GLOBAL_DATA_PTR;
16
16
17
+
#define FDTDEC_MAX_SIZE (2 * 1024 * 1024)
18
+
17
19
static int dm_test_fdtdec_set_carveout(struct unit_test_state *uts)
18
20
{
19
21
struct fdt_memory resv;
20
22
void *blob;
21
23
const fdt32_t *prop;
22
-
int blob_sz, len, offset;
24
+
int blob_sz, len, offset, fdt_sz;
25
+
26
+
fdt_sz = fdt_totalsize(gd->fdt_blob);
27
+
ut_assert(fdt_sz > 0 && fdt_sz < FDTDEC_MAX_SIZE);
23
28
24
-
blob_sz = fdt_totalsize(gd->fdt_blob) + 4096;
29
+
blob_sz = fdt_sz + 4096;
25
30
blob = malloc(blob_sz);
26
31
ut_assertnonnull(blob);
27
32
···
67
72
fdt_size_t size;
68
73
void *blob;
69
74
unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
70
-
int blob_sz, parent, subnode;
75
+
int blob_sz, parent, subnode, fdt_sz;
71
76
uint32_t phandle, phandle1;
72
77
73
-
blob_sz = fdt_totalsize(gd->fdt_blob) + 128;
78
+
fdt_sz = fdt_totalsize(gd->fdt_blob);
79
+
ut_assert(fdt_sz > 0 && fdt_sz < FDTDEC_MAX_SIZE);
80
+
81
+
blob_sz = fdt_sz + 128;
74
82
blob = malloc(blob_sz);
75
83
ut_assertnonnull(blob);
76
84
···
138
146
void *blob;
139
147
ulong val;
140
148
struct smbios3_entry *entry;
141
-
int chosen, blob_sz;
149
+
int chosen, blob_sz, fdt_sz;
142
150
const fdt64_t *prop;
143
151
144
152
if (!CONFIG_IS_ENABLED(GENERATE_SMBIOS_TABLE)) {
145
153
return -EAGAIN;
146
154
}
147
155
148
-
blob_sz = fdt_totalsize(gd->fdt_blob) + 4096;
156
+
fdt_sz = fdt_totalsize(gd->fdt_blob);
157
+
ut_assert(fdt_sz > 0 && fdt_sz < FDTDEC_MAX_SIZE);
158
+
159
+
blob_sz = fdt_sz + 4096;
149
160
blob = memalign(8, blob_sz);
150
161
ut_assertnonnull(blob);
151
162
+1
-1
tools/binman/pyproject.toml
+1
-1
tools/binman/pyproject.toml
+1
-1
tools/buildman/pyproject.toml
+1
-1
tools/buildman/pyproject.toml
+1
-1
tools/dtoc/pyproject.toml
+1
-1
tools/dtoc/pyproject.toml
+1
-1
tools/libfdt/fdt_rw.c
+1
-1
tools/libfdt/fdt_rw.c
+1
-1
tools/patman/pyproject.toml
+1
-1
tools/patman/pyproject.toml
+20
-4
tools/rkcommon.c
+20
-4
tools/rkcommon.c
···
76
76
/**
77
77
* struct header0_info - header block for boot ROM
78
78
*
79
-
* This is stored at SD card block 64 (where each block is 512 bytes, or at
80
-
* the start of SPI flash. It is encoded with RC4.
79
+
* This is stored at MMC block 64 (where each block is 512 bytes), or at
80
+
* the start of SPI flash. It is encoded with RC4 with the below rc4_key.
81
+
*
82
+
* In Rockchip terminology:
83
+
*
84
+
* "init" means the stage that is loaded into SRAM. TPL if there is one, SPL
85
+
* otherwise.
86
+
*
87
+
* "boot" means the next stages after "init" stage that are loaded by the
88
+
* BootROM into DRAM. Only applicable if "init" stage returns to BootROM (via
89
+
* the appropriate ROCKCHIP_BACK_TO_BROM symbol, BOOT_DEVICE_BOOTROM is used as
90
+
* boot device for the next stage and the "init" stage successfully booted) and
91
+
* if "init_boot_size" > "init_size".
92
+
* Basically, it is the content of "init" plus the SPL or even U-Boot proper if
93
+
* relevant.
81
94
*
82
95
* @magic: Magic (must be RK_MAGIC)
83
96
* @disable_rc4: 0 to use rc4 for boot image, 1 to use plain binary
84
-
* @init_offset: Offset in blocks of the SPL code from this header
85
-
* block. E.g. 4 means 2KB after the start of this header.
97
+
* @init_offset: Offset in 512-byte blocks of the "init" code from the
98
+
* start of this header. For instance, 4 means 2KiB.
99
+
* @init_size: Size (in blocks) of the "init" code.
100
+
* @init_boot_size: Size (in blocks) of the "init" and "boot" code combined.
101
+
*
86
102
* Other fields are not used by U-Boot
87
103
*/
88
104
struct header0_info {