"Das U-Boot" Source Tree
Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
CI: https://dev.azure.com/sr0718/u-boot/_build/results?buildId=389&view=results
- kirkwood: Enable bootstd and other modernization for OpenRD boards
(Tony)
- board: solidrun: clearfog: enable ddr odt0 on write for both
chip-select (Josua)
- configs: mvebu_espressobin_ultra-88f3720_defconfig: enable full
bootflow functionality (Ben)
- Initial support for PXA1908 and samsung-coreprimevelte (Duje)
+422
-58
+8
MAINTAINERS
+8
MAINTAINERS
···
386
386
F: drivers/pci/pci-aardvark.c
387
387
F: drivers/pci/pci_mvebu.c
388
388
389
+
ARM MARVELL PXA1908
390
+
M: Duje Mihanović <duje.mihanovic@skole.hr>
391
+
S: Maintained
392
+
T: git git://git.dujemihanovic.xyz/u-boot.git
393
+
F: arch/arm/dts/pxa1908*
394
+
F: arch/arm/mach-mmp/
395
+
F: include/configs/pxa1908.h
396
+
389
397
ARM MARVELL SERIAL DRIVERS
390
398
M: Pali Rohár <pali@kernel.org>
391
399
M: Stefan Roese <sr@denx.de>
+11
arch/arm/Kconfig
+11
arch/arm/Kconfig
···
842
842
Support for the MediaTek SoCs family developed by MediaTek Inc.
843
843
Please refer to doc/README.mediatek for more information.
844
844
845
+
config ARCH_MMP
846
+
bool "Marvell MMP"
847
+
select ARM64
848
+
select DM
849
+
select DM_SERIAL
850
+
select OF_CONTROL
851
+
select SAVE_PREV_BL_FDT_ADDR
852
+
select SAVE_PREV_BL_INITRAMFS_START_ADDR
853
+
845
854
config ARCH_LPC32XX
846
855
bool "NXP LPC32xx platform"
847
856
select CPU_ARM926EJS
···
2309
2318
source "arch/arm/mach-meson/Kconfig"
2310
2319
2311
2320
source "arch/arm/mach-mediatek/Kconfig"
2321
+
2322
+
source "arch/arm/mach-mmp/Kconfig"
2312
2323
2313
2324
source "arch/arm/mach-qemu/Kconfig"
2314
2325
+1
arch/arm/Makefile
+1
arch/arm/Makefile
···
69
69
machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx
70
70
machine-$(CONFIG_ARCH_MEDIATEK) += mediatek
71
71
machine-$(CONFIG_ARCH_MESON) += meson
72
+
machine-$(CONFIG_ARCH_MMP) += mmp
72
73
machine-$(CONFIG_ARCH_MVEBU) += mvebu
73
74
machine-$(CONFIG_ARCH_NEXELL) += nexell
74
75
machine-$(CONFIG_ARCH_NPCM) += npcm
+2
arch/arm/dts/Makefile
+2
arch/arm/dts/Makefile
···
1226
1226
dtb-$(CONFIG_TARGET_CORSTONE1000) += corstone1000-mps3.dtb \
1227
1227
corstone1000-fvp.dtb
1228
1228
1229
+
dtb-$(CONFIG_TARGET_COREPRIMEVELTE) += pxa1908-samsung-coreprimevelte.dtb
1230
+
1229
1231
include $(srctree)/scripts/Makefile.dts
1230
1232
1231
1233
# Add any required device tree compiler flags here
+74
arch/arm/dts/pxa1908-samsung-coreprimevelte.dts
+74
arch/arm/dts/pxa1908-samsung-coreprimevelte.dts
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
#include "pxa1908.dtsi"
3
+
4
+
/ {
5
+
pxa,rev-id = <3928 2>;
6
+
model = "Samsung Galaxy Core Prime VE LTE";
7
+
compatible = "samsung,coreprimevelte", "marvell,pxa1908";
8
+
9
+
aliases {
10
+
serial0 = &uart0;
11
+
};
12
+
13
+
chosen {
14
+
#address-cells = <2>;
15
+
#size-cells = <2>;
16
+
ranges;
17
+
18
+
stdout-path = "serial0:115200n8";
19
+
20
+
/* S-Boot places the initramfs here */
21
+
linux,initrd-start = <0x4d70000>;
22
+
linux,initrd-end = <0x5000000>;
23
+
24
+
fb0: framebuffer@17177000 {
25
+
compatible = "simple-framebuffer";
26
+
reg = <0 0x17177000 0 (480 * 800 * 4)>;
27
+
width = <480>;
28
+
height = <800>;
29
+
stride = <(480 * 4)>;
30
+
format = "a8r8g8b8";
31
+
};
32
+
};
33
+
34
+
memory {
35
+
device_type = "memory";
36
+
reg = <0 0x1000000 0 0x3f000000>;
37
+
};
38
+
39
+
reserved-memory {
40
+
#address-cells = <2>;
41
+
#size-cells = <2>;
42
+
ranges;
43
+
44
+
framebuffer@17000000 {
45
+
reg = <0 0x17000000 0 0x1800000>;
46
+
no-map;
47
+
};
48
+
49
+
gpu@9000000 {
50
+
reg = <0 0x9000000 0 0x1000000>;
51
+
};
52
+
53
+
/* Communications processor, aka modem */
54
+
cp@5000000 {
55
+
reg = <0 0x5000000 0 0x3000000>;
56
+
};
57
+
58
+
cm3@a000000 {
59
+
reg = <0 0xa000000 0 0x80000>;
60
+
};
61
+
62
+
seclog@8000000 {
63
+
reg = <0 0x8000000 0 0x100000>;
64
+
};
65
+
66
+
ramoops@8100000 {
67
+
compatible = "ramoops";
68
+
reg = <0 0x8100000 0 0x40000>;
69
+
record-size = <0x8000>;
70
+
console-size = <0x20000>;
71
+
max-reason = <5>;
72
+
};
73
+
};
74
+
};
+106
arch/arm/dts/pxa1908.dtsi
+106
arch/arm/dts/pxa1908.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/dts-v1/;
3
+
4
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
5
+
6
+
/ {
7
+
model = "Marvell Armada PXA1908";
8
+
compatible = "marvell,pxa1908";
9
+
#address-cells = <2>;
10
+
#size-cells = <2>;
11
+
interrupt-parent = <&gic>;
12
+
13
+
cpus {
14
+
#address-cells = <2>;
15
+
#size-cells = <0>;
16
+
17
+
cpu0: cpu@0 {
18
+
device_type = "cpu";
19
+
compatible = "arm,cortex-a53";
20
+
reg = <0 0>;
21
+
enable-method = "psci";
22
+
};
23
+
24
+
cpu1: cpu@1 {
25
+
device_type = "cpu";
26
+
compatible = "arm,cortex-a53";
27
+
reg = <0 1>;
28
+
enable-method = "psci";
29
+
};
30
+
31
+
cpu2: cpu@2 {
32
+
device_type = "cpu";
33
+
compatible = "arm,cortex-a53";
34
+
reg = <0 2>;
35
+
enable-method = "psci";
36
+
};
37
+
38
+
cpu3: cpu@3 {
39
+
device_type = "cpu";
40
+
compatible = "arm,cortex-a53";
41
+
reg = <0 3>;
42
+
enable-method = "psci";
43
+
};
44
+
};
45
+
46
+
psci {
47
+
compatible = "arm,psci-0.2";
48
+
method = "smc";
49
+
};
50
+
51
+
timer {
52
+
compatible = "arm,armv8-timer";
53
+
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
54
+
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
55
+
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
56
+
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
57
+
};
58
+
59
+
soc {
60
+
compatible = "simple-bus";
61
+
#address-cells = <2>;
62
+
#size-cells = <2>;
63
+
ranges;
64
+
65
+
gic: interrupt-controller@d1df9000 {
66
+
compatible = "arm,gic-400";
67
+
reg = <0 0xd1df9000 0 0x1000>,
68
+
<0 0xd1dfa000 0 0x2000>,
69
+
/* The subsequent registers are guesses. */
70
+
<0 0xd1dfc000 0 0x2000>,
71
+
<0 0xd1dfe000 0 0x2000>;
72
+
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
73
+
interrupt-controller;
74
+
#interrupt-cells = <3>;
75
+
};
76
+
77
+
apb@d4000000 {
78
+
compatible = "simple-bus";
79
+
reg = <0 0xd4000000 0 0x200000>;
80
+
#address-cells = <1>;
81
+
#size-cells = <1>;
82
+
ranges = <0 0 0xd4000000 0x200000>;
83
+
84
+
uart0: serial@17000 {
85
+
compatible = "mrvl,mmp-uart", "intel,xscale-uart";
86
+
reg = <0x17000 0x1000>;
87
+
clock-frequency = <14745600>;
88
+
reg-shift = <2>;
89
+
};
90
+
91
+
uart1: serial@18000 {
92
+
compatible = "mrvl,mmp-uart", "intel,xscale-uart";
93
+
reg = <0x18000 0x1000>;
94
+
clock-frequency = <14745600>;
95
+
reg-shift = <2>;
96
+
};
97
+
98
+
uart2: serial@36000 {
99
+
compatible = "mrvl,mmp-uart", "intel,xscale-uart";
100
+
reg = <0x36000 0x1000>;
101
+
clock-frequency = <117000000>;
102
+
reg-shift = <2>;
103
+
};
104
+
};
105
+
};
106
+
};
+1
arch/arm/mach-kirkwood/Kconfig
+1
arch/arm/mach-kirkwood/Kconfig
+12
arch/arm/mach-mmp/Kconfig
+12
arch/arm/mach-mmp/Kconfig
+1
arch/arm/mach-mmp/Makefile
+1
arch/arm/mach-mmp/Makefile
···
1
+
obj-y += board.o mmu.o
+84
arch/arm/mach-mmp/board.c
+84
arch/arm/mach-mmp/board.c
···
1
+
// SPDX-License-Identifier: GPL-2.0+
2
+
/*
3
+
* Copyright (c) 2024
4
+
* Duje Mihanović <duje.mihanovic@skole.hr>
5
+
*/
6
+
#include <errno.h>
7
+
#include <init.h>
8
+
#include <fdt_support.h>
9
+
#include <asm/io.h>
10
+
#include <asm/global_data.h>
11
+
12
+
DECLARE_GLOBAL_DATA_PTR;
13
+
14
+
/* Timer constants */
15
+
#define APBC_COUNTER_CLK_SEL 0xd4015064
16
+
#define COUNTER_BASE 0xd4101000
17
+
#define COUNTER_EN BIT(0)
18
+
#define COUNTER_HALT_ON_DEBUG BIT(1)
19
+
20
+
int timer_init(void)
21
+
{
22
+
u32 tmp = readl(APBC_COUNTER_CLK_SEL);
23
+
24
+
if ((tmp >> 16) != 0x319)
25
+
return -1;
26
+
27
+
/* Set timer frequency to 26MHz */
28
+
writel(tmp | 1, APBC_COUNTER_CLK_SEL);
29
+
writel(COUNTER_EN | COUNTER_HALT_ON_DEBUG, COUNTER_BASE);
30
+
31
+
gd->arch.timer_rate_hz = 26000000;
32
+
33
+
return 0;
34
+
}
35
+
36
+
int board_init(void)
37
+
{
38
+
return 0;
39
+
}
40
+
41
+
int dram_init(void)
42
+
{
43
+
if (fdtdec_setup_mem_size_base() != 0)
44
+
puts("fdtdec_setup_mem_size_base() has failed\n");
45
+
46
+
return 0;
47
+
}
48
+
49
+
#ifndef CONFIG_SYSRESET
50
+
void reset_cpu(void)
51
+
{
52
+
}
53
+
#endif
54
+
55
+
/* Stolen from arch/arm/mach-snapdragon/board.c */
56
+
int board_fdt_blob_setup(void **fdtp)
57
+
{
58
+
struct fdt_header *fdt;
59
+
bool internal_valid, external_valid;
60
+
int ret = 0;
61
+
62
+
fdt = (struct fdt_header *)get_prev_bl_fdt_addr();
63
+
external_valid = fdt && !fdt_check_header(fdt);
64
+
internal_valid = !fdt_check_header(*fdtp);
65
+
66
+
/*
67
+
* There is no point returning an error here, U-Boot can't do anything useful in this situation.
68
+
* Bail out while we can still print a useful error message.
69
+
*/
70
+
if (!internal_valid && !external_valid)
71
+
panic("Internal FDT is invalid and no external FDT was provided! (fdt=%#llx)\n",
72
+
(phys_addr_t)fdt);
73
+
74
+
if (internal_valid) {
75
+
debug("Using built in FDT\n");
76
+
ret = -EEXIST;
77
+
} else {
78
+
debug("Using external FDT\n");
79
+
/* So we can use it before returning */
80
+
*fdtp = fdt;
81
+
}
82
+
83
+
return ret;
84
+
}
+30
arch/arm/mach-mmp/mmu.c
+30
arch/arm/mach-mmp/mmu.c
···
1
+
// SPDX-License-Identifier: GPL-2.0+
2
+
/*
3
+
* Copyright (c) 2024
4
+
* Duje Mihanović <duje.mihanovic@skole.hr>
5
+
*/
6
+
#include <asm/armv8/mmu.h>
7
+
#include <linux/sizes.h>
8
+
9
+
static struct mm_region pxa1908_mem_map[] = {
10
+
{
11
+
.virt = 0x0UL,
12
+
.phys = 0x0UL,
13
+
.size = 2UL * SZ_1G,
14
+
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
15
+
PTE_BLOCK_INNER_SHARE
16
+
},
17
+
{
18
+
.virt = 0x80000000UL,
19
+
.phys = 0x80000000UL,
20
+
.size = 2UL * SZ_1G,
21
+
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
22
+
PTE_BLOCK_INNER_SHARE |
23
+
PTE_BLOCK_PXN | PTE_BLOCK_UXN
24
+
},
25
+
{
26
+
0,
27
+
}
28
+
};
29
+
30
+
struct mm_region *mem_map = pxa1908_mem_map;
+20
board/Marvell/openrd/openrd.env
+20
board/Marvell/openrd/openrd.env
···
1
+
/* SPDX-License-Identifier: GPL-2.0+ */
2
+
/*
3
+
* Copyright (C) 2024 Tony Dinh <mibodhi@gmail.com>
4
+
*
5
+
* Environment variables configurations
6
+
*/
7
+
8
+
kernel_addr_r=0x800000
9
+
fdt_addr_r=0x2c00000
10
+
ramdisk_addr_r=0x01100000
11
+
scriptaddr=0x200000
12
+
fdtfile=CONFIG_DEFAULT_DEVICE_TREE.dtb
13
+
mtdparts=CONFIG_MTDPARTS_DEFAULT
14
+
console=ttyS0,115200
15
+
16
+
/* Standard Boot */
17
+
bootcmd=
18
+
bootflow scan -lb
19
+
failed=
20
+
echo CONFIG_SYS_BOARD boot failed - please check your image
+12
board/samsung/coreprimevelte/Kconfig
+12
board/samsung/coreprimevelte/Kconfig
+6
board/samsung/coreprimevelte/MAINTAINERS
+6
board/samsung/coreprimevelte/MAINTAINERS
+1
-1
board/solidrun/clearfog/clearfog.c
+1
-1
board/solidrun/clearfog/clearfog.c
+18
configs/coreprimevelte_defconfig
+18
configs/coreprimevelte_defconfig
···
1
+
CONFIG_ARM=y
2
+
CONFIG_SKIP_LOWLEVEL_INIT=y
3
+
CONFIG_COUNTER_FREQUENCY=26000000
4
+
CONFIG_ARCH_CPU_INIT=y
5
+
CONFIG_ARCH_MMP=y
6
+
CONFIG_TEXT_BASE=0x1000000
7
+
CONFIG_NR_DRAM_BANKS=2
8
+
CONFIG_DEFAULT_DEVICE_TREE="pxa1908-samsung-coreprimevelte"
9
+
CONFIG_TARGET_COREPRIMEVELTE=y
10
+
CONFIG_SYS_LOAD_ADDR=0x1000000
11
+
CONFIG_ARMV8_PSCI=y
12
+
CONFIG_FIT=y
13
+
# CONFIG_DISPLAY_CPUINFO is not set
14
+
CONFIG_HUSH_PARSER=y
15
+
CONFIG_CMD_DM=y
16
+
CONFIG_OF_BOARD=y
17
+
CONFIG_SYS_NS16550=y
18
+
CONFIG_SYS_NS16550_MEM32=y
+1
configs/mvebu_espressobin_ultra-88f3720_defconfig
+1
configs/mvebu_espressobin_ultra-88f3720_defconfig
+5
-13
configs/openrd_base_defconfig
+5
-13
configs/openrd_base_defconfig
···
4
4
CONFIG_ARCH_CPU_INIT=y
5
5
CONFIG_SYS_THUMB_BUILD=y
6
6
CONFIG_ARCH_KIRKWOOD=y
7
+
CONFIG_SUPPORT_PASSING_ATAGS=y
8
+
CONFIG_CMDLINE_TAG=y
9
+
CONFIG_INITRD_TAG=y
7
10
CONFIG_SYS_KWD_CONFIG="board/Marvell/openrd/kwbimage.cfg"
8
11
CONFIG_TEXT_BASE=0x600000
9
12
CONFIG_NR_DRAM_BANKS=2
10
-
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000
11
13
CONFIG_TARGET_OPENRD=y
12
14
CONFIG_ENV_SIZE=0x20000
13
15
CONFIG_ENV_OFFSET=0x80000
14
16
CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-openrd-base"
15
17
CONFIG_SYS_LOAD_ADDR=0x800000
16
18
CONFIG_IDENT_STRING="\nOpenRD-Base"
17
-
# CONFIG_SYS_MALLOC_F is not set
18
19
CONFIG_HAS_BOARD_SIZE_LIMIT=y
19
20
CONFIG_BOARD_SIZE_LIMIT=524288
21
+
CONFIG_BOOTSTD_FULL=y
20
22
CONFIG_BOOTDELAY=3
21
-
CONFIG_USE_BOOTCOMMAND=y
22
-
CONFIG_BOOTCOMMAND="${x_bootcmd_kernel}; setenv bootargs ${x_bootargs} ${x_bootargs_root}; ${x_bootcmd_usb}; bootm 0x6400000;"
23
23
CONFIG_USE_PREBOOT=y
24
24
CONFIG_LOGLEVEL=2
25
25
# CONFIG_DISPLAY_BOARDINFO is not set
···
30
30
CONFIG_CMD_NAND=y
31
31
CONFIG_CMD_USB=y
32
32
# CONFIG_CMD_SETEXPR is not set
33
-
CONFIG_CMD_DHCP=y
34
-
CONFIG_CMD_MII=y
35
-
CONFIG_CMD_PING=y
36
-
CONFIG_CMD_EXT2=y
37
-
CONFIG_CMD_FAT=y
38
-
CONFIG_CMD_JFFS2=y
39
33
CONFIG_CMD_MTDPARTS=y
40
34
CONFIG_MTDIDS_DEFAULT="nand0=nand_mtd"
41
35
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand_mtd:0x100000@0x000000(uboot),0x400000@0x100000(uImage),0x1fb00000@0x500000(rootfs)"
42
36
CONFIG_CMD_UBI=y
43
-
CONFIG_ISO_PARTITION=y
44
37
CONFIG_OF_CONTROL=y
45
38
CONFIG_ENV_OVERWRITE=y
46
39
CONFIG_ENV_IS_IN_NAND=y
47
40
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
48
41
CONFIG_NETCONSOLE=y
49
42
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
43
+
CONFIG_NET_RANDOM_ETHADDR=y
50
44
CONFIG_SYS_ATA_STRIDE=4
51
45
CONFIG_SYS_ATA_DATA_OFFSET=0x100
52
46
CONFIG_SYS_ATA_REG_OFFSET=0x100
···
59
53
CONFIG_MTD_RAW_NAND=y
60
54
CONFIG_MVGBE=y
61
55
CONFIG_MII=y
62
-
CONFIG_SYS_NS16550_SERIAL=y
63
-
CONFIG_SYS_NS16550_REG_SIZE=-4
64
56
CONFIG_USB=y
65
57
CONFIG_USB_EHCI_HCD=y
+5
-13
configs/openrd_client_defconfig
+5
-13
configs/openrd_client_defconfig
···
4
4
CONFIG_ARCH_CPU_INIT=y
5
5
CONFIG_SYS_THUMB_BUILD=y
6
6
CONFIG_ARCH_KIRKWOOD=y
7
+
CONFIG_SUPPORT_PASSING_ATAGS=y
8
+
CONFIG_CMDLINE_TAG=y
9
+
CONFIG_INITRD_TAG=y
7
10
CONFIG_SYS_KWD_CONFIG="board/Marvell/openrd/kwbimage.cfg"
8
11
CONFIG_TEXT_BASE=0x600000
9
12
CONFIG_NR_DRAM_BANKS=2
10
-
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000
11
13
CONFIG_TARGET_OPENRD=y
12
14
CONFIG_BOARD_IS_OPENRD_CLIENT=y
13
15
CONFIG_ENV_SIZE=0x20000
···
15
17
CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-openrd-client"
16
18
CONFIG_SYS_LOAD_ADDR=0x800000
17
19
CONFIG_IDENT_STRING="\nOpenRD-Client"
18
-
# CONFIG_SYS_MALLOC_F is not set
19
20
CONFIG_HAS_BOARD_SIZE_LIMIT=y
20
21
CONFIG_BOARD_SIZE_LIMIT=524288
22
+
CONFIG_BOOTSTD_FULL=y
21
23
CONFIG_BOOTDELAY=3
22
-
CONFIG_USE_BOOTCOMMAND=y
23
-
CONFIG_BOOTCOMMAND="${x_bootcmd_kernel}; setenv bootargs ${x_bootargs} ${x_bootargs_root}; ${x_bootcmd_usb}; bootm 0x6400000;"
24
24
CONFIG_USE_PREBOOT=y
25
25
CONFIG_LOGLEVEL=2
26
26
# CONFIG_DISPLAY_BOARDINFO is not set
···
31
31
CONFIG_CMD_NAND=y
32
32
CONFIG_CMD_USB=y
33
33
# CONFIG_CMD_SETEXPR is not set
34
-
CONFIG_CMD_DHCP=y
35
-
CONFIG_CMD_MII=y
36
-
CONFIG_CMD_PING=y
37
-
CONFIG_CMD_EXT2=y
38
-
CONFIG_CMD_FAT=y
39
-
CONFIG_CMD_JFFS2=y
40
34
CONFIG_CMD_MTDPARTS=y
41
35
CONFIG_MTDIDS_DEFAULT="nand0=nand_mtd"
42
36
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand_mtd:0x100000@0x000000(uboot),0x400000@0x100000(uImage),0x1fb00000@0x500000(rootfs)"
43
37
CONFIG_CMD_UBI=y
44
-
CONFIG_ISO_PARTITION=y
45
38
CONFIG_OF_CONTROL=y
46
39
CONFIG_ENV_OVERWRITE=y
47
40
CONFIG_ENV_IS_IN_NAND=y
48
41
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
49
42
CONFIG_NETCONSOLE=y
50
43
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
44
+
CONFIG_NET_RANDOM_ETHADDR=y
51
45
CONFIG_SYS_ATA_STRIDE=4
52
46
CONFIG_SYS_ATA_DATA_OFFSET=0x100
53
47
CONFIG_SYS_ATA_REG_OFFSET=0x100
···
60
54
CONFIG_MTD_RAW_NAND=y
61
55
CONFIG_MVGBE=y
62
56
CONFIG_MII=y
63
-
CONFIG_SYS_NS16550_SERIAL=y
64
-
CONFIG_SYS_NS16550_REG_SIZE=-4
65
57
CONFIG_USB=y
66
58
CONFIG_USB_EHCI_HCD=y
+5
-13
configs/openrd_ultimate_defconfig
+5
-13
configs/openrd_ultimate_defconfig
···
4
4
CONFIG_ARCH_CPU_INIT=y
5
5
CONFIG_SYS_THUMB_BUILD=y
6
6
CONFIG_ARCH_KIRKWOOD=y
7
+
CONFIG_SUPPORT_PASSING_ATAGS=y
8
+
CONFIG_CMDLINE_TAG=y
9
+
CONFIG_INITRD_TAG=y
7
10
CONFIG_SYS_KWD_CONFIG="board/Marvell/openrd/kwbimage.cfg"
8
11
CONFIG_TEXT_BASE=0x600000
9
12
CONFIG_NR_DRAM_BANKS=2
10
-
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000
11
13
CONFIG_TARGET_OPENRD=y
12
14
CONFIG_BOARD_IS_OPENRD_ULTIMATE=y
13
15
CONFIG_ENV_SIZE=0x20000
···
15
17
CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-openrd-ultimate"
16
18
CONFIG_SYS_LOAD_ADDR=0x800000
17
19
CONFIG_IDENT_STRING="\nOpenRD-Ultimate"
18
-
# CONFIG_SYS_MALLOC_F is not set
19
20
CONFIG_HAS_BOARD_SIZE_LIMIT=y
20
21
CONFIG_BOARD_SIZE_LIMIT=524288
22
+
CONFIG_BOOTSTD_FULL=y
21
23
CONFIG_BOOTDELAY=3
22
-
CONFIG_USE_BOOTCOMMAND=y
23
-
CONFIG_BOOTCOMMAND="${x_bootcmd_kernel}; setenv bootargs ${x_bootargs} ${x_bootargs_root}; ${x_bootcmd_usb}; bootm 0x6400000;"
24
24
CONFIG_USE_PREBOOT=y
25
25
CONFIG_LOGLEVEL=2
26
26
# CONFIG_DISPLAY_BOARDINFO is not set
···
31
31
CONFIG_CMD_NAND=y
32
32
CONFIG_CMD_USB=y
33
33
# CONFIG_CMD_SETEXPR is not set
34
-
CONFIG_CMD_DHCP=y
35
-
CONFIG_CMD_MII=y
36
-
CONFIG_CMD_PING=y
37
-
CONFIG_CMD_EXT2=y
38
-
CONFIG_CMD_FAT=y
39
-
CONFIG_CMD_JFFS2=y
40
34
CONFIG_CMD_MTDPARTS=y
41
35
CONFIG_MTDIDS_DEFAULT="nand0=nand_mtd"
42
36
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand_mtd:0x100000@0x000000(uboot),0x400000@0x100000(uImage),0x1fb00000@0x500000(rootfs)"
43
37
CONFIG_CMD_UBI=y
44
-
CONFIG_ISO_PARTITION=y
45
38
CONFIG_OF_CONTROL=y
46
39
CONFIG_ENV_OVERWRITE=y
47
40
CONFIG_ENV_IS_IN_NAND=y
48
41
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
49
42
CONFIG_NETCONSOLE=y
50
43
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
44
+
CONFIG_NET_RANDOM_ETHADDR=y
51
45
CONFIG_SYS_ATA_STRIDE=4
52
46
CONFIG_SYS_ATA_DATA_OFFSET=0x100
53
47
CONFIG_SYS_ATA_REG_OFFSET=0x100
···
60
54
CONFIG_MTD_RAW_NAND=y
61
55
CONFIG_MVGBE=y
62
56
CONFIG_MII=y
63
-
CONFIG_SYS_NS16550_SERIAL=y
64
-
CONFIG_SYS_NS16550_REG_SIZE=-4
65
57
CONFIG_USB=y
66
58
CONFIG_USB_EHCI_HCD=y
+1
drivers/serial/ns16550.c
+1
drivers/serial/ns16550.c
···
605
605
{ .compatible = "ingenic,jz4780-uart", .data = PORT_JZ4780 },
606
606
{ .compatible = "nvidia,tegra20-uart", .data = PORT_NS16550 },
607
607
{ .compatible = "snps,dw-apb-uart", .data = PORT_NS16550 },
608
+
{ .compatible = "intel,xscale-uart", .data = PORT_NS16550 },
608
609
{}
609
610
};
610
611
#endif /* OF_REAL */
-18
include/configs/openrd.h
-18
include/configs/openrd.h
···
15
15
16
16
#include "mv-common.h"
17
17
18
-
/*
19
-
* Environment variables configurations
20
-
*/
21
-
/*
22
-
* max 4k env size is enough, but in case of nand
23
-
* it has to be rounded to sector size
24
-
*/
25
-
26
-
/*
27
-
* Default environment variables
28
-
*/
29
-
30
-
#define CFG_EXTRA_ENV_SETTINGS "x_bootargs=console=ttyS0,115200 " \
31
-
CONFIG_MTDPARTS_DEFAULT " rw ubi.mtd=2,2048\0" \
32
-
"x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \
33
-
"x_bootcmd_usb=usb start\0" \
34
-
"x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0"
35
-
36
18
#endif /* _CONFIG_OPENRD_BASE_H */
+18
include/configs/pxa1908.h
+18
include/configs/pxa1908.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0+ */
2
+
/*
3
+
* Copyright (c) 2024
4
+
* Duje Mihanović <duje.mihanovic@skole.hr>
5
+
*/
6
+
7
+
#ifndef __PXA1908_H
8
+
#define __PXA1908_H
9
+
10
+
#define CFG_SYS_SDRAM_BASE 0x1000000
11
+
#define CFG_SYS_INIT_RAM_ADDR 0x10000000
12
+
#define CFG_SYS_INIT_RAM_SIZE 0x4000
13
+
#define CFG_SYS_NS16550_IER 0x40
14
+
#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
15
+
#define CFG_EXTRA_ENV_SETTINGS \
16
+
"bootcmd=bootm $prevbl_initrd_start_addr\0"
17
+
18
+
#endif