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net: gmac_rockchip: Add support for rk3128

- needs SCLK_MAC/SCLK_MAC_SRC support in clock driver

Signed-off-by: Alex Bee <knaerzche@gmail.com>

+59
+59
drivers/net/gmac_rockchip.c
··· 16 16 #include <asm/arch-rockchip/clock.h> 17 17 #include <asm/arch-rockchip/hardware.h> 18 18 #include <asm/arch-rockchip/grf_px30.h> 19 + #include <asm/arch-rockchip/grf_rk3128.h> 19 20 #include <asm/arch-rockchip/grf_rk322x.h> 20 21 #include <asm/arch-rockchip/grf_rk3288.h> 21 22 #include <asm/arch-rockchip/grf_rk3308.h> ··· 116 117 return 0; 117 118 } 118 119 120 + static int rk3128_gmac_fix_mac_speed(struct dw_eth_dev *priv) 121 + { 122 + struct rk3128_grf *grf; 123 + int clk, speed; 124 + 125 + enum { 126 + RK3128_GMAC_SPEED_MASK = BIT(10), 127 + RK3128_GMAC_SPEED_10M = 0 << 10, 128 + RK3128_GMAC_SPEED_100M = 1 << 10, 129 + RK3128_GMAC_CLK_SEL_MASK = BIT(11), 130 + RK3128_GMAC_CLK_SEL_2_5M = 0 << 11, 131 + RK3128_GMAC_CLK_SEL_25M = 1 << 11, 132 + }; 133 + 134 + switch (priv->phydev->speed) { 135 + case 10: 136 + clk = RK3128_GMAC_CLK_SEL_2_5M; 137 + speed = RK3128_GMAC_SPEED_10M; 138 + break; 139 + case 100: 140 + clk = RK3128_GMAC_CLK_SEL_25M; 141 + speed = RK3128_GMAC_SPEED_100M; 142 + break; 143 + default: 144 + debug("Unknown phy speed: %d\n", priv->phydev->speed); 145 + return -EINVAL; 146 + } 147 + 148 + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 149 + rk_clrsetreg(&grf->mac_con1, 150 + RK3128_GMAC_CLK_SEL_MASK | RK3128_GMAC_SPEED_MASK, 151 + clk | speed); 152 + 153 + return 0; 154 + } 155 + 119 156 static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv) 120 157 { 121 158 struct rk322x_grf *grf; ··· 357 394 PX30_GMAC_PHY_INTF_SEL_MASK, 358 395 PX30_GMAC_PHY_INTF_SEL_RMII); 359 396 } 397 + 398 + static void rk3128_gmac_set_to_rmii(struct gmac_rockchip_plat *pdata) 399 + { 400 + struct rk3128_grf *grf; 401 + 402 + enum { 403 + RK3128_GMAC_PHY_INTF_SEL_MASK = GENMASK(8, 6), 404 + RK3128_GMAC_PHY_INTF_SEL_RMII = BIT(14), 405 + }; 406 + 407 + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 408 + rk_clrsetreg(&grf->mac_con1, RK3128_GMAC_PHY_INTF_SEL_MASK, 409 + RK3128_GMAC_PHY_INTF_SEL_RMII); 410 + } 411 + 360 412 361 413 static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_plat *pdata) 362 414 { ··· 695 747 .set_to_rmii = px30_gmac_set_to_rmii, 696 748 }; 697 749 750 + const struct rk_gmac_ops rk3128_gmac_ops = { 751 + .fix_mac_speed = rk3128_gmac_fix_mac_speed, 752 + .set_to_rmii = rk3128_gmac_set_to_rmii, 753 + }; 754 + 698 755 const struct rk_gmac_ops rk3228_gmac_ops = { 699 756 .fix_mac_speed = rk3228_gmac_fix_mac_speed, 700 757 .set_to_rgmii = rk3228_gmac_set_to_rgmii, ··· 733 790 static const struct udevice_id rockchip_gmac_ids[] = { 734 791 { .compatible = "rockchip,px30-gmac", 735 792 .data = (ulong)&px30_gmac_ops }, 793 + { .compatible = "rockchip,rk3128-gmac", 794 + .data = (ulong)&rk3128_gmac_ops }, 736 795 { .compatible = "rockchip,rk3228-gmac", 737 796 .data = (ulong)&rk3228_gmac_ops }, 738 797 { .compatible = "rockchip,rk3288-gmac",