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Merge tag 'u-boot-dfu-20241017' of https://source.denx.de/u-boot/custodians/u-boot-dfu

u-boot-dfu-20241017

CI: https://source.denx.de/u-boot/custodians/u-boot-dfu/-/pipelines/22742

Usb Gadget:
- Fix cdns3 endpoint configuration by setting maxpacket
- Fix dwc3 cache handling when using DMA

Fastboot:
- Make AVB_VERIFY depends on FASTBOOT

Tom Rini d17661a5 9e1cd2f2

+33 -7
+1
common/Kconfig
··· 850 850 depends on LIBAVB 851 851 depends on MMC 852 852 depends on PARTITION_UUIDS 853 + depends on FASTBOOT 853 854 help 854 855 This option enables compilation of bootloader-dependent operations, 855 856 used by Android Verified Boot 2.0 library (libavb). Includes:
+8
drivers/usb/cdns3/gadget.c
··· 1637 1637 else 1638 1638 priv_ep->trb_burst_size = 16; 1639 1639 1640 + /* 1641 + * The Endpoint is configured to handle a maximum packet size of 1642 + * max_packet_size. Hence, set priv_ep->endpoint.maxpacket to 1643 + * max_packet_size. This is necessary to ensure that the TD_SIZE 1644 + * is calculated correctly in cdns3_ep_run_transfer(). 1645 + */ 1646 + priv_ep->endpoint.maxpacket = max_packet_size; 1647 + 1640 1648 ret = cdns3_ep_onchip_buffer_reserve(priv_dev, buffering + 1, 1641 1649 !!priv_ep->dir); 1642 1650 if (ret) {
+2
drivers/usb/dwc3/core.h
··· 670 670 * @ep0_trb: dma address of ep0_trb 671 671 * @ep0_usb_req: dummy req used while handling STD USB requests 672 672 * @ep0_bounce_addr: dma address of ep0_bounce 673 + * @setup_buf_addr: dma address of setup_buf 673 674 * @scratch_addr: dma address of scratchbuf 674 675 * @lock: for synchronizing 675 676 * @dev: pointer to our struct device ··· 757 758 dma_addr_t ep0_trb_addr; 758 759 dma_addr_t ep0_bounce_addr; 759 760 dma_addr_t scratch_addr; 761 + dma_addr_t setup_buf_addr; 760 762 struct dwc3_request ep0_usb_req; 761 763 762 764 /* device lock */
+4 -2
drivers/usb/dwc3/ep0.c
··· 380 380 dep = dwc->eps[0]; 381 381 dwc->ep0_usb_req.dep = dep; 382 382 dwc->ep0_usb_req.request.length = sizeof(*response_pkt); 383 - dwc->ep0_usb_req.request.buf = dwc->setup_buf; 383 + dwc->ep0_usb_req.request.buf = (void *)dwc->setup_buf_addr; 384 384 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl; 385 385 386 386 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); ··· 662 662 dep = dwc->eps[0]; 663 663 dwc->ep0_usb_req.dep = dep; 664 664 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket; 665 - dwc->ep0_usb_req.request.buf = dwc->setup_buf; 665 + dwc->ep0_usb_req.request.buf = (void *)dwc->setup_buf_addr; 666 666 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl; 667 667 668 668 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); ··· 741 741 742 742 if (!dwc->gadget_driver) 743 743 goto out; 744 + 745 + dwc3_invalidate_cache((uintptr_t)ctrl, sizeof(*ctrl)); 744 746 745 747 len = le16_to_cpu(ctrl->wLength); 746 748 if (!len) {
+6 -4
drivers/usb/dwc3/gadget.c
··· 2534 2534 while (left > 0) { 2535 2535 union dwc3_event event; 2536 2536 2537 + dwc3_invalidate_cache((uintptr_t)evt->buf, evt->length); 2538 + 2537 2539 event.raw = *(u32 *) (evt->buf + evt->lpos); 2538 2540 2539 2541 dwc3_process_event_entry(dwc, &event); ··· 2653 2655 goto err1; 2654 2656 } 2655 2657 2656 - dwc->setup_buf = memalign(CONFIG_SYS_CACHELINE_SIZE, 2657 - DWC3_EP0_BOUNCE_SIZE); 2658 + dwc->setup_buf = dma_alloc_coherent(DWC3_EP0_BOUNCE_SIZE, 2659 + (unsigned long *)&dwc->setup_buf_addr); 2658 2660 if (!dwc->setup_buf) { 2659 2661 ret = -ENOMEM; 2660 2662 goto err2; ··· 2701 2703 dma_free_coherent(dwc->ep0_bounce); 2702 2704 2703 2705 err3: 2704 - kfree(dwc->setup_buf); 2706 + dma_free_coherent(dwc->setup_buf); 2705 2707 2706 2708 err2: 2707 2709 dma_free_coherent(dwc->ep0_trb); ··· 2723 2725 2724 2726 dma_free_coherent(dwc->ep0_bounce); 2725 2727 2726 - kfree(dwc->setup_buf); 2728 + dma_free_coherent(dwc->setup_buf); 2727 2729 2728 2730 dma_free_coherent(dwc->ep0_trb); 2729 2731
+12 -1
drivers/usb/dwc3/io.h
··· 50 50 51 51 static inline void dwc3_flush_cache(uintptr_t addr, int length) 52 52 { 53 - flush_dcache_range(addr, addr + ROUND(length, CACHELINE_SIZE)); 53 + uintptr_t start_addr = (uintptr_t)addr & ~(CACHELINE_SIZE - 1); 54 + uintptr_t end_addr = ALIGN((uintptr_t)addr + length, CACHELINE_SIZE); 55 + 56 + flush_dcache_range((unsigned long)start_addr, (unsigned long)end_addr); 57 + } 58 + 59 + static inline void dwc3_invalidate_cache(uintptr_t addr, int length) 60 + { 61 + uintptr_t start_addr = (uintptr_t)addr & ~(CACHELINE_SIZE - 1); 62 + uintptr_t end_addr = ALIGN((uintptr_t)addr + length, CACHELINE_SIZE); 63 + 64 + invalidate_dcache_range((unsigned long)start_addr, (unsigned long)end_addr); 54 65 } 55 66 #endif /* __DRIVERS_USB_DWC3_IO_H */