"Das U-Boot" Source Tree
net: add Microsemi/Microchip MDIO driver
Add Microsemi/Microchip MDIO driver for interfaces found in their network
switches.
Driver is based on the Linux version.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Acked-by: Jerome Forissier <jerome@forissier.org>
authored by
Robert Marko
and committed by
Jerome Forissier
dfc39f9c
c832cd3b
+145
+8
drivers/net/Kconfig
+8
drivers/net/Kconfig
···
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This driver supports the MDIO bus of Aspeed AST2600 SOC. The driver
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currently supports Clause 22.
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config MDIO_MSCC_MIIM
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bool "Microsemi MIIM interface support"
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depends on DM_MDIO
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select REGMAP
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help
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This driver supports MDIO interface found in Microsemi and Microchip
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network switches.
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config MDIO_MUX_MMIOREG
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bool "MDIO MUX accessed as a MMIO register access"
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depends on DM_MDIO_MUX
+1
drivers/net/Makefile
+1
drivers/net/Makefile
···
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obj-$(CONFIG_MACB) += macb.o
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obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
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obj-$(CONFIG_MDIO_IPQ4019) += mdio-ipq4019.o
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obj-$(CONFIG_MDIO_MSCC_MIIM) += mdio-mscc-miim.o
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obj-$(CONFIG_MDIO_GPIO_BITBANG) += mdio_gpio.o
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obj-$(CONFIG_MDIO_MT7531_MMIO) += mdio-mt7531-mmio.o
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obj-$(CONFIG_MDIO_MUX_I2CREG) += mdio_mux_i2creg.o
+136
drivers/net/mdio-mscc-miim.c
+136
drivers/net/mdio-mscc-miim.c
···
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// SPDX-License-Identifier: GPL-2.0+
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#include <asm/io.h>
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#include <dm.h>
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#include <time.h>
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#include <regmap.h>
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#include <miiphy.h>
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#include <linux/bitfield.h>
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#define MSCC_MIIM_REG_STATUS 0x0
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#define MSCC_MIIM_STATUS_STAT_PENDING BIT(2)
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#define MSCC_MIIM_STATUS_STAT_BUSY BIT(3)
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#define MSCC_MIIM_REG_CMD 0x8
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#define MSCC_MIIM_CMD_OPR_WRITE BIT(1)
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#define MSCC_MIIM_CMD_OPR_READ BIT(2)
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#define MSCC_MIIM_CMD_WRDATA_SHIFT 4
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#define MSCC_MIIM_CMD_REGAD_SHIFT 20
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#define MSCC_MIIM_CMD_PHYAD_SHIFT 25
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#define MSCC_MIIM_CMD_VLD BIT(31)
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#define MSCC_MIIM_REG_DATA 0xC
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#define MSCC_MIIM_DATA_ERROR (BIT(16) | BIT(17))
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#define MSCC_MIIM_DATA_MASK GENMASK(15, 0)
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#define MSCC_MIIM_REG_CFG 0x10
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#define MSCC_MIIM_CFG_PRESCALE_MASK GENMASK(7, 0)
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/* 01 = Clause 22, 00 = Clause 45 */
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#define MSCC_MIIM_CFG_ST_CFG_MASK GENMASK(10, 9)
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#define MSCC_MIIM_C22 1
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#define MSCC_MIIM_C45 0
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#define MSCC_MDIO_TIMEOUT 10000
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#define MSCC_MDIO_SLEEP 50
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struct mscc_mdio_priv {
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struct regmap *map;
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};
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static int mscc_mdio_wait_busy(struct mscc_mdio_priv *priv)
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{
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u32 busy;
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return regmap_read_poll_timeout(priv->map, MSCC_MIIM_REG_STATUS, busy,
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(busy & MSCC_MIIM_STATUS_STAT_BUSY) == 0,
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MSCC_MDIO_SLEEP,
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MSCC_MDIO_TIMEOUT);
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}
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static int mscc_mdio_read(struct udevice *dev, int addr, int devad, int reg)
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{
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struct mscc_mdio_priv *priv = dev_get_priv(dev);
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u32 val;
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int ret;
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if (mscc_mdio_wait_busy(priv))
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return -ETIMEDOUT;
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ret = regmap_write(priv->map, MSCC_MIIM_REG_CMD,
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MSCC_MIIM_CMD_VLD |
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(addr << MSCC_MIIM_CMD_PHYAD_SHIFT) |
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(reg << MSCC_MIIM_CMD_REGAD_SHIFT) |
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MSCC_MIIM_CMD_OPR_READ);
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if (ret)
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return ret;
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if (mscc_mdio_wait_busy(priv))
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return -ETIMEDOUT;
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regmap_read(priv->map, MSCC_MIIM_REG_DATA, &val);
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if (val & MSCC_MIIM_DATA_ERROR)
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return -EIO;
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return FIELD_GET(MSCC_MIIM_DATA_MASK, val);
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}
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int mscc_mdio_write(struct udevice *dev, int addr, int devad, int reg, u16 val)
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{
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struct mscc_mdio_priv *priv = dev_get_priv(dev);
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int ret;
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if (mscc_mdio_wait_busy(priv))
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return -ETIMEDOUT;
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ret = regmap_write(priv->map, MSCC_MIIM_REG_CMD,
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MSCC_MIIM_CMD_VLD |
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(addr << MSCC_MIIM_CMD_PHYAD_SHIFT) |
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(reg << MSCC_MIIM_CMD_REGAD_SHIFT) |
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(val << MSCC_MIIM_CMD_WRDATA_SHIFT) |
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MSCC_MIIM_CMD_OPR_WRITE);
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return ret;
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}
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static const struct mdio_ops mscc_mdio_ops = {
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.read = mscc_mdio_read,
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.write = mscc_mdio_write,
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};
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static int mscc_mdio_bind(struct udevice *dev)
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{
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if (ofnode_valid(dev_ofnode(dev)))
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device_set_name(dev, ofnode_get_name(dev_ofnode(dev)));
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return 0;
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}
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static int mscc_mdio_probe(struct udevice *dev)
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{
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struct mscc_mdio_priv *priv = dev_get_priv(dev);
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int ret;
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ret = regmap_init_mem(dev_ofnode(dev), &priv->map);
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if (ret)
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return -EINVAL;
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/* Enter Clause 22 mode */
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ret = regmap_update_bits(priv->map, MSCC_MIIM_REG_CFG,
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MSCC_MIIM_CFG_ST_CFG_MASK,
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FIELD_PREP(MSCC_MIIM_CFG_ST_CFG_MASK,
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MSCC_MIIM_C22));
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return ret;
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}
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static const struct udevice_id mscc_mdio_ids[] = {
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{ .compatible = "mscc,ocelot-miim", },
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{ }
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};
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U_BOOT_DRIVER(mscc_mdio) = {
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.name = "mscc_mdio",
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.id = UCLASS_MDIO,
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.of_match = mscc_mdio_ids,
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.bind = mscc_mdio_bind,
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.probe = mscc_mdio_probe,
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.ops = &mscc_mdio_ops,
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.priv_auto = sizeof(struct mscc_mdio_priv),
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};