"Das U-Boot" Source Tree
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh
These are mainly DBSC5 DRAM controller specific fixes and updates for
current release. There is the long overdue BL31 start V4H board code as
well, that should be in the current release to make the V4H White Hawk
board usable with SPL, and a fallback U-Boot PSCI implementation
enablement to make sure the board always boots. And finally, there are
two comment fixes.
+258
-105
+4
arch/arm/dts/r8a779g0-u-boot.dtsi
+4
arch/arm/dts/r8a779g0-u-boot.dtsi
-2
board/renesas/common/Makefile
-2
board/renesas/common/Makefile
+126
board/renesas/common/gen4-common.c
+126
board/renesas/common/gen4-common.c
···
7
7
8
8
#include <asm/arch/renesas.h>
9
9
#include <asm/arch/sys_proto.h>
10
+
#include <asm/armv8/mmu.h>
10
11
#include <asm/global_data.h>
11
12
#include <asm/io.h>
12
13
#include <asm/mach-types.h>
13
14
#include <asm/processor.h>
14
15
#include <asm/system.h>
16
+
#include <image.h>
15
17
#include <linux/errno.h>
16
18
17
19
#define RST_BASE 0xE6160000 /* Domain0 */
···
88
90
{
89
91
return 0;
90
92
}
93
+
94
+
/* R-Car Gen4 TFA BL31 handoff structure and handling. */
95
+
struct param_header {
96
+
u8 type;
97
+
u8 version;
98
+
u16 size;
99
+
u32 attr;
100
+
};
101
+
102
+
struct tfa_image_info {
103
+
struct param_header h;
104
+
uintptr_t image_base;
105
+
u32 image_size;
106
+
u32 image_max_size;
107
+
};
108
+
109
+
struct aapcs64_params {
110
+
u64 arg0;
111
+
u64 arg1;
112
+
u64 arg2;
113
+
u64 arg3;
114
+
u64 arg4;
115
+
u64 arg5;
116
+
u64 arg6;
117
+
u64 arg7;
118
+
};
119
+
120
+
struct entry_point_info {
121
+
struct param_header h;
122
+
uintptr_t pc;
123
+
u32 spsr;
124
+
struct aapcs64_params args;
125
+
};
126
+
127
+
struct bl2_to_bl31_params_mem {
128
+
struct tfa_image_info bl32_image_info;
129
+
struct tfa_image_info bl33_image_info;
130
+
struct entry_point_info bl33_ep_info;
131
+
struct entry_point_info bl32_ep_info;
132
+
};
133
+
134
+
/* Default jump address, return to U-Boot */
135
+
#define BL33_BASE 0x44100000
136
+
/* Custom parameters address passed to TFA by ICUMXA loader */
137
+
#define PARAMS_BASE 0x46422200
138
+
139
+
/* Usually such a structure is produced by ICUMXA and passed in at 0x46422200 */
140
+
static const struct bl2_to_bl31_params_mem blinfo_template = {
141
+
.bl33_ep_info.h.type = 1, /* PARAM_EP */
142
+
.bl33_ep_info.h.version = 2, /* Version 2 */
143
+
.bl33_ep_info.h.size = sizeof(struct entry_point_info),
144
+
.bl33_ep_info.h.attr = 0x81, /* Executable | Non-Secure */
145
+
.bl33_ep_info.spsr = 0x2c9, /* Mode=EL2, SP=ELX, Exceptions=OFF */
146
+
.bl33_ep_info.pc = BL33_BASE,
147
+
148
+
.bl33_image_info.h.type = 1, /* PARAM_EP */
149
+
.bl33_image_info.h.version = 2, /* Version 2 */
150
+
.bl33_image_info.h.size = sizeof(struct image_info),
151
+
.bl33_image_info.h.attr = 0,
152
+
.bl33_image_info.image_base = BL33_BASE,
153
+
};
154
+
155
+
static bool tfa_bl31_image_loaded;
156
+
static ulong tfa_bl31_image_addr;
157
+
158
+
static void tfa_bl31_image_process(ulong image, size_t size)
159
+
{
160
+
/* Custom parameters address passed to TFA by ICUMXA loader */
161
+
struct bl2_to_bl31_params_mem *blinfo = (struct bl2_to_bl31_params_mem *)PARAMS_BASE;
162
+
163
+
/* Not in EL3, do nothing. */
164
+
if (current_el() != 3)
165
+
return;
166
+
167
+
/* Clear a page and copy template */
168
+
memset((void *)PARAMS_BASE, 0, PAGE_SIZE);
169
+
memcpy(blinfo, &blinfo_template, sizeof(*blinfo));
170
+
tfa_bl31_image_addr = image;
171
+
tfa_bl31_image_loaded = true;
172
+
}
173
+
174
+
U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TFA_BL31, tfa_bl31_image_process);
175
+
176
+
void armv8_switch_to_el2_prep(u64 args, u64 mach_nr, u64 fdt_addr,
177
+
u64 arg4, u64 entry_point, u64 es_flag)
178
+
{
179
+
typedef void __noreturn (*image_entry_noargs_t)(void);
180
+
image_entry_noargs_t image_entry =
181
+
(image_entry_noargs_t)(void *)tfa_bl31_image_addr;
182
+
struct bl2_to_bl31_params_mem *blinfo =
183
+
(struct bl2_to_bl31_params_mem *)PARAMS_BASE;
184
+
185
+
/* Not in EL3, do nothing. */
186
+
if (current_el() != 3)
187
+
return;
188
+
189
+
/*
190
+
* Destination address in arch/arm/cpu/armv8/transition.S
191
+
* right past the first bl in armv8_switch_to_el2() to let
192
+
* the rest of U-Boot pre-Linux code run. The code does run
193
+
* without stack pointer!
194
+
*/
195
+
const u64 ep = ((u64)(uintptr_t)&armv8_switch_to_el2) + 4;
196
+
197
+
/* If TFA BL31 was not part of the fitImage, do regular boot. */
198
+
if (!tfa_bl31_image_loaded)
199
+
return;
200
+
201
+
/*
202
+
* Set up kernel entry point and parameters:
203
+
* x0 is FDT address, x1..x3 must be 0
204
+
*/
205
+
blinfo->bl33_ep_info.pc = ep;
206
+
blinfo->bl33_ep_info.args.arg0 = args;
207
+
blinfo->bl33_ep_info.args.arg1 = mach_nr;
208
+
blinfo->bl33_ep_info.args.arg2 = fdt_addr;
209
+
blinfo->bl33_ep_info.args.arg3 = arg4;
210
+
blinfo->bl33_ep_info.args.arg4 = entry_point;
211
+
blinfo->bl33_ep_info.args.arg5 = es_flag;
212
+
blinfo->bl33_image_info.image_base = ep;
213
+
214
+
/* Jump to TFA BL31 */
215
+
image_entry();
216
+
}
+1
-1
board/renesas/common/gen4-spl.c
+1
-1
board/renesas/common/gen4-spl.c
+2
configs/r8a779g0_whitehawk_defconfig
+2
configs/r8a779g0_whitehawk_defconfig
+2
-1
drivers/ram/renesas/dbsc5/dbsc5.c
+2
-1
drivers/ram/renesas/dbsc5/dbsc5.c
···
59
59
60
60
struct renesas_dbsc5_data r8a779g0_dbsc5_data = {
61
61
.clock_node = "renesas,r8a779g0-cpg-mssr",
62
-
.reset_node = "renesas,r8a779g0-rst"
62
+
.reset_node = "renesas,r8a779g0-rst",
63
+
.otp_node = "renesas,r8a779g0-otp",
63
64
};
64
65
65
66
static const struct udevice_id renesas_dbsc5_ids[] = {
+1
drivers/ram/renesas/dbsc5/dbsc5.h
+1
drivers/ram/renesas/dbsc5/dbsc5.h
+66
-101
drivers/ram/renesas/dbsc5/dram.c
+66
-101
drivers/ram/renesas/dbsc5/dram.c
···
4
4
*/
5
5
6
6
#include <asm/io.h>
7
+
#include <dbsc5.h>
7
8
#include <dm.h>
8
9
#include <errno.h>
9
10
#include <hang.h>
···
11
12
#include <linux/iopoll.h>
12
13
#include <linux/sizes.h>
13
14
#include "dbsc5.h"
14
-
15
-
/* The number of channels V4H has */
16
-
#define DRAM_CH_CNT 4
17
-
/* The number of slices V4H has */
18
-
#define SLICE_CNT 2
19
-
/* The number of chip select V4H has */
20
-
#define CS_CNT 2
21
15
22
16
/* Number of array elements in Data Slice */
23
17
#define DDR_PHY_SLICE_REGSET_SIZE_V4H 0x100
···
220
214
#define PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS DDR_REGDEF(0x00, 0x09, 0x103F)
221
215
#define PHY_WDQLVL_STATUS_OBS DDR_REGDEF(0x00, 0x20, 0x1043)
222
216
#define PHY_DATA_DC_CAL_START DDR_REGDEF(0x18, 0x01, 0x104D)
217
+
#define PHY_SLV_DLY_CTRL_GATE_DISABLE DDR_REGDEF(0x10, 0x01, 0x104E)
223
218
#define PHY_REGULATOR_EN_CNT DDR_REGDEF(0x18, 0x06, 0x1050)
224
219
#define PHY_VREF_INITIAL_START_POINT DDR_REGDEF(0x00, 0x09, 0x1055)
225
220
#define PHY_VREF_INITIAL_STOP_POINT DDR_REGDEF(0x10, 0x09, 0x1055)
···
469
464
0x00000000, 0x00500050, 0x00500050, 0x00500050,
470
465
0x00500050, 0x0D000050, 0x10100004, 0x06102010,
471
466
0x61619041, 0x07097000, 0x00644180, 0x00803280,
472
-
0x00808001, 0x13010100, 0x02000016, 0x10001003,
467
+
0x00808001, 0x13010101, 0x02000016, 0x10001003,
473
468
0x06093E42, 0x0F063D01, 0x011700C8, 0x04100140,
474
469
0x00000100, 0x000001D1, 0x05000068, 0x00030402,
475
470
0x01400000, 0x80800300, 0x00160010, 0x76543210,
···
512
507
0x00040101, 0x00000000, 0x00000000, 0x00000064,
513
508
0x00000000, 0x00000000, 0x39421B42, 0x00010124,
514
509
0x00520052, 0x00000052, 0x00000000, 0x00000000,
515
-
0x00000000, 0x00000000, 0x00000000, 0x00000000,
516
-
0x00000000, 0x00000000, 0x00000000, 0x07030102,
510
+
0x00010001, 0x00000000, 0x00000000, 0x00010001,
511
+
0x00000000, 0x00000000, 0x00010001, 0x07030102,
517
512
0x01030307, 0x00000054, 0x00004096, 0x08200820,
518
513
0x08200820, 0x08200820, 0x08200820, 0x00000820,
519
514
0x004103B8, 0x0000003F, 0x000C0006, 0x00000000,
···
1294
1289
};
1295
1290
1296
1291
static const struct dbsc5_table_patch dbsc5_table_patch_adr_g_mbpsdiv_572 = {
1297
-
PHY_PAD_ACS_RX_PCLK_CLK_SEL, 0x03
1292
+
PHY_PAD_ACS_RX_PCLK_CLK_SEL, 0x02
1298
1293
};
1299
1294
1300
1295
static const struct dbsc5_table_patch dbsc5_table_patch_adr_g_mbpsdiv_400[] = {
···
1374
1369
1375
1370
#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva)))
1376
1371
1377
-
struct renesas_dbsc5_board_config {
1378
-
/* Channels in use */
1379
-
u8 bdcfg_phyvalid;
1380
-
/* Read vref (SoC) training range */
1381
-
u32 bdcfg_vref_r;
1382
-
/* Write vref (MR14, MR15) training range */
1383
-
u16 bdcfg_vref_w;
1384
-
/* CA vref (MR12) training range */
1385
-
u16 bdcfg_vref_ca;
1386
-
/* RFM required check */
1387
-
bool bdcfg_rfm_chk;
1388
-
1389
-
/* Board parameter about channels */
1390
-
struct {
1391
-
/*
1392
-
* 0x00: 4Gb dual channel die / 2Gb single channel die
1393
-
* 0x01: 6Gb dual channel die / 3Gb single channel die
1394
-
* 0x02: 8Gb dual channel die / 4Gb single channel die
1395
-
* 0x03: 12Gb dual channel die / 6Gb single channel die
1396
-
* 0x04: 16Gb dual channel die / 8Gb single channel die
1397
-
* 0x05: 24Gb dual channel die / 12Gb single channel die
1398
-
* 0x06: 32Gb dual channel die / 16Gb single channel die
1399
-
* 0x07: 24Gb single channel die
1400
-
* 0x08: 32Gb single channel die
1401
-
* 0xFF: NO_MEMORY
1402
-
*/
1403
-
u8 bdcfg_ddr_density[CS_CNT];
1404
-
/* SoC caX([6][5][4][3][2][1][0]) -> MEM caY: */
1405
-
u32 bdcfg_ca_swap;
1406
-
/* SoC dqsX([1][0]) -> MEM dqsY: */
1407
-
u8 bdcfg_dqs_swap;
1408
-
/* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm: (8 means DM) */
1409
-
u32 bdcfg_dq_swap[SLICE_CNT];
1410
-
/* SoC dm -> MEM dqY/dm: (8 means DM) */
1411
-
u8 bdcfg_dm_swap[SLICE_CNT];
1412
-
/* SoC ckeX([1][0]) -> MEM csY */
1413
-
u8 bdcfg_cs_swap;
1414
-
} ch[4];
1415
-
};
1416
-
1417
1372
struct renesas_dbsc5_dram_priv {
1418
1373
void __iomem *regs;
1419
1374
void __iomem *cpg_regs;
···
1713
1668
{
1714
1669
struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev);
1715
1670
void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET;
1716
-
u32 i, ch, reg;
1671
+
u32 i, ch, chk, reg;
1717
1672
1718
1673
for (i = 0; i < 2; i++) {
1719
1674
do {
1720
1675
reg = status;
1721
-
r_foreach_vch(dev, ch)
1676
+
chk = 0;
1677
+
r_foreach_vch(dev, ch) {
1722
1678
reg &= readl(regs_dbsc_d + DBSC_DBPDSTAT1(ch));
1723
-
} while (reg != status);
1679
+
chk |= readl(regs_dbsc_d + DBSC_DBPDSTAT0(ch));
1680
+
}
1681
+
} while (reg != status && !(chk & BIT(0)));
1724
1682
}
1725
1683
}
1726
1684
···
2192
2150
if (js1[i].fx3 * 2 * priv->ddr_mbpsdiv >= priv->ddr_mbps * 3)
2193
2151
break;
2194
2152
2195
-
priv->js1_ind = max(i, JS1_USABLEC_SPEC_HI);
2153
+
priv->js1_ind = clamp(i, 0, JS1_USABLEC_SPEC_HI);
2196
2154
2197
2155
priv->RL = js1[priv->js1_ind].RLset1;
2198
2156
priv->WL = js1[priv->js1_ind].WLsetA;
···
2635
2593
*/
2636
2594
dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(11),
2637
2595
priv->RL + 4 + priv->js2[JS2_tWCK2DQO_HF] -
2638
-
js1[priv->js1_ind].ODTLon - priv->js2[JS2_tODTon_min]);
2596
+
js1[priv->js1_ind].ODTLon - priv->js2[JS2_tODTon_min] + 2);
2639
2597
2640
2598
/* DBTR12.TWRRD_S : WL + BL/2 + tWTR_S, TWRRD_L : WL + BL + tWTR_L */
2641
2599
dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(12),
···
3491
3449
{
3492
3450
struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev);
3493
3451
const u32 rank = priv->ch_have_this_cs[1] ? 0x2 : 0x1;
3494
-
u32 slv_dly_center[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
3495
-
u32 slv_dly_center_cyc;
3496
-
u32 slv_dly_center_dly;
3452
+
u32 phy_slv_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
3453
+
u32 phy_slv_dly_avg[DRAM_CH_CNT][SLICE_CNT];
3497
3454
u32 slv_dly_min[DRAM_CH_CNT][SLICE_CNT];
3498
3455
u32 slv_dly_max[DRAM_CH_CNT][SLICE_CNT];
3499
-
u32 slv_dly_min_tmp[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
3500
-
u32 slv_dly_max_tmp[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
3501
3456
u32 phy_dcc_code_min[DRAM_CH_CNT][SLICE_CNT];
3502
3457
u32 phy_dcc_code_max[DRAM_CH_CNT][SLICE_CNT];
3503
3458
u32 phy_dcc_code_mid;
···
3521
3476
dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_PER_CS_TRAINING_INDEX, cs);
3522
3477
r_foreach_vch(dev, ch) {
3523
3478
for (slice = 0; slice < SLICE_CNT; slice++) {
3524
-
slv_dly_center[ch][cs][slice] =
3525
-
dbsc5_ddr_getval_slice(dev, ch, slice, PHY_CLK_WRDQS_SLAVE_DELAY);
3526
-
slv_dly_center_cyc = slv_dly_center[ch][cs][slice] & 0x180;
3527
-
slv_dly_center_dly = slv_dly_center[ch][cs][slice] & 0x7F;
3528
-
slv_dly_min_tmp[ch][cs][slice] =
3529
-
slv_dly_center_cyc |
3530
-
(slv_dly_center_dly * ratio_min / ratio_min_div);
3531
-
slv_dly_max_tmp[ch][cs][slice] = slv_dly_center_cyc;
3532
-
if ((slv_dly_center_dly * ratio_max) > (0x7F * ratio_max_div))
3533
-
slv_dly_max_tmp[ch][cs][slice] |= 0x7F;
3534
-
else
3535
-
slv_dly_max_tmp[ch][cs][slice] |= slv_dly_center_dly * ratio_max / ratio_max_div;
3479
+
phy_slv_dly[ch][cs][slice] =
3480
+
dbsc5_ddr_getval_slice(dev, ch, slice,
3481
+
PHY_CLK_WRDQS_SLAVE_DELAY);
3536
3482
}
3537
3483
}
3538
3484
}
···
3540
3486
r_foreach_vch(dev, ch) {
3541
3487
for (slice = 0; slice < SLICE_CNT; slice++) {
3542
3488
if (rank == 0x2) {
3543
-
if (slv_dly_max_tmp[ch][0][slice] < slv_dly_max_tmp[ch][1][slice])
3544
-
slv_dly_max[ch][slice] = slv_dly_max_tmp[ch][1][slice];
3545
-
else
3546
-
slv_dly_max[ch][slice] = slv_dly_max_tmp[ch][0][slice];
3547
-
3548
-
if (slv_dly_min_tmp[ch][0][slice] < slv_dly_min_tmp[ch][1][slice])
3549
-
slv_dly_min[ch][slice] = slv_dly_min_tmp[ch][0][slice];
3550
-
else
3551
-
slv_dly_min[ch][slice] = slv_dly_min_tmp[ch][1][slice];
3489
+
/* Calculate average between ranks */
3490
+
phy_slv_dly_avg[ch][slice] = (phy_slv_dly[ch][0][slice] +
3491
+
phy_slv_dly[ch][1][slice]) / 2;
3552
3492
} else {
3553
-
slv_dly_max[ch][slice] = slv_dly_max_tmp[ch][0][slice];
3554
-
slv_dly_min[ch][slice] = slv_dly_min_tmp[ch][0][slice];
3493
+
phy_slv_dly_avg[ch][slice] = phy_slv_dly[ch][0][slice];
3555
3494
}
3495
+
/* Determine the search range */
3496
+
slv_dly_min[ch][slice] = (phy_slv_dly_avg[ch][slice] & 0x07F) * ratio_min / ratio_min_div;
3497
+
slv_dly_max[ch][slice] = (phy_slv_dly_avg[ch][slice] & 0x07F) * ratio_max / ratio_max_div;
3498
+
if (slv_dly_max[ch][slice] > 0x7F)
3499
+
slv_dly_max[ch][slice] = 0x7F;
3556
3500
}
3557
3501
}
3502
+
3503
+
dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_SLV_DLY_CTRL_GATE_DISABLE, 0x1);
3558
3504
3559
3505
for (i = 0; i <= 0x7F; i++) {
3560
3506
r_foreach_vch(dev, ch) {
···
3621
3567
for (slice = 0; slice < SLICE_CNT; slice++) {
3622
3568
dbsc5_ddr_setval_slice(dev, ch, slice,
3623
3569
PHY_CLK_WRDQS_SLAVE_DELAY,
3624
-
slv_dly_center[ch][cs][slice]);
3570
+
phy_slv_dly[ch][cs][slice]);
3625
3571
dbsc5_ddr_setval_slice(dev, ch, slice,
3626
3572
SC_PHY_WCK_CALC, 0x1);
3627
3573
dbsc5_ddr_setval(dev, ch, SC_PHY_MANUAL_UPDATE, 0x1);
3628
3574
}
3629
3575
}
3630
3576
}
3577
+
3578
+
dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_SLV_DLY_CTRL_GATE_DISABLE, 0x0);
3579
+
3631
3580
dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_PER_CS_TRAINING_MULTICAST_EN, 0x1);
3632
3581
3633
3582
r_foreach_vch(dev, ch) {
···
4369
4318
{
4370
4319
#define RST_MODEMR0 0x0
4371
4320
#define RST_MODEMR1 0x4
4321
+
#define OTP_MONITOR17 0x1144
4372
4322
struct renesas_dbsc5_data *data = (struct renesas_dbsc5_data *)dev_get_driver_data(dev);
4373
4323
ofnode cnode = ofnode_by_compatible(ofnode_null(), data->clock_node);
4374
4324
ofnode rnode = ofnode_by_compatible(ofnode_null(), data->reset_node);
4325
+
ofnode onode = ofnode_by_compatible(ofnode_null(), data->otp_node);
4375
4326
struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev);
4376
4327
void __iomem *regs_dbsc_a = priv->regs + DBSC5_DBSC_A_OFFSET;
4377
4328
void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET;
4378
4329
phys_addr_t rregs = ofnode_get_addr(rnode);
4379
4330
const u32 modemr0 = readl(rregs + RST_MODEMR0);
4380
4331
const u32 modemr1 = readl(rregs + RST_MODEMR1);
4381
-
u32 breg, reg, md, sscg;
4332
+
phys_addr_t oregs = ofnode_get_addr(onode);
4333
+
const u32 otpmon17 = readl(oregs + OTP_MONITOR17);
4334
+
u32 breg, reg, md, sscg, product;
4382
4335
u32 ch, cs;
4383
4336
4384
4337
/* Get board data */
···
4433
4386
4434
4387
/* Decode DDR operating frequency from MD[37:36,19,17] pins */
4435
4388
md = ((modemr0 & BIT(19)) >> 18) | ((modemr0 & BIT(17)) >> 17);
4389
+
product = otpmon17 & 0xff;
4436
4390
sscg = (modemr1 >> 4) & 0x03;
4437
4391
if (sscg == 2) {
4438
4392
printf("MD[37:36] setting 0x%x not supported!", sscg);
4439
4393
hang();
4440
4394
}
4441
4395
4442
-
if (md == 0) {
4443
-
if (sscg == 0) {
4444
-
priv->ddr_mbps = 6400;
4445
-
priv->ddr_mbpsdiv = 1;
4446
-
} else {
4447
-
priv->ddr_mbps = 19000;
4448
-
priv->ddr_mbpsdiv = 3;
4449
-
}
4450
-
} else if (md == 1) {
4451
-
priv->ddr_mbps = 6000;
4452
-
priv->ddr_mbpsdiv = 1;
4453
-
} else if (md == 1) {
4454
-
priv->ddr_mbps = 5500;
4455
-
priv->ddr_mbpsdiv = 1;
4456
-
} else if (md == 1) {
4396
+
if (product == 0x2) { /* V4H-3 */
4457
4397
priv->ddr_mbps = 4800;
4458
4398
priv->ddr_mbpsdiv = 1;
4399
+
} else if (product == 0x1) { /* V4H-5 */
4400
+
if (md == 3)
4401
+
priv->ddr_mbps = 4800;
4402
+
else
4403
+
priv->ddr_mbps = 5000;
4404
+
priv->ddr_mbpsdiv = 1;
4405
+
} else { /* V4H-7 */
4406
+
if (md == 0) {
4407
+
if (sscg == 0) {
4408
+
priv->ddr_mbps = 6400;
4409
+
priv->ddr_mbpsdiv = 1;
4410
+
} else {
4411
+
priv->ddr_mbps = 19000;
4412
+
priv->ddr_mbpsdiv = 3;
4413
+
}
4414
+
} else if (md == 1) {
4415
+
priv->ddr_mbps = 6000;
4416
+
priv->ddr_mbpsdiv = 1;
4417
+
} else if (md == 2) {
4418
+
priv->ddr_mbps = 5500;
4419
+
priv->ddr_mbpsdiv = 1;
4420
+
} else if (md == 3) {
4421
+
priv->ddr_mbps = 4800;
4422
+
priv->ddr_mbpsdiv = 1;
4423
+
}
4459
4424
}
4460
4425
4461
4426
priv->ddr_mul = CLK_DIV(priv->ddr_mbps, priv->ddr_mbpsdiv * 2,
+56
include/dbsc5.h
+56
include/dbsc5.h
···
1
+
// SPDX-License-Identifier: GPL-2.0+
2
+
/*
3
+
* Copyright (C) 2024-2025 Renesas Electronics Corp.
4
+
*/
5
+
6
+
#ifndef __INCLUDE_DBSC5_H__
7
+
#define __INCLUDE_DBSC5_H__
8
+
9
+
/* The number of channels V4H has */
10
+
#define DRAM_CH_CNT 4
11
+
/* The number of slices V4H has */
12
+
#define SLICE_CNT 2
13
+
/* The number of chip select V4H has */
14
+
#define CS_CNT 2
15
+
16
+
struct renesas_dbsc5_board_config {
17
+
/* Channels in use */
18
+
u8 bdcfg_phyvalid;
19
+
/* Read vref (SoC) training range */
20
+
u32 bdcfg_vref_r;
21
+
/* Write vref (MR14, MR15) training range */
22
+
u16 bdcfg_vref_w;
23
+
/* CA vref (MR12) training range */
24
+
u16 bdcfg_vref_ca;
25
+
/* RFM required check */
26
+
bool bdcfg_rfm_chk;
27
+
28
+
/* Board parameter about channels */
29
+
struct {
30
+
/*
31
+
* 0x00: 4Gb dual channel die / 2Gb single channel die
32
+
* 0x01: 6Gb dual channel die / 3Gb single channel die
33
+
* 0x02: 8Gb dual channel die / 4Gb single channel die
34
+
* 0x03: 12Gb dual channel die / 6Gb single channel die
35
+
* 0x04: 16Gb dual channel die / 8Gb single channel die
36
+
* 0x05: 24Gb dual channel die / 12Gb single channel die
37
+
* 0x06: 32Gb dual channel die / 16Gb single channel die
38
+
* 0x07: 24Gb single channel die
39
+
* 0x08: 32Gb single channel die
40
+
* 0xFF: NO_MEMORY
41
+
*/
42
+
u8 bdcfg_ddr_density[CS_CNT];
43
+
/* SoC caX([6][5][4][3][2][1][0]) -> MEM caY: */
44
+
u32 bdcfg_ca_swap;
45
+
/* SoC dqsX([1][0]) -> MEM dqsY: */
46
+
u8 bdcfg_dqs_swap;
47
+
/* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm: (8 means DM) */
48
+
u32 bdcfg_dq_swap[SLICE_CNT];
49
+
/* SoC dm -> MEM dqY/dm: (8 means DM) */
50
+
u8 bdcfg_dm_swap[SLICE_CNT];
51
+
/* SoC ckeX([1][0]) -> MEM csY */
52
+
u8 bdcfg_cs_swap;
53
+
} ch[4];
54
+
};
55
+
56
+
#endif /* __INCLUDE_DBSC5_H__ */