A Modern GPGPU API & wip linux RDNA2+ Driver
rdna
driver
linux
gpu
amdgpu: wip compute shader dispatch
+97
-9
+86
drivers/amdgpu/cmds.cpp
+86
drivers/amdgpu/cmds.cpp
···
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#include "gpuinfo.h"
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#include "kestrel/kestrel.h"
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#include "impl.h"
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#include "amdgfxregs.h"
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#include "sid.h"
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#include <amdgpu_drm.h>
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#include "pm4_encoder.h"
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#include "sdma_encoder.h"
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#include <cstdint>
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void memset_transfer(CommandListImpl *impl, kes_gpuptr_t addr, std::size_t size, uint32_t value) {
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assert(impl->queue->type == KesQueueTypeTransfer, "memset_transfer: requires queue of Transfer type");
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not_implemented("write_timestamp: not implemented for queue type: {}", cl->queue->type);
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}
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}
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struct Shader {};
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struct DispatchInfo {
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uint32_t x;
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uint32_t y;
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uint32_t z;
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uint64_t indirect_va;
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};
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void amdgpu_emit_dispatch_packets(GpuInfo &ginfo, Pm4Encoder &enc, Shader &shader, DispatchInfo &dinfo) {
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// @todo: get this from device settings
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uint32_t dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) | S_00B800_TUNNEL_ENABLE(1);
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// @todo: support predicating
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auto predicating = false;
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// @todo: support
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auto ordered = false;
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if (ordered) {
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dispatch_initiator &= ~S_00B800_ORDER_MODE(1);
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}
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// @todo: get from shader info
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auto wave_size = 32;
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if (wave_size == 32) {
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dispatch_initiator |= S_00B800_CS_W32_EN(1);
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}
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if (dinfo.indirect_va) {
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// mesa align32 workaround not needed; only for GFX7
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enc.emit(PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) | PKT3_SHADER_TYPE_S(1));
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enc.emit(dinfo.indirect_va);
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enc.emit(dinfo.indirect_va >> 32);
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enc.emit(dispatch_initiator);
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} else {
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// @todo: load block-size into shader regs.
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// @todo: unaligned?
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enc.emit(PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) | PKT3_SHADER_TYPE_S(1));
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enc.emit(dinfo.x);
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enc.emit(dinfo.y);
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enc.emit(dinfo.z);
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enc.emit(dispatch_initiator);
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}
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}
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void amdgpu_cmd_dispatch(KesCommandList pcl, uint32_t x, uint32_t y, uint32_t z) {
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auto *cl = reinterpret_cast<CommandListImpl *>(pcl);
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assert(cl, "dispatch: command list handle invalid: {}", (void *)pcl);
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auto hw_ip_type = hw_ip_type_from_queue_type(cl->queue->type);
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Pm4Encoder enc(cl->queue->dev->info, hw_ip_type, cl->cs);
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Shader tmp{};
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DispatchInfo dinfo{
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.x = x,
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.y = y,
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.z = z,
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.indirect_va = 0
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};
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amdgpu_emit_dispatch_packets(cl->queue->dev->info, enc, tmp, dinfo);
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}
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void amdgpu_cmd_dispatch_indirect(KesCommandList pcl, uint64_t indirect_addr) {
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auto *cl = reinterpret_cast<CommandListImpl *>(pcl);
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assert(cl, "dispatch: command list handle invalid: {}", (void *)pcl);
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auto hw_ip_type = hw_ip_type_from_queue_type(cl->queue->type);
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Pm4Encoder enc(cl->queue->dev->info, hw_ip_type, cl->cs);
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Shader tmp{};
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DispatchInfo dinfo{
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.indirect_va = indirect_addr
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};
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amdgpu_emit_dispatch_packets(cl->queue->dev->info, enc, tmp, dinfo);
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}
+4
drivers/amdgpu/impl.h
+4
drivers/amdgpu/impl.h
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void amdgpu_cmd_signal_after(KesCommandList, KesStage before, kes_gpuptr_t addr, uint64_t value, KesSignal);
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void amdgpu_cmd_wait_before(KesCommandList, KesStage after, kes_gpuptr_t addr, uint64_t value, KesOp, KesHazardFlags, uint64_t mask);
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void amdgpu_cmd_dispatch(KesCommandList pcl, uint32_t x, uint32_t y, uint32_t z);
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void amdgpu_cmd_dispatch_indirect(KesCommandList pcl, uint64_t indirect_addr);
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}
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uint32_t hw_ip_type_from_queue_type(KesQueueType qt);
+2
drivers/amdgpu/interface.cpp
+2
drivers/amdgpu/interface.cpp
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fns->fn_cmd_write_timestamp = amdgpu_cmd_write_timestamp;
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fns->fn_cmd_signal_after = amdgpu_cmd_signal_after;
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fns->fn_cmd_wait_before = amdgpu_cmd_wait_before;
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fns->fn_cmd_dispatch = amdgpu_cmd_dispatch;
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fns->fn_cmd_dispatch_indirect = amdgpu_cmd_dispatch_indirect;
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}
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-6
drivers/amdgpu/pm4_encoder.cpp
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-6
drivers/amdgpu/pm4_encoder.cpp
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#include "sid.h"
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#include <amdgpu_drm.h>
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Pm4Encoder::Pm4Encoder(GpuInfo &info, uint8_t ip_type) : info(info), ip_type(ip_type) {
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Pm4Encoder::Pm4Encoder(GpuInfo &info, uint8_t ip_type, CommandStream &cs) : info(info), ip_type(ip_type), cs(cs) {
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}
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void Pm4Encoder::emit(uint32_t value) {
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buf.push_back(value);
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}
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void Pm4Encoder::emit(std::span<uint32_t> values) {
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buf.insert(buf.end(), values.begin(), values.end());
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cs.emit(value);
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}
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void Pm4Encoder::set_reg_seq(uint32_t reg, uint32_t num, uint32_t idx, uint32_t bank_offset, uint32_t bank_end, uint32_t packet, uint32_t reset_filter_cam) {
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drivers/amdgpu/pm4_encoder.h
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-3
drivers/amdgpu/pm4_encoder.h
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#include <span>
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#include <vector>
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#include "cmdstream.h"
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#include "gpuinfo.h"
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class Pm4Encoder {
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public:
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Pm4Encoder(GpuInfo &info, uint8_t ip_type);
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Pm4Encoder(GpuInfo &info, uint8_t ip_type, CommandStream &cs);
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void emit(uint32_t value);
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void emit(std::span<uint32_t> values);
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void emit_32bit_pointer(uint32_t sh_offset, uint64_t va);
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void emit_64bit_pointer(uint32_t sh_offset, uint64_t va);
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GpuInfo &info;
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uint8_t ip_type;
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CommandStream &cs;
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std::vector<uint32_t> buf;
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bool context_roll;
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};