A Modern GPGPU API & wip linux RDNA2+ Driver
rdna
driver
linux
gpu
amdgpu: example 07 now works!
+45
-33
+38
-33
drivers/amdgpu/compiler/compiler.cpp
+38
-33
drivers/amdgpu/compiler/compiler.cpp
···
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struct Compiler {
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gir::Module& mod;
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RDNA2Assembler as;
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+
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uint32_t sgpr_allocator = 6;
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uint32_t vgpr_allocator = 3;
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};
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void lower_simple(Compiler &);
···
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log("shader written to {}", filename);
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}
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std::string_view rdna2_backend_intrinsic_to_string(uint32_t intrinsic_id) {
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switch(intrinsic_id) {
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case (uint32_t)AmdIntrinsics::GlobalLoadDwordAddTID_Scale4: return "GlobalLoadDwordAddTID_Scale4";
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case (uint32_t)AmdIntrinsics::GlobalStoreDwordAddTID_Scale4: return "GlobalStoreDwordAddTID_Scale4";
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default: return "?";
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}
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}
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void rdna2_compile(gir::Module &mod, void *write_ptr, uint64_t base_addr) {
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Compiler compiler(mod);
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gir::pass_normalize(mod);
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-
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lower_simple(compiler);
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lower_memory_loads(compiler);
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gir::pass_eliminate_dead_code(mod);
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analyze_uniformity(compiler);
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gir::pass_eliminate_dead_code(mod);
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allocate_registers(compiler);
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auto txt = gir::dump_module(mod, rdna2_backend_intrinsic_to_string);
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log("\nIntermediate Representation:\n{}", txt);
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codegen(compiler);
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···
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return 0;
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}
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void allocate_registers(Compiler &cc) {
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uint32_t sgpr_start = 6;
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uint32_t vgpr_start = 3;
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// @todo: improve register allocation and also reuse non-live
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// registers.
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for (auto &inst : cc.mod.insts) {
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if (inst.meta.phys_reg != ~0u) continue;
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void allocate_sgpr(Compiler &c, gir::Inst &inst) {
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if (inst.meta.phys_reg == ~0u) {
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inst.meta.phys_reg = c.sgpr_allocator++;
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}
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}
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// @todo: additionally, some types require a kind of align/size difference
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// (flat_load_dword16 needs 4 align, 16 size).
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// find next one / seq of regs of this kind
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auto count = required_regs_for_type(inst.type);
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if (inst.meta.is_uniform) {
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inst.meta.phys_reg = sgpr_start;
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sgpr_start += count;
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} else {
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inst.meta.phys_reg = vgpr_start;
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vgpr_start += count;
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}
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void allocate_vgpr(Compiler &c, gir::Inst &inst) {
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if (inst.meta.phys_reg == ~0u) {
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inst.meta.phys_reg = c.sgpr_allocator++;
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}
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}
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···
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if (imm == -1) return RDNA2Assembler::vsrc::int_neg_1;
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if (imm >= 1 && imm <= 64) return (RDNA2Assembler::vsrc)((uint)RDNA2Assembler::vsrc::int_pos_1 + imm - 1);
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if (imm < 0 && imm >= -16) return (RDNA2Assembler::vsrc)((uint)RDNA2Assembler::vsrc::int_neg_1 - imm - 1);
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// @todo: this needs to be additionally added after the
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return RDNA2Assembler::vsrc::literal_constant;
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}
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auto reg = inst.meta.phys_reg;
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if (inst.meta.is_uniform) {
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return (RDNA2Assembler::vsrc)((uint)RDNA2Assembler::vsrc::sgpr0 + reg);
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allocate_sgpr(c, inst);
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return (RDNA2Assembler::vsrc)((uint)RDNA2Assembler::vsrc::sgpr0 + inst.meta.phys_reg);
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} else {
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return (RDNA2Assembler::vsrc)((uint)RDNA2Assembler::vsrc::vgpr0 + reg);
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allocate_vgpr(c, inst);
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return (RDNA2Assembler::vsrc)((uint)RDNA2Assembler::vsrc::vgpr0 + inst.meta.phys_reg);
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}
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}
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···
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}
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assert(inst.meta.is_uniform, "Cannot use non-uniform value as ssrc");
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allocate_sgpr(c, inst);
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return (RDNA2Assembler::ssrc)((uint)RDNA2Assembler::ssrc::sgpr0 + inst.meta.phys_reg);
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}
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···
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case (uint32_t)AmdIntrinsics::GlobalLoadDwordAddTID_Scale4: {
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auto saddr = get_ssrc(cc, inst.operands[0]);
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allocate_vgpr(cc, inst);
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// @todo: how do we know what to do about the cache flags?
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cc.as.global(
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RDNA2Assembler::global_opcode::global_load_dword_addtid,
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false, false, false, false,
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0, // 12-bit immediate offset (0 for now)
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0, // vaddr (0 = use addtid mode)
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(uint8_t)saddr, // saddr base pointer
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inst.meta.phys_reg, // vdst destination register
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0 // unused in addtid mode
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0,
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inst.meta.phys_reg,
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(uint8_t)saddr,
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0,
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0
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);
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// @todo: wait for load to complete. this is very conservative
···
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case gir::Op::Add: {
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if (inst.type == gir::Type::I32) {
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if (inst.meta.is_uniform) {
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// Scalar add: s_add_u32
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allocate_sgpr(cc, inst);
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auto src0 = get_ssrc(cc, inst.operands[0]);
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auto src1 = get_ssrc(cc, inst.operands[1]);
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cc.as.sop2(
···
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src1
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);
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} else {
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// Vector add: v_add_nc_u32 (non-carry version)
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allocate_vgpr(cc, inst);
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// vsrc1 MUST be a VGPR, src0 can be anything (SGPR, VGPR, const)
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auto& op0 = cc.mod.deref(inst.operands[0]);
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auto& op1 = cc.mod.deref(inst.operands[1]);
+7
test/examples/07_hello_dispatch/hello_dispatch.cpp
+7
test/examples/07_hello_dispatch/hello_dispatch.cpp
···
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printf("x[2]: %u\n", ((uint32_t *)x.cpu)[2]);
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printf("x[3]: %u\n", ((uint32_t *)x.cpu)[3]);
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sleep(1);
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printf("x[0]: %u\n", ((uint32_t *)x.cpu)[0]);
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printf("x[1]: %u\n", ((uint32_t *)x.cpu)[1]);
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printf("x[2]: %u\n", ((uint32_t *)x.cpu)[2]);
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printf("x[3]: %u\n", ((uint32_t *)x.cpu)[3]);
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return 0;
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}