Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2017-2026 NVIDIA CORPORATION. All rights reserved.
4 */
5
6#include <linux/io.h>
7#include <linux/iommu.h>
8#include <linux/module.h>
9#include <linux/mod_devicetable.h>
10#include <linux/of.h>
11#include <linux/of_platform.h>
12#include <linux/platform_device.h>
13
14#include <soc/tegra/mc.h>
15
16#if defined(CONFIG_ARCH_TEGRA_186_SOC)
17#include <dt-bindings/memory/tegra186-mc.h>
18#endif
19
20#include "mc.h"
21
22#define MC_SID_STREAMID_OVERRIDE_MASK GENMASK(7, 0)
23#define MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED BIT(16)
24#define MC_SID_STREAMID_SECURITY_OVERRIDE BIT(8)
25
26static int tegra186_mc_probe(struct tegra_mc *mc)
27{
28 struct platform_device *pdev = to_platform_device(mc->dev);
29 struct resource *res;
30 unsigned int i;
31 char name[8];
32 int err;
33
34 /*
35 * From Tegra264, the SID region is not present in MC node and BROADCAST is first.
36 * The common function 'tegra_mc_probe()' already maps first region entry from DT.
37 * Check if the SID region is present in DT then map BROADCAST. Otherwise, consider
38 * the first entry mapped in mc probe as the BROADCAST region. This is done to avoid
39 * mapping the region twice when SID is not present and keep backward compatibility.
40 */
41 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sid");
42 if (res)
43 mc->bcast_ch_regs = devm_platform_ioremap_resource_byname(pdev, "broadcast");
44 else
45 mc->bcast_ch_regs = mc->regs;
46
47 if (IS_ERR(mc->bcast_ch_regs)) {
48 if (PTR_ERR(mc->bcast_ch_regs) == -EINVAL) {
49 dev_warn(&pdev->dev,
50 "Broadcast channel is missing, please update your device-tree\n");
51 mc->bcast_ch_regs = NULL;
52 goto populate;
53 }
54
55 return PTR_ERR(mc->bcast_ch_regs);
56 }
57
58 mc->ch_regs = devm_kcalloc(mc->dev, mc->soc->num_channels, sizeof(*mc->ch_regs),
59 GFP_KERNEL);
60 if (!mc->ch_regs)
61 return -ENOMEM;
62
63 for (i = 0; i < mc->soc->num_channels; i++) {
64 snprintf(name, sizeof(name), "ch%u", i);
65
66 mc->ch_regs[i] = devm_platform_ioremap_resource_byname(pdev, name);
67 if (IS_ERR(mc->ch_regs[i]))
68 return PTR_ERR(mc->ch_regs[i]);
69 }
70
71populate:
72 err = of_platform_populate(mc->dev->of_node, NULL, NULL, mc->dev);
73 if (err < 0)
74 return err;
75
76 return 0;
77}
78
79static void tegra186_mc_remove(struct tegra_mc *mc)
80{
81 of_platform_depopulate(mc->dev);
82}
83
84#if IS_ENABLED(CONFIG_IOMMU_API)
85static void tegra186_mc_client_sid_override(struct tegra_mc *mc,
86 const struct tegra_mc_client *client,
87 unsigned int sid)
88{
89 u32 value, old;
90
91 if (client->regs.sid.security == 0 && client->regs.sid.override == 0)
92 return;
93
94 value = readl(mc->regs + client->regs.sid.security);
95 if ((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0) {
96 /*
97 * If the secure firmware has locked this down the override
98 * for this memory client, there's nothing we can do here.
99 */
100 if (value & MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED)
101 return;
102
103 /*
104 * Otherwise, try to set the override itself. Typically the
105 * secure firmware will never have set this configuration.
106 * Instead, it will either have disabled write access to
107 * this field, or it will already have set an explicit
108 * override itself.
109 */
110 WARN_ON((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0);
111
112 value |= MC_SID_STREAMID_SECURITY_OVERRIDE;
113 writel(value, mc->regs + client->regs.sid.security);
114 }
115
116 value = readl(mc->regs + client->regs.sid.override);
117 old = value & MC_SID_STREAMID_OVERRIDE_MASK;
118
119 if (old != sid) {
120 dev_dbg(mc->dev, "overriding SID %x for %s with %x\n", old,
121 client->name, sid);
122 writel(sid, mc->regs + client->regs.sid.override);
123 }
124}
125#endif
126
127static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev)
128{
129#if IS_ENABLED(CONFIG_IOMMU_API)
130 struct of_phandle_args args;
131 unsigned int i, index = 0;
132 u32 sid;
133
134 if (!tegra_dev_iommu_get_stream_id(dev, &sid))
135 return 0;
136
137 while (!of_parse_phandle_with_args(dev->of_node, "interconnects", "#interconnect-cells",
138 index, &args)) {
139 if (args.np == mc->dev->of_node && args.args_count != 0) {
140 for (i = 0; i < mc->soc->num_clients; i++) {
141 const struct tegra_mc_client *client = &mc->soc->clients[i];
142
143 if (client->id == args.args[0])
144 tegra186_mc_client_sid_override(
145 mc, client,
146 sid & MC_SID_STREAMID_OVERRIDE_MASK);
147 }
148 }
149
150 index++;
151 }
152#endif
153
154 return 0;
155}
156
157static int tegra186_mc_resume(struct tegra_mc *mc)
158{
159#if IS_ENABLED(CONFIG_IOMMU_API)
160 unsigned int i;
161
162 for (i = 0; i < mc->soc->num_clients; i++) {
163 const struct tegra_mc_client *client = &mc->soc->clients[i];
164
165 tegra186_mc_client_sid_override(mc, client, client->sid);
166 }
167#endif
168
169 return 0;
170}
171
172const struct tegra_mc_ops tegra186_mc_ops = {
173 .probe = tegra186_mc_probe,
174 .remove = tegra186_mc_remove,
175 .resume = tegra186_mc_resume,
176 .probe_device = tegra186_mc_probe_device,
177};
178
179#if defined(CONFIG_ARCH_TEGRA_186_SOC)
180static const struct tegra_mc_client tegra186_mc_clients[] = {
181 {
182 .id = TEGRA186_MEMORY_CLIENT_PTCR,
183 .name = "ptcr",
184 .sid = TEGRA186_SID_PASSTHROUGH,
185 .regs = {
186 .sid = {
187 .override = 0x000,
188 .security = 0x004,
189 },
190 },
191 }, {
192 .id = TEGRA186_MEMORY_CLIENT_AFIR,
193 .name = "afir",
194 .sid = TEGRA186_SID_AFI,
195 .regs = {
196 .sid = {
197 .override = 0x070,
198 .security = 0x074,
199 },
200 },
201 }, {
202 .id = TEGRA186_MEMORY_CLIENT_HDAR,
203 .name = "hdar",
204 .sid = TEGRA186_SID_HDA,
205 .regs = {
206 .sid = {
207 .override = 0x0a8,
208 .security = 0x0ac,
209 },
210 },
211 }, {
212 .id = TEGRA186_MEMORY_CLIENT_HOST1XDMAR,
213 .name = "host1xdmar",
214 .sid = TEGRA186_SID_HOST1X,
215 .regs = {
216 .sid = {
217 .override = 0x0b0,
218 .security = 0x0b4,
219 },
220 },
221 }, {
222 .id = TEGRA186_MEMORY_CLIENT_NVENCSRD,
223 .name = "nvencsrd",
224 .sid = TEGRA186_SID_NVENC,
225 .regs = {
226 .sid = {
227 .override = 0x0e0,
228 .security = 0x0e4,
229 },
230 },
231 }, {
232 .id = TEGRA186_MEMORY_CLIENT_SATAR,
233 .name = "satar",
234 .sid = TEGRA186_SID_SATA,
235 .regs = {
236 .sid = {
237 .override = 0x0f8,
238 .security = 0x0fc,
239 },
240 },
241 }, {
242 .id = TEGRA186_MEMORY_CLIENT_MPCORER,
243 .name = "mpcorer",
244 .sid = TEGRA186_SID_PASSTHROUGH,
245 .regs = {
246 .sid = {
247 .override = 0x138,
248 .security = 0x13c,
249 },
250 },
251 }, {
252 .id = TEGRA186_MEMORY_CLIENT_NVENCSWR,
253 .name = "nvencswr",
254 .sid = TEGRA186_SID_NVENC,
255 .regs = {
256 .sid = {
257 .override = 0x158,
258 .security = 0x15c,
259 },
260 },
261 }, {
262 .id = TEGRA186_MEMORY_CLIENT_AFIW,
263 .name = "afiw",
264 .sid = TEGRA186_SID_AFI,
265 .regs = {
266 .sid = {
267 .override = 0x188,
268 .security = 0x18c,
269 },
270 },
271 }, {
272 .id = TEGRA186_MEMORY_CLIENT_HDAW,
273 .name = "hdaw",
274 .sid = TEGRA186_SID_HDA,
275 .regs = {
276 .sid = {
277 .override = 0x1a8,
278 .security = 0x1ac,
279 },
280 },
281 }, {
282 .id = TEGRA186_MEMORY_CLIENT_MPCOREW,
283 .name = "mpcorew",
284 .sid = TEGRA186_SID_PASSTHROUGH,
285 .regs = {
286 .sid = {
287 .override = 0x1c8,
288 .security = 0x1cc,
289 },
290 },
291 }, {
292 .id = TEGRA186_MEMORY_CLIENT_SATAW,
293 .name = "sataw",
294 .sid = TEGRA186_SID_SATA,
295 .regs = {
296 .sid = {
297 .override = 0x1e8,
298 .security = 0x1ec,
299 },
300 },
301 }, {
302 .id = TEGRA186_MEMORY_CLIENT_ISPRA,
303 .name = "ispra",
304 .sid = TEGRA186_SID_ISP,
305 .regs = {
306 .sid = {
307 .override = 0x220,
308 .security = 0x224,
309 },
310 },
311 }, {
312 .id = TEGRA186_MEMORY_CLIENT_ISPWA,
313 .name = "ispwa",
314 .sid = TEGRA186_SID_ISP,
315 .regs = {
316 .sid = {
317 .override = 0x230,
318 .security = 0x234,
319 },
320 },
321 }, {
322 .id = TEGRA186_MEMORY_CLIENT_ISPWB,
323 .name = "ispwb",
324 .sid = TEGRA186_SID_ISP,
325 .regs = {
326 .sid = {
327 .override = 0x238,
328 .security = 0x23c,
329 },
330 },
331 }, {
332 .id = TEGRA186_MEMORY_CLIENT_XUSB_HOSTR,
333 .name = "xusb_hostr",
334 .sid = TEGRA186_SID_XUSB_HOST,
335 .regs = {
336 .sid = {
337 .override = 0x250,
338 .security = 0x254,
339 },
340 },
341 }, {
342 .id = TEGRA186_MEMORY_CLIENT_XUSB_HOSTW,
343 .name = "xusb_hostw",
344 .sid = TEGRA186_SID_XUSB_HOST,
345 .regs = {
346 .sid = {
347 .override = 0x258,
348 .security = 0x25c,
349 },
350 },
351 }, {
352 .id = TEGRA186_MEMORY_CLIENT_XUSB_DEVR,
353 .name = "xusb_devr",
354 .sid = TEGRA186_SID_XUSB_DEV,
355 .regs = {
356 .sid = {
357 .override = 0x260,
358 .security = 0x264,
359 },
360 },
361 }, {
362 .id = TEGRA186_MEMORY_CLIENT_XUSB_DEVW,
363 .name = "xusb_devw",
364 .sid = TEGRA186_SID_XUSB_DEV,
365 .regs = {
366 .sid = {
367 .override = 0x268,
368 .security = 0x26c,
369 },
370 },
371 }, {
372 .id = TEGRA186_MEMORY_CLIENT_TSECSRD,
373 .name = "tsecsrd",
374 .sid = TEGRA186_SID_TSEC,
375 .regs = {
376 .sid = {
377 .override = 0x2a0,
378 .security = 0x2a4,
379 },
380 },
381 }, {
382 .id = TEGRA186_MEMORY_CLIENT_TSECSWR,
383 .name = "tsecswr",
384 .sid = TEGRA186_SID_TSEC,
385 .regs = {
386 .sid = {
387 .override = 0x2a8,
388 .security = 0x2ac,
389 },
390 },
391 }, {
392 .id = TEGRA186_MEMORY_CLIENT_GPUSRD,
393 .name = "gpusrd",
394 .sid = TEGRA186_SID_GPU,
395 .regs = {
396 .sid = {
397 .override = 0x2c0,
398 .security = 0x2c4,
399 },
400 },
401 }, {
402 .id = TEGRA186_MEMORY_CLIENT_GPUSWR,
403 .name = "gpuswr",
404 .sid = TEGRA186_SID_GPU,
405 .regs = {
406 .sid = {
407 .override = 0x2c8,
408 .security = 0x2cc,
409 },
410 },
411 }, {
412 .id = TEGRA186_MEMORY_CLIENT_SDMMCRA,
413 .name = "sdmmcra",
414 .sid = TEGRA186_SID_SDMMC1,
415 .regs = {
416 .sid = {
417 .override = 0x300,
418 .security = 0x304,
419 },
420 },
421 }, {
422 .id = TEGRA186_MEMORY_CLIENT_SDMMCRAA,
423 .name = "sdmmcraa",
424 .sid = TEGRA186_SID_SDMMC2,
425 .regs = {
426 .sid = {
427 .override = 0x308,
428 .security = 0x30c,
429 },
430 },
431 }, {
432 .id = TEGRA186_MEMORY_CLIENT_SDMMCR,
433 .name = "sdmmcr",
434 .sid = TEGRA186_SID_SDMMC3,
435 .regs = {
436 .sid = {
437 .override = 0x310,
438 .security = 0x314,
439 },
440 },
441 }, {
442 .id = TEGRA186_MEMORY_CLIENT_SDMMCRAB,
443 .name = "sdmmcrab",
444 .sid = TEGRA186_SID_SDMMC4,
445 .regs = {
446 .sid = {
447 .override = 0x318,
448 .security = 0x31c,
449 },
450 },
451 }, {
452 .id = TEGRA186_MEMORY_CLIENT_SDMMCWA,
453 .name = "sdmmcwa",
454 .sid = TEGRA186_SID_SDMMC1,
455 .regs = {
456 .sid = {
457 .override = 0x320,
458 .security = 0x324,
459 },
460 },
461 }, {
462 .id = TEGRA186_MEMORY_CLIENT_SDMMCWAA,
463 .name = "sdmmcwaa",
464 .sid = TEGRA186_SID_SDMMC2,
465 .regs = {
466 .sid = {
467 .override = 0x328,
468 .security = 0x32c,
469 },
470 },
471 }, {
472 .id = TEGRA186_MEMORY_CLIENT_SDMMCW,
473 .name = "sdmmcw",
474 .sid = TEGRA186_SID_SDMMC3,
475 .regs = {
476 .sid = {
477 .override = 0x330,
478 .security = 0x334,
479 },
480 },
481 }, {
482 .id = TEGRA186_MEMORY_CLIENT_SDMMCWAB,
483 .name = "sdmmcwab",
484 .sid = TEGRA186_SID_SDMMC4,
485 .regs = {
486 .sid = {
487 .override = 0x338,
488 .security = 0x33c,
489 },
490 },
491 }, {
492 .id = TEGRA186_MEMORY_CLIENT_VICSRD,
493 .name = "vicsrd",
494 .sid = TEGRA186_SID_VIC,
495 .regs = {
496 .sid = {
497 .override = 0x360,
498 .security = 0x364,
499 },
500 },
501 }, {
502 .id = TEGRA186_MEMORY_CLIENT_VICSWR,
503 .name = "vicswr",
504 .sid = TEGRA186_SID_VIC,
505 .regs = {
506 .sid = {
507 .override = 0x368,
508 .security = 0x36c,
509 },
510 },
511 }, {
512 .id = TEGRA186_MEMORY_CLIENT_VIW,
513 .name = "viw",
514 .sid = TEGRA186_SID_VI,
515 .regs = {
516 .sid = {
517 .override = 0x390,
518 .security = 0x394,
519 },
520 },
521 }, {
522 .id = TEGRA186_MEMORY_CLIENT_NVDECSRD,
523 .name = "nvdecsrd",
524 .sid = TEGRA186_SID_NVDEC,
525 .regs = {
526 .sid = {
527 .override = 0x3c0,
528 .security = 0x3c4,
529 },
530 },
531 }, {
532 .id = TEGRA186_MEMORY_CLIENT_NVDECSWR,
533 .name = "nvdecswr",
534 .sid = TEGRA186_SID_NVDEC,
535 .regs = {
536 .sid = {
537 .override = 0x3c8,
538 .security = 0x3cc,
539 },
540 },
541 }, {
542 .id = TEGRA186_MEMORY_CLIENT_APER,
543 .name = "aper",
544 .sid = TEGRA186_SID_APE,
545 .regs = {
546 .sid = {
547 .override = 0x3d0,
548 .security = 0x3d4,
549 },
550 },
551 }, {
552 .id = TEGRA186_MEMORY_CLIENT_APEW,
553 .name = "apew",
554 .sid = TEGRA186_SID_APE,
555 .regs = {
556 .sid = {
557 .override = 0x3d8,
558 .security = 0x3dc,
559 },
560 },
561 }, {
562 .id = TEGRA186_MEMORY_CLIENT_NVJPGSRD,
563 .name = "nvjpgsrd",
564 .sid = TEGRA186_SID_NVJPG,
565 .regs = {
566 .sid = {
567 .override = 0x3f0,
568 .security = 0x3f4,
569 },
570 },
571 }, {
572 .id = TEGRA186_MEMORY_CLIENT_NVJPGSWR,
573 .name = "nvjpgswr",
574 .sid = TEGRA186_SID_NVJPG,
575 .regs = {
576 .sid = {
577 .override = 0x3f8,
578 .security = 0x3fc,
579 },
580 },
581 }, {
582 .id = TEGRA186_MEMORY_CLIENT_SESRD,
583 .name = "sesrd",
584 .sid = TEGRA186_SID_SE,
585 .regs = {
586 .sid = {
587 .override = 0x400,
588 .security = 0x404,
589 },
590 },
591 }, {
592 .id = TEGRA186_MEMORY_CLIENT_SESWR,
593 .name = "seswr",
594 .sid = TEGRA186_SID_SE,
595 .regs = {
596 .sid = {
597 .override = 0x408,
598 .security = 0x40c,
599 },
600 },
601 }, {
602 .id = TEGRA186_MEMORY_CLIENT_ETRR,
603 .name = "etrr",
604 .sid = TEGRA186_SID_ETR,
605 .regs = {
606 .sid = {
607 .override = 0x420,
608 .security = 0x424,
609 },
610 },
611 }, {
612 .id = TEGRA186_MEMORY_CLIENT_ETRW,
613 .name = "etrw",
614 .sid = TEGRA186_SID_ETR,
615 .regs = {
616 .sid = {
617 .override = 0x428,
618 .security = 0x42c,
619 },
620 },
621 }, {
622 .id = TEGRA186_MEMORY_CLIENT_TSECSRDB,
623 .name = "tsecsrdb",
624 .sid = TEGRA186_SID_TSECB,
625 .regs = {
626 .sid = {
627 .override = 0x430,
628 .security = 0x434,
629 },
630 },
631 }, {
632 .id = TEGRA186_MEMORY_CLIENT_TSECSWRB,
633 .name = "tsecswrb",
634 .sid = TEGRA186_SID_TSECB,
635 .regs = {
636 .sid = {
637 .override = 0x438,
638 .security = 0x43c,
639 },
640 },
641 }, {
642 .id = TEGRA186_MEMORY_CLIENT_GPUSRD2,
643 .name = "gpusrd2",
644 .sid = TEGRA186_SID_GPU,
645 .regs = {
646 .sid = {
647 .override = 0x440,
648 .security = 0x444,
649 },
650 },
651 }, {
652 .id = TEGRA186_MEMORY_CLIENT_GPUSWR2,
653 .name = "gpuswr2",
654 .sid = TEGRA186_SID_GPU,
655 .regs = {
656 .sid = {
657 .override = 0x448,
658 .security = 0x44c,
659 },
660 },
661 }, {
662 .id = TEGRA186_MEMORY_CLIENT_AXISR,
663 .name = "axisr",
664 .sid = TEGRA186_SID_GPCDMA_0,
665 .regs = {
666 .sid = {
667 .override = 0x460,
668 .security = 0x464,
669 },
670 },
671 }, {
672 .id = TEGRA186_MEMORY_CLIENT_AXISW,
673 .name = "axisw",
674 .sid = TEGRA186_SID_GPCDMA_0,
675 .regs = {
676 .sid = {
677 .override = 0x468,
678 .security = 0x46c,
679 },
680 },
681 }, {
682 .id = TEGRA186_MEMORY_CLIENT_EQOSR,
683 .name = "eqosr",
684 .sid = TEGRA186_SID_EQOS,
685 .regs = {
686 .sid = {
687 .override = 0x470,
688 .security = 0x474,
689 },
690 },
691 }, {
692 .id = TEGRA186_MEMORY_CLIENT_EQOSW,
693 .name = "eqosw",
694 .sid = TEGRA186_SID_EQOS,
695 .regs = {
696 .sid = {
697 .override = 0x478,
698 .security = 0x47c,
699 },
700 },
701 }, {
702 .id = TEGRA186_MEMORY_CLIENT_UFSHCR,
703 .name = "ufshcr",
704 .sid = TEGRA186_SID_UFSHC,
705 .regs = {
706 .sid = {
707 .override = 0x480,
708 .security = 0x484,
709 },
710 },
711 }, {
712 .id = TEGRA186_MEMORY_CLIENT_UFSHCW,
713 .name = "ufshcw",
714 .sid = TEGRA186_SID_UFSHC,
715 .regs = {
716 .sid = {
717 .override = 0x488,
718 .security = 0x48c,
719 },
720 },
721 }, {
722 .id = TEGRA186_MEMORY_CLIENT_NVDISPLAYR,
723 .name = "nvdisplayr",
724 .sid = TEGRA186_SID_NVDISPLAY,
725 .regs = {
726 .sid = {
727 .override = 0x490,
728 .security = 0x494,
729 },
730 },
731 }, {
732 .id = TEGRA186_MEMORY_CLIENT_BPMPR,
733 .name = "bpmpr",
734 .sid = TEGRA186_SID_BPMP,
735 .regs = {
736 .sid = {
737 .override = 0x498,
738 .security = 0x49c,
739 },
740 },
741 }, {
742 .id = TEGRA186_MEMORY_CLIENT_BPMPW,
743 .name = "bpmpw",
744 .sid = TEGRA186_SID_BPMP,
745 .regs = {
746 .sid = {
747 .override = 0x4a0,
748 .security = 0x4a4,
749 },
750 },
751 }, {
752 .id = TEGRA186_MEMORY_CLIENT_BPMPDMAR,
753 .name = "bpmpdmar",
754 .sid = TEGRA186_SID_BPMP,
755 .regs = {
756 .sid = {
757 .override = 0x4a8,
758 .security = 0x4ac,
759 },
760 },
761 }, {
762 .id = TEGRA186_MEMORY_CLIENT_BPMPDMAW,
763 .name = "bpmpdmaw",
764 .sid = TEGRA186_SID_BPMP,
765 .regs = {
766 .sid = {
767 .override = 0x4b0,
768 .security = 0x4b4,
769 },
770 },
771 }, {
772 .id = TEGRA186_MEMORY_CLIENT_AONR,
773 .name = "aonr",
774 .sid = TEGRA186_SID_AON,
775 .regs = {
776 .sid = {
777 .override = 0x4b8,
778 .security = 0x4bc,
779 },
780 },
781 }, {
782 .id = TEGRA186_MEMORY_CLIENT_AONW,
783 .name = "aonw",
784 .sid = TEGRA186_SID_AON,
785 .regs = {
786 .sid = {
787 .override = 0x4c0,
788 .security = 0x4c4,
789 },
790 },
791 }, {
792 .id = TEGRA186_MEMORY_CLIENT_AONDMAR,
793 .name = "aondmar",
794 .sid = TEGRA186_SID_AON,
795 .regs = {
796 .sid = {
797 .override = 0x4c8,
798 .security = 0x4cc,
799 },
800 },
801 }, {
802 .id = TEGRA186_MEMORY_CLIENT_AONDMAW,
803 .name = "aondmaw",
804 .sid = TEGRA186_SID_AON,
805 .regs = {
806 .sid = {
807 .override = 0x4d0,
808 .security = 0x4d4,
809 },
810 },
811 }, {
812 .id = TEGRA186_MEMORY_CLIENT_SCER,
813 .name = "scer",
814 .sid = TEGRA186_SID_SCE,
815 .regs = {
816 .sid = {
817 .override = 0x4d8,
818 .security = 0x4dc,
819 },
820 },
821 }, {
822 .id = TEGRA186_MEMORY_CLIENT_SCEW,
823 .name = "scew",
824 .sid = TEGRA186_SID_SCE,
825 .regs = {
826 .sid = {
827 .override = 0x4e0,
828 .security = 0x4e4,
829 },
830 },
831 }, {
832 .id = TEGRA186_MEMORY_CLIENT_SCEDMAR,
833 .name = "scedmar",
834 .sid = TEGRA186_SID_SCE,
835 .regs = {
836 .sid = {
837 .override = 0x4e8,
838 .security = 0x4ec,
839 },
840 },
841 }, {
842 .id = TEGRA186_MEMORY_CLIENT_SCEDMAW,
843 .name = "scedmaw",
844 .sid = TEGRA186_SID_SCE,
845 .regs = {
846 .sid = {
847 .override = 0x4f0,
848 .security = 0x4f4,
849 },
850 },
851 }, {
852 .id = TEGRA186_MEMORY_CLIENT_APEDMAR,
853 .name = "apedmar",
854 .sid = TEGRA186_SID_APE,
855 .regs = {
856 .sid = {
857 .override = 0x4f8,
858 .security = 0x4fc,
859 },
860 },
861 }, {
862 .id = TEGRA186_MEMORY_CLIENT_APEDMAW,
863 .name = "apedmaw",
864 .sid = TEGRA186_SID_APE,
865 .regs = {
866 .sid = {
867 .override = 0x500,
868 .security = 0x504,
869 },
870 },
871 }, {
872 .id = TEGRA186_MEMORY_CLIENT_NVDISPLAYR1,
873 .name = "nvdisplayr1",
874 .sid = TEGRA186_SID_NVDISPLAY,
875 .regs = {
876 .sid = {
877 .override = 0x508,
878 .security = 0x50c,
879 },
880 },
881 }, {
882 .id = TEGRA186_MEMORY_CLIENT_VICSRD1,
883 .name = "vicsrd1",
884 .sid = TEGRA186_SID_VIC,
885 .regs = {
886 .sid = {
887 .override = 0x510,
888 .security = 0x514,
889 },
890 },
891 }, {
892 .id = TEGRA186_MEMORY_CLIENT_NVDECSRD1,
893 .name = "nvdecsrd1",
894 .sid = TEGRA186_SID_NVDEC,
895 .regs = {
896 .sid = {
897 .override = 0x518,
898 .security = 0x51c,
899 },
900 },
901 },
902};
903
904static const struct tegra_mc_intmask tegra186_mc_intmasks[] = {
905 {
906 .reg = MC_INTMASK,
907 .mask = MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
908 MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
909 MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
910 },
911};
912
913const struct tegra_mc_soc tegra186_mc_soc = {
914 .num_clients = ARRAY_SIZE(tegra186_mc_clients),
915 .clients = tegra186_mc_clients,
916 .num_address_bits = 40,
917 .num_channels = 4,
918 .client_id_mask = 0xff,
919 .intmasks = tegra186_mc_intmasks,
920 .num_intmasks = ARRAY_SIZE(tegra186_mc_intmasks),
921 .ops = &tegra186_mc_ops,
922 .ch_intmask = 0x0000000f,
923 .global_intstatus_channel_shift = 0,
924 .regs = &tegra20_mc_regs,
925 .handle_irq = tegra30_mc_irq_handlers,
926 .num_interrupts = ARRAY_SIZE(tegra30_mc_irq_handlers),
927 .mc_addr_hi_mask = 0x3,
928 .mc_err_status_type_mask = (0x7 << 28),
929};
930#endif