Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
memory: tegra: Prepare for supporting multiple intmask registers
Add a new structure for the intmask register e.g. MC_INTMASK_0 and
it's mask value. Add an array of these new structures to prepare for
supporting multiple intmask registers. This is done in preparation for
adding support for Tegra264 which supports multiple intmask registers.
Signed-off-by: Ketan Patil <ketanp@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Link: https://patch.msgid.link/20260226163115.1152181-6-ketanp@nvidia.com
[krzk: Fix checkpatch warning]
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
authored by
Ketan Patil
and committed by
Krzysztof Kozlowski
9f261451
2e4cfaa7
+125
-40
+9
-7
drivers/memory/tegra/mc.c
+9
-7
drivers/memory/tegra/mc.c
···
586
586
}
587
587
588
588
/* mask all interrupts to avoid flooding */
589
-
status = mc_ch_readl(mc, channel, MC_INTSTATUS) & mc->soc->intmask;
589
+
status = mc_ch_readl(mc, channel, MC_INTSTATUS) & mc->soc->intmasks[0].mask;
590
590
} else {
591
-
status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask;
591
+
status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmasks[0].mask;
592
592
}
593
593
594
594
if (!status)
···
969
969
}
970
970
}
971
971
972
-
if (mc->soc->num_channels)
973
-
mc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->intmask,
974
-
MC_INTMASK);
975
-
else
976
-
mc_writel(mc, mc->soc->intmask, MC_INTMASK);
972
+
for (i = 0; i < mc->soc->num_intmasks; i++) {
973
+
if (mc->soc->num_channels)
974
+
mc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->intmasks[i].mask,
975
+
mc->soc->intmasks[i].reg);
976
+
else
977
+
mc_writel(mc, mc->soc->intmasks[i].mask, mc->soc->intmasks[i].reg);
978
+
}
977
979
}
978
980
979
981
if (mc->soc->reset_ops) {
+10
-2
drivers/memory/tegra/tegra114.c
+10
-2
drivers/memory/tegra/tegra114.c
···
1101
1101
TEGRA114_MC_RESET(VI, 0x200, 0x204, 17),
1102
1102
};
1103
1103
1104
+
static const struct tegra_mc_intmask tegra114_mc_intmasks[] = {
1105
+
{
1106
+
.reg = MC_INTMASK,
1107
+
.mask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION |
1108
+
MC_INT_DECERR_EMEM,
1109
+
},
1110
+
};
1111
+
1104
1112
const struct tegra_mc_soc tegra114_mc_soc = {
1105
1113
.clients = tegra114_mc_clients,
1106
1114
.num_clients = ARRAY_SIZE(tegra114_mc_clients),
···
1116
1108
.atom_size = 32,
1117
1109
.client_id_mask = 0x7f,
1118
1110
.smmu = &tegra114_smmu_soc,
1119
-
.intmask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION |
1120
-
MC_INT_DECERR_EMEM,
1111
+
.intmasks = tegra114_mc_intmasks,
1112
+
.num_intmasks = ARRAY_SIZE(tegra114_mc_intmasks),
1121
1113
.reset_ops = &tegra_mc_reset_ops_common,
1122
1114
.resets = tegra114_mc_resets,
1123
1115
.num_resets = ARRAY_SIZE(tegra114_mc_resets),
+22
-6
drivers/memory/tegra/tegra124.c
+22
-6
drivers/memory/tegra/tegra124.c
···
1258
1258
.num_asids = 128,
1259
1259
};
1260
1260
1261
+
static const struct tegra_mc_intmask tegra124_mc_intmasks[] = {
1262
+
{
1263
+
.reg = MC_INTMASK,
1264
+
.mask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1265
+
MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1266
+
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1267
+
},
1268
+
};
1269
+
1261
1270
const struct tegra_mc_soc tegra124_mc_soc = {
1262
1271
.clients = tegra124_mc_clients,
1263
1272
.num_clients = ARRAY_SIZE(tegra124_mc_clients),
···
1276
1267
.smmu = &tegra124_smmu_soc,
1277
1268
.emem_regs = tegra124_mc_emem_regs,
1278
1269
.num_emem_regs = ARRAY_SIZE(tegra124_mc_emem_regs),
1279
-
.intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1280
-
MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1281
-
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1270
+
.intmasks = tegra124_mc_intmasks,
1271
+
.num_intmasks = ARRAY_SIZE(tegra124_mc_intmasks),
1282
1272
.reset_ops = &tegra_mc_reset_ops_common,
1283
1273
.resets = tegra124_mc_resets,
1284
1274
.num_resets = ARRAY_SIZE(tegra124_mc_resets),
···
1305
1297
.num_asids = 128,
1306
1298
};
1307
1299
1300
+
static const struct tegra_mc_intmask tegra132_mc_intmasks[] = {
1301
+
{
1302
+
.reg = MC_INTMASK,
1303
+
.mask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1304
+
MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1305
+
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1306
+
},
1307
+
};
1308
+
1308
1309
const struct tegra_mc_soc tegra132_mc_soc = {
1309
1310
.clients = tegra124_mc_clients,
1310
1311
.num_clients = ARRAY_SIZE(tegra124_mc_clients),
···
1321
1304
.atom_size = 32,
1322
1305
.client_id_mask = 0x7f,
1323
1306
.smmu = &tegra132_smmu_soc,
1324
-
.intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1325
-
MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1326
-
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1307
+
.intmasks = tegra132_mc_intmasks,
1308
+
.num_intmasks = ARRAY_SIZE(tegra132_mc_intmasks),
1327
1309
.reset_ops = &tegra_mc_reset_ops_common,
1328
1310
.resets = tegra124_mc_resets,
1329
1311
.num_resets = ARRAY_SIZE(tegra124_mc_resets),
+11
-3
drivers/memory/tegra/tegra186.c
+11
-3
drivers/memory/tegra/tegra186.c
···
901
901
},
902
902
};
903
903
904
+
static const struct tegra_mc_intmask tegra186_mc_intmasks[] = {
905
+
{
906
+
.reg = MC_INTMASK,
907
+
.mask = MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
908
+
MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
909
+
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
910
+
},
911
+
};
912
+
904
913
const struct tegra_mc_soc tegra186_mc_soc = {
905
914
.num_clients = ARRAY_SIZE(tegra186_mc_clients),
906
915
.clients = tegra186_mc_clients,
907
916
.num_address_bits = 40,
908
917
.num_channels = 4,
909
918
.client_id_mask = 0xff,
910
-
.intmask = MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
911
-
MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
912
-
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
919
+
.intmasks = tegra186_mc_intmasks,
920
+
.num_intmasks = ARRAY_SIZE(tegra186_mc_intmasks),
913
921
.ops = &tegra186_mc_ops,
914
922
.ch_intmask = 0x0000000f,
915
923
.global_intstatus_channel_shift = 0,
+11
-4
drivers/memory/tegra/tegra194.c
+11
-4
drivers/memory/tegra/tegra194.c
···
1343
1343
},
1344
1344
};
1345
1345
1346
+
static const struct tegra_mc_intmask tegra194_mc_intmasks[] = {
1347
+
{
1348
+
.reg = MC_INTMASK,
1349
+
.mask = MC_INT_DECERR_ROUTE_SANITY | MC_INT_DECERR_GENERALIZED_CARVEOUT |
1350
+
MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1351
+
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1352
+
},
1353
+
};
1354
+
1346
1355
const struct tegra_mc_soc tegra194_mc_soc = {
1347
1356
.num_clients = ARRAY_SIZE(tegra194_mc_clients),
1348
1357
.clients = tegra194_mc_clients,
1349
1358
.num_address_bits = 40,
1350
1359
.num_channels = 16,
1351
1360
.client_id_mask = 0xff,
1352
-
.intmask = MC_INT_DECERR_ROUTE_SANITY |
1353
-
MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
1354
-
MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1355
-
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1361
+
.intmasks = tegra194_mc_intmasks,
1362
+
.num_intmasks = ARRAY_SIZE(tegra194_mc_intmasks),
1356
1363
.has_addr_hi_reg = true,
1357
1364
.ops = &tegra186_mc_ops,
1358
1365
.icc_ops = &tegra_mc_icc_ops,
+11
-3
drivers/memory/tegra/tegra20.c
+11
-3
drivers/memory/tegra/tegra20.c
···
695
695
unsigned int bit;
696
696
697
697
/* mask all interrupts to avoid flooding */
698
-
status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask;
698
+
status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmasks[0].mask;
699
699
if (!status)
700
700
return IRQ_NONE;
701
701
···
769
769
.probe = tegra20_mc_probe,
770
770
};
771
771
772
+
static const struct tegra_mc_intmask tegra20_mc_intmasks[] = {
773
+
{
774
+
.reg = MC_INTMASK,
775
+
.mask = MC_INT_SECURITY_VIOLATION | MC_INT_INVALID_GART_PAGE |
776
+
MC_INT_DECERR_EMEM,
777
+
},
778
+
};
779
+
772
780
const struct tegra_mc_soc tegra20_mc_soc = {
773
781
.clients = tegra20_mc_clients,
774
782
.num_clients = ARRAY_SIZE(tegra20_mc_clients),
775
783
.num_address_bits = 32,
776
784
.client_id_mask = 0x3f,
777
-
.intmask = MC_INT_SECURITY_VIOLATION | MC_INT_INVALID_GART_PAGE |
778
-
MC_INT_DECERR_EMEM,
785
+
.intmasks = tegra20_mc_intmasks,
786
+
.num_intmasks = ARRAY_SIZE(tegra20_mc_intmasks),
779
787
.reset_ops = &tegra20_mc_reset_ops,
780
788
.resets = tegra20_mc_resets,
781
789
.num_resets = ARRAY_SIZE(tegra20_mc_resets),
+11
-3
drivers/memory/tegra/tegra210.c
+11
-3
drivers/memory/tegra/tegra210.c
···
1273
1273
TEGRA210_MC_RESET(TSECB, 0x970, 0x974, 13),
1274
1274
};
1275
1275
1276
+
static const struct tegra_mc_intmask tegra210_mc_intmasks[] = {
1277
+
{
1278
+
.reg = MC_INTMASK,
1279
+
.mask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1280
+
MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1281
+
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1282
+
},
1283
+
};
1284
+
1276
1285
const struct tegra_mc_soc tegra210_mc_soc = {
1277
1286
.clients = tegra210_mc_clients,
1278
1287
.num_clients = ARRAY_SIZE(tegra210_mc_clients),
···
1289
1280
.atom_size = 64,
1290
1281
.client_id_mask = 0xff,
1291
1282
.smmu = &tegra210_smmu_soc,
1292
-
.intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1293
-
MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1294
-
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1283
+
.intmasks = tegra210_mc_intmasks,
1284
+
.num_intmasks = ARRAY_SIZE(tegra210_mc_intmasks),
1295
1285
.reset_ops = &tegra_mc_reset_ops_common,
1296
1286
.resets = tegra210_mc_resets,
1297
1287
.num_resets = ARRAY_SIZE(tegra210_mc_resets),
+11
-4
drivers/memory/tegra/tegra234.c
+11
-4
drivers/memory/tegra/tegra234.c
···
1132
1132
.set = tegra234_mc_icc_set,
1133
1133
};
1134
1134
1135
+
static const struct tegra_mc_intmask tegra234_mc_intmasks[] = {
1136
+
{
1137
+
.reg = MC_INTMASK,
1138
+
.mask = MC_INT_DECERR_ROUTE_SANITY | MC_INT_DECERR_GENERALIZED_CARVEOUT |
1139
+
MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1140
+
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1141
+
},
1142
+
};
1143
+
1135
1144
const struct tegra_mc_soc tegra234_mc_soc = {
1136
1145
.num_clients = ARRAY_SIZE(tegra234_mc_clients),
1137
1146
.clients = tegra234_mc_clients,
1138
1147
.num_address_bits = 40,
1139
1148
.num_channels = 16,
1140
1149
.client_id_mask = 0x1ff,
1141
-
.intmask = MC_INT_DECERR_ROUTE_SANITY |
1142
-
MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
1143
-
MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1144
-
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1150
+
.intmasks = tegra234_mc_intmasks,
1151
+
.num_intmasks = ARRAY_SIZE(tegra234_mc_intmasks),
1145
1152
.has_addr_hi_reg = true,
1146
1153
.ops = &tegra186_mc_ops,
1147
1154
.icc_ops = &tegra234_mc_icc_ops,
+12
-5
drivers/memory/tegra/tegra264.c
+12
-5
drivers/memory/tegra/tegra264.c
···
1
1
// SPDX-License-Identifier: GPL-2.0-only
2
2
/*
3
-
* Copyright (C) 2025, NVIDIA CORPORATION. All rights reserved.
3
+
* Copyright (C) 2025-2026, NVIDIA CORPORATION. All rights reserved.
4
4
*/
5
5
6
6
#include <dt-bindings/memory/nvidia,tegra264.h>
···
290
290
.set = tegra264_mc_icc_set,
291
291
};
292
292
293
+
static const struct tegra_mc_intmask tegra264_mc_intmasks[] = {
294
+
{
295
+
.reg = MC_INTMASK,
296
+
.mask = MC_INT_DECERR_ROUTE_SANITY | MC_INT_DECERR_GENERALIZED_CARVEOUT |
297
+
MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
298
+
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
299
+
},
300
+
};
301
+
293
302
const struct tegra_mc_soc tegra264_mc_soc = {
294
303
.num_clients = ARRAY_SIZE(tegra264_mc_clients),
295
304
.clients = tegra264_mc_clients,
296
305
.num_address_bits = 40,
297
306
.num_channels = 16,
298
307
.client_id_mask = 0x1ff,
299
-
.intmask = MC_INT_DECERR_ROUTE_SANITY |
300
-
MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
301
-
MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
302
-
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
308
+
.intmasks = tegra264_mc_intmasks,
309
+
.num_intmasks = ARRAY_SIZE(tegra264_mc_intmasks),
303
310
.has_addr_hi_reg = true,
304
311
.ops = &tegra186_mc_ops,
305
312
.icc_ops = &tegra264_mc_icc_ops,
+10
-2
drivers/memory/tegra/tegra30.c
+10
-2
drivers/memory/tegra/tegra30.c
···
1384
1384
.set = tegra30_mc_icc_set,
1385
1385
};
1386
1386
1387
+
static const struct tegra_mc_intmask tegra30_mc_intmasks[] = {
1388
+
{
1389
+
.reg = MC_INTMASK,
1390
+
.mask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION |
1391
+
MC_INT_DECERR_EMEM,
1392
+
},
1393
+
};
1394
+
1387
1395
const struct tegra_mc_soc tegra30_mc_soc = {
1388
1396
.clients = tegra30_mc_clients,
1389
1397
.num_clients = ARRAY_SIZE(tegra30_mc_clients),
···
1401
1393
.smmu = &tegra30_smmu_soc,
1402
1394
.emem_regs = tegra30_mc_emem_regs,
1403
1395
.num_emem_regs = ARRAY_SIZE(tegra30_mc_emem_regs),
1404
-
.intmask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION |
1405
-
MC_INT_DECERR_EMEM,
1396
+
.intmasks = tegra30_mc_intmasks,
1397
+
.num_intmasks = ARRAY_SIZE(tegra30_mc_intmasks),
1406
1398
.reset_ops = &tegra_mc_reset_ops_common,
1407
1399
.resets = tegra30_mc_resets,
1408
1400
.num_resets = ARRAY_SIZE(tegra30_mc_resets),
+7
-1
include/soc/tegra/mc.h
+7
-1
include/soc/tegra/mc.h
···
185
185
unsigned int err_route_add;
186
186
};
187
187
188
+
struct tegra_mc_intmask {
189
+
u32 reg;
190
+
u32 mask;
191
+
};
192
+
188
193
struct tegra_mc_soc {
189
194
const struct tegra_mc_client *clients;
190
195
unsigned int num_clients;
···
207
202
208
203
const struct tegra_smmu_soc *smmu;
209
204
210
-
u32 intmask;
211
205
u32 ch_intmask;
212
206
u32 global_intstatus_channel_shift;
213
207
bool has_addr_hi_reg;
···
223
219
unsigned int num_interrupts;
224
220
unsigned int mc_addr_hi_mask;
225
221
unsigned int mc_err_status_type_mask;
222
+
const struct tegra_mc_intmask *intmasks;
223
+
unsigned int num_intmasks;
226
224
};
227
225
228
226
struct tegra_mc {