Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'riscv-dt-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt
RISC-V Devicetrees for v6.16
Starfive:
All Starfive this time (again), enabling the usb3 port on the framework
laptop mainboard, and a few cleanup patches that are syncing things with
the dts used by U-Boot.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-dt-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
riscv: dts: starfive: jh7110-common: bootph-pre-ram hinting needed by boot loader
riscv: dts: starfive: jh7110-common: add eeprom node to i2c5
riscv: dts: starfive: jh7110-common: qspi flash setting read-delay 2 cycles max 100MHz
riscv: dts: starfive: jh7110-common: add CPU BUS PERH QSPI clocks to syscrg
riscv: dts: starfive: jh7110-common: use macros for MMC0 pins
riscv: dts: starfive: fml13v01: enable USB 3.0 port
Link: https://lore.kernel.org/r/20250516-gap-exploring-f8f516ab4e1c@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+57
-14
+38
-14
arch/riscv/boot/dts/starfive/jh7110-common.dtsi
+38
-14
arch/riscv/boot/dts/starfive/jh7110-common.dtsi
···
8
8
#include "jh7110.dtsi"
9
9
#include "jh7110-pinfunc.h"
10
10
#include <dt-bindings/gpio/gpio.h>
11
+
#include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>
11
12
12
13
/ {
13
14
aliases {
···
29
28
memory@40000000 {
30
29
device_type = "memory";
31
30
reg = <0x0 0x40000000 0x1 0x0>;
31
+
bootph-pre-ram;
32
32
};
33
33
34
34
gpio-restart {
···
247
245
};
248
246
};
249
247
};
248
+
249
+
eeprom@50 {
250
+
compatible = "atmel,24c04";
251
+
reg = <0x50>;
252
+
bootph-pre-ram;
253
+
pagesize = <16>;
254
+
};
250
255
};
251
256
252
257
&i2c6 {
···
271
262
assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
272
263
assigned-clock-rates = <50000000>;
273
264
bus-width = <8>;
265
+
bootph-pre-ram;
274
266
cap-mmc-highspeed;
275
267
mmc-ddr-1_8v;
276
268
mmc-hs200-1_8v;
···
289
279
assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
290
280
assigned-clock-rates = <50000000>;
291
281
bus-width = <4>;
282
+
bootph-pre-ram;
292
283
no-sdio;
293
284
no-mmc;
294
285
cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
···
328
317
nor_flash: flash@0 {
329
318
compatible = "jedec,spi-nor";
330
319
reg = <0>;
331
-
cdns,read-delay = <5>;
332
-
spi-max-frequency = <12000000>;
320
+
bootph-pre-ram;
321
+
cdns,read-delay = <2>;
322
+
spi-max-frequency = <100000000>;
333
323
cdns,tshsl-ns = <1>;
334
324
cdns,tsd2d-ns = <1>;
335
325
cdns,tchsh-ns = <1>;
···
365
353
};
366
354
367
355
&syscrg {
368
-
assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>,
356
+
assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
357
+
<&syscrg JH7110_SYSCLK_BUS_ROOT>,
358
+
<&syscrg JH7110_SYSCLK_PERH_ROOT>,
359
+
<&syscrg JH7110_SYSCLK_QSPI_REF>,
360
+
<&syscrg JH7110_SYSCLK_CPU_CORE>,
369
361
<&pllclk JH7110_PLLCLK_PLL0_OUT>;
370
-
assigned-clock-rates = <500000000>, <1500000000>;
362
+
assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
363
+
<&pllclk JH7110_PLLCLK_PLL2_OUT>,
364
+
<&pllclk JH7110_PLLCLK_PLL2_OUT>,
365
+
<&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
366
+
assigned-clock-rates = <0>, <0>, <0>, <0>, <500000000>, <1500000000>;
371
367
};
372
368
373
369
&sysgpio {
···
408
388
};
409
389
410
390
i2c5_pins: i2c5-0 {
391
+
bootph-pre-ram;
392
+
411
393
i2c-pins {
412
394
pinmux = <GPIOMUX(19, GPOUT_LOW,
413
395
GPOEN_SYS_I2C5_CLK,
···
418
396
GPOEN_SYS_I2C5_DATA,
419
397
GPI_SYS_I2C5_DATA)>;
420
398
bias-disable; /* external pull-up */
399
+
bootph-pre-ram;
421
400
input-enable;
422
401
input-schmitt-enable;
423
402
};
···
451
428
};
452
429
453
430
mmc-pins {
454
-
pinmux = <PINMUX(64, 0)>,
455
-
<PINMUX(65, 0)>,
456
-
<PINMUX(66, 0)>,
457
-
<PINMUX(67, 0)>,
458
-
<PINMUX(68, 0)>,
459
-
<PINMUX(69, 0)>,
460
-
<PINMUX(70, 0)>,
461
-
<PINMUX(71, 0)>,
462
-
<PINMUX(72, 0)>,
463
-
<PINMUX(73, 0)>;
431
+
pinmux = <PINMUX(PAD_SD0_CLK, 0)>,
432
+
<PINMUX(PAD_SD0_CMD, 0)>,
433
+
<PINMUX(PAD_SD0_DATA0, 0)>,
434
+
<PINMUX(PAD_SD0_DATA1, 0)>,
435
+
<PINMUX(PAD_SD0_DATA2, 0)>,
436
+
<PINMUX(PAD_SD0_DATA3, 0)>,
437
+
<PINMUX(PAD_SD0_DATA4, 0)>,
438
+
<PINMUX(PAD_SD0_DATA5, 0)>,
439
+
<PINMUX(PAD_SD0_DATA6, 0)>,
440
+
<PINMUX(PAD_SD0_DATA7, 0)>;
464
441
bias-pull-up;
465
442
drive-strength = <12>;
466
443
input-enable;
···
647
624
};
648
625
649
626
&uart0 {
627
+
bootph-pre-ram;
650
628
pinctrl-names = "default";
651
629
pinctrl-0 = <&uart0_pins>;
652
630
status = "okay";
+19
arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
+19
arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
···
43
43
slew-rate = <0>;
44
44
};
45
45
};
46
+
47
+
usb0_pins: usb0-0 {
48
+
vbus-pins {
49
+
pinmux = <GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS,
50
+
GPOEN_ENABLE,
51
+
GPI_NONE)>;
52
+
bias-disable;
53
+
input-disable;
54
+
input-schmitt-disable;
55
+
slew-rate = <0>;
56
+
};
57
+
};
46
58
};
47
59
48
60
&usb0 {
49
61
dr_mode = "host";
62
+
pinctrl-names = "default";
63
+
pinctrl-0 = <&usb0_pins>;
50
64
status = "okay";
65
+
};
66
+
67
+
&usb_cdns3 {
68
+
phys = <&usbphy0>, <&pciephy0>;
69
+
phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy";
51
70
};