Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
spi: support controllers with multiple data lanes
Add support for SPI controllers with multiple physical SPI data lanes.
(A data lane in this context means lines connected to a serializer, so a
controller with two data lanes would have two serializers in a single
controller).
This is common in the type of controller that can be used with parallel
flash memories, but can be used for general purpose SPI as well.
To indicate support, a controller just needs to set ctlr->num_data_lanes
to something greater than 1. Peripherals indicate which lane they are
connected to via device tree (ACPI support can be added if needed).
The spi-{tx,rx}-bus-width DT properties can now be arrays. The length of
the array indicates the number of data lanes, and each element indicates
the bus width of that lane. For now, we restrict all lanes to have the
same bus width to keep things simple. Support for an optional controller
lane mapping property is also implemented.
Signed-off-by: David Lechner <dlechner@baylibre.com>
Link: https://patch.msgid.link/20260123-spi-add-multi-bus-support-v6-3-12af183c06eb@baylibre.com
Signed-off-by: Mark Brown <broonie@kernel.org>
authored by
David Lechner
and committed by
Mark Brown
002d561f
31eab842
+162
-4
+140
-4
drivers/spi/spi.c
+140
-4
drivers/spi/spi.c
···
2354
2354
static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
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struct device_node *nc)
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{
2357
-
u32 value, cs[SPI_DEVICE_CS_CNT_MAX];
2358
-
int rc, idx;
2357
+
u32 value, cs[SPI_DEVICE_CS_CNT_MAX], map[SPI_DEVICE_DATA_LANE_CNT_MAX];
2358
+
int rc, idx, max_num_data_lanes;
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/* Mode (clock phase/polarity/etc.) */
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if (of_property_read_bool(nc, "spi-cpha"))
···
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spi->mode |= SPI_CS_HIGH;
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/* Device DUAL/QUAD mode */
2373
-
if (!of_property_read_u32(nc, "spi-tx-bus-width", &value)) {
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+
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+
rc = of_property_read_variable_u32_array(nc, "spi-tx-lane-map", map, 1,
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+
ARRAY_SIZE(map));
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+
if (rc >= 0) {
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+
max_num_data_lanes = rc;
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+
for (idx = 0; idx < max_num_data_lanes; idx++)
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+
spi->tx_lane_map[idx] = map[idx];
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+
} else if (rc == -EINVAL) {
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/* Default lane map is identity mapping. */
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max_num_data_lanes = ARRAY_SIZE(spi->tx_lane_map);
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+
for (idx = 0; idx < max_num_data_lanes; idx++)
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spi->tx_lane_map[idx] = idx;
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+
} else {
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+
dev_err(&ctlr->dev,
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+
"failed to read spi-tx-lane-map property: %d\n", rc);
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+
return rc;
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}
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+
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rc = of_property_count_u32_elems(nc, "spi-tx-bus-width");
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+
if (rc < 0 && rc != -EINVAL) {
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dev_err(&ctlr->dev,
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+
"failed to read spi-tx-bus-width property: %d\n", rc);
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+
return rc;
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+
}
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+
if (rc > max_num_data_lanes) {
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dev_err(&ctlr->dev,
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+
"spi-tx-bus-width has more elements (%d) than spi-tx-lane-map (%d)\n",
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+
rc, max_num_data_lanes);
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+
return -EINVAL;
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+
}
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+
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if (rc == -EINVAL) {
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+
/* Default when property is not present. */
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spi->num_tx_lanes = 1;
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+
} else {
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u32 first_value;
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+
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spi->num_tx_lanes = rc;
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+
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for (idx = 0; idx < spi->num_tx_lanes; idx++) {
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rc = of_property_read_u32_index(nc, "spi-tx-bus-width",
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idx, &value);
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if (rc)
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return rc;
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+
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/*
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* For now, we only support all lanes having the same
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* width so we can keep using the existing mode flags.
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*/
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+
if (!idx)
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first_value = value;
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else if (first_value != value) {
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dev_err(&ctlr->dev,
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+
"spi-tx-bus-width has inconsistent values: first %d vs later %d\n",
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+
first_value, value);
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+
return -EINVAL;
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+
}
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+
}
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+
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switch (value) {
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case 0:
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spi->mode |= SPI_NO_TX;
···
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}
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}
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-
if (!of_property_read_u32(nc, "spi-rx-bus-width", &value)) {
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for (idx = 0; idx < spi->num_tx_lanes; idx++) {
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+
if (spi->tx_lane_map[idx] >= spi->controller->num_data_lanes) {
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+
dev_err(&ctlr->dev,
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+
"spi-tx-lane-map has invalid value %d (num_data_lanes=%d)\n",
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+
spi->tx_lane_map[idx],
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+
spi->controller->num_data_lanes);
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+
return -EINVAL;
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+
}
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+
}
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+
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+
rc = of_property_read_variable_u32_array(nc, "spi-rx-lane-map", map, 1,
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+
ARRAY_SIZE(map));
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+
if (rc >= 0) {
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+
max_num_data_lanes = rc;
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+
for (idx = 0; idx < max_num_data_lanes; idx++)
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spi->rx_lane_map[idx] = map[idx];
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+
} else if (rc == -EINVAL) {
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+
/* Default lane map is identity mapping. */
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max_num_data_lanes = ARRAY_SIZE(spi->rx_lane_map);
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+
for (idx = 0; idx < max_num_data_lanes; idx++)
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+
spi->rx_lane_map[idx] = idx;
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+
} else {
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dev_err(&ctlr->dev,
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+
"failed to read spi-rx-lane-map property: %d\n", rc);
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+
return rc;
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+
}
2423
+
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+
rc = of_property_count_u32_elems(nc, "spi-rx-bus-width");
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+
if (rc < 0 && rc != -EINVAL) {
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+
dev_err(&ctlr->dev,
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+
"failed to read spi-rx-bus-width property: %d\n", rc);
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+
return rc;
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+
}
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+
if (rc > max_num_data_lanes) {
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+
dev_err(&ctlr->dev,
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+
"spi-rx-bus-width has more elements (%d) than spi-rx-lane-map (%d)\n",
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rc, max_num_data_lanes);
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+
return -EINVAL;
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+
}
2436
+
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+
if (rc == -EINVAL) {
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+
/* Default when property is not present. */
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+
spi->num_rx_lanes = 1;
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+
} else {
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+
u32 first_value;
2442
+
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+
spi->num_rx_lanes = rc;
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+
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+
for (idx = 0; idx < spi->num_rx_lanes; idx++) {
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+
rc = of_property_read_u32_index(nc, "spi-rx-bus-width",
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+
idx, &value);
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+
if (rc)
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+
return rc;
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+
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+
/*
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* For now, we only support all lanes having the same
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+
* width so we can keep using the existing mode flags.
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+
*/
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+
if (!idx)
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+
first_value = value;
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+
else if (first_value != value) {
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+
dev_err(&ctlr->dev,
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+
"spi-rx-bus-width has inconsistent values: first %d vs later %d\n",
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+
first_value, value);
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+
return -EINVAL;
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+
}
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+
}
2464
+
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switch (value) {
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case 0:
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spi->mode |= SPI_NO_RX;
···
2540
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"spi-rx-bus-width %d not supported\n",
2541
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value);
2542
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break;
2418
+
}
2419
+
}
2420
+
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+
for (idx = 0; idx < spi->num_rx_lanes; idx++) {
2422
+
if (spi->rx_lane_map[idx] >= spi->controller->num_data_lanes) {
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+
dev_err(&ctlr->dev,
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+
"spi-rx-lane-map has invalid value %d (num_data_lanes=%d)\n",
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+
spi->rx_lane_map[idx],
2426
+
spi->controller->num_data_lanes);
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+
return -EINVAL;
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}
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}
2545
2430
···
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mutex_init(&ctlr->add_lock);
3202
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ctlr->bus_num = -1;
3203
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ctlr->num_chipselect = 1;
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+
ctlr->num_data_lanes = 1;
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ctlr->target = target;
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if (IS_ENABLED(CONFIG_SPI_SLAVE) && target)
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ctlr->dev.class = &spi_target_class;
+22
include/linux/spi/spi.h
+22
include/linux/spi/spi.h
···
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/* Max no. of CS supported per spi device */
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#define SPI_DEVICE_CS_CNT_MAX 4
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+
/* Max no. of data lanes supported per spi device */
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+
#define SPI_DEVICE_DATA_LANE_CNT_MAX 8
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+
26
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struct dma_chan;
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struct software_node;
28
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struct ptp_system_timestamp;
···
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* @cs_index_mask: Bit mask of the active chipselect(s) in the chipselect array
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* @cs_gpiod: Array of GPIO descriptors of the corresponding chipselect lines
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* (optional, NULL when not using a GPIO line)
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+
* @tx_lane_map: Map of peripheral lanes (index) to controller lanes (value).
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+
* @num_tx_lanes: Number of transmit lanes wired up.
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+
* @rx_lane_map: Map of peripheral lanes (index) to controller lanes (value).
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+
* @num_rx_lanes: Number of receive lanes wired up.
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*
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* A @spi_device is used to interchange data between an SPI target device
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* (usually a discrete chip) and CPU memory.
···
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u32 cs_index_mask : SPI_DEVICE_CS_CNT_MAX;
249
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struct gpio_desc *cs_gpiod[SPI_DEVICE_CS_CNT_MAX]; /* Chip select gpio desc */
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+
245
+
/* Multi-lane SPI controller support. */
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+
u8 tx_lane_map[SPI_DEVICE_DATA_LANE_CNT_MAX];
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+
u8 num_tx_lanes;
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+
u8 rx_lane_map[SPI_DEVICE_DATA_LANE_CNT_MAX];
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+
u8 num_rx_lanes;
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252
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/*
253
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* Likely need more hooks for more protocol options affecting how
···
414
401
* SPI targets, and are numbered from zero to num_chipselects.
415
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* each target has a chipselect signal, but it's common that not
416
403
* every chipselect is connected to a target.
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+
* @num_data_lanes: Number of data lanes supported by this controller. Default is 1.
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* @dma_alignment: SPI controller constraint on DMA buffers alignment.
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* @mode_bits: flags understood by this controller driver
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* @buswidth_override_bits: flags to override for this controller driver
···
589
575
* might use board-specific GPIOs.
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*/
591
577
u16 num_chipselect;
578
+
579
+
/*
580
+
* Some specialized SPI controllers can have more than one physical
581
+
* data lane interface per controller (each having it's own serializer).
582
+
* This specifies the number of data lanes in that case. Other
583
+
* controllers do not need to set this (defaults to 1).
584
+
*/
585
+
u16 num_data_lanes;
592
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593
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/* Some SPI controllers pose alignment requirements on DMAable
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* buffers; let protocol drivers know about these requirements.