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drm/amd/display: Fix dcn401_optimize_bandwidth

[Why&How]
We should check for != zstate disallow and programming extend blank from a
different struct.

Reviewed-by: Leo Chen <leo.chen@amd.com>
Reviewed-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Charlene Liu and committed by
Alex Deucher 002f32db 44081e86

+2 -2
+2 -2
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
··· 1483 1483 dc->clk_mgr, 1484 1484 context, 1485 1485 true); 1486 - if (context->bw_ctx.bw.dcn.clk.zstate_support == DCN_ZSTATE_SUPPORT_ALLOW) { 1486 + if (context->bw_ctx.bw.dcn.clk.zstate_support != DCN_ZSTATE_SUPPORT_DISALLOW) { 1487 1487 for (i = 0; i < dc->res_pool->pipe_count; ++i) { 1488 1488 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1489 1489 ··· 1491 1491 && pipe_ctx->stream->adjust.v_total_min == pipe_ctx->stream->adjust.v_total_max 1492 1492 && pipe_ctx->stream->adjust.v_total_max > pipe_ctx->stream->timing.v_total) 1493 1493 pipe_ctx->plane_res.hubp->funcs->program_extended_blank(pipe_ctx->plane_res.hubp, 1494 - pipe_ctx->dlg_regs.min_dst_y_next_start); 1494 + pipe_ctx->hubp_regs.dlg_regs.min_dst_y_next_start); 1495 1495 } 1496 1496 } 1497 1497 }